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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
b6c02715 | 30 | #include <asm/proto.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
6a9401a7 | 33 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 34 | #include <asm/amd_iommu_types.h> |
c6da992e | 35 | #include <asm/amd_iommu.h> |
b6c02715 JR |
36 | |
37 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
38 | ||
815b33fd | 39 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 40 | |
b6c02715 JR |
41 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
42 | ||
bd60b735 JR |
43 | /* A list of preallocated protection domains */ |
44 | static LIST_HEAD(iommu_pd_list); | |
45 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
46 | ||
0feae533 JR |
47 | /* |
48 | * Domain for untranslated devices - only allocated | |
49 | * if iommu=pt passed on kernel cmd line. | |
50 | */ | |
51 | static struct protection_domain *pt_domain; | |
52 | ||
26961efe | 53 | static struct iommu_ops amd_iommu_ops; |
26961efe | 54 | |
431b2a20 JR |
55 | /* |
56 | * general struct to manage commands send to an IOMMU | |
57 | */ | |
d6449536 | 58 | struct iommu_cmd { |
b6c02715 JR |
59 | u32 data[4]; |
60 | }; | |
61 | ||
04bfdd84 | 62 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 63 | |
15898bbc JR |
64 | /**************************************************************************** |
65 | * | |
66 | * Helper functions | |
67 | * | |
68 | ****************************************************************************/ | |
69 | ||
70 | static inline u16 get_device_id(struct device *dev) | |
71 | { | |
72 | struct pci_dev *pdev = to_pci_dev(dev); | |
73 | ||
74 | return calc_devid(pdev->bus->number, pdev->devfn); | |
75 | } | |
76 | ||
657cbb6b JR |
77 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
78 | { | |
79 | return dev->archdata.iommu; | |
80 | } | |
81 | ||
71c70984 JR |
82 | /* |
83 | * In this function the list of preallocated protection domains is traversed to | |
84 | * find the domain for a specific device | |
85 | */ | |
86 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
87 | { | |
88 | struct dma_ops_domain *entry, *ret = NULL; | |
89 | unsigned long flags; | |
90 | u16 alias = amd_iommu_alias_table[devid]; | |
91 | ||
92 | if (list_empty(&iommu_pd_list)) | |
93 | return NULL; | |
94 | ||
95 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
96 | ||
97 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
98 | if (entry->target_dev == devid || | |
99 | entry->target_dev == alias) { | |
100 | ret = entry; | |
101 | break; | |
102 | } | |
103 | } | |
104 | ||
105 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
106 | ||
107 | return ret; | |
108 | } | |
109 | ||
98fc5a69 JR |
110 | /* |
111 | * This function checks if the driver got a valid device from the caller to | |
112 | * avoid dereferencing invalid pointers. | |
113 | */ | |
114 | static bool check_device(struct device *dev) | |
115 | { | |
116 | u16 devid; | |
117 | ||
118 | if (!dev || !dev->dma_mask) | |
119 | return false; | |
120 | ||
121 | /* No device or no PCI device */ | |
339d3261 | 122 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
123 | return false; |
124 | ||
125 | devid = get_device_id(dev); | |
126 | ||
127 | /* Out of our scope? */ | |
128 | if (devid > amd_iommu_last_bdf) | |
129 | return false; | |
130 | ||
131 | if (amd_iommu_rlookup_table[devid] == NULL) | |
132 | return false; | |
133 | ||
134 | return true; | |
135 | } | |
136 | ||
657cbb6b JR |
137 | static int iommu_init_device(struct device *dev) |
138 | { | |
139 | struct iommu_dev_data *dev_data; | |
140 | struct pci_dev *pdev; | |
141 | u16 devid, alias; | |
142 | ||
143 | if (dev->archdata.iommu) | |
144 | return 0; | |
145 | ||
146 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
147 | if (!dev_data) | |
148 | return -ENOMEM; | |
149 | ||
b00d3bcf JR |
150 | dev_data->dev = dev; |
151 | ||
657cbb6b JR |
152 | devid = get_device_id(dev); |
153 | alias = amd_iommu_alias_table[devid]; | |
154 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
155 | if (pdev) | |
156 | dev_data->alias = &pdev->dev; | |
157 | ||
24100055 JR |
158 | atomic_set(&dev_data->bind, 0); |
159 | ||
657cbb6b JR |
160 | dev->archdata.iommu = dev_data; |
161 | ||
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static void iommu_uninit_device(struct device *dev) | |
167 | { | |
168 | kfree(dev->archdata.iommu); | |
169 | } | |
b7cc9554 JR |
170 | |
171 | void __init amd_iommu_uninit_devices(void) | |
172 | { | |
173 | struct pci_dev *pdev = NULL; | |
174 | ||
175 | for_each_pci_dev(pdev) { | |
176 | ||
177 | if (!check_device(&pdev->dev)) | |
178 | continue; | |
179 | ||
180 | iommu_uninit_device(&pdev->dev); | |
181 | } | |
182 | } | |
183 | ||
184 | int __init amd_iommu_init_devices(void) | |
185 | { | |
186 | struct pci_dev *pdev = NULL; | |
187 | int ret = 0; | |
188 | ||
189 | for_each_pci_dev(pdev) { | |
190 | ||
191 | if (!check_device(&pdev->dev)) | |
192 | continue; | |
193 | ||
194 | ret = iommu_init_device(&pdev->dev); | |
195 | if (ret) | |
196 | goto out_free; | |
197 | } | |
198 | ||
199 | return 0; | |
200 | ||
201 | out_free: | |
202 | ||
203 | amd_iommu_uninit_devices(); | |
204 | ||
205 | return ret; | |
206 | } | |
7f26508b JR |
207 | #ifdef CONFIG_AMD_IOMMU_STATS |
208 | ||
209 | /* | |
210 | * Initialization code for statistics collection | |
211 | */ | |
212 | ||
da49f6df | 213 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 214 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 215 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 216 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 217 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 218 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 219 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 220 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 221 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 222 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 223 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 224 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 225 | |
7f26508b | 226 | static struct dentry *stats_dir; |
7f26508b JR |
227 | static struct dentry *de_fflush; |
228 | ||
229 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
230 | { | |
231 | if (stats_dir == NULL) | |
232 | return; | |
233 | ||
234 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
235 | &cnt->value); | |
236 | } | |
237 | ||
238 | static void amd_iommu_stats_init(void) | |
239 | { | |
240 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
241 | if (stats_dir == NULL) | |
242 | return; | |
243 | ||
7f26508b JR |
244 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
245 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
246 | |
247 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 248 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 249 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 250 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 251 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 252 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 253 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 254 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 255 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 256 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 257 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 258 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
259 | } |
260 | ||
261 | #endif | |
262 | ||
a80dc3e0 JR |
263 | /**************************************************************************** |
264 | * | |
265 | * Interrupt handling functions | |
266 | * | |
267 | ****************************************************************************/ | |
268 | ||
e3e59876 JR |
269 | static void dump_dte_entry(u16 devid) |
270 | { | |
271 | int i; | |
272 | ||
273 | for (i = 0; i < 8; ++i) | |
274 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
275 | amd_iommu_dev_table[devid].data[i]); | |
276 | } | |
277 | ||
945b4ac4 JR |
278 | static void dump_command(unsigned long phys_addr) |
279 | { | |
280 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
281 | int i; | |
282 | ||
283 | for (i = 0; i < 4; ++i) | |
284 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
285 | } | |
286 | ||
a345b23b | 287 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
288 | { |
289 | u32 *event = __evt; | |
290 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
291 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
292 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
293 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
294 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
295 | ||
4c6f40d4 | 296 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
297 | |
298 | switch (type) { | |
299 | case EVENT_TYPE_ILL_DEV: | |
300 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
301 | "address=0x%016llx flags=0x%04x]\n", | |
302 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
303 | address, flags); | |
e3e59876 | 304 | dump_dte_entry(devid); |
90008ee4 JR |
305 | break; |
306 | case EVENT_TYPE_IO_FAULT: | |
307 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
308 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
309 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
310 | domid, address, flags); | |
311 | break; | |
312 | case EVENT_TYPE_DEV_TAB_ERR: | |
313 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
314 | "address=0x%016llx flags=0x%04x]\n", | |
315 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
316 | address, flags); | |
317 | break; | |
318 | case EVENT_TYPE_PAGE_TAB_ERR: | |
319 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
320 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
321 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
322 | domid, address, flags); | |
323 | break; | |
324 | case EVENT_TYPE_ILL_CMD: | |
325 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 326 | dump_command(address); |
90008ee4 JR |
327 | break; |
328 | case EVENT_TYPE_CMD_HARD_ERR: | |
329 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
330 | "flags=0x%04x]\n", address, flags); | |
331 | break; | |
332 | case EVENT_TYPE_IOTLB_INV_TO: | |
333 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
334 | "address=0x%016llx]\n", | |
335 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
336 | address); | |
337 | break; | |
338 | case EVENT_TYPE_INV_DEV_REQ: | |
339 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
340 | "address=0x%016llx flags=0x%04x]\n", | |
341 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
342 | address, flags); | |
343 | break; | |
344 | default: | |
345 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
346 | } | |
347 | } | |
348 | ||
349 | static void iommu_poll_events(struct amd_iommu *iommu) | |
350 | { | |
351 | u32 head, tail; | |
352 | unsigned long flags; | |
353 | ||
354 | spin_lock_irqsave(&iommu->lock, flags); | |
355 | ||
356 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
357 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
358 | ||
359 | while (head != tail) { | |
a345b23b | 360 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
361 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
362 | } | |
363 | ||
364 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
365 | ||
366 | spin_unlock_irqrestore(&iommu->lock, flags); | |
367 | } | |
368 | ||
a80dc3e0 JR |
369 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
370 | { | |
90008ee4 JR |
371 | struct amd_iommu *iommu; |
372 | ||
3bd22172 | 373 | for_each_iommu(iommu) |
90008ee4 JR |
374 | iommu_poll_events(iommu); |
375 | ||
376 | return IRQ_HANDLED; | |
a80dc3e0 JR |
377 | } |
378 | ||
431b2a20 JR |
379 | /**************************************************************************** |
380 | * | |
381 | * IOMMU command queuing functions | |
382 | * | |
383 | ****************************************************************************/ | |
384 | ||
ac0ea6e9 JR |
385 | static int wait_on_sem(volatile u64 *sem) |
386 | { | |
387 | int i = 0; | |
388 | ||
389 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
390 | udelay(1); | |
391 | i += 1; | |
392 | } | |
393 | ||
394 | if (i == LOOP_TIMEOUT) { | |
395 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
396 | return -EIO; | |
397 | } | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
403 | struct iommu_cmd *cmd, | |
404 | u32 tail) | |
405 | { | |
406 | u8 *target; | |
407 | ||
408 | target = iommu->cmd_buf + tail; | |
409 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
410 | ||
411 | /* Copy command to buffer */ | |
412 | memcpy(target, cmd, sizeof(*cmd)); | |
413 | ||
414 | /* Tell the IOMMU about it */ | |
415 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
416 | } | |
417 | ||
815b33fd | 418 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 419 | { |
815b33fd JR |
420 | WARN_ON(address & 0x7ULL); |
421 | ||
ded46737 | 422 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
423 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
424 | cmd->data[1] = upper_32_bits(__pa(address)); | |
425 | cmd->data[2] = 1; | |
ded46737 JR |
426 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
427 | } | |
428 | ||
94fe79e2 JR |
429 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
430 | { | |
431 | memset(cmd, 0, sizeof(*cmd)); | |
432 | cmd->data[0] = devid; | |
433 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
434 | } | |
435 | ||
11b6402c JR |
436 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
437 | size_t size, u16 domid, int pde) | |
438 | { | |
439 | u64 pages; | |
440 | int s; | |
441 | ||
442 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
443 | s = 0; | |
444 | ||
445 | if (pages > 1) { | |
446 | /* | |
447 | * If we have to flush more than one page, flush all | |
448 | * TLB entries for this domain | |
449 | */ | |
450 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
451 | s = 1; | |
452 | } | |
453 | ||
454 | address &= PAGE_MASK; | |
455 | ||
456 | memset(cmd, 0, sizeof(*cmd)); | |
457 | cmd->data[1] |= domid; | |
458 | cmd->data[2] = lower_32_bits(address); | |
459 | cmd->data[3] = upper_32_bits(address); | |
460 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
461 | if (s) /* size bit - we flush more than one 4kb page */ | |
462 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
463 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
464 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
465 | } | |
466 | ||
cb41ed85 JR |
467 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
468 | u64 address, size_t size) | |
469 | { | |
470 | u64 pages; | |
471 | int s; | |
472 | ||
473 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
474 | s = 0; | |
475 | ||
476 | if (pages > 1) { | |
477 | /* | |
478 | * If we have to flush more than one page, flush all | |
479 | * TLB entries for this domain | |
480 | */ | |
481 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
482 | s = 1; | |
483 | } | |
484 | ||
485 | address &= PAGE_MASK; | |
486 | ||
487 | memset(cmd, 0, sizeof(*cmd)); | |
488 | cmd->data[0] = devid; | |
489 | cmd->data[0] |= (qdep & 0xff) << 24; | |
490 | cmd->data[1] = devid; | |
491 | cmd->data[2] = lower_32_bits(address); | |
492 | cmd->data[3] = upper_32_bits(address); | |
493 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
494 | if (s) | |
495 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
496 | } | |
497 | ||
431b2a20 JR |
498 | /* |
499 | * Writes the command to the IOMMUs command buffer and informs the | |
ac0ea6e9 | 500 | * hardware about the new command. |
431b2a20 | 501 | */ |
815b33fd | 502 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 503 | { |
ac0ea6e9 | 504 | u32 left, tail, head, next_tail; |
815b33fd | 505 | unsigned long flags; |
a19ae1ec | 506 | |
549c90dc | 507 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
508 | |
509 | again: | |
815b33fd | 510 | spin_lock_irqsave(&iommu->lock, flags); |
ac0ea6e9 JR |
511 | |
512 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
513 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
514 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
515 | left = (head - next_tail) % iommu->cmd_buf_size; | |
516 | ||
517 | if (left <= 2) { | |
518 | struct iommu_cmd sync_cmd; | |
519 | volatile u64 sem = 0; | |
520 | int ret; | |
521 | ||
522 | build_completion_wait(&sync_cmd, (u64)&sem); | |
523 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
524 | ||
525 | spin_unlock_irqrestore(&iommu->lock, flags); | |
526 | ||
527 | if ((ret = wait_on_sem(&sem)) != 0) | |
528 | return ret; | |
529 | ||
530 | goto again; | |
531 | } | |
532 | ||
533 | copy_cmd_to_buffer(iommu, cmd, tail); | |
534 | ||
535 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 536 | iommu->need_sync = true; |
ac0ea6e9 | 537 | |
a19ae1ec JR |
538 | spin_unlock_irqrestore(&iommu->lock, flags); |
539 | ||
815b33fd | 540 | return 0; |
8d201968 JR |
541 | } |
542 | ||
543 | /* | |
544 | * This function queues a completion wait command into the command | |
545 | * buffer of an IOMMU | |
546 | */ | |
a19ae1ec JR |
547 | static int iommu_completion_wait(struct amd_iommu *iommu) |
548 | { | |
815b33fd JR |
549 | struct iommu_cmd cmd; |
550 | volatile u64 sem = 0; | |
ac0ea6e9 | 551 | int ret; |
7e4f88da | 552 | |
09ee17eb | 553 | if (!iommu->need_sync) |
815b33fd | 554 | return 0; |
09ee17eb | 555 | |
815b33fd | 556 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 557 | |
815b33fd | 558 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 559 | if (ret) |
815b33fd | 560 | return ret; |
84df8175 | 561 | |
ac0ea6e9 | 562 | return wait_on_sem(&sem); |
a19ae1ec JR |
563 | } |
564 | ||
d8c13085 JR |
565 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
566 | { | |
567 | struct iommu_cmd cmd; | |
568 | ||
569 | build_inv_dte(&cmd, devid); | |
570 | ||
571 | return iommu_queue_command(iommu, &cmd); | |
572 | } | |
573 | ||
7d0c5cc5 JR |
574 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
575 | { | |
576 | u32 devid; | |
577 | ||
578 | for (devid = 0; devid <= 0xffff; ++devid) | |
579 | iommu_flush_dte(iommu, devid); | |
580 | ||
581 | iommu_completion_wait(iommu); | |
582 | } | |
583 | ||
584 | /* | |
585 | * This function uses heavy locking and may disable irqs for some time. But | |
586 | * this is no issue because it is only called during resume. | |
587 | */ | |
588 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
589 | { | |
590 | u32 dom_id; | |
591 | ||
592 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { | |
593 | struct iommu_cmd cmd; | |
594 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
595 | dom_id, 1); | |
596 | iommu_queue_command(iommu, &cmd); | |
597 | } | |
598 | ||
599 | iommu_completion_wait(iommu); | |
600 | } | |
601 | ||
602 | void iommu_flush_all_caches(struct amd_iommu *iommu) | |
603 | { | |
604 | iommu_flush_dte_all(iommu); | |
605 | iommu_flush_tlb_all(iommu); | |
606 | } | |
607 | ||
cb41ed85 JR |
608 | /* |
609 | * Command send function for flushing on-device TLB | |
610 | */ | |
611 | static int device_flush_iotlb(struct device *dev, u64 address, size_t size) | |
612 | { | |
613 | struct pci_dev *pdev = to_pci_dev(dev); | |
614 | struct amd_iommu *iommu; | |
615 | struct iommu_cmd cmd; | |
616 | u16 devid; | |
617 | int qdep; | |
618 | ||
619 | qdep = pci_ats_queue_depth(pdev); | |
620 | devid = get_device_id(dev); | |
621 | iommu = amd_iommu_rlookup_table[devid]; | |
622 | ||
623 | build_inv_iotlb_pages(&cmd, devid, qdep, address, size); | |
624 | ||
625 | return iommu_queue_command(iommu, &cmd); | |
626 | } | |
627 | ||
431b2a20 JR |
628 | /* |
629 | * Command send function for invalidating a device table entry | |
630 | */ | |
d8c13085 | 631 | static int device_flush_dte(struct device *dev) |
3fa43655 JR |
632 | { |
633 | struct amd_iommu *iommu; | |
cb41ed85 | 634 | struct pci_dev *pdev; |
3fa43655 | 635 | u16 devid; |
cb41ed85 | 636 | int ret; |
3fa43655 | 637 | |
cb41ed85 | 638 | pdev = to_pci_dev(dev); |
3fa43655 JR |
639 | devid = get_device_id(dev); |
640 | iommu = amd_iommu_rlookup_table[devid]; | |
641 | ||
cb41ed85 JR |
642 | ret = iommu_flush_dte(iommu, devid); |
643 | if (ret) | |
644 | return ret; | |
645 | ||
646 | if (pci_ats_enabled(pdev)) | |
647 | ret = device_flush_iotlb(dev, 0, ~0UL); | |
648 | ||
649 | return ret; | |
3fa43655 JR |
650 | } |
651 | ||
431b2a20 JR |
652 | /* |
653 | * TLB invalidation function which is called from the mapping functions. | |
654 | * It invalidates a single PTE if the range to flush is within a single | |
655 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
656 | */ | |
17b124bf JR |
657 | static void __domain_flush_pages(struct protection_domain *domain, |
658 | u64 address, size_t size, int pde) | |
a19ae1ec | 659 | { |
cb41ed85 | 660 | struct iommu_dev_data *dev_data; |
11b6402c JR |
661 | struct iommu_cmd cmd; |
662 | int ret = 0, i; | |
a19ae1ec | 663 | |
11b6402c | 664 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 665 | |
6de8ad9b JR |
666 | for (i = 0; i < amd_iommus_present; ++i) { |
667 | if (!domain->dev_iommu[i]) | |
668 | continue; | |
669 | ||
670 | /* | |
671 | * Devices of this domain are behind this IOMMU | |
672 | * We need a TLB flush | |
673 | */ | |
11b6402c | 674 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
675 | } |
676 | ||
cb41ed85 JR |
677 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
678 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); | |
679 | ||
680 | if (!pci_ats_enabled(pdev)) | |
681 | continue; | |
682 | ||
683 | ret |= device_flush_iotlb(dev_data->dev, address, size); | |
684 | } | |
685 | ||
11b6402c | 686 | WARN_ON(ret); |
6de8ad9b JR |
687 | } |
688 | ||
17b124bf JR |
689 | static void domain_flush_pages(struct protection_domain *domain, |
690 | u64 address, size_t size) | |
6de8ad9b | 691 | { |
17b124bf | 692 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 693 | } |
b6c02715 | 694 | |
1c655773 | 695 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 696 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 697 | { |
17b124bf | 698 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
699 | } |
700 | ||
42a49f96 | 701 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 702 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 703 | { |
17b124bf JR |
704 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
705 | } | |
706 | ||
707 | static void domain_flush_complete(struct protection_domain *domain) | |
708 | { | |
709 | int i; | |
710 | ||
711 | for (i = 0; i < amd_iommus_present; ++i) { | |
712 | if (!domain->dev_iommu[i]) | |
713 | continue; | |
714 | ||
715 | /* | |
716 | * Devices of this domain are behind this IOMMU | |
717 | * We need to wait for completion of all commands. | |
718 | */ | |
719 | iommu_completion_wait(amd_iommus[i]); | |
720 | } | |
42a49f96 CW |
721 | } |
722 | ||
b00d3bcf | 723 | |
43f49609 | 724 | /* |
b00d3bcf | 725 | * This function flushes the DTEs for all devices in domain |
43f49609 | 726 | */ |
17b124bf | 727 | static void domain_flush_devices(struct protection_domain *domain) |
b00d3bcf JR |
728 | { |
729 | struct iommu_dev_data *dev_data; | |
730 | unsigned long flags; | |
731 | ||
732 | spin_lock_irqsave(&domain->lock, flags); | |
733 | ||
734 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
d8c13085 | 735 | device_flush_dte(dev_data->dev); |
b00d3bcf JR |
736 | |
737 | spin_unlock_irqrestore(&domain->lock, flags); | |
738 | } | |
739 | ||
431b2a20 JR |
740 | /**************************************************************************** |
741 | * | |
742 | * The functions below are used the create the page table mappings for | |
743 | * unity mapped regions. | |
744 | * | |
745 | ****************************************************************************/ | |
746 | ||
308973d3 JR |
747 | /* |
748 | * This function is used to add another level to an IO page table. Adding | |
749 | * another level increases the size of the address space by 9 bits to a size up | |
750 | * to 64 bits. | |
751 | */ | |
752 | static bool increase_address_space(struct protection_domain *domain, | |
753 | gfp_t gfp) | |
754 | { | |
755 | u64 *pte; | |
756 | ||
757 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
758 | /* address space already 64 bit large */ | |
759 | return false; | |
760 | ||
761 | pte = (void *)get_zeroed_page(gfp); | |
762 | if (!pte) | |
763 | return false; | |
764 | ||
765 | *pte = PM_LEVEL_PDE(domain->mode, | |
766 | virt_to_phys(domain->pt_root)); | |
767 | domain->pt_root = pte; | |
768 | domain->mode += 1; | |
769 | domain->updated = true; | |
770 | ||
771 | return true; | |
772 | } | |
773 | ||
774 | static u64 *alloc_pte(struct protection_domain *domain, | |
775 | unsigned long address, | |
cbb9d729 | 776 | unsigned long page_size, |
308973d3 JR |
777 | u64 **pte_page, |
778 | gfp_t gfp) | |
779 | { | |
cbb9d729 | 780 | int level, end_lvl; |
308973d3 | 781 | u64 *pte, *page; |
cbb9d729 JR |
782 | |
783 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
784 | |
785 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
786 | increase_address_space(domain, gfp); | |
787 | ||
cbb9d729 JR |
788 | level = domain->mode - 1; |
789 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
790 | address = PAGE_SIZE_ALIGN(address, page_size); | |
791 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
792 | |
793 | while (level > end_lvl) { | |
794 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
795 | page = (u64 *)get_zeroed_page(gfp); | |
796 | if (!page) | |
797 | return NULL; | |
798 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
799 | } | |
800 | ||
cbb9d729 JR |
801 | /* No level skipping support yet */ |
802 | if (PM_PTE_LEVEL(*pte) != level) | |
803 | return NULL; | |
804 | ||
308973d3 JR |
805 | level -= 1; |
806 | ||
807 | pte = IOMMU_PTE_PAGE(*pte); | |
808 | ||
809 | if (pte_page && level == end_lvl) | |
810 | *pte_page = pte; | |
811 | ||
812 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
813 | } | |
814 | ||
815 | return pte; | |
816 | } | |
817 | ||
818 | /* | |
819 | * This function checks if there is a PTE for a given dma address. If | |
820 | * there is one, it returns the pointer to it. | |
821 | */ | |
24cd7723 | 822 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
823 | { |
824 | int level; | |
825 | u64 *pte; | |
826 | ||
24cd7723 JR |
827 | if (address > PM_LEVEL_SIZE(domain->mode)) |
828 | return NULL; | |
829 | ||
830 | level = domain->mode - 1; | |
831 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 832 | |
24cd7723 JR |
833 | while (level > 0) { |
834 | ||
835 | /* Not Present */ | |
308973d3 JR |
836 | if (!IOMMU_PTE_PRESENT(*pte)) |
837 | return NULL; | |
838 | ||
24cd7723 JR |
839 | /* Large PTE */ |
840 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
841 | unsigned long pte_mask, __pte; | |
842 | ||
843 | /* | |
844 | * If we have a series of large PTEs, make | |
845 | * sure to return a pointer to the first one. | |
846 | */ | |
847 | pte_mask = PTE_PAGE_SIZE(*pte); | |
848 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
849 | __pte = ((unsigned long)pte) & pte_mask; | |
850 | ||
851 | return (u64 *)__pte; | |
852 | } | |
853 | ||
854 | /* No level skipping support yet */ | |
855 | if (PM_PTE_LEVEL(*pte) != level) | |
856 | return NULL; | |
857 | ||
308973d3 JR |
858 | level -= 1; |
859 | ||
24cd7723 | 860 | /* Walk to the next level */ |
308973d3 JR |
861 | pte = IOMMU_PTE_PAGE(*pte); |
862 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
863 | } |
864 | ||
865 | return pte; | |
866 | } | |
867 | ||
431b2a20 JR |
868 | /* |
869 | * Generic mapping functions. It maps a physical address into a DMA | |
870 | * address space. It allocates the page table pages if necessary. | |
871 | * In the future it can be extended to a generic mapping function | |
872 | * supporting all features of AMD IOMMU page tables like level skipping | |
873 | * and full 64 bit address spaces. | |
874 | */ | |
38e817fe JR |
875 | static int iommu_map_page(struct protection_domain *dom, |
876 | unsigned long bus_addr, | |
877 | unsigned long phys_addr, | |
abdc5eb3 | 878 | int prot, |
cbb9d729 | 879 | unsigned long page_size) |
bd0e5211 | 880 | { |
8bda3092 | 881 | u64 __pte, *pte; |
cbb9d729 | 882 | int i, count; |
abdc5eb3 | 883 | |
bad1cac2 | 884 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
885 | return -EINVAL; |
886 | ||
cbb9d729 JR |
887 | bus_addr = PAGE_ALIGN(bus_addr); |
888 | phys_addr = PAGE_ALIGN(phys_addr); | |
889 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
890 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
891 | ||
892 | for (i = 0; i < count; ++i) | |
893 | if (IOMMU_PTE_PRESENT(pte[i])) | |
894 | return -EBUSY; | |
bd0e5211 | 895 | |
cbb9d729 JR |
896 | if (page_size > PAGE_SIZE) { |
897 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
898 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
899 | } else | |
900 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 901 | |
bd0e5211 JR |
902 | if (prot & IOMMU_PROT_IR) |
903 | __pte |= IOMMU_PTE_IR; | |
904 | if (prot & IOMMU_PROT_IW) | |
905 | __pte |= IOMMU_PTE_IW; | |
906 | ||
cbb9d729 JR |
907 | for (i = 0; i < count; ++i) |
908 | pte[i] = __pte; | |
bd0e5211 | 909 | |
04bfdd84 JR |
910 | update_domain(dom); |
911 | ||
bd0e5211 JR |
912 | return 0; |
913 | } | |
914 | ||
24cd7723 JR |
915 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
916 | unsigned long bus_addr, | |
917 | unsigned long page_size) | |
eb74ff6c | 918 | { |
24cd7723 JR |
919 | unsigned long long unmap_size, unmapped; |
920 | u64 *pte; | |
921 | ||
922 | BUG_ON(!is_power_of_2(page_size)); | |
923 | ||
924 | unmapped = 0; | |
eb74ff6c | 925 | |
24cd7723 JR |
926 | while (unmapped < page_size) { |
927 | ||
928 | pte = fetch_pte(dom, bus_addr); | |
929 | ||
930 | if (!pte) { | |
931 | /* | |
932 | * No PTE for this address | |
933 | * move forward in 4kb steps | |
934 | */ | |
935 | unmap_size = PAGE_SIZE; | |
936 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
937 | /* 4kb PTE found for this address */ | |
938 | unmap_size = PAGE_SIZE; | |
939 | *pte = 0ULL; | |
940 | } else { | |
941 | int count, i; | |
942 | ||
943 | /* Large PTE found which maps this address */ | |
944 | unmap_size = PTE_PAGE_SIZE(*pte); | |
945 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
946 | for (i = 0; i < count; i++) | |
947 | pte[i] = 0ULL; | |
948 | } | |
949 | ||
950 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
951 | unmapped += unmap_size; | |
952 | } | |
953 | ||
954 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 955 | |
24cd7723 | 956 | return unmapped; |
eb74ff6c | 957 | } |
eb74ff6c | 958 | |
431b2a20 JR |
959 | /* |
960 | * This function checks if a specific unity mapping entry is needed for | |
961 | * this specific IOMMU. | |
962 | */ | |
bd0e5211 JR |
963 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
964 | struct unity_map_entry *entry) | |
965 | { | |
966 | u16 bdf, i; | |
967 | ||
968 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
969 | bdf = amd_iommu_alias_table[i]; | |
970 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
971 | return 1; | |
972 | } | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
431b2a20 JR |
977 | /* |
978 | * This function actually applies the mapping to the page table of the | |
979 | * dma_ops domain. | |
980 | */ | |
bd0e5211 JR |
981 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
982 | struct unity_map_entry *e) | |
983 | { | |
984 | u64 addr; | |
985 | int ret; | |
986 | ||
987 | for (addr = e->address_start; addr < e->address_end; | |
988 | addr += PAGE_SIZE) { | |
abdc5eb3 | 989 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 990 | PAGE_SIZE); |
bd0e5211 JR |
991 | if (ret) |
992 | return ret; | |
993 | /* | |
994 | * if unity mapping is in aperture range mark the page | |
995 | * as allocated in the aperture | |
996 | */ | |
997 | if (addr < dma_dom->aperture_size) | |
c3239567 | 998 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 999 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1000 | } |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
171e7b37 JR |
1005 | /* |
1006 | * Init the unity mappings for a specific IOMMU in the system | |
1007 | * | |
1008 | * Basically iterates over all unity mapping entries and applies them to | |
1009 | * the default domain DMA of that IOMMU if necessary. | |
1010 | */ | |
1011 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1012 | { | |
1013 | struct unity_map_entry *entry; | |
1014 | int ret; | |
1015 | ||
1016 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1017 | if (!iommu_for_unity_map(iommu, entry)) | |
1018 | continue; | |
1019 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1020 | if (ret) | |
1021 | return ret; | |
1022 | } | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
431b2a20 JR |
1027 | /* |
1028 | * Inits the unity mappings required for a specific device | |
1029 | */ | |
bd0e5211 JR |
1030 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1031 | u16 devid) | |
1032 | { | |
1033 | struct unity_map_entry *e; | |
1034 | int ret; | |
1035 | ||
1036 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1037 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1038 | continue; | |
1039 | ret = dma_ops_unity_map(dma_dom, e); | |
1040 | if (ret) | |
1041 | return ret; | |
1042 | } | |
1043 | ||
1044 | return 0; | |
1045 | } | |
1046 | ||
431b2a20 JR |
1047 | /**************************************************************************** |
1048 | * | |
1049 | * The next functions belong to the address allocator for the dma_ops | |
1050 | * interface functions. They work like the allocators in the other IOMMU | |
1051 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1052 | * the aperture. Maybe it could be enhanced in the future to a more | |
1053 | * efficient allocator. | |
1054 | * | |
1055 | ****************************************************************************/ | |
d3086444 | 1056 | |
431b2a20 | 1057 | /* |
384de729 | 1058 | * The address allocator core functions. |
431b2a20 JR |
1059 | * |
1060 | * called with domain->lock held | |
1061 | */ | |
384de729 | 1062 | |
171e7b37 JR |
1063 | /* |
1064 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1065 | * ranges. | |
1066 | */ | |
1067 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1068 | unsigned long start_page, | |
1069 | unsigned int pages) | |
1070 | { | |
1071 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1072 | ||
1073 | if (start_page + pages > last_page) | |
1074 | pages = last_page - start_page; | |
1075 | ||
1076 | for (i = start_page; i < start_page + pages; ++i) { | |
1077 | int index = i / APERTURE_RANGE_PAGES; | |
1078 | int page = i % APERTURE_RANGE_PAGES; | |
1079 | __set_bit(page, dom->aperture[index]->bitmap); | |
1080 | } | |
1081 | } | |
1082 | ||
9cabe89b JR |
1083 | /* |
1084 | * This function is used to add a new aperture range to an existing | |
1085 | * aperture in case of dma_ops domain allocation or address allocation | |
1086 | * failure. | |
1087 | */ | |
576175c2 | 1088 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1089 | bool populate, gfp_t gfp) |
1090 | { | |
1091 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1092 | struct amd_iommu *iommu; |
d91afd15 | 1093 | unsigned long i; |
9cabe89b | 1094 | |
f5e9705c JR |
1095 | #ifdef CONFIG_IOMMU_STRESS |
1096 | populate = false; | |
1097 | #endif | |
1098 | ||
9cabe89b JR |
1099 | if (index >= APERTURE_MAX_RANGES) |
1100 | return -ENOMEM; | |
1101 | ||
1102 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1103 | if (!dma_dom->aperture[index]) | |
1104 | return -ENOMEM; | |
1105 | ||
1106 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1107 | if (!dma_dom->aperture[index]->bitmap) | |
1108 | goto out_free; | |
1109 | ||
1110 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1111 | ||
1112 | if (populate) { | |
1113 | unsigned long address = dma_dom->aperture_size; | |
1114 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1115 | u64 *pte, *pte_page; | |
1116 | ||
1117 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1118 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1119 | &pte_page, gfp); |
1120 | if (!pte) | |
1121 | goto out_free; | |
1122 | ||
1123 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1124 | ||
1125 | address += APERTURE_RANGE_SIZE / 64; | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1130 | ||
b595076a | 1131 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1132 | for_each_iommu(iommu) { |
1133 | if (iommu->exclusion_start && | |
1134 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1135 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1136 | unsigned long startpage; | |
1137 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1138 | iommu->exclusion_length, | |
1139 | PAGE_SIZE); | |
1140 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1141 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1142 | } | |
00cd122a JR |
1143 | } |
1144 | ||
1145 | /* | |
1146 | * Check for areas already mapped as present in the new aperture | |
1147 | * range and mark those pages as reserved in the allocator. Such | |
1148 | * mappings may already exist as a result of requested unity | |
1149 | * mappings for devices. | |
1150 | */ | |
1151 | for (i = dma_dom->aperture[index]->offset; | |
1152 | i < dma_dom->aperture_size; | |
1153 | i += PAGE_SIZE) { | |
24cd7723 | 1154 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1155 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1156 | continue; | |
1157 | ||
1158 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1159 | } | |
1160 | ||
04bfdd84 JR |
1161 | update_domain(&dma_dom->domain); |
1162 | ||
9cabe89b JR |
1163 | return 0; |
1164 | ||
1165 | out_free: | |
04bfdd84 JR |
1166 | update_domain(&dma_dom->domain); |
1167 | ||
9cabe89b JR |
1168 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1169 | ||
1170 | kfree(dma_dom->aperture[index]); | |
1171 | dma_dom->aperture[index] = NULL; | |
1172 | ||
1173 | return -ENOMEM; | |
1174 | } | |
1175 | ||
384de729 JR |
1176 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1177 | struct dma_ops_domain *dom, | |
1178 | unsigned int pages, | |
1179 | unsigned long align_mask, | |
1180 | u64 dma_mask, | |
1181 | unsigned long start) | |
1182 | { | |
803b8cb4 | 1183 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1184 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1185 | int i = start >> APERTURE_RANGE_SHIFT; | |
1186 | unsigned long boundary_size; | |
1187 | unsigned long address = -1; | |
1188 | unsigned long limit; | |
1189 | ||
803b8cb4 JR |
1190 | next_bit >>= PAGE_SHIFT; |
1191 | ||
384de729 JR |
1192 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1193 | PAGE_SIZE) >> PAGE_SHIFT; | |
1194 | ||
1195 | for (;i < max_index; ++i) { | |
1196 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1197 | ||
1198 | if (dom->aperture[i]->offset >= dma_mask) | |
1199 | break; | |
1200 | ||
1201 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1202 | dma_mask >> PAGE_SHIFT); | |
1203 | ||
1204 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1205 | limit, next_bit, pages, 0, | |
1206 | boundary_size, align_mask); | |
1207 | if (address != -1) { | |
1208 | address = dom->aperture[i]->offset + | |
1209 | (address << PAGE_SHIFT); | |
803b8cb4 | 1210 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1211 | break; |
1212 | } | |
1213 | ||
1214 | next_bit = 0; | |
1215 | } | |
1216 | ||
1217 | return address; | |
1218 | } | |
1219 | ||
d3086444 JR |
1220 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1221 | struct dma_ops_domain *dom, | |
6d4f343f | 1222 | unsigned int pages, |
832a90c3 JR |
1223 | unsigned long align_mask, |
1224 | u64 dma_mask) | |
d3086444 | 1225 | { |
d3086444 | 1226 | unsigned long address; |
d3086444 | 1227 | |
fe16f088 JR |
1228 | #ifdef CONFIG_IOMMU_STRESS |
1229 | dom->next_address = 0; | |
1230 | dom->need_flush = true; | |
1231 | #endif | |
d3086444 | 1232 | |
384de729 | 1233 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1234 | dma_mask, dom->next_address); |
d3086444 | 1235 | |
1c655773 | 1236 | if (address == -1) { |
803b8cb4 | 1237 | dom->next_address = 0; |
384de729 JR |
1238 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1239 | dma_mask, 0); | |
1c655773 JR |
1240 | dom->need_flush = true; |
1241 | } | |
d3086444 | 1242 | |
384de729 | 1243 | if (unlikely(address == -1)) |
8fd524b3 | 1244 | address = DMA_ERROR_CODE; |
d3086444 JR |
1245 | |
1246 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1247 | ||
1248 | return address; | |
1249 | } | |
1250 | ||
431b2a20 JR |
1251 | /* |
1252 | * The address free function. | |
1253 | * | |
1254 | * called with domain->lock held | |
1255 | */ | |
d3086444 JR |
1256 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1257 | unsigned long address, | |
1258 | unsigned int pages) | |
1259 | { | |
384de729 JR |
1260 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1261 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1262 | |
384de729 JR |
1263 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1264 | ||
47bccd6b JR |
1265 | #ifdef CONFIG_IOMMU_STRESS |
1266 | if (i < 4) | |
1267 | return; | |
1268 | #endif | |
80be308d | 1269 | |
803b8cb4 | 1270 | if (address >= dom->next_address) |
80be308d | 1271 | dom->need_flush = true; |
384de729 JR |
1272 | |
1273 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1274 | |
a66022c4 | 1275 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1276 | |
d3086444 JR |
1277 | } |
1278 | ||
431b2a20 JR |
1279 | /**************************************************************************** |
1280 | * | |
1281 | * The next functions belong to the domain allocation. A domain is | |
1282 | * allocated for every IOMMU as the default domain. If device isolation | |
1283 | * is enabled, every device get its own domain. The most important thing | |
1284 | * about domains is the page table mapping the DMA address space they | |
1285 | * contain. | |
1286 | * | |
1287 | ****************************************************************************/ | |
1288 | ||
aeb26f55 JR |
1289 | /* |
1290 | * This function adds a protection domain to the global protection domain list | |
1291 | */ | |
1292 | static void add_domain_to_list(struct protection_domain *domain) | |
1293 | { | |
1294 | unsigned long flags; | |
1295 | ||
1296 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1297 | list_add(&domain->list, &amd_iommu_pd_list); | |
1298 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1299 | } | |
1300 | ||
1301 | /* | |
1302 | * This function removes a protection domain to the global | |
1303 | * protection domain list | |
1304 | */ | |
1305 | static void del_domain_from_list(struct protection_domain *domain) | |
1306 | { | |
1307 | unsigned long flags; | |
1308 | ||
1309 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1310 | list_del(&domain->list); | |
1311 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1312 | } | |
1313 | ||
ec487d1a JR |
1314 | static u16 domain_id_alloc(void) |
1315 | { | |
1316 | unsigned long flags; | |
1317 | int id; | |
1318 | ||
1319 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1320 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1321 | BUG_ON(id == 0); | |
1322 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1323 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1324 | else | |
1325 | id = 0; | |
1326 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1327 | ||
1328 | return id; | |
1329 | } | |
1330 | ||
a2acfb75 JR |
1331 | static void domain_id_free(int id) |
1332 | { | |
1333 | unsigned long flags; | |
1334 | ||
1335 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1336 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1337 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1338 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1339 | } | |
a2acfb75 | 1340 | |
86db2e5d | 1341 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1342 | { |
1343 | int i, j; | |
1344 | u64 *p1, *p2, *p3; | |
1345 | ||
86db2e5d | 1346 | p1 = domain->pt_root; |
ec487d1a JR |
1347 | |
1348 | if (!p1) | |
1349 | return; | |
1350 | ||
1351 | for (i = 0; i < 512; ++i) { | |
1352 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1353 | continue; | |
1354 | ||
1355 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1356 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1357 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1358 | continue; | |
1359 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1360 | free_page((unsigned long)p3); | |
1361 | } | |
1362 | ||
1363 | free_page((unsigned long)p2); | |
1364 | } | |
1365 | ||
1366 | free_page((unsigned long)p1); | |
86db2e5d JR |
1367 | |
1368 | domain->pt_root = NULL; | |
ec487d1a JR |
1369 | } |
1370 | ||
431b2a20 JR |
1371 | /* |
1372 | * Free a domain, only used if something went wrong in the | |
1373 | * allocation path and we need to free an already allocated page table | |
1374 | */ | |
ec487d1a JR |
1375 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1376 | { | |
384de729 JR |
1377 | int i; |
1378 | ||
ec487d1a JR |
1379 | if (!dom) |
1380 | return; | |
1381 | ||
aeb26f55 JR |
1382 | del_domain_from_list(&dom->domain); |
1383 | ||
86db2e5d | 1384 | free_pagetable(&dom->domain); |
ec487d1a | 1385 | |
384de729 JR |
1386 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1387 | if (!dom->aperture[i]) | |
1388 | continue; | |
1389 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1390 | kfree(dom->aperture[i]); | |
1391 | } | |
ec487d1a JR |
1392 | |
1393 | kfree(dom); | |
1394 | } | |
1395 | ||
431b2a20 JR |
1396 | /* |
1397 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1398 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1399 | * structures required for the dma_ops interface |
1400 | */ | |
87a64d52 | 1401 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1402 | { |
1403 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1404 | |
1405 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1406 | if (!dma_dom) | |
1407 | return NULL; | |
1408 | ||
1409 | spin_lock_init(&dma_dom->domain.lock); | |
1410 | ||
1411 | dma_dom->domain.id = domain_id_alloc(); | |
1412 | if (dma_dom->domain.id == 0) | |
1413 | goto free_dma_dom; | |
7c392cbe | 1414 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1415 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1416 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1417 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1418 | dma_dom->domain.priv = dma_dom; |
1419 | if (!dma_dom->domain.pt_root) | |
1420 | goto free_dma_dom; | |
ec487d1a | 1421 | |
1c655773 | 1422 | dma_dom->need_flush = false; |
bd60b735 | 1423 | dma_dom->target_dev = 0xffff; |
1c655773 | 1424 | |
aeb26f55 JR |
1425 | add_domain_to_list(&dma_dom->domain); |
1426 | ||
576175c2 | 1427 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1428 | goto free_dma_dom; |
ec487d1a | 1429 | |
431b2a20 | 1430 | /* |
ec487d1a JR |
1431 | * mark the first page as allocated so we never return 0 as |
1432 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1433 | */ |
384de729 | 1434 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1435 | dma_dom->next_address = 0; |
ec487d1a | 1436 | |
ec487d1a JR |
1437 | |
1438 | return dma_dom; | |
1439 | ||
1440 | free_dma_dom: | |
1441 | dma_ops_domain_free(dma_dom); | |
1442 | ||
1443 | return NULL; | |
1444 | } | |
1445 | ||
5b28df6f JR |
1446 | /* |
1447 | * little helper function to check whether a given protection domain is a | |
1448 | * dma_ops domain | |
1449 | */ | |
1450 | static bool dma_ops_domain(struct protection_domain *domain) | |
1451 | { | |
1452 | return domain->flags & PD_DMA_OPS_MASK; | |
1453 | } | |
1454 | ||
407d733e | 1455 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1456 | { |
b20ac0d4 | 1457 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1458 | |
38ddf41b JR |
1459 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1460 | << DEV_ENTRY_MODE_SHIFT; | |
1461 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1462 | |
b20ac0d4 | 1463 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1464 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1465 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1466 | } |
1467 | ||
1468 | static void clear_dte_entry(u16 devid) | |
1469 | { | |
15898bbc JR |
1470 | /* remove entry from the device table seen by the hardware */ |
1471 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1472 | amd_iommu_dev_table[devid].data[1] = 0; | |
1473 | amd_iommu_dev_table[devid].data[2] = 0; | |
1474 | ||
1475 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1476 | } |
1477 | ||
1478 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1479 | { | |
1480 | struct iommu_dev_data *dev_data; | |
1481 | struct amd_iommu *iommu; | |
1482 | u16 devid; | |
1483 | ||
1484 | devid = get_device_id(dev); | |
1485 | iommu = amd_iommu_rlookup_table[devid]; | |
1486 | dev_data = get_dev_data(dev); | |
1487 | ||
1488 | /* Update data structures */ | |
1489 | dev_data->domain = domain; | |
1490 | list_add(&dev_data->list, &domain->dev_list); | |
1491 | set_dte_entry(devid, domain); | |
1492 | ||
1493 | /* Do reference counting */ | |
1494 | domain->dev_iommu[iommu->index] += 1; | |
1495 | domain->dev_cnt += 1; | |
1496 | ||
1497 | /* Flush the DTE entry */ | |
d8c13085 | 1498 | device_flush_dte(dev); |
7f760ddd JR |
1499 | } |
1500 | ||
1501 | static void do_detach(struct device *dev) | |
1502 | { | |
1503 | struct iommu_dev_data *dev_data; | |
1504 | struct amd_iommu *iommu; | |
1505 | u16 devid; | |
1506 | ||
1507 | devid = get_device_id(dev); | |
1508 | iommu = amd_iommu_rlookup_table[devid]; | |
1509 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1510 | |
1511 | /* decrease reference counters */ | |
7f760ddd JR |
1512 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1513 | dev_data->domain->dev_cnt -= 1; | |
1514 | ||
1515 | /* Update data structures */ | |
1516 | dev_data->domain = NULL; | |
1517 | list_del(&dev_data->list); | |
1518 | clear_dte_entry(devid); | |
15898bbc | 1519 | |
7f760ddd | 1520 | /* Flush the DTE entry */ |
d8c13085 | 1521 | device_flush_dte(dev); |
2b681faf JR |
1522 | } |
1523 | ||
1524 | /* | |
1525 | * If a device is not yet associated with a domain, this function does | |
1526 | * assigns it visible for the hardware | |
1527 | */ | |
15898bbc JR |
1528 | static int __attach_device(struct device *dev, |
1529 | struct protection_domain *domain) | |
2b681faf | 1530 | { |
657cbb6b | 1531 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1532 | int ret; |
657cbb6b | 1533 | |
657cbb6b JR |
1534 | dev_data = get_dev_data(dev); |
1535 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1536 | |
657cbb6b JR |
1537 | if (!alias_data) |
1538 | return -EINVAL; | |
15898bbc | 1539 | |
2b681faf JR |
1540 | /* lock domain */ |
1541 | spin_lock(&domain->lock); | |
1542 | ||
15898bbc | 1543 | /* Some sanity checks */ |
84fe6c19 | 1544 | ret = -EBUSY; |
657cbb6b JR |
1545 | if (alias_data->domain != NULL && |
1546 | alias_data->domain != domain) | |
84fe6c19 | 1547 | goto out_unlock; |
eba6ac60 | 1548 | |
657cbb6b JR |
1549 | if (dev_data->domain != NULL && |
1550 | dev_data->domain != domain) | |
84fe6c19 | 1551 | goto out_unlock; |
15898bbc JR |
1552 | |
1553 | /* Do real assignment */ | |
7f760ddd JR |
1554 | if (dev_data->alias != dev) { |
1555 | alias_data = get_dev_data(dev_data->alias); | |
1556 | if (alias_data->domain == NULL) | |
1557 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1558 | |
1559 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1560 | } |
15898bbc | 1561 | |
7f760ddd JR |
1562 | if (dev_data->domain == NULL) |
1563 | do_attach(dev, domain); | |
eba6ac60 | 1564 | |
24100055 JR |
1565 | atomic_inc(&dev_data->bind); |
1566 | ||
84fe6c19 JL |
1567 | ret = 0; |
1568 | ||
1569 | out_unlock: | |
1570 | ||
eba6ac60 JR |
1571 | /* ready */ |
1572 | spin_unlock(&domain->lock); | |
15898bbc | 1573 | |
84fe6c19 | 1574 | return ret; |
0feae533 | 1575 | } |
b20ac0d4 | 1576 | |
407d733e JR |
1577 | /* |
1578 | * If a device is not yet associated with a domain, this function does | |
1579 | * assigns it visible for the hardware | |
1580 | */ | |
15898bbc JR |
1581 | static int attach_device(struct device *dev, |
1582 | struct protection_domain *domain) | |
0feae533 | 1583 | { |
eba6ac60 | 1584 | unsigned long flags; |
15898bbc | 1585 | int ret; |
eba6ac60 JR |
1586 | |
1587 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1588 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1589 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1590 | ||
0feae533 JR |
1591 | /* |
1592 | * We might boot into a crash-kernel here. The crashed kernel | |
1593 | * left the caches in the IOMMU dirty. So we have to flush | |
1594 | * here to evict all dirty stuff. | |
1595 | */ | |
17b124bf | 1596 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1597 | |
1598 | return ret; | |
b20ac0d4 JR |
1599 | } |
1600 | ||
355bf553 JR |
1601 | /* |
1602 | * Removes a device from a protection domain (unlocked) | |
1603 | */ | |
15898bbc | 1604 | static void __detach_device(struct device *dev) |
355bf553 | 1605 | { |
657cbb6b | 1606 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1607 | struct iommu_dev_data *alias_data; |
2ca76279 | 1608 | struct protection_domain *domain; |
7c392cbe | 1609 | unsigned long flags; |
c4596114 | 1610 | |
7f760ddd | 1611 | BUG_ON(!dev_data->domain); |
355bf553 | 1612 | |
2ca76279 JR |
1613 | domain = dev_data->domain; |
1614 | ||
1615 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1616 | |
7f760ddd | 1617 | if (dev_data->alias != dev) { |
24100055 | 1618 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1619 | if (atomic_dec_and_test(&alias_data->bind)) |
1620 | do_detach(dev_data->alias); | |
24100055 JR |
1621 | } |
1622 | ||
7f760ddd JR |
1623 | if (atomic_dec_and_test(&dev_data->bind)) |
1624 | do_detach(dev); | |
1625 | ||
2ca76279 | 1626 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1627 | |
1628 | /* | |
1629 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1630 | * passthrough domain if it is detached from any other domain. |
1631 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1632 | */ |
d3ad9373 JR |
1633 | if (iommu_pass_through && |
1634 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1635 | __attach_device(dev, pt_domain); |
355bf553 JR |
1636 | } |
1637 | ||
1638 | /* | |
1639 | * Removes a device from a protection domain (with devtable_lock held) | |
1640 | */ | |
15898bbc | 1641 | static void detach_device(struct device *dev) |
355bf553 JR |
1642 | { |
1643 | unsigned long flags; | |
1644 | ||
1645 | /* lock device table */ | |
1646 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1647 | __detach_device(dev); |
355bf553 JR |
1648 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1649 | } | |
e275a2a0 | 1650 | |
15898bbc JR |
1651 | /* |
1652 | * Find out the protection domain structure for a given PCI device. This | |
1653 | * will give us the pointer to the page table root for example. | |
1654 | */ | |
1655 | static struct protection_domain *domain_for_device(struct device *dev) | |
1656 | { | |
1657 | struct protection_domain *dom; | |
657cbb6b | 1658 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1659 | unsigned long flags; |
1660 | u16 devid, alias; | |
1661 | ||
657cbb6b JR |
1662 | devid = get_device_id(dev); |
1663 | alias = amd_iommu_alias_table[devid]; | |
1664 | dev_data = get_dev_data(dev); | |
1665 | alias_data = get_dev_data(dev_data->alias); | |
1666 | if (!alias_data) | |
1667 | return NULL; | |
15898bbc JR |
1668 | |
1669 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1670 | dom = dev_data->domain; |
15898bbc | 1671 | if (dom == NULL && |
657cbb6b JR |
1672 | alias_data->domain != NULL) { |
1673 | __attach_device(dev, alias_data->domain); | |
1674 | dom = alias_data->domain; | |
15898bbc JR |
1675 | } |
1676 | ||
1677 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1678 | ||
1679 | return dom; | |
1680 | } | |
1681 | ||
e275a2a0 JR |
1682 | static int device_change_notifier(struct notifier_block *nb, |
1683 | unsigned long action, void *data) | |
1684 | { | |
1685 | struct device *dev = data; | |
98fc5a69 | 1686 | u16 devid; |
e275a2a0 JR |
1687 | struct protection_domain *domain; |
1688 | struct dma_ops_domain *dma_domain; | |
1689 | struct amd_iommu *iommu; | |
1ac4cbbc | 1690 | unsigned long flags; |
e275a2a0 | 1691 | |
98fc5a69 JR |
1692 | if (!check_device(dev)) |
1693 | return 0; | |
e275a2a0 | 1694 | |
98fc5a69 JR |
1695 | devid = get_device_id(dev); |
1696 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1697 | |
1698 | switch (action) { | |
c1eee67b | 1699 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1700 | |
1701 | domain = domain_for_device(dev); | |
1702 | ||
e275a2a0 JR |
1703 | if (!domain) |
1704 | goto out; | |
a1ca331c JR |
1705 | if (iommu_pass_through) |
1706 | break; | |
15898bbc | 1707 | detach_device(dev); |
1ac4cbbc JR |
1708 | break; |
1709 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1710 | |
1711 | iommu_init_device(dev); | |
1712 | ||
1713 | domain = domain_for_device(dev); | |
1714 | ||
1ac4cbbc JR |
1715 | /* allocate a protection domain if a device is added */ |
1716 | dma_domain = find_protection_domain(devid); | |
1717 | if (dma_domain) | |
1718 | goto out; | |
87a64d52 | 1719 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1720 | if (!dma_domain) |
1721 | goto out; | |
1722 | dma_domain->target_dev = devid; | |
1723 | ||
1724 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1725 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1726 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1727 | ||
e275a2a0 | 1728 | break; |
657cbb6b JR |
1729 | case BUS_NOTIFY_DEL_DEVICE: |
1730 | ||
1731 | iommu_uninit_device(dev); | |
1732 | ||
e275a2a0 JR |
1733 | default: |
1734 | goto out; | |
1735 | } | |
1736 | ||
d8c13085 | 1737 | device_flush_dte(dev); |
e275a2a0 JR |
1738 | iommu_completion_wait(iommu); |
1739 | ||
1740 | out: | |
1741 | return 0; | |
1742 | } | |
1743 | ||
b25ae679 | 1744 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1745 | .notifier_call = device_change_notifier, |
1746 | }; | |
355bf553 | 1747 | |
8638c491 JR |
1748 | void amd_iommu_init_notifier(void) |
1749 | { | |
1750 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1751 | } | |
1752 | ||
431b2a20 JR |
1753 | /***************************************************************************** |
1754 | * | |
1755 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1756 | * | |
1757 | *****************************************************************************/ | |
1758 | ||
1759 | /* | |
1760 | * In the dma_ops path we only have the struct device. This function | |
1761 | * finds the corresponding IOMMU, the protection domain and the | |
1762 | * requestor id for a given device. | |
1763 | * If the device is not yet associated with a domain this is also done | |
1764 | * in this function. | |
1765 | */ | |
94f6d190 | 1766 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1767 | { |
94f6d190 | 1768 | struct protection_domain *domain; |
b20ac0d4 | 1769 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1770 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1771 | |
f99c0f1c | 1772 | if (!check_device(dev)) |
94f6d190 | 1773 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1774 | |
94f6d190 JR |
1775 | domain = domain_for_device(dev); |
1776 | if (domain != NULL && !dma_ops_domain(domain)) | |
1777 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1778 | |
94f6d190 JR |
1779 | if (domain != NULL) |
1780 | return domain; | |
b20ac0d4 | 1781 | |
15898bbc | 1782 | /* Device not bount yet - bind it */ |
94f6d190 | 1783 | dma_dom = find_protection_domain(devid); |
15898bbc | 1784 | if (!dma_dom) |
94f6d190 JR |
1785 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1786 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1787 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1788 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1789 | |
94f6d190 | 1790 | return &dma_dom->domain; |
b20ac0d4 JR |
1791 | } |
1792 | ||
04bfdd84 JR |
1793 | static void update_device_table(struct protection_domain *domain) |
1794 | { | |
492667da | 1795 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1796 | |
492667da JR |
1797 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
1798 | u16 devid = get_device_id(dev_data->dev); | |
1799 | set_dte_entry(devid, domain); | |
04bfdd84 JR |
1800 | } |
1801 | } | |
1802 | ||
1803 | static void update_domain(struct protection_domain *domain) | |
1804 | { | |
1805 | if (!domain->updated) | |
1806 | return; | |
1807 | ||
1808 | update_device_table(domain); | |
17b124bf JR |
1809 | |
1810 | domain_flush_devices(domain); | |
1811 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1812 | |
1813 | domain->updated = false; | |
1814 | } | |
1815 | ||
8bda3092 JR |
1816 | /* |
1817 | * This function fetches the PTE for a given address in the aperture | |
1818 | */ | |
1819 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1820 | unsigned long address) | |
1821 | { | |
384de729 | 1822 | struct aperture_range *aperture; |
8bda3092 JR |
1823 | u64 *pte, *pte_page; |
1824 | ||
384de729 JR |
1825 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1826 | if (!aperture) | |
1827 | return NULL; | |
1828 | ||
1829 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1830 | if (!pte) { |
cbb9d729 | 1831 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1832 | GFP_ATOMIC); |
384de729 JR |
1833 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1834 | } else | |
8c8c143c | 1835 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1836 | |
04bfdd84 | 1837 | update_domain(&dom->domain); |
8bda3092 JR |
1838 | |
1839 | return pte; | |
1840 | } | |
1841 | ||
431b2a20 JR |
1842 | /* |
1843 | * This is the generic map function. It maps one 4kb page at paddr to | |
1844 | * the given address in the DMA address space for the domain. | |
1845 | */ | |
680525e0 | 1846 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1847 | unsigned long address, |
1848 | phys_addr_t paddr, | |
1849 | int direction) | |
1850 | { | |
1851 | u64 *pte, __pte; | |
1852 | ||
1853 | WARN_ON(address > dom->aperture_size); | |
1854 | ||
1855 | paddr &= PAGE_MASK; | |
1856 | ||
8bda3092 | 1857 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1858 | if (!pte) |
8fd524b3 | 1859 | return DMA_ERROR_CODE; |
cb76c322 JR |
1860 | |
1861 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1862 | ||
1863 | if (direction == DMA_TO_DEVICE) | |
1864 | __pte |= IOMMU_PTE_IR; | |
1865 | else if (direction == DMA_FROM_DEVICE) | |
1866 | __pte |= IOMMU_PTE_IW; | |
1867 | else if (direction == DMA_BIDIRECTIONAL) | |
1868 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1869 | ||
1870 | WARN_ON(*pte); | |
1871 | ||
1872 | *pte = __pte; | |
1873 | ||
1874 | return (dma_addr_t)address; | |
1875 | } | |
1876 | ||
431b2a20 JR |
1877 | /* |
1878 | * The generic unmapping function for on page in the DMA address space. | |
1879 | */ | |
680525e0 | 1880 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1881 | unsigned long address) |
1882 | { | |
384de729 | 1883 | struct aperture_range *aperture; |
cb76c322 JR |
1884 | u64 *pte; |
1885 | ||
1886 | if (address >= dom->aperture_size) | |
1887 | return; | |
1888 | ||
384de729 JR |
1889 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1890 | if (!aperture) | |
1891 | return; | |
1892 | ||
1893 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1894 | if (!pte) | |
1895 | return; | |
cb76c322 | 1896 | |
8c8c143c | 1897 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1898 | |
1899 | WARN_ON(!*pte); | |
1900 | ||
1901 | *pte = 0ULL; | |
1902 | } | |
1903 | ||
431b2a20 JR |
1904 | /* |
1905 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1906 | * contiguous memory region into DMA address space. It is used by all |
1907 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1908 | * Must be called with the domain lock held. |
1909 | */ | |
cb76c322 | 1910 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1911 | struct dma_ops_domain *dma_dom, |
1912 | phys_addr_t paddr, | |
1913 | size_t size, | |
6d4f343f | 1914 | int dir, |
832a90c3 JR |
1915 | bool align, |
1916 | u64 dma_mask) | |
cb76c322 JR |
1917 | { |
1918 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1919 | dma_addr_t address, start, ret; |
cb76c322 | 1920 | unsigned int pages; |
6d4f343f | 1921 | unsigned long align_mask = 0; |
cb76c322 JR |
1922 | int i; |
1923 | ||
e3c449f5 | 1924 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1925 | paddr &= PAGE_MASK; |
1926 | ||
8ecaf8f1 JR |
1927 | INC_STATS_COUNTER(total_map_requests); |
1928 | ||
c1858976 JR |
1929 | if (pages > 1) |
1930 | INC_STATS_COUNTER(cross_page); | |
1931 | ||
6d4f343f JR |
1932 | if (align) |
1933 | align_mask = (1UL << get_order(size)) - 1; | |
1934 | ||
11b83888 | 1935 | retry: |
832a90c3 JR |
1936 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1937 | dma_mask); | |
8fd524b3 | 1938 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1939 | /* |
1940 | * setting next_address here will let the address | |
1941 | * allocator only scan the new allocated range in the | |
1942 | * first run. This is a small optimization. | |
1943 | */ | |
1944 | dma_dom->next_address = dma_dom->aperture_size; | |
1945 | ||
576175c2 | 1946 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1947 | goto out; |
1948 | ||
1949 | /* | |
af901ca1 | 1950 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1951 | * allocation again |
1952 | */ | |
1953 | goto retry; | |
1954 | } | |
cb76c322 JR |
1955 | |
1956 | start = address; | |
1957 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1958 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1959 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1960 | goto out_unmap; |
1961 | ||
cb76c322 JR |
1962 | paddr += PAGE_SIZE; |
1963 | start += PAGE_SIZE; | |
1964 | } | |
1965 | address += offset; | |
1966 | ||
5774f7c5 JR |
1967 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1968 | ||
afa9fdc2 | 1969 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 1970 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 1971 | dma_dom->need_flush = false; |
318afd41 | 1972 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 1973 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1974 | |
cb76c322 JR |
1975 | out: |
1976 | return address; | |
53812c11 JR |
1977 | |
1978 | out_unmap: | |
1979 | ||
1980 | for (--i; i >= 0; --i) { | |
1981 | start -= PAGE_SIZE; | |
680525e0 | 1982 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1983 | } |
1984 | ||
1985 | dma_ops_free_addresses(dma_dom, address, pages); | |
1986 | ||
8fd524b3 | 1987 | return DMA_ERROR_CODE; |
cb76c322 JR |
1988 | } |
1989 | ||
431b2a20 JR |
1990 | /* |
1991 | * Does the reverse of the __map_single function. Must be called with | |
1992 | * the domain lock held too | |
1993 | */ | |
cd8c82e8 | 1994 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1995 | dma_addr_t dma_addr, |
1996 | size_t size, | |
1997 | int dir) | |
1998 | { | |
04e0463e | 1999 | dma_addr_t flush_addr; |
cb76c322 JR |
2000 | dma_addr_t i, start; |
2001 | unsigned int pages; | |
2002 | ||
8fd524b3 | 2003 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2004 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2005 | return; |
2006 | ||
04e0463e | 2007 | flush_addr = dma_addr; |
e3c449f5 | 2008 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2009 | dma_addr &= PAGE_MASK; |
2010 | start = dma_addr; | |
2011 | ||
2012 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2013 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2014 | start += PAGE_SIZE; |
2015 | } | |
2016 | ||
5774f7c5 JR |
2017 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2018 | ||
cb76c322 | 2019 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2020 | |
80be308d | 2021 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2022 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2023 | dma_dom->need_flush = false; |
2024 | } | |
cb76c322 JR |
2025 | } |
2026 | ||
431b2a20 JR |
2027 | /* |
2028 | * The exported map_single function for dma_ops. | |
2029 | */ | |
51491367 FT |
2030 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2031 | unsigned long offset, size_t size, | |
2032 | enum dma_data_direction dir, | |
2033 | struct dma_attrs *attrs) | |
4da70b9e JR |
2034 | { |
2035 | unsigned long flags; | |
4da70b9e | 2036 | struct protection_domain *domain; |
4da70b9e | 2037 | dma_addr_t addr; |
832a90c3 | 2038 | u64 dma_mask; |
51491367 | 2039 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2040 | |
0f2a86f2 JR |
2041 | INC_STATS_COUNTER(cnt_map_single); |
2042 | ||
94f6d190 JR |
2043 | domain = get_domain(dev); |
2044 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2045 | return (dma_addr_t)paddr; |
94f6d190 JR |
2046 | else if (IS_ERR(domain)) |
2047 | return DMA_ERROR_CODE; | |
4da70b9e | 2048 | |
f99c0f1c JR |
2049 | dma_mask = *dev->dma_mask; |
2050 | ||
4da70b9e | 2051 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2052 | |
cd8c82e8 | 2053 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2054 | dma_mask); |
8fd524b3 | 2055 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2056 | goto out; |
2057 | ||
17b124bf | 2058 | domain_flush_complete(domain); |
4da70b9e JR |
2059 | |
2060 | out: | |
2061 | spin_unlock_irqrestore(&domain->lock, flags); | |
2062 | ||
2063 | return addr; | |
2064 | } | |
2065 | ||
431b2a20 JR |
2066 | /* |
2067 | * The exported unmap_single function for dma_ops. | |
2068 | */ | |
51491367 FT |
2069 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2070 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2071 | { |
2072 | unsigned long flags; | |
4da70b9e | 2073 | struct protection_domain *domain; |
4da70b9e | 2074 | |
146a6917 JR |
2075 | INC_STATS_COUNTER(cnt_unmap_single); |
2076 | ||
94f6d190 JR |
2077 | domain = get_domain(dev); |
2078 | if (IS_ERR(domain)) | |
5b28df6f JR |
2079 | return; |
2080 | ||
4da70b9e JR |
2081 | spin_lock_irqsave(&domain->lock, flags); |
2082 | ||
cd8c82e8 | 2083 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2084 | |
17b124bf | 2085 | domain_flush_complete(domain); |
4da70b9e JR |
2086 | |
2087 | spin_unlock_irqrestore(&domain->lock, flags); | |
2088 | } | |
2089 | ||
431b2a20 JR |
2090 | /* |
2091 | * This is a special map_sg function which is used if we should map a | |
2092 | * device which is not handled by an AMD IOMMU in the system. | |
2093 | */ | |
65b050ad JR |
2094 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2095 | int nelems, int dir) | |
2096 | { | |
2097 | struct scatterlist *s; | |
2098 | int i; | |
2099 | ||
2100 | for_each_sg(sglist, s, nelems, i) { | |
2101 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2102 | s->dma_length = s->length; | |
2103 | } | |
2104 | ||
2105 | return nelems; | |
2106 | } | |
2107 | ||
431b2a20 JR |
2108 | /* |
2109 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2110 | * lists). | |
2111 | */ | |
65b050ad | 2112 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2113 | int nelems, enum dma_data_direction dir, |
2114 | struct dma_attrs *attrs) | |
65b050ad JR |
2115 | { |
2116 | unsigned long flags; | |
65b050ad | 2117 | struct protection_domain *domain; |
65b050ad JR |
2118 | int i; |
2119 | struct scatterlist *s; | |
2120 | phys_addr_t paddr; | |
2121 | int mapped_elems = 0; | |
832a90c3 | 2122 | u64 dma_mask; |
65b050ad | 2123 | |
d03f067a JR |
2124 | INC_STATS_COUNTER(cnt_map_sg); |
2125 | ||
94f6d190 JR |
2126 | domain = get_domain(dev); |
2127 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2128 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2129 | else if (IS_ERR(domain)) |
2130 | return 0; | |
dbcc112e | 2131 | |
832a90c3 | 2132 | dma_mask = *dev->dma_mask; |
65b050ad | 2133 | |
65b050ad JR |
2134 | spin_lock_irqsave(&domain->lock, flags); |
2135 | ||
2136 | for_each_sg(sglist, s, nelems, i) { | |
2137 | paddr = sg_phys(s); | |
2138 | ||
cd8c82e8 | 2139 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2140 | paddr, s->length, dir, false, |
2141 | dma_mask); | |
65b050ad JR |
2142 | |
2143 | if (s->dma_address) { | |
2144 | s->dma_length = s->length; | |
2145 | mapped_elems++; | |
2146 | } else | |
2147 | goto unmap; | |
65b050ad JR |
2148 | } |
2149 | ||
17b124bf | 2150 | domain_flush_complete(domain); |
65b050ad JR |
2151 | |
2152 | out: | |
2153 | spin_unlock_irqrestore(&domain->lock, flags); | |
2154 | ||
2155 | return mapped_elems; | |
2156 | unmap: | |
2157 | for_each_sg(sglist, s, mapped_elems, i) { | |
2158 | if (s->dma_address) | |
cd8c82e8 | 2159 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2160 | s->dma_length, dir); |
2161 | s->dma_address = s->dma_length = 0; | |
2162 | } | |
2163 | ||
2164 | mapped_elems = 0; | |
2165 | ||
2166 | goto out; | |
2167 | } | |
2168 | ||
431b2a20 JR |
2169 | /* |
2170 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2171 | * lists). | |
2172 | */ | |
65b050ad | 2173 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2174 | int nelems, enum dma_data_direction dir, |
2175 | struct dma_attrs *attrs) | |
65b050ad JR |
2176 | { |
2177 | unsigned long flags; | |
65b050ad JR |
2178 | struct protection_domain *domain; |
2179 | struct scatterlist *s; | |
65b050ad JR |
2180 | int i; |
2181 | ||
55877a6b JR |
2182 | INC_STATS_COUNTER(cnt_unmap_sg); |
2183 | ||
94f6d190 JR |
2184 | domain = get_domain(dev); |
2185 | if (IS_ERR(domain)) | |
5b28df6f JR |
2186 | return; |
2187 | ||
65b050ad JR |
2188 | spin_lock_irqsave(&domain->lock, flags); |
2189 | ||
2190 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2191 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2192 | s->dma_length, dir); |
65b050ad JR |
2193 | s->dma_address = s->dma_length = 0; |
2194 | } | |
2195 | ||
17b124bf | 2196 | domain_flush_complete(domain); |
65b050ad JR |
2197 | |
2198 | spin_unlock_irqrestore(&domain->lock, flags); | |
2199 | } | |
2200 | ||
431b2a20 JR |
2201 | /* |
2202 | * The exported alloc_coherent function for dma_ops. | |
2203 | */ | |
5d8b53cf JR |
2204 | static void *alloc_coherent(struct device *dev, size_t size, |
2205 | dma_addr_t *dma_addr, gfp_t flag) | |
2206 | { | |
2207 | unsigned long flags; | |
2208 | void *virt_addr; | |
5d8b53cf | 2209 | struct protection_domain *domain; |
5d8b53cf | 2210 | phys_addr_t paddr; |
832a90c3 | 2211 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2212 | |
c8f0fb36 JR |
2213 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2214 | ||
94f6d190 JR |
2215 | domain = get_domain(dev); |
2216 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2217 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2218 | *dma_addr = __pa(virt_addr); | |
2219 | return virt_addr; | |
94f6d190 JR |
2220 | } else if (IS_ERR(domain)) |
2221 | return NULL; | |
5d8b53cf | 2222 | |
f99c0f1c JR |
2223 | dma_mask = dev->coherent_dma_mask; |
2224 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2225 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2226 | |
2227 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2228 | if (!virt_addr) | |
b25ae679 | 2229 | return NULL; |
5d8b53cf | 2230 | |
5d8b53cf JR |
2231 | paddr = virt_to_phys(virt_addr); |
2232 | ||
832a90c3 JR |
2233 | if (!dma_mask) |
2234 | dma_mask = *dev->dma_mask; | |
2235 | ||
5d8b53cf JR |
2236 | spin_lock_irqsave(&domain->lock, flags); |
2237 | ||
cd8c82e8 | 2238 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2239 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2240 | |
8fd524b3 | 2241 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2242 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2243 | goto out_free; |
367d04c4 | 2244 | } |
5d8b53cf | 2245 | |
17b124bf | 2246 | domain_flush_complete(domain); |
5d8b53cf | 2247 | |
5d8b53cf JR |
2248 | spin_unlock_irqrestore(&domain->lock, flags); |
2249 | ||
2250 | return virt_addr; | |
5b28df6f JR |
2251 | |
2252 | out_free: | |
2253 | ||
2254 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2255 | ||
2256 | return NULL; | |
5d8b53cf JR |
2257 | } |
2258 | ||
431b2a20 JR |
2259 | /* |
2260 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2261 | */ |
5d8b53cf JR |
2262 | static void free_coherent(struct device *dev, size_t size, |
2263 | void *virt_addr, dma_addr_t dma_addr) | |
2264 | { | |
2265 | unsigned long flags; | |
5d8b53cf | 2266 | struct protection_domain *domain; |
5d8b53cf | 2267 | |
5d31ee7e JR |
2268 | INC_STATS_COUNTER(cnt_free_coherent); |
2269 | ||
94f6d190 JR |
2270 | domain = get_domain(dev); |
2271 | if (IS_ERR(domain)) | |
5b28df6f JR |
2272 | goto free_mem; |
2273 | ||
5d8b53cf JR |
2274 | spin_lock_irqsave(&domain->lock, flags); |
2275 | ||
cd8c82e8 | 2276 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2277 | |
17b124bf | 2278 | domain_flush_complete(domain); |
5d8b53cf JR |
2279 | |
2280 | spin_unlock_irqrestore(&domain->lock, flags); | |
2281 | ||
2282 | free_mem: | |
2283 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2284 | } | |
2285 | ||
b39ba6ad JR |
2286 | /* |
2287 | * This function is called by the DMA layer to find out if we can handle a | |
2288 | * particular device. It is part of the dma_ops. | |
2289 | */ | |
2290 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2291 | { | |
420aef8a | 2292 | return check_device(dev); |
b39ba6ad JR |
2293 | } |
2294 | ||
c432f3df | 2295 | /* |
431b2a20 JR |
2296 | * The function for pre-allocating protection domains. |
2297 | * | |
c432f3df JR |
2298 | * If the driver core informs the DMA layer if a driver grabs a device |
2299 | * we don't need to preallocate the protection domains anymore. | |
2300 | * For now we have to. | |
2301 | */ | |
0e93dd88 | 2302 | static void prealloc_protection_domains(void) |
c432f3df JR |
2303 | { |
2304 | struct pci_dev *dev = NULL; | |
2305 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2306 | u16 devid; |
c432f3df | 2307 | |
d18c69d3 | 2308 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2309 | |
2310 | /* Do we handle this device? */ | |
2311 | if (!check_device(&dev->dev)) | |
c432f3df | 2312 | continue; |
98fc5a69 JR |
2313 | |
2314 | /* Is there already any domain for it? */ | |
15898bbc | 2315 | if (domain_for_device(&dev->dev)) |
c432f3df | 2316 | continue; |
98fc5a69 JR |
2317 | |
2318 | devid = get_device_id(&dev->dev); | |
2319 | ||
87a64d52 | 2320 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2321 | if (!dma_dom) |
2322 | continue; | |
2323 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2324 | dma_dom->target_dev = devid; |
2325 | ||
15898bbc | 2326 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2327 | |
bd60b735 | 2328 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2329 | } |
2330 | } | |
2331 | ||
160c1d8e | 2332 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2333 | .alloc_coherent = alloc_coherent, |
2334 | .free_coherent = free_coherent, | |
51491367 FT |
2335 | .map_page = map_page, |
2336 | .unmap_page = unmap_page, | |
6631ee9d JR |
2337 | .map_sg = map_sg, |
2338 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2339 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2340 | }; |
2341 | ||
431b2a20 JR |
2342 | /* |
2343 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2344 | */ | |
f5325094 JR |
2345 | |
2346 | void __init amd_iommu_init_api(void) | |
2347 | { | |
2348 | register_iommu(&amd_iommu_ops); | |
2349 | } | |
2350 | ||
6631ee9d JR |
2351 | int __init amd_iommu_init_dma_ops(void) |
2352 | { | |
2353 | struct amd_iommu *iommu; | |
6631ee9d JR |
2354 | int ret; |
2355 | ||
431b2a20 JR |
2356 | /* |
2357 | * first allocate a default protection domain for every IOMMU we | |
2358 | * found in the system. Devices not assigned to any other | |
2359 | * protection domain will be assigned to the default one. | |
2360 | */ | |
3bd22172 | 2361 | for_each_iommu(iommu) { |
87a64d52 | 2362 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2363 | if (iommu->default_dom == NULL) |
2364 | return -ENOMEM; | |
e2dc14a2 | 2365 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2366 | ret = iommu_init_unity_mappings(iommu); |
2367 | if (ret) | |
2368 | goto free_domains; | |
2369 | } | |
2370 | ||
431b2a20 | 2371 | /* |
8793abeb | 2372 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2373 | */ |
8793abeb | 2374 | prealloc_protection_domains(); |
6631ee9d JR |
2375 | |
2376 | iommu_detected = 1; | |
75f1cdf1 | 2377 | swiotlb = 0; |
6631ee9d | 2378 | |
431b2a20 | 2379 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2380 | dma_ops = &amd_iommu_dma_ops; |
2381 | ||
7f26508b JR |
2382 | amd_iommu_stats_init(); |
2383 | ||
6631ee9d JR |
2384 | return 0; |
2385 | ||
2386 | free_domains: | |
2387 | ||
3bd22172 | 2388 | for_each_iommu(iommu) { |
6631ee9d JR |
2389 | if (iommu->default_dom) |
2390 | dma_ops_domain_free(iommu->default_dom); | |
2391 | } | |
2392 | ||
2393 | return ret; | |
2394 | } | |
6d98cd80 JR |
2395 | |
2396 | /***************************************************************************** | |
2397 | * | |
2398 | * The following functions belong to the exported interface of AMD IOMMU | |
2399 | * | |
2400 | * This interface allows access to lower level functions of the IOMMU | |
2401 | * like protection domain handling and assignement of devices to domains | |
2402 | * which is not possible with the dma_ops interface. | |
2403 | * | |
2404 | *****************************************************************************/ | |
2405 | ||
6d98cd80 JR |
2406 | static void cleanup_domain(struct protection_domain *domain) |
2407 | { | |
492667da | 2408 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2409 | unsigned long flags; |
6d98cd80 JR |
2410 | |
2411 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2412 | ||
492667da JR |
2413 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2414 | struct device *dev = dev_data->dev; | |
2415 | ||
04e856c0 | 2416 | __detach_device(dev); |
492667da JR |
2417 | atomic_set(&dev_data->bind, 0); |
2418 | } | |
6d98cd80 JR |
2419 | |
2420 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2421 | } | |
2422 | ||
2650815f JR |
2423 | static void protection_domain_free(struct protection_domain *domain) |
2424 | { | |
2425 | if (!domain) | |
2426 | return; | |
2427 | ||
aeb26f55 JR |
2428 | del_domain_from_list(domain); |
2429 | ||
2650815f JR |
2430 | if (domain->id) |
2431 | domain_id_free(domain->id); | |
2432 | ||
2433 | kfree(domain); | |
2434 | } | |
2435 | ||
2436 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2437 | { |
2438 | struct protection_domain *domain; | |
2439 | ||
2440 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2441 | if (!domain) | |
2650815f | 2442 | return NULL; |
c156e347 JR |
2443 | |
2444 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2445 | mutex_init(&domain->api_lock); |
c156e347 JR |
2446 | domain->id = domain_id_alloc(); |
2447 | if (!domain->id) | |
2650815f | 2448 | goto out_err; |
7c392cbe | 2449 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2450 | |
aeb26f55 JR |
2451 | add_domain_to_list(domain); |
2452 | ||
2650815f JR |
2453 | return domain; |
2454 | ||
2455 | out_err: | |
2456 | kfree(domain); | |
2457 | ||
2458 | return NULL; | |
2459 | } | |
2460 | ||
2461 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2462 | { | |
2463 | struct protection_domain *domain; | |
2464 | ||
2465 | domain = protection_domain_alloc(); | |
2466 | if (!domain) | |
c156e347 | 2467 | goto out_free; |
2650815f JR |
2468 | |
2469 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2470 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2471 | if (!domain->pt_root) | |
2472 | goto out_free; | |
2473 | ||
2474 | dom->priv = domain; | |
2475 | ||
2476 | return 0; | |
2477 | ||
2478 | out_free: | |
2650815f | 2479 | protection_domain_free(domain); |
c156e347 JR |
2480 | |
2481 | return -ENOMEM; | |
2482 | } | |
2483 | ||
98383fc3 JR |
2484 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2485 | { | |
2486 | struct protection_domain *domain = dom->priv; | |
2487 | ||
2488 | if (!domain) | |
2489 | return; | |
2490 | ||
2491 | if (domain->dev_cnt > 0) | |
2492 | cleanup_domain(domain); | |
2493 | ||
2494 | BUG_ON(domain->dev_cnt != 0); | |
2495 | ||
2496 | free_pagetable(domain); | |
2497 | ||
8b408fe4 | 2498 | protection_domain_free(domain); |
98383fc3 JR |
2499 | |
2500 | dom->priv = NULL; | |
2501 | } | |
2502 | ||
684f2888 JR |
2503 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2504 | struct device *dev) | |
2505 | { | |
657cbb6b | 2506 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2507 | struct amd_iommu *iommu; |
684f2888 JR |
2508 | u16 devid; |
2509 | ||
98fc5a69 | 2510 | if (!check_device(dev)) |
684f2888 JR |
2511 | return; |
2512 | ||
98fc5a69 | 2513 | devid = get_device_id(dev); |
684f2888 | 2514 | |
657cbb6b | 2515 | if (dev_data->domain != NULL) |
15898bbc | 2516 | detach_device(dev); |
684f2888 JR |
2517 | |
2518 | iommu = amd_iommu_rlookup_table[devid]; | |
2519 | if (!iommu) | |
2520 | return; | |
2521 | ||
d8c13085 | 2522 | device_flush_dte(dev); |
684f2888 JR |
2523 | iommu_completion_wait(iommu); |
2524 | } | |
2525 | ||
01106066 JR |
2526 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2527 | struct device *dev) | |
2528 | { | |
2529 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2530 | struct iommu_dev_data *dev_data; |
01106066 | 2531 | struct amd_iommu *iommu; |
15898bbc | 2532 | int ret; |
01106066 JR |
2533 | u16 devid; |
2534 | ||
98fc5a69 | 2535 | if (!check_device(dev)) |
01106066 JR |
2536 | return -EINVAL; |
2537 | ||
657cbb6b JR |
2538 | dev_data = dev->archdata.iommu; |
2539 | ||
98fc5a69 | 2540 | devid = get_device_id(dev); |
01106066 JR |
2541 | |
2542 | iommu = amd_iommu_rlookup_table[devid]; | |
2543 | if (!iommu) | |
2544 | return -EINVAL; | |
2545 | ||
657cbb6b | 2546 | if (dev_data->domain) |
15898bbc | 2547 | detach_device(dev); |
01106066 | 2548 | |
15898bbc | 2549 | ret = attach_device(dev, domain); |
01106066 JR |
2550 | |
2551 | iommu_completion_wait(iommu); | |
2552 | ||
15898bbc | 2553 | return ret; |
01106066 JR |
2554 | } |
2555 | ||
468e2366 JR |
2556 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2557 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2558 | { |
468e2366 | 2559 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2560 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2561 | int prot = 0; |
2562 | int ret; | |
2563 | ||
2564 | if (iommu_prot & IOMMU_READ) | |
2565 | prot |= IOMMU_PROT_IR; | |
2566 | if (iommu_prot & IOMMU_WRITE) | |
2567 | prot |= IOMMU_PROT_IW; | |
2568 | ||
5d214fe6 | 2569 | mutex_lock(&domain->api_lock); |
795e74f7 | 2570 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2571 | mutex_unlock(&domain->api_lock); |
2572 | ||
795e74f7 | 2573 | return ret; |
c6229ca6 JR |
2574 | } |
2575 | ||
468e2366 JR |
2576 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2577 | int gfp_order) | |
eb74ff6c | 2578 | { |
eb74ff6c | 2579 | struct protection_domain *domain = dom->priv; |
468e2366 | 2580 | unsigned long page_size, unmap_size; |
eb74ff6c | 2581 | |
468e2366 | 2582 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2583 | |
5d214fe6 | 2584 | mutex_lock(&domain->api_lock); |
468e2366 | 2585 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2586 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2587 | |
17b124bf | 2588 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2589 | |
468e2366 | 2590 | return get_order(unmap_size); |
eb74ff6c JR |
2591 | } |
2592 | ||
645c4c8d JR |
2593 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2594 | unsigned long iova) | |
2595 | { | |
2596 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2597 | unsigned long offset_mask; |
645c4c8d | 2598 | phys_addr_t paddr; |
f03152bb | 2599 | u64 *pte, __pte; |
645c4c8d | 2600 | |
24cd7723 | 2601 | pte = fetch_pte(domain, iova); |
645c4c8d | 2602 | |
a6d41a40 | 2603 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2604 | return 0; |
2605 | ||
f03152bb JR |
2606 | if (PM_PTE_LEVEL(*pte) == 0) |
2607 | offset_mask = PAGE_SIZE - 1; | |
2608 | else | |
2609 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2610 | ||
2611 | __pte = *pte & PM_ADDR_MASK; | |
2612 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2613 | |
2614 | return paddr; | |
2615 | } | |
2616 | ||
dbb9fd86 SY |
2617 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2618 | unsigned long cap) | |
2619 | { | |
80a506b8 JR |
2620 | switch (cap) { |
2621 | case IOMMU_CAP_CACHE_COHERENCY: | |
2622 | return 1; | |
2623 | } | |
2624 | ||
dbb9fd86 SY |
2625 | return 0; |
2626 | } | |
2627 | ||
26961efe JR |
2628 | static struct iommu_ops amd_iommu_ops = { |
2629 | .domain_init = amd_iommu_domain_init, | |
2630 | .domain_destroy = amd_iommu_domain_destroy, | |
2631 | .attach_dev = amd_iommu_attach_device, | |
2632 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2633 | .map = amd_iommu_map, |
2634 | .unmap = amd_iommu_unmap, | |
26961efe | 2635 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2636 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2637 | }; |
2638 | ||
0feae533 JR |
2639 | /***************************************************************************** |
2640 | * | |
2641 | * The next functions do a basic initialization of IOMMU for pass through | |
2642 | * mode | |
2643 | * | |
2644 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2645 | * DMA-API translation. | |
2646 | * | |
2647 | *****************************************************************************/ | |
2648 | ||
2649 | int __init amd_iommu_init_passthrough(void) | |
2650 | { | |
15898bbc | 2651 | struct amd_iommu *iommu; |
0feae533 | 2652 | struct pci_dev *dev = NULL; |
15898bbc | 2653 | u16 devid; |
0feae533 | 2654 | |
af901ca1 | 2655 | /* allocate passthrough domain */ |
0feae533 JR |
2656 | pt_domain = protection_domain_alloc(); |
2657 | if (!pt_domain) | |
2658 | return -ENOMEM; | |
2659 | ||
2660 | pt_domain->mode |= PAGE_MODE_NONE; | |
2661 | ||
6c54aabd | 2662 | for_each_pci_dev(dev) { |
98fc5a69 | 2663 | if (!check_device(&dev->dev)) |
0feae533 JR |
2664 | continue; |
2665 | ||
98fc5a69 JR |
2666 | devid = get_device_id(&dev->dev); |
2667 | ||
15898bbc | 2668 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2669 | if (!iommu) |
2670 | continue; | |
2671 | ||
15898bbc | 2672 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2673 | } |
2674 | ||
2675 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2676 | ||
2677 | return 0; | |
2678 | } |