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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
a66022c4 | 21 | #include <linux/bitmap.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
815b33fd | 28 | #include <linux/delay.h> |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
6a9401a7 | 32 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 33 | #include <asm/amd_iommu_types.h> |
c6da992e | 34 | #include <asm/amd_iommu.h> |
b6c02715 JR |
35 | |
36 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
37 | ||
815b33fd | 38 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 39 | |
b6c02715 JR |
40 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
41 | ||
bd60b735 JR |
42 | /* A list of preallocated protection domains */ |
43 | static LIST_HEAD(iommu_pd_list); | |
44 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
45 | ||
0feae533 JR |
46 | /* |
47 | * Domain for untranslated devices - only allocated | |
48 | * if iommu=pt passed on kernel cmd line. | |
49 | */ | |
50 | static struct protection_domain *pt_domain; | |
51 | ||
26961efe | 52 | static struct iommu_ops amd_iommu_ops; |
26961efe | 53 | |
431b2a20 JR |
54 | /* |
55 | * general struct to manage commands send to an IOMMU | |
56 | */ | |
d6449536 | 57 | struct iommu_cmd { |
b6c02715 JR |
58 | u32 data[4]; |
59 | }; | |
60 | ||
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
657cbb6b JR |
76 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
77 | { | |
78 | return dev->archdata.iommu; | |
79 | } | |
80 | ||
71c70984 JR |
81 | /* |
82 | * In this function the list of preallocated protection domains is traversed to | |
83 | * find the domain for a specific device | |
84 | */ | |
85 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
86 | { | |
87 | struct dma_ops_domain *entry, *ret = NULL; | |
88 | unsigned long flags; | |
89 | u16 alias = amd_iommu_alias_table[devid]; | |
90 | ||
91 | if (list_empty(&iommu_pd_list)) | |
92 | return NULL; | |
93 | ||
94 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
95 | ||
96 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
97 | if (entry->target_dev == devid || | |
98 | entry->target_dev == alias) { | |
99 | ret = entry; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
98fc5a69 JR |
109 | /* |
110 | * This function checks if the driver got a valid device from the caller to | |
111 | * avoid dereferencing invalid pointers. | |
112 | */ | |
113 | static bool check_device(struct device *dev) | |
114 | { | |
115 | u16 devid; | |
116 | ||
117 | if (!dev || !dev->dma_mask) | |
118 | return false; | |
119 | ||
120 | /* No device or no PCI device */ | |
339d3261 | 121 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
122 | return false; |
123 | ||
124 | devid = get_device_id(dev); | |
125 | ||
126 | /* Out of our scope? */ | |
127 | if (devid > amd_iommu_last_bdf) | |
128 | return false; | |
129 | ||
130 | if (amd_iommu_rlookup_table[devid] == NULL) | |
131 | return false; | |
132 | ||
133 | return true; | |
134 | } | |
135 | ||
657cbb6b JR |
136 | static int iommu_init_device(struct device *dev) |
137 | { | |
138 | struct iommu_dev_data *dev_data; | |
139 | struct pci_dev *pdev; | |
140 | u16 devid, alias; | |
141 | ||
142 | if (dev->archdata.iommu) | |
143 | return 0; | |
144 | ||
145 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
146 | if (!dev_data) | |
147 | return -ENOMEM; | |
148 | ||
b00d3bcf JR |
149 | dev_data->dev = dev; |
150 | ||
657cbb6b JR |
151 | devid = get_device_id(dev); |
152 | alias = amd_iommu_alias_table[devid]; | |
153 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
154 | if (pdev) | |
155 | dev_data->alias = &pdev->dev; | |
156 | ||
24100055 JR |
157 | atomic_set(&dev_data->bind, 0); |
158 | ||
657cbb6b JR |
159 | dev->archdata.iommu = dev_data; |
160 | ||
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static void iommu_uninit_device(struct device *dev) | |
166 | { | |
167 | kfree(dev->archdata.iommu); | |
168 | } | |
b7cc9554 JR |
169 | |
170 | void __init amd_iommu_uninit_devices(void) | |
171 | { | |
172 | struct pci_dev *pdev = NULL; | |
173 | ||
174 | for_each_pci_dev(pdev) { | |
175 | ||
176 | if (!check_device(&pdev->dev)) | |
177 | continue; | |
178 | ||
179 | iommu_uninit_device(&pdev->dev); | |
180 | } | |
181 | } | |
182 | ||
183 | int __init amd_iommu_init_devices(void) | |
184 | { | |
185 | struct pci_dev *pdev = NULL; | |
186 | int ret = 0; | |
187 | ||
188 | for_each_pci_dev(pdev) { | |
189 | ||
190 | if (!check_device(&pdev->dev)) | |
191 | continue; | |
192 | ||
193 | ret = iommu_init_device(&pdev->dev); | |
194 | if (ret) | |
195 | goto out_free; | |
196 | } | |
197 | ||
198 | return 0; | |
199 | ||
200 | out_free: | |
201 | ||
202 | amd_iommu_uninit_devices(); | |
203 | ||
204 | return ret; | |
205 | } | |
7f26508b JR |
206 | #ifdef CONFIG_AMD_IOMMU_STATS |
207 | ||
208 | /* | |
209 | * Initialization code for statistics collection | |
210 | */ | |
211 | ||
da49f6df | 212 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 213 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 214 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 215 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 216 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 217 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 218 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 219 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 220 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 221 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 222 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 223 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 224 | |
7f26508b | 225 | static struct dentry *stats_dir; |
7f26508b JR |
226 | static struct dentry *de_fflush; |
227 | ||
228 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
229 | { | |
230 | if (stats_dir == NULL) | |
231 | return; | |
232 | ||
233 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
234 | &cnt->value); | |
235 | } | |
236 | ||
237 | static void amd_iommu_stats_init(void) | |
238 | { | |
239 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
240 | if (stats_dir == NULL) | |
241 | return; | |
242 | ||
7f26508b JR |
243 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
244 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
245 | |
246 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 247 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 248 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 249 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 250 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 251 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 252 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 253 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 254 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 255 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 256 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 257 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
258 | } |
259 | ||
260 | #endif | |
261 | ||
a80dc3e0 JR |
262 | /**************************************************************************** |
263 | * | |
264 | * Interrupt handling functions | |
265 | * | |
266 | ****************************************************************************/ | |
267 | ||
e3e59876 JR |
268 | static void dump_dte_entry(u16 devid) |
269 | { | |
270 | int i; | |
271 | ||
272 | for (i = 0; i < 8; ++i) | |
273 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
274 | amd_iommu_dev_table[devid].data[i]); | |
275 | } | |
276 | ||
945b4ac4 JR |
277 | static void dump_command(unsigned long phys_addr) |
278 | { | |
279 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < 4; ++i) | |
283 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
284 | } | |
285 | ||
a345b23b | 286 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
287 | { |
288 | u32 *event = __evt; | |
289 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
290 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
291 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
292 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
293 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
294 | ||
4c6f40d4 | 295 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
296 | |
297 | switch (type) { | |
298 | case EVENT_TYPE_ILL_DEV: | |
299 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
300 | "address=0x%016llx flags=0x%04x]\n", | |
301 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
302 | address, flags); | |
e3e59876 | 303 | dump_dte_entry(devid); |
90008ee4 JR |
304 | break; |
305 | case EVENT_TYPE_IO_FAULT: | |
306 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
307 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
308 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
309 | domid, address, flags); | |
310 | break; | |
311 | case EVENT_TYPE_DEV_TAB_ERR: | |
312 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
313 | "address=0x%016llx flags=0x%04x]\n", | |
314 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
315 | address, flags); | |
316 | break; | |
317 | case EVENT_TYPE_PAGE_TAB_ERR: | |
318 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
319 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
320 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
321 | domid, address, flags); | |
322 | break; | |
323 | case EVENT_TYPE_ILL_CMD: | |
324 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 325 | dump_command(address); |
90008ee4 JR |
326 | break; |
327 | case EVENT_TYPE_CMD_HARD_ERR: | |
328 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
329 | "flags=0x%04x]\n", address, flags); | |
330 | break; | |
331 | case EVENT_TYPE_IOTLB_INV_TO: | |
332 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
333 | "address=0x%016llx]\n", | |
334 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
335 | address); | |
336 | break; | |
337 | case EVENT_TYPE_INV_DEV_REQ: | |
338 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
339 | "address=0x%016llx flags=0x%04x]\n", | |
340 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
341 | address, flags); | |
342 | break; | |
343 | default: | |
344 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
345 | } | |
346 | } | |
347 | ||
348 | static void iommu_poll_events(struct amd_iommu *iommu) | |
349 | { | |
350 | u32 head, tail; | |
351 | unsigned long flags; | |
352 | ||
353 | spin_lock_irqsave(&iommu->lock, flags); | |
354 | ||
355 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
356 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
357 | ||
358 | while (head != tail) { | |
a345b23b | 359 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
360 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
361 | } | |
362 | ||
363 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
364 | ||
365 | spin_unlock_irqrestore(&iommu->lock, flags); | |
366 | } | |
367 | ||
a80dc3e0 JR |
368 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
369 | { | |
90008ee4 JR |
370 | struct amd_iommu *iommu; |
371 | ||
3bd22172 | 372 | for_each_iommu(iommu) |
90008ee4 JR |
373 | iommu_poll_events(iommu); |
374 | ||
375 | return IRQ_HANDLED; | |
a80dc3e0 JR |
376 | } |
377 | ||
431b2a20 JR |
378 | /**************************************************************************** |
379 | * | |
380 | * IOMMU command queuing functions | |
381 | * | |
382 | ****************************************************************************/ | |
383 | ||
815b33fd | 384 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 385 | { |
815b33fd JR |
386 | WARN_ON(address & 0x7ULL); |
387 | ||
ded46737 | 388 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
389 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
390 | cmd->data[1] = upper_32_bits(__pa(address)); | |
391 | cmd->data[2] = 1; | |
ded46737 JR |
392 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
393 | } | |
394 | ||
94fe79e2 JR |
395 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
396 | { | |
397 | memset(cmd, 0, sizeof(*cmd)); | |
398 | cmd->data[0] = devid; | |
399 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
400 | } | |
401 | ||
11b6402c JR |
402 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
403 | size_t size, u16 domid, int pde) | |
404 | { | |
405 | u64 pages; | |
406 | int s; | |
407 | ||
408 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
409 | s = 0; | |
410 | ||
411 | if (pages > 1) { | |
412 | /* | |
413 | * If we have to flush more than one page, flush all | |
414 | * TLB entries for this domain | |
415 | */ | |
416 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
417 | s = 1; | |
418 | } | |
419 | ||
420 | address &= PAGE_MASK; | |
421 | ||
422 | memset(cmd, 0, sizeof(*cmd)); | |
423 | cmd->data[1] |= domid; | |
424 | cmd->data[2] = lower_32_bits(address); | |
425 | cmd->data[3] = upper_32_bits(address); | |
426 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
427 | if (s) /* size bit - we flush more than one 4kb page */ | |
428 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
429 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
430 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
431 | } | |
432 | ||
431b2a20 JR |
433 | /* |
434 | * Writes the command to the IOMMUs command buffer and informs the | |
435 | * hardware about the new command. Must be called with iommu->lock held. | |
436 | */ | |
815b33fd | 437 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 438 | { |
815b33fd | 439 | unsigned long flags; |
a19ae1ec JR |
440 | u32 tail, head; |
441 | u8 *target; | |
442 | ||
549c90dc | 443 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
815b33fd | 444 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 445 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
8a7c5ef3 | 446 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
447 | memcpy_toio(target, cmd, sizeof(*cmd)); |
448 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
449 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
450 | if (tail == head) | |
451 | return -ENOMEM; | |
452 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
815b33fd | 453 | iommu->need_sync = true; |
a19ae1ec JR |
454 | spin_unlock_irqrestore(&iommu->lock, flags); |
455 | ||
815b33fd | 456 | return 0; |
8d201968 JR |
457 | } |
458 | ||
459 | /* | |
460 | * This function queues a completion wait command into the command | |
461 | * buffer of an IOMMU | |
462 | */ | |
a19ae1ec JR |
463 | static int iommu_completion_wait(struct amd_iommu *iommu) |
464 | { | |
815b33fd JR |
465 | struct iommu_cmd cmd; |
466 | volatile u64 sem = 0; | |
467 | int ret, i = 0; | |
7e4f88da | 468 | |
09ee17eb | 469 | if (!iommu->need_sync) |
815b33fd | 470 | return 0; |
09ee17eb | 471 | |
815b33fd | 472 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 473 | |
815b33fd | 474 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 475 | if (ret) |
815b33fd | 476 | return ret; |
84df8175 | 477 | |
815b33fd JR |
478 | while (sem == 0 && i < LOOP_TIMEOUT) { |
479 | udelay(1); | |
480 | i += 1; | |
481 | } | |
a19ae1ec | 482 | |
815b33fd JR |
483 | if (i == LOOP_TIMEOUT) { |
484 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
61985a04 | 485 | ret = -EIO; |
815b33fd | 486 | } |
8eed9833 | 487 | |
a19ae1ec JR |
488 | return 0; |
489 | } | |
490 | ||
0518a3a4 JR |
491 | static void iommu_flush_complete(struct protection_domain *domain) |
492 | { | |
493 | int i; | |
494 | ||
495 | for (i = 0; i < amd_iommus_present; ++i) { | |
496 | if (!domain->dev_iommu[i]) | |
497 | continue; | |
498 | ||
499 | /* | |
500 | * Devices of this domain are behind this IOMMU | |
501 | * We need to wait for completion of all commands. | |
502 | */ | |
503 | iommu_completion_wait(amd_iommus[i]); | |
504 | } | |
505 | } | |
506 | ||
431b2a20 JR |
507 | /* |
508 | * Command send function for invalidating a device table entry | |
509 | */ | |
3fa43655 JR |
510 | static int iommu_flush_device(struct device *dev) |
511 | { | |
512 | struct amd_iommu *iommu; | |
b00d3bcf | 513 | struct iommu_cmd cmd; |
3fa43655 JR |
514 | u16 devid; |
515 | ||
516 | devid = get_device_id(dev); | |
517 | iommu = amd_iommu_rlookup_table[devid]; | |
518 | ||
94fe79e2 | 519 | build_inv_dte(&cmd, devid); |
b00d3bcf JR |
520 | |
521 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
522 | } |
523 | ||
431b2a20 JR |
524 | /* |
525 | * TLB invalidation function which is called from the mapping functions. | |
526 | * It invalidates a single PTE if the range to flush is within a single | |
527 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
528 | */ | |
6de8ad9b JR |
529 | static void __iommu_flush_pages(struct protection_domain *domain, |
530 | u64 address, size_t size, int pde) | |
a19ae1ec | 531 | { |
11b6402c JR |
532 | struct iommu_cmd cmd; |
533 | int ret = 0, i; | |
a19ae1ec | 534 | |
11b6402c | 535 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 536 | |
6de8ad9b JR |
537 | for (i = 0; i < amd_iommus_present; ++i) { |
538 | if (!domain->dev_iommu[i]) | |
539 | continue; | |
540 | ||
541 | /* | |
542 | * Devices of this domain are behind this IOMMU | |
543 | * We need a TLB flush | |
544 | */ | |
11b6402c | 545 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
546 | } |
547 | ||
11b6402c | 548 | WARN_ON(ret); |
6de8ad9b JR |
549 | } |
550 | ||
551 | static void iommu_flush_pages(struct protection_domain *domain, | |
552 | u64 address, size_t size) | |
553 | { | |
554 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 555 | } |
b6c02715 | 556 | |
1c655773 | 557 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 558 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 559 | { |
dcd1e92e | 560 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
561 | } |
562 | ||
42a49f96 | 563 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 564 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 565 | { |
dcd1e92e | 566 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
567 | } |
568 | ||
b00d3bcf | 569 | |
43f49609 | 570 | /* |
b00d3bcf | 571 | * This function flushes the DTEs for all devices in domain |
43f49609 | 572 | */ |
b00d3bcf JR |
573 | static void iommu_flush_domain_devices(struct protection_domain *domain) |
574 | { | |
575 | struct iommu_dev_data *dev_data; | |
576 | unsigned long flags; | |
577 | ||
578 | spin_lock_irqsave(&domain->lock, flags); | |
579 | ||
580 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
581 | iommu_flush_device(dev_data->dev); | |
582 | ||
583 | spin_unlock_irqrestore(&domain->lock, flags); | |
584 | } | |
585 | ||
586 | static void iommu_flush_all_domain_devices(void) | |
43f49609 | 587 | { |
09b42804 | 588 | struct protection_domain *domain; |
e394d72a | 589 | unsigned long flags; |
18811f55 | 590 | |
09b42804 | 591 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 592 | |
09b42804 | 593 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
b00d3bcf | 594 | iommu_flush_domain_devices(domain); |
09b42804 | 595 | iommu_flush_complete(domain); |
bfd1be18 | 596 | } |
e394d72a | 597 | |
09b42804 | 598 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
599 | } |
600 | ||
b00d3bcf JR |
601 | void amd_iommu_flush_all_devices(void) |
602 | { | |
603 | iommu_flush_all_domain_devices(); | |
604 | } | |
605 | ||
09b42804 JR |
606 | /* |
607 | * This function uses heavy locking and may disable irqs for some time. But | |
608 | * this is no issue because it is only called during resume. | |
609 | */ | |
bfd1be18 | 610 | void amd_iommu_flush_all_domains(void) |
e394d72a | 611 | { |
e3306664 | 612 | struct protection_domain *domain; |
09b42804 JR |
613 | unsigned long flags; |
614 | ||
615 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 616 | |
e3306664 | 617 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 618 | spin_lock(&domain->lock); |
e3306664 JR |
619 | iommu_flush_tlb_pde(domain); |
620 | iommu_flush_complete(domain); | |
09b42804 | 621 | spin_unlock(&domain->lock); |
e3306664 | 622 | } |
09b42804 JR |
623 | |
624 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
625 | } |
626 | ||
431b2a20 JR |
627 | /**************************************************************************** |
628 | * | |
629 | * The functions below are used the create the page table mappings for | |
630 | * unity mapped regions. | |
631 | * | |
632 | ****************************************************************************/ | |
633 | ||
308973d3 JR |
634 | /* |
635 | * This function is used to add another level to an IO page table. Adding | |
636 | * another level increases the size of the address space by 9 bits to a size up | |
637 | * to 64 bits. | |
638 | */ | |
639 | static bool increase_address_space(struct protection_domain *domain, | |
640 | gfp_t gfp) | |
641 | { | |
642 | u64 *pte; | |
643 | ||
644 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
645 | /* address space already 64 bit large */ | |
646 | return false; | |
647 | ||
648 | pte = (void *)get_zeroed_page(gfp); | |
649 | if (!pte) | |
650 | return false; | |
651 | ||
652 | *pte = PM_LEVEL_PDE(domain->mode, | |
653 | virt_to_phys(domain->pt_root)); | |
654 | domain->pt_root = pte; | |
655 | domain->mode += 1; | |
656 | domain->updated = true; | |
657 | ||
658 | return true; | |
659 | } | |
660 | ||
661 | static u64 *alloc_pte(struct protection_domain *domain, | |
662 | unsigned long address, | |
cbb9d729 | 663 | unsigned long page_size, |
308973d3 JR |
664 | u64 **pte_page, |
665 | gfp_t gfp) | |
666 | { | |
cbb9d729 | 667 | int level, end_lvl; |
308973d3 | 668 | u64 *pte, *page; |
cbb9d729 JR |
669 | |
670 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
671 | |
672 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
673 | increase_address_space(domain, gfp); | |
674 | ||
cbb9d729 JR |
675 | level = domain->mode - 1; |
676 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
677 | address = PAGE_SIZE_ALIGN(address, page_size); | |
678 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
679 | |
680 | while (level > end_lvl) { | |
681 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
682 | page = (u64 *)get_zeroed_page(gfp); | |
683 | if (!page) | |
684 | return NULL; | |
685 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
686 | } | |
687 | ||
cbb9d729 JR |
688 | /* No level skipping support yet */ |
689 | if (PM_PTE_LEVEL(*pte) != level) | |
690 | return NULL; | |
691 | ||
308973d3 JR |
692 | level -= 1; |
693 | ||
694 | pte = IOMMU_PTE_PAGE(*pte); | |
695 | ||
696 | if (pte_page && level == end_lvl) | |
697 | *pte_page = pte; | |
698 | ||
699 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
700 | } | |
701 | ||
702 | return pte; | |
703 | } | |
704 | ||
705 | /* | |
706 | * This function checks if there is a PTE for a given dma address. If | |
707 | * there is one, it returns the pointer to it. | |
708 | */ | |
24cd7723 | 709 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
710 | { |
711 | int level; | |
712 | u64 *pte; | |
713 | ||
24cd7723 JR |
714 | if (address > PM_LEVEL_SIZE(domain->mode)) |
715 | return NULL; | |
716 | ||
717 | level = domain->mode - 1; | |
718 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 719 | |
24cd7723 JR |
720 | while (level > 0) { |
721 | ||
722 | /* Not Present */ | |
308973d3 JR |
723 | if (!IOMMU_PTE_PRESENT(*pte)) |
724 | return NULL; | |
725 | ||
24cd7723 JR |
726 | /* Large PTE */ |
727 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
728 | unsigned long pte_mask, __pte; | |
729 | ||
730 | /* | |
731 | * If we have a series of large PTEs, make | |
732 | * sure to return a pointer to the first one. | |
733 | */ | |
734 | pte_mask = PTE_PAGE_SIZE(*pte); | |
735 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
736 | __pte = ((unsigned long)pte) & pte_mask; | |
737 | ||
738 | return (u64 *)__pte; | |
739 | } | |
740 | ||
741 | /* No level skipping support yet */ | |
742 | if (PM_PTE_LEVEL(*pte) != level) | |
743 | return NULL; | |
744 | ||
308973d3 JR |
745 | level -= 1; |
746 | ||
24cd7723 | 747 | /* Walk to the next level */ |
308973d3 JR |
748 | pte = IOMMU_PTE_PAGE(*pte); |
749 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
750 | } |
751 | ||
752 | return pte; | |
753 | } | |
754 | ||
431b2a20 JR |
755 | /* |
756 | * Generic mapping functions. It maps a physical address into a DMA | |
757 | * address space. It allocates the page table pages if necessary. | |
758 | * In the future it can be extended to a generic mapping function | |
759 | * supporting all features of AMD IOMMU page tables like level skipping | |
760 | * and full 64 bit address spaces. | |
761 | */ | |
38e817fe JR |
762 | static int iommu_map_page(struct protection_domain *dom, |
763 | unsigned long bus_addr, | |
764 | unsigned long phys_addr, | |
abdc5eb3 | 765 | int prot, |
cbb9d729 | 766 | unsigned long page_size) |
bd0e5211 | 767 | { |
8bda3092 | 768 | u64 __pte, *pte; |
cbb9d729 | 769 | int i, count; |
abdc5eb3 | 770 | |
bad1cac2 | 771 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
772 | return -EINVAL; |
773 | ||
cbb9d729 JR |
774 | bus_addr = PAGE_ALIGN(bus_addr); |
775 | phys_addr = PAGE_ALIGN(phys_addr); | |
776 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
777 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
778 | ||
779 | for (i = 0; i < count; ++i) | |
780 | if (IOMMU_PTE_PRESENT(pte[i])) | |
781 | return -EBUSY; | |
bd0e5211 | 782 | |
cbb9d729 JR |
783 | if (page_size > PAGE_SIZE) { |
784 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
785 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
786 | } else | |
787 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 788 | |
bd0e5211 JR |
789 | if (prot & IOMMU_PROT_IR) |
790 | __pte |= IOMMU_PTE_IR; | |
791 | if (prot & IOMMU_PROT_IW) | |
792 | __pte |= IOMMU_PTE_IW; | |
793 | ||
cbb9d729 JR |
794 | for (i = 0; i < count; ++i) |
795 | pte[i] = __pte; | |
bd0e5211 | 796 | |
04bfdd84 JR |
797 | update_domain(dom); |
798 | ||
bd0e5211 JR |
799 | return 0; |
800 | } | |
801 | ||
24cd7723 JR |
802 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
803 | unsigned long bus_addr, | |
804 | unsigned long page_size) | |
eb74ff6c | 805 | { |
24cd7723 JR |
806 | unsigned long long unmap_size, unmapped; |
807 | u64 *pte; | |
808 | ||
809 | BUG_ON(!is_power_of_2(page_size)); | |
810 | ||
811 | unmapped = 0; | |
eb74ff6c | 812 | |
24cd7723 JR |
813 | while (unmapped < page_size) { |
814 | ||
815 | pte = fetch_pte(dom, bus_addr); | |
816 | ||
817 | if (!pte) { | |
818 | /* | |
819 | * No PTE for this address | |
820 | * move forward in 4kb steps | |
821 | */ | |
822 | unmap_size = PAGE_SIZE; | |
823 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
824 | /* 4kb PTE found for this address */ | |
825 | unmap_size = PAGE_SIZE; | |
826 | *pte = 0ULL; | |
827 | } else { | |
828 | int count, i; | |
829 | ||
830 | /* Large PTE found which maps this address */ | |
831 | unmap_size = PTE_PAGE_SIZE(*pte); | |
832 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
833 | for (i = 0; i < count; i++) | |
834 | pte[i] = 0ULL; | |
835 | } | |
836 | ||
837 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
838 | unmapped += unmap_size; | |
839 | } | |
840 | ||
841 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 842 | |
24cd7723 | 843 | return unmapped; |
eb74ff6c | 844 | } |
eb74ff6c | 845 | |
431b2a20 JR |
846 | /* |
847 | * This function checks if a specific unity mapping entry is needed for | |
848 | * this specific IOMMU. | |
849 | */ | |
bd0e5211 JR |
850 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
851 | struct unity_map_entry *entry) | |
852 | { | |
853 | u16 bdf, i; | |
854 | ||
855 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
856 | bdf = amd_iommu_alias_table[i]; | |
857 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
858 | return 1; | |
859 | } | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
431b2a20 JR |
864 | /* |
865 | * This function actually applies the mapping to the page table of the | |
866 | * dma_ops domain. | |
867 | */ | |
bd0e5211 JR |
868 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
869 | struct unity_map_entry *e) | |
870 | { | |
871 | u64 addr; | |
872 | int ret; | |
873 | ||
874 | for (addr = e->address_start; addr < e->address_end; | |
875 | addr += PAGE_SIZE) { | |
abdc5eb3 | 876 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 877 | PAGE_SIZE); |
bd0e5211 JR |
878 | if (ret) |
879 | return ret; | |
880 | /* | |
881 | * if unity mapping is in aperture range mark the page | |
882 | * as allocated in the aperture | |
883 | */ | |
884 | if (addr < dma_dom->aperture_size) | |
c3239567 | 885 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 886 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
887 | } |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
171e7b37 JR |
892 | /* |
893 | * Init the unity mappings for a specific IOMMU in the system | |
894 | * | |
895 | * Basically iterates over all unity mapping entries and applies them to | |
896 | * the default domain DMA of that IOMMU if necessary. | |
897 | */ | |
898 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
899 | { | |
900 | struct unity_map_entry *entry; | |
901 | int ret; | |
902 | ||
903 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
904 | if (!iommu_for_unity_map(iommu, entry)) | |
905 | continue; | |
906 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
907 | if (ret) | |
908 | return ret; | |
909 | } | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
431b2a20 JR |
914 | /* |
915 | * Inits the unity mappings required for a specific device | |
916 | */ | |
bd0e5211 JR |
917 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
918 | u16 devid) | |
919 | { | |
920 | struct unity_map_entry *e; | |
921 | int ret; | |
922 | ||
923 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
924 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
925 | continue; | |
926 | ret = dma_ops_unity_map(dma_dom, e); | |
927 | if (ret) | |
928 | return ret; | |
929 | } | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
431b2a20 JR |
934 | /**************************************************************************** |
935 | * | |
936 | * The next functions belong to the address allocator for the dma_ops | |
937 | * interface functions. They work like the allocators in the other IOMMU | |
938 | * drivers. Its basically a bitmap which marks the allocated pages in | |
939 | * the aperture. Maybe it could be enhanced in the future to a more | |
940 | * efficient allocator. | |
941 | * | |
942 | ****************************************************************************/ | |
d3086444 | 943 | |
431b2a20 | 944 | /* |
384de729 | 945 | * The address allocator core functions. |
431b2a20 JR |
946 | * |
947 | * called with domain->lock held | |
948 | */ | |
384de729 | 949 | |
171e7b37 JR |
950 | /* |
951 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
952 | * ranges. | |
953 | */ | |
954 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
955 | unsigned long start_page, | |
956 | unsigned int pages) | |
957 | { | |
958 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
959 | ||
960 | if (start_page + pages > last_page) | |
961 | pages = last_page - start_page; | |
962 | ||
963 | for (i = start_page; i < start_page + pages; ++i) { | |
964 | int index = i / APERTURE_RANGE_PAGES; | |
965 | int page = i % APERTURE_RANGE_PAGES; | |
966 | __set_bit(page, dom->aperture[index]->bitmap); | |
967 | } | |
968 | } | |
969 | ||
9cabe89b JR |
970 | /* |
971 | * This function is used to add a new aperture range to an existing | |
972 | * aperture in case of dma_ops domain allocation or address allocation | |
973 | * failure. | |
974 | */ | |
576175c2 | 975 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
976 | bool populate, gfp_t gfp) |
977 | { | |
978 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 979 | struct amd_iommu *iommu; |
d91afd15 | 980 | unsigned long i; |
9cabe89b | 981 | |
f5e9705c JR |
982 | #ifdef CONFIG_IOMMU_STRESS |
983 | populate = false; | |
984 | #endif | |
985 | ||
9cabe89b JR |
986 | if (index >= APERTURE_MAX_RANGES) |
987 | return -ENOMEM; | |
988 | ||
989 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
990 | if (!dma_dom->aperture[index]) | |
991 | return -ENOMEM; | |
992 | ||
993 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
994 | if (!dma_dom->aperture[index]->bitmap) | |
995 | goto out_free; | |
996 | ||
997 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
998 | ||
999 | if (populate) { | |
1000 | unsigned long address = dma_dom->aperture_size; | |
1001 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1002 | u64 *pte, *pte_page; | |
1003 | ||
1004 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1005 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1006 | &pte_page, gfp); |
1007 | if (!pte) | |
1008 | goto out_free; | |
1009 | ||
1010 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1011 | ||
1012 | address += APERTURE_RANGE_SIZE / 64; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1017 | ||
b595076a | 1018 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1019 | for_each_iommu(iommu) { |
1020 | if (iommu->exclusion_start && | |
1021 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1022 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1023 | unsigned long startpage; | |
1024 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1025 | iommu->exclusion_length, | |
1026 | PAGE_SIZE); | |
1027 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1028 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1029 | } | |
00cd122a JR |
1030 | } |
1031 | ||
1032 | /* | |
1033 | * Check for areas already mapped as present in the new aperture | |
1034 | * range and mark those pages as reserved in the allocator. Such | |
1035 | * mappings may already exist as a result of requested unity | |
1036 | * mappings for devices. | |
1037 | */ | |
1038 | for (i = dma_dom->aperture[index]->offset; | |
1039 | i < dma_dom->aperture_size; | |
1040 | i += PAGE_SIZE) { | |
24cd7723 | 1041 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1042 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1043 | continue; | |
1044 | ||
1045 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1046 | } | |
1047 | ||
04bfdd84 JR |
1048 | update_domain(&dma_dom->domain); |
1049 | ||
9cabe89b JR |
1050 | return 0; |
1051 | ||
1052 | out_free: | |
04bfdd84 JR |
1053 | update_domain(&dma_dom->domain); |
1054 | ||
9cabe89b JR |
1055 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1056 | ||
1057 | kfree(dma_dom->aperture[index]); | |
1058 | dma_dom->aperture[index] = NULL; | |
1059 | ||
1060 | return -ENOMEM; | |
1061 | } | |
1062 | ||
384de729 JR |
1063 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1064 | struct dma_ops_domain *dom, | |
1065 | unsigned int pages, | |
1066 | unsigned long align_mask, | |
1067 | u64 dma_mask, | |
1068 | unsigned long start) | |
1069 | { | |
803b8cb4 | 1070 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1071 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1072 | int i = start >> APERTURE_RANGE_SHIFT; | |
1073 | unsigned long boundary_size; | |
1074 | unsigned long address = -1; | |
1075 | unsigned long limit; | |
1076 | ||
803b8cb4 JR |
1077 | next_bit >>= PAGE_SHIFT; |
1078 | ||
384de729 JR |
1079 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1080 | PAGE_SIZE) >> PAGE_SHIFT; | |
1081 | ||
1082 | for (;i < max_index; ++i) { | |
1083 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1084 | ||
1085 | if (dom->aperture[i]->offset >= dma_mask) | |
1086 | break; | |
1087 | ||
1088 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1089 | dma_mask >> PAGE_SHIFT); | |
1090 | ||
1091 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1092 | limit, next_bit, pages, 0, | |
1093 | boundary_size, align_mask); | |
1094 | if (address != -1) { | |
1095 | address = dom->aperture[i]->offset + | |
1096 | (address << PAGE_SHIFT); | |
803b8cb4 | 1097 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1098 | break; |
1099 | } | |
1100 | ||
1101 | next_bit = 0; | |
1102 | } | |
1103 | ||
1104 | return address; | |
1105 | } | |
1106 | ||
d3086444 JR |
1107 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1108 | struct dma_ops_domain *dom, | |
6d4f343f | 1109 | unsigned int pages, |
832a90c3 JR |
1110 | unsigned long align_mask, |
1111 | u64 dma_mask) | |
d3086444 | 1112 | { |
d3086444 | 1113 | unsigned long address; |
d3086444 | 1114 | |
fe16f088 JR |
1115 | #ifdef CONFIG_IOMMU_STRESS |
1116 | dom->next_address = 0; | |
1117 | dom->need_flush = true; | |
1118 | #endif | |
d3086444 | 1119 | |
384de729 | 1120 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1121 | dma_mask, dom->next_address); |
d3086444 | 1122 | |
1c655773 | 1123 | if (address == -1) { |
803b8cb4 | 1124 | dom->next_address = 0; |
384de729 JR |
1125 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1126 | dma_mask, 0); | |
1c655773 JR |
1127 | dom->need_flush = true; |
1128 | } | |
d3086444 | 1129 | |
384de729 | 1130 | if (unlikely(address == -1)) |
8fd524b3 | 1131 | address = DMA_ERROR_CODE; |
d3086444 JR |
1132 | |
1133 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1134 | ||
1135 | return address; | |
1136 | } | |
1137 | ||
431b2a20 JR |
1138 | /* |
1139 | * The address free function. | |
1140 | * | |
1141 | * called with domain->lock held | |
1142 | */ | |
d3086444 JR |
1143 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1144 | unsigned long address, | |
1145 | unsigned int pages) | |
1146 | { | |
384de729 JR |
1147 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1148 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1149 | |
384de729 JR |
1150 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1151 | ||
47bccd6b JR |
1152 | #ifdef CONFIG_IOMMU_STRESS |
1153 | if (i < 4) | |
1154 | return; | |
1155 | #endif | |
80be308d | 1156 | |
803b8cb4 | 1157 | if (address >= dom->next_address) |
80be308d | 1158 | dom->need_flush = true; |
384de729 JR |
1159 | |
1160 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1161 | |
a66022c4 | 1162 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1163 | |
d3086444 JR |
1164 | } |
1165 | ||
431b2a20 JR |
1166 | /**************************************************************************** |
1167 | * | |
1168 | * The next functions belong to the domain allocation. A domain is | |
1169 | * allocated for every IOMMU as the default domain. If device isolation | |
1170 | * is enabled, every device get its own domain. The most important thing | |
1171 | * about domains is the page table mapping the DMA address space they | |
1172 | * contain. | |
1173 | * | |
1174 | ****************************************************************************/ | |
1175 | ||
aeb26f55 JR |
1176 | /* |
1177 | * This function adds a protection domain to the global protection domain list | |
1178 | */ | |
1179 | static void add_domain_to_list(struct protection_domain *domain) | |
1180 | { | |
1181 | unsigned long flags; | |
1182 | ||
1183 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1184 | list_add(&domain->list, &amd_iommu_pd_list); | |
1185 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1186 | } | |
1187 | ||
1188 | /* | |
1189 | * This function removes a protection domain to the global | |
1190 | * protection domain list | |
1191 | */ | |
1192 | static void del_domain_from_list(struct protection_domain *domain) | |
1193 | { | |
1194 | unsigned long flags; | |
1195 | ||
1196 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1197 | list_del(&domain->list); | |
1198 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1199 | } | |
1200 | ||
ec487d1a JR |
1201 | static u16 domain_id_alloc(void) |
1202 | { | |
1203 | unsigned long flags; | |
1204 | int id; | |
1205 | ||
1206 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1207 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1208 | BUG_ON(id == 0); | |
1209 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1210 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1211 | else | |
1212 | id = 0; | |
1213 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1214 | ||
1215 | return id; | |
1216 | } | |
1217 | ||
a2acfb75 JR |
1218 | static void domain_id_free(int id) |
1219 | { | |
1220 | unsigned long flags; | |
1221 | ||
1222 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1223 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1224 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1225 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1226 | } | |
a2acfb75 | 1227 | |
86db2e5d | 1228 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1229 | { |
1230 | int i, j; | |
1231 | u64 *p1, *p2, *p3; | |
1232 | ||
86db2e5d | 1233 | p1 = domain->pt_root; |
ec487d1a JR |
1234 | |
1235 | if (!p1) | |
1236 | return; | |
1237 | ||
1238 | for (i = 0; i < 512; ++i) { | |
1239 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1240 | continue; | |
1241 | ||
1242 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1243 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1244 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1245 | continue; | |
1246 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1247 | free_page((unsigned long)p3); | |
1248 | } | |
1249 | ||
1250 | free_page((unsigned long)p2); | |
1251 | } | |
1252 | ||
1253 | free_page((unsigned long)p1); | |
86db2e5d JR |
1254 | |
1255 | domain->pt_root = NULL; | |
ec487d1a JR |
1256 | } |
1257 | ||
431b2a20 JR |
1258 | /* |
1259 | * Free a domain, only used if something went wrong in the | |
1260 | * allocation path and we need to free an already allocated page table | |
1261 | */ | |
ec487d1a JR |
1262 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1263 | { | |
384de729 JR |
1264 | int i; |
1265 | ||
ec487d1a JR |
1266 | if (!dom) |
1267 | return; | |
1268 | ||
aeb26f55 JR |
1269 | del_domain_from_list(&dom->domain); |
1270 | ||
86db2e5d | 1271 | free_pagetable(&dom->domain); |
ec487d1a | 1272 | |
384de729 JR |
1273 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1274 | if (!dom->aperture[i]) | |
1275 | continue; | |
1276 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1277 | kfree(dom->aperture[i]); | |
1278 | } | |
ec487d1a JR |
1279 | |
1280 | kfree(dom); | |
1281 | } | |
1282 | ||
431b2a20 JR |
1283 | /* |
1284 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1285 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1286 | * structures required for the dma_ops interface |
1287 | */ | |
87a64d52 | 1288 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1289 | { |
1290 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1291 | |
1292 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1293 | if (!dma_dom) | |
1294 | return NULL; | |
1295 | ||
1296 | spin_lock_init(&dma_dom->domain.lock); | |
1297 | ||
1298 | dma_dom->domain.id = domain_id_alloc(); | |
1299 | if (dma_dom->domain.id == 0) | |
1300 | goto free_dma_dom; | |
7c392cbe | 1301 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1302 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1303 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1304 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1305 | dma_dom->domain.priv = dma_dom; |
1306 | if (!dma_dom->domain.pt_root) | |
1307 | goto free_dma_dom; | |
ec487d1a | 1308 | |
1c655773 | 1309 | dma_dom->need_flush = false; |
bd60b735 | 1310 | dma_dom->target_dev = 0xffff; |
1c655773 | 1311 | |
aeb26f55 JR |
1312 | add_domain_to_list(&dma_dom->domain); |
1313 | ||
576175c2 | 1314 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1315 | goto free_dma_dom; |
ec487d1a | 1316 | |
431b2a20 | 1317 | /* |
ec487d1a JR |
1318 | * mark the first page as allocated so we never return 0 as |
1319 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1320 | */ |
384de729 | 1321 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1322 | dma_dom->next_address = 0; |
ec487d1a | 1323 | |
ec487d1a JR |
1324 | |
1325 | return dma_dom; | |
1326 | ||
1327 | free_dma_dom: | |
1328 | dma_ops_domain_free(dma_dom); | |
1329 | ||
1330 | return NULL; | |
1331 | } | |
1332 | ||
5b28df6f JR |
1333 | /* |
1334 | * little helper function to check whether a given protection domain is a | |
1335 | * dma_ops domain | |
1336 | */ | |
1337 | static bool dma_ops_domain(struct protection_domain *domain) | |
1338 | { | |
1339 | return domain->flags & PD_DMA_OPS_MASK; | |
1340 | } | |
1341 | ||
407d733e | 1342 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1343 | { |
b20ac0d4 | 1344 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1345 | |
38ddf41b JR |
1346 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1347 | << DEV_ENTRY_MODE_SHIFT; | |
1348 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1349 | |
b20ac0d4 | 1350 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1351 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1352 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1353 | } |
1354 | ||
1355 | static void clear_dte_entry(u16 devid) | |
1356 | { | |
15898bbc JR |
1357 | /* remove entry from the device table seen by the hardware */ |
1358 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1359 | amd_iommu_dev_table[devid].data[1] = 0; | |
1360 | amd_iommu_dev_table[devid].data[2] = 0; | |
1361 | ||
1362 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1363 | } |
1364 | ||
1365 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1366 | { | |
1367 | struct iommu_dev_data *dev_data; | |
1368 | struct amd_iommu *iommu; | |
1369 | u16 devid; | |
1370 | ||
1371 | devid = get_device_id(dev); | |
1372 | iommu = amd_iommu_rlookup_table[devid]; | |
1373 | dev_data = get_dev_data(dev); | |
1374 | ||
1375 | /* Update data structures */ | |
1376 | dev_data->domain = domain; | |
1377 | list_add(&dev_data->list, &domain->dev_list); | |
1378 | set_dte_entry(devid, domain); | |
1379 | ||
1380 | /* Do reference counting */ | |
1381 | domain->dev_iommu[iommu->index] += 1; | |
1382 | domain->dev_cnt += 1; | |
1383 | ||
1384 | /* Flush the DTE entry */ | |
3fa43655 | 1385 | iommu_flush_device(dev); |
7f760ddd JR |
1386 | } |
1387 | ||
1388 | static void do_detach(struct device *dev) | |
1389 | { | |
1390 | struct iommu_dev_data *dev_data; | |
1391 | struct amd_iommu *iommu; | |
1392 | u16 devid; | |
1393 | ||
1394 | devid = get_device_id(dev); | |
1395 | iommu = amd_iommu_rlookup_table[devid]; | |
1396 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1397 | |
1398 | /* decrease reference counters */ | |
7f760ddd JR |
1399 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1400 | dev_data->domain->dev_cnt -= 1; | |
1401 | ||
1402 | /* Update data structures */ | |
1403 | dev_data->domain = NULL; | |
1404 | list_del(&dev_data->list); | |
1405 | clear_dte_entry(devid); | |
15898bbc | 1406 | |
7f760ddd | 1407 | /* Flush the DTE entry */ |
3fa43655 | 1408 | iommu_flush_device(dev); |
2b681faf JR |
1409 | } |
1410 | ||
1411 | /* | |
1412 | * If a device is not yet associated with a domain, this function does | |
1413 | * assigns it visible for the hardware | |
1414 | */ | |
15898bbc JR |
1415 | static int __attach_device(struct device *dev, |
1416 | struct protection_domain *domain) | |
2b681faf | 1417 | { |
657cbb6b | 1418 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1419 | int ret; |
657cbb6b | 1420 | |
657cbb6b JR |
1421 | dev_data = get_dev_data(dev); |
1422 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1423 | |
657cbb6b JR |
1424 | if (!alias_data) |
1425 | return -EINVAL; | |
15898bbc | 1426 | |
2b681faf JR |
1427 | /* lock domain */ |
1428 | spin_lock(&domain->lock); | |
1429 | ||
15898bbc | 1430 | /* Some sanity checks */ |
84fe6c19 | 1431 | ret = -EBUSY; |
657cbb6b JR |
1432 | if (alias_data->domain != NULL && |
1433 | alias_data->domain != domain) | |
84fe6c19 | 1434 | goto out_unlock; |
eba6ac60 | 1435 | |
657cbb6b JR |
1436 | if (dev_data->domain != NULL && |
1437 | dev_data->domain != domain) | |
84fe6c19 | 1438 | goto out_unlock; |
15898bbc JR |
1439 | |
1440 | /* Do real assignment */ | |
7f760ddd JR |
1441 | if (dev_data->alias != dev) { |
1442 | alias_data = get_dev_data(dev_data->alias); | |
1443 | if (alias_data->domain == NULL) | |
1444 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1445 | |
1446 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1447 | } |
15898bbc | 1448 | |
7f760ddd JR |
1449 | if (dev_data->domain == NULL) |
1450 | do_attach(dev, domain); | |
eba6ac60 | 1451 | |
24100055 JR |
1452 | atomic_inc(&dev_data->bind); |
1453 | ||
84fe6c19 JL |
1454 | ret = 0; |
1455 | ||
1456 | out_unlock: | |
1457 | ||
eba6ac60 JR |
1458 | /* ready */ |
1459 | spin_unlock(&domain->lock); | |
15898bbc | 1460 | |
84fe6c19 | 1461 | return ret; |
0feae533 | 1462 | } |
b20ac0d4 | 1463 | |
407d733e JR |
1464 | /* |
1465 | * If a device is not yet associated with a domain, this function does | |
1466 | * assigns it visible for the hardware | |
1467 | */ | |
15898bbc JR |
1468 | static int attach_device(struct device *dev, |
1469 | struct protection_domain *domain) | |
0feae533 | 1470 | { |
eba6ac60 | 1471 | unsigned long flags; |
15898bbc | 1472 | int ret; |
eba6ac60 JR |
1473 | |
1474 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1475 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1476 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1477 | ||
0feae533 JR |
1478 | /* |
1479 | * We might boot into a crash-kernel here. The crashed kernel | |
1480 | * left the caches in the IOMMU dirty. So we have to flush | |
1481 | * here to evict all dirty stuff. | |
1482 | */ | |
dcd1e92e | 1483 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1484 | |
1485 | return ret; | |
b20ac0d4 JR |
1486 | } |
1487 | ||
355bf553 JR |
1488 | /* |
1489 | * Removes a device from a protection domain (unlocked) | |
1490 | */ | |
15898bbc | 1491 | static void __detach_device(struct device *dev) |
355bf553 | 1492 | { |
657cbb6b | 1493 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1494 | struct iommu_dev_data *alias_data; |
2ca76279 | 1495 | struct protection_domain *domain; |
7c392cbe | 1496 | unsigned long flags; |
c4596114 | 1497 | |
7f760ddd | 1498 | BUG_ON(!dev_data->domain); |
355bf553 | 1499 | |
2ca76279 JR |
1500 | domain = dev_data->domain; |
1501 | ||
1502 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1503 | |
7f760ddd | 1504 | if (dev_data->alias != dev) { |
24100055 | 1505 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1506 | if (atomic_dec_and_test(&alias_data->bind)) |
1507 | do_detach(dev_data->alias); | |
24100055 JR |
1508 | } |
1509 | ||
7f760ddd JR |
1510 | if (atomic_dec_and_test(&dev_data->bind)) |
1511 | do_detach(dev); | |
1512 | ||
2ca76279 | 1513 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1514 | |
1515 | /* | |
1516 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1517 | * passthrough domain if it is detached from any other domain. |
1518 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1519 | */ |
d3ad9373 JR |
1520 | if (iommu_pass_through && |
1521 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1522 | __attach_device(dev, pt_domain); |
355bf553 JR |
1523 | } |
1524 | ||
1525 | /* | |
1526 | * Removes a device from a protection domain (with devtable_lock held) | |
1527 | */ | |
15898bbc | 1528 | static void detach_device(struct device *dev) |
355bf553 JR |
1529 | { |
1530 | unsigned long flags; | |
1531 | ||
1532 | /* lock device table */ | |
1533 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1534 | __detach_device(dev); |
355bf553 JR |
1535 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1536 | } | |
e275a2a0 | 1537 | |
15898bbc JR |
1538 | /* |
1539 | * Find out the protection domain structure for a given PCI device. This | |
1540 | * will give us the pointer to the page table root for example. | |
1541 | */ | |
1542 | static struct protection_domain *domain_for_device(struct device *dev) | |
1543 | { | |
1544 | struct protection_domain *dom; | |
657cbb6b | 1545 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1546 | unsigned long flags; |
1547 | u16 devid, alias; | |
1548 | ||
657cbb6b JR |
1549 | devid = get_device_id(dev); |
1550 | alias = amd_iommu_alias_table[devid]; | |
1551 | dev_data = get_dev_data(dev); | |
1552 | alias_data = get_dev_data(dev_data->alias); | |
1553 | if (!alias_data) | |
1554 | return NULL; | |
15898bbc JR |
1555 | |
1556 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1557 | dom = dev_data->domain; |
15898bbc | 1558 | if (dom == NULL && |
657cbb6b JR |
1559 | alias_data->domain != NULL) { |
1560 | __attach_device(dev, alias_data->domain); | |
1561 | dom = alias_data->domain; | |
15898bbc JR |
1562 | } |
1563 | ||
1564 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1565 | ||
1566 | return dom; | |
1567 | } | |
1568 | ||
e275a2a0 JR |
1569 | static int device_change_notifier(struct notifier_block *nb, |
1570 | unsigned long action, void *data) | |
1571 | { | |
1572 | struct device *dev = data; | |
98fc5a69 | 1573 | u16 devid; |
e275a2a0 JR |
1574 | struct protection_domain *domain; |
1575 | struct dma_ops_domain *dma_domain; | |
1576 | struct amd_iommu *iommu; | |
1ac4cbbc | 1577 | unsigned long flags; |
e275a2a0 | 1578 | |
98fc5a69 JR |
1579 | if (!check_device(dev)) |
1580 | return 0; | |
e275a2a0 | 1581 | |
98fc5a69 JR |
1582 | devid = get_device_id(dev); |
1583 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1584 | |
1585 | switch (action) { | |
c1eee67b | 1586 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1587 | |
1588 | domain = domain_for_device(dev); | |
1589 | ||
e275a2a0 JR |
1590 | if (!domain) |
1591 | goto out; | |
a1ca331c JR |
1592 | if (iommu_pass_through) |
1593 | break; | |
15898bbc | 1594 | detach_device(dev); |
1ac4cbbc JR |
1595 | break; |
1596 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1597 | |
1598 | iommu_init_device(dev); | |
1599 | ||
1600 | domain = domain_for_device(dev); | |
1601 | ||
1ac4cbbc JR |
1602 | /* allocate a protection domain if a device is added */ |
1603 | dma_domain = find_protection_domain(devid); | |
1604 | if (dma_domain) | |
1605 | goto out; | |
87a64d52 | 1606 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1607 | if (!dma_domain) |
1608 | goto out; | |
1609 | dma_domain->target_dev = devid; | |
1610 | ||
1611 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1612 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1613 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1614 | ||
e275a2a0 | 1615 | break; |
657cbb6b JR |
1616 | case BUS_NOTIFY_DEL_DEVICE: |
1617 | ||
1618 | iommu_uninit_device(dev); | |
1619 | ||
e275a2a0 JR |
1620 | default: |
1621 | goto out; | |
1622 | } | |
1623 | ||
3fa43655 | 1624 | iommu_flush_device(dev); |
e275a2a0 JR |
1625 | iommu_completion_wait(iommu); |
1626 | ||
1627 | out: | |
1628 | return 0; | |
1629 | } | |
1630 | ||
b25ae679 | 1631 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1632 | .notifier_call = device_change_notifier, |
1633 | }; | |
355bf553 | 1634 | |
8638c491 JR |
1635 | void amd_iommu_init_notifier(void) |
1636 | { | |
1637 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1638 | } | |
1639 | ||
431b2a20 JR |
1640 | /***************************************************************************** |
1641 | * | |
1642 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1643 | * | |
1644 | *****************************************************************************/ | |
1645 | ||
1646 | /* | |
1647 | * In the dma_ops path we only have the struct device. This function | |
1648 | * finds the corresponding IOMMU, the protection domain and the | |
1649 | * requestor id for a given device. | |
1650 | * If the device is not yet associated with a domain this is also done | |
1651 | * in this function. | |
1652 | */ | |
94f6d190 | 1653 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1654 | { |
94f6d190 | 1655 | struct protection_domain *domain; |
b20ac0d4 | 1656 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1657 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1658 | |
f99c0f1c | 1659 | if (!check_device(dev)) |
94f6d190 | 1660 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1661 | |
94f6d190 JR |
1662 | domain = domain_for_device(dev); |
1663 | if (domain != NULL && !dma_ops_domain(domain)) | |
1664 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1665 | |
94f6d190 JR |
1666 | if (domain != NULL) |
1667 | return domain; | |
b20ac0d4 | 1668 | |
15898bbc | 1669 | /* Device not bount yet - bind it */ |
94f6d190 | 1670 | dma_dom = find_protection_domain(devid); |
15898bbc | 1671 | if (!dma_dom) |
94f6d190 JR |
1672 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1673 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1674 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1675 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1676 | |
94f6d190 | 1677 | return &dma_dom->domain; |
b20ac0d4 JR |
1678 | } |
1679 | ||
04bfdd84 JR |
1680 | static void update_device_table(struct protection_domain *domain) |
1681 | { | |
492667da | 1682 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1683 | |
492667da JR |
1684 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
1685 | u16 devid = get_device_id(dev_data->dev); | |
1686 | set_dte_entry(devid, domain); | |
04bfdd84 JR |
1687 | } |
1688 | } | |
1689 | ||
1690 | static void update_domain(struct protection_domain *domain) | |
1691 | { | |
1692 | if (!domain->updated) | |
1693 | return; | |
1694 | ||
1695 | update_device_table(domain); | |
b00d3bcf | 1696 | iommu_flush_domain_devices(domain); |
601367d7 | 1697 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1698 | |
1699 | domain->updated = false; | |
1700 | } | |
1701 | ||
8bda3092 JR |
1702 | /* |
1703 | * This function fetches the PTE for a given address in the aperture | |
1704 | */ | |
1705 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1706 | unsigned long address) | |
1707 | { | |
384de729 | 1708 | struct aperture_range *aperture; |
8bda3092 JR |
1709 | u64 *pte, *pte_page; |
1710 | ||
384de729 JR |
1711 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1712 | if (!aperture) | |
1713 | return NULL; | |
1714 | ||
1715 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1716 | if (!pte) { |
cbb9d729 | 1717 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1718 | GFP_ATOMIC); |
384de729 JR |
1719 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1720 | } else | |
8c8c143c | 1721 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1722 | |
04bfdd84 | 1723 | update_domain(&dom->domain); |
8bda3092 JR |
1724 | |
1725 | return pte; | |
1726 | } | |
1727 | ||
431b2a20 JR |
1728 | /* |
1729 | * This is the generic map function. It maps one 4kb page at paddr to | |
1730 | * the given address in the DMA address space for the domain. | |
1731 | */ | |
680525e0 | 1732 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1733 | unsigned long address, |
1734 | phys_addr_t paddr, | |
1735 | int direction) | |
1736 | { | |
1737 | u64 *pte, __pte; | |
1738 | ||
1739 | WARN_ON(address > dom->aperture_size); | |
1740 | ||
1741 | paddr &= PAGE_MASK; | |
1742 | ||
8bda3092 | 1743 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1744 | if (!pte) |
8fd524b3 | 1745 | return DMA_ERROR_CODE; |
cb76c322 JR |
1746 | |
1747 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1748 | ||
1749 | if (direction == DMA_TO_DEVICE) | |
1750 | __pte |= IOMMU_PTE_IR; | |
1751 | else if (direction == DMA_FROM_DEVICE) | |
1752 | __pte |= IOMMU_PTE_IW; | |
1753 | else if (direction == DMA_BIDIRECTIONAL) | |
1754 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1755 | ||
1756 | WARN_ON(*pte); | |
1757 | ||
1758 | *pte = __pte; | |
1759 | ||
1760 | return (dma_addr_t)address; | |
1761 | } | |
1762 | ||
431b2a20 JR |
1763 | /* |
1764 | * The generic unmapping function for on page in the DMA address space. | |
1765 | */ | |
680525e0 | 1766 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1767 | unsigned long address) |
1768 | { | |
384de729 | 1769 | struct aperture_range *aperture; |
cb76c322 JR |
1770 | u64 *pte; |
1771 | ||
1772 | if (address >= dom->aperture_size) | |
1773 | return; | |
1774 | ||
384de729 JR |
1775 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1776 | if (!aperture) | |
1777 | return; | |
1778 | ||
1779 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1780 | if (!pte) | |
1781 | return; | |
cb76c322 | 1782 | |
8c8c143c | 1783 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1784 | |
1785 | WARN_ON(!*pte); | |
1786 | ||
1787 | *pte = 0ULL; | |
1788 | } | |
1789 | ||
431b2a20 JR |
1790 | /* |
1791 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1792 | * contiguous memory region into DMA address space. It is used by all |
1793 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1794 | * Must be called with the domain lock held. |
1795 | */ | |
cb76c322 | 1796 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1797 | struct dma_ops_domain *dma_dom, |
1798 | phys_addr_t paddr, | |
1799 | size_t size, | |
6d4f343f | 1800 | int dir, |
832a90c3 JR |
1801 | bool align, |
1802 | u64 dma_mask) | |
cb76c322 JR |
1803 | { |
1804 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1805 | dma_addr_t address, start, ret; |
cb76c322 | 1806 | unsigned int pages; |
6d4f343f | 1807 | unsigned long align_mask = 0; |
cb76c322 JR |
1808 | int i; |
1809 | ||
e3c449f5 | 1810 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1811 | paddr &= PAGE_MASK; |
1812 | ||
8ecaf8f1 JR |
1813 | INC_STATS_COUNTER(total_map_requests); |
1814 | ||
c1858976 JR |
1815 | if (pages > 1) |
1816 | INC_STATS_COUNTER(cross_page); | |
1817 | ||
6d4f343f JR |
1818 | if (align) |
1819 | align_mask = (1UL << get_order(size)) - 1; | |
1820 | ||
11b83888 | 1821 | retry: |
832a90c3 JR |
1822 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1823 | dma_mask); | |
8fd524b3 | 1824 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1825 | /* |
1826 | * setting next_address here will let the address | |
1827 | * allocator only scan the new allocated range in the | |
1828 | * first run. This is a small optimization. | |
1829 | */ | |
1830 | dma_dom->next_address = dma_dom->aperture_size; | |
1831 | ||
576175c2 | 1832 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1833 | goto out; |
1834 | ||
1835 | /* | |
af901ca1 | 1836 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1837 | * allocation again |
1838 | */ | |
1839 | goto retry; | |
1840 | } | |
cb76c322 JR |
1841 | |
1842 | start = address; | |
1843 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1844 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1845 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1846 | goto out_unmap; |
1847 | ||
cb76c322 JR |
1848 | paddr += PAGE_SIZE; |
1849 | start += PAGE_SIZE; | |
1850 | } | |
1851 | address += offset; | |
1852 | ||
5774f7c5 JR |
1853 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1854 | ||
afa9fdc2 | 1855 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1856 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1857 | dma_dom->need_flush = false; |
318afd41 | 1858 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1859 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1860 | |
cb76c322 JR |
1861 | out: |
1862 | return address; | |
53812c11 JR |
1863 | |
1864 | out_unmap: | |
1865 | ||
1866 | for (--i; i >= 0; --i) { | |
1867 | start -= PAGE_SIZE; | |
680525e0 | 1868 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1869 | } |
1870 | ||
1871 | dma_ops_free_addresses(dma_dom, address, pages); | |
1872 | ||
8fd524b3 | 1873 | return DMA_ERROR_CODE; |
cb76c322 JR |
1874 | } |
1875 | ||
431b2a20 JR |
1876 | /* |
1877 | * Does the reverse of the __map_single function. Must be called with | |
1878 | * the domain lock held too | |
1879 | */ | |
cd8c82e8 | 1880 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1881 | dma_addr_t dma_addr, |
1882 | size_t size, | |
1883 | int dir) | |
1884 | { | |
04e0463e | 1885 | dma_addr_t flush_addr; |
cb76c322 JR |
1886 | dma_addr_t i, start; |
1887 | unsigned int pages; | |
1888 | ||
8fd524b3 | 1889 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1890 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1891 | return; |
1892 | ||
04e0463e | 1893 | flush_addr = dma_addr; |
e3c449f5 | 1894 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1895 | dma_addr &= PAGE_MASK; |
1896 | start = dma_addr; | |
1897 | ||
1898 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1899 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1900 | start += PAGE_SIZE; |
1901 | } | |
1902 | ||
5774f7c5 JR |
1903 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1904 | ||
cb76c322 | 1905 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1906 | |
80be308d | 1907 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
04e0463e | 1908 | iommu_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
1909 | dma_dom->need_flush = false; |
1910 | } | |
cb76c322 JR |
1911 | } |
1912 | ||
431b2a20 JR |
1913 | /* |
1914 | * The exported map_single function for dma_ops. | |
1915 | */ | |
51491367 FT |
1916 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1917 | unsigned long offset, size_t size, | |
1918 | enum dma_data_direction dir, | |
1919 | struct dma_attrs *attrs) | |
4da70b9e JR |
1920 | { |
1921 | unsigned long flags; | |
4da70b9e | 1922 | struct protection_domain *domain; |
4da70b9e | 1923 | dma_addr_t addr; |
832a90c3 | 1924 | u64 dma_mask; |
51491367 | 1925 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1926 | |
0f2a86f2 JR |
1927 | INC_STATS_COUNTER(cnt_map_single); |
1928 | ||
94f6d190 JR |
1929 | domain = get_domain(dev); |
1930 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 1931 | return (dma_addr_t)paddr; |
94f6d190 JR |
1932 | else if (IS_ERR(domain)) |
1933 | return DMA_ERROR_CODE; | |
4da70b9e | 1934 | |
f99c0f1c JR |
1935 | dma_mask = *dev->dma_mask; |
1936 | ||
4da70b9e | 1937 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 1938 | |
cd8c82e8 | 1939 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 1940 | dma_mask); |
8fd524b3 | 1941 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1942 | goto out; |
1943 | ||
0518a3a4 | 1944 | iommu_flush_complete(domain); |
4da70b9e JR |
1945 | |
1946 | out: | |
1947 | spin_unlock_irqrestore(&domain->lock, flags); | |
1948 | ||
1949 | return addr; | |
1950 | } | |
1951 | ||
431b2a20 JR |
1952 | /* |
1953 | * The exported unmap_single function for dma_ops. | |
1954 | */ | |
51491367 FT |
1955 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1956 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1957 | { |
1958 | unsigned long flags; | |
4da70b9e | 1959 | struct protection_domain *domain; |
4da70b9e | 1960 | |
146a6917 JR |
1961 | INC_STATS_COUNTER(cnt_unmap_single); |
1962 | ||
94f6d190 JR |
1963 | domain = get_domain(dev); |
1964 | if (IS_ERR(domain)) | |
5b28df6f JR |
1965 | return; |
1966 | ||
4da70b9e JR |
1967 | spin_lock_irqsave(&domain->lock, flags); |
1968 | ||
cd8c82e8 | 1969 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 1970 | |
0518a3a4 | 1971 | iommu_flush_complete(domain); |
4da70b9e JR |
1972 | |
1973 | spin_unlock_irqrestore(&domain->lock, flags); | |
1974 | } | |
1975 | ||
431b2a20 JR |
1976 | /* |
1977 | * This is a special map_sg function which is used if we should map a | |
1978 | * device which is not handled by an AMD IOMMU in the system. | |
1979 | */ | |
65b050ad JR |
1980 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1981 | int nelems, int dir) | |
1982 | { | |
1983 | struct scatterlist *s; | |
1984 | int i; | |
1985 | ||
1986 | for_each_sg(sglist, s, nelems, i) { | |
1987 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1988 | s->dma_length = s->length; | |
1989 | } | |
1990 | ||
1991 | return nelems; | |
1992 | } | |
1993 | ||
431b2a20 JR |
1994 | /* |
1995 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1996 | * lists). | |
1997 | */ | |
65b050ad | 1998 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1999 | int nelems, enum dma_data_direction dir, |
2000 | struct dma_attrs *attrs) | |
65b050ad JR |
2001 | { |
2002 | unsigned long flags; | |
65b050ad | 2003 | struct protection_domain *domain; |
65b050ad JR |
2004 | int i; |
2005 | struct scatterlist *s; | |
2006 | phys_addr_t paddr; | |
2007 | int mapped_elems = 0; | |
832a90c3 | 2008 | u64 dma_mask; |
65b050ad | 2009 | |
d03f067a JR |
2010 | INC_STATS_COUNTER(cnt_map_sg); |
2011 | ||
94f6d190 JR |
2012 | domain = get_domain(dev); |
2013 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2014 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2015 | else if (IS_ERR(domain)) |
2016 | return 0; | |
dbcc112e | 2017 | |
832a90c3 | 2018 | dma_mask = *dev->dma_mask; |
65b050ad | 2019 | |
65b050ad JR |
2020 | spin_lock_irqsave(&domain->lock, flags); |
2021 | ||
2022 | for_each_sg(sglist, s, nelems, i) { | |
2023 | paddr = sg_phys(s); | |
2024 | ||
cd8c82e8 | 2025 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2026 | paddr, s->length, dir, false, |
2027 | dma_mask); | |
65b050ad JR |
2028 | |
2029 | if (s->dma_address) { | |
2030 | s->dma_length = s->length; | |
2031 | mapped_elems++; | |
2032 | } else | |
2033 | goto unmap; | |
65b050ad JR |
2034 | } |
2035 | ||
0518a3a4 | 2036 | iommu_flush_complete(domain); |
65b050ad JR |
2037 | |
2038 | out: | |
2039 | spin_unlock_irqrestore(&domain->lock, flags); | |
2040 | ||
2041 | return mapped_elems; | |
2042 | unmap: | |
2043 | for_each_sg(sglist, s, mapped_elems, i) { | |
2044 | if (s->dma_address) | |
cd8c82e8 | 2045 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2046 | s->dma_length, dir); |
2047 | s->dma_address = s->dma_length = 0; | |
2048 | } | |
2049 | ||
2050 | mapped_elems = 0; | |
2051 | ||
2052 | goto out; | |
2053 | } | |
2054 | ||
431b2a20 JR |
2055 | /* |
2056 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2057 | * lists). | |
2058 | */ | |
65b050ad | 2059 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2060 | int nelems, enum dma_data_direction dir, |
2061 | struct dma_attrs *attrs) | |
65b050ad JR |
2062 | { |
2063 | unsigned long flags; | |
65b050ad JR |
2064 | struct protection_domain *domain; |
2065 | struct scatterlist *s; | |
65b050ad JR |
2066 | int i; |
2067 | ||
55877a6b JR |
2068 | INC_STATS_COUNTER(cnt_unmap_sg); |
2069 | ||
94f6d190 JR |
2070 | domain = get_domain(dev); |
2071 | if (IS_ERR(domain)) | |
5b28df6f JR |
2072 | return; |
2073 | ||
65b050ad JR |
2074 | spin_lock_irqsave(&domain->lock, flags); |
2075 | ||
2076 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2077 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2078 | s->dma_length, dir); |
65b050ad JR |
2079 | s->dma_address = s->dma_length = 0; |
2080 | } | |
2081 | ||
0518a3a4 | 2082 | iommu_flush_complete(domain); |
65b050ad JR |
2083 | |
2084 | spin_unlock_irqrestore(&domain->lock, flags); | |
2085 | } | |
2086 | ||
431b2a20 JR |
2087 | /* |
2088 | * The exported alloc_coherent function for dma_ops. | |
2089 | */ | |
5d8b53cf JR |
2090 | static void *alloc_coherent(struct device *dev, size_t size, |
2091 | dma_addr_t *dma_addr, gfp_t flag) | |
2092 | { | |
2093 | unsigned long flags; | |
2094 | void *virt_addr; | |
5d8b53cf | 2095 | struct protection_domain *domain; |
5d8b53cf | 2096 | phys_addr_t paddr; |
832a90c3 | 2097 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2098 | |
c8f0fb36 JR |
2099 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2100 | ||
94f6d190 JR |
2101 | domain = get_domain(dev); |
2102 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2103 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2104 | *dma_addr = __pa(virt_addr); | |
2105 | return virt_addr; | |
94f6d190 JR |
2106 | } else if (IS_ERR(domain)) |
2107 | return NULL; | |
5d8b53cf | 2108 | |
f99c0f1c JR |
2109 | dma_mask = dev->coherent_dma_mask; |
2110 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2111 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2112 | |
2113 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2114 | if (!virt_addr) | |
b25ae679 | 2115 | return NULL; |
5d8b53cf | 2116 | |
5d8b53cf JR |
2117 | paddr = virt_to_phys(virt_addr); |
2118 | ||
832a90c3 JR |
2119 | if (!dma_mask) |
2120 | dma_mask = *dev->dma_mask; | |
2121 | ||
5d8b53cf JR |
2122 | spin_lock_irqsave(&domain->lock, flags); |
2123 | ||
cd8c82e8 | 2124 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2125 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2126 | |
8fd524b3 | 2127 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2128 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2129 | goto out_free; |
367d04c4 | 2130 | } |
5d8b53cf | 2131 | |
0518a3a4 | 2132 | iommu_flush_complete(domain); |
5d8b53cf | 2133 | |
5d8b53cf JR |
2134 | spin_unlock_irqrestore(&domain->lock, flags); |
2135 | ||
2136 | return virt_addr; | |
5b28df6f JR |
2137 | |
2138 | out_free: | |
2139 | ||
2140 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2141 | ||
2142 | return NULL; | |
5d8b53cf JR |
2143 | } |
2144 | ||
431b2a20 JR |
2145 | /* |
2146 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2147 | */ |
5d8b53cf JR |
2148 | static void free_coherent(struct device *dev, size_t size, |
2149 | void *virt_addr, dma_addr_t dma_addr) | |
2150 | { | |
2151 | unsigned long flags; | |
5d8b53cf | 2152 | struct protection_domain *domain; |
5d8b53cf | 2153 | |
5d31ee7e JR |
2154 | INC_STATS_COUNTER(cnt_free_coherent); |
2155 | ||
94f6d190 JR |
2156 | domain = get_domain(dev); |
2157 | if (IS_ERR(domain)) | |
5b28df6f JR |
2158 | goto free_mem; |
2159 | ||
5d8b53cf JR |
2160 | spin_lock_irqsave(&domain->lock, flags); |
2161 | ||
cd8c82e8 | 2162 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2163 | |
0518a3a4 | 2164 | iommu_flush_complete(domain); |
5d8b53cf JR |
2165 | |
2166 | spin_unlock_irqrestore(&domain->lock, flags); | |
2167 | ||
2168 | free_mem: | |
2169 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2170 | } | |
2171 | ||
b39ba6ad JR |
2172 | /* |
2173 | * This function is called by the DMA layer to find out if we can handle a | |
2174 | * particular device. It is part of the dma_ops. | |
2175 | */ | |
2176 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2177 | { | |
420aef8a | 2178 | return check_device(dev); |
b39ba6ad JR |
2179 | } |
2180 | ||
c432f3df | 2181 | /* |
431b2a20 JR |
2182 | * The function for pre-allocating protection domains. |
2183 | * | |
c432f3df JR |
2184 | * If the driver core informs the DMA layer if a driver grabs a device |
2185 | * we don't need to preallocate the protection domains anymore. | |
2186 | * For now we have to. | |
2187 | */ | |
0e93dd88 | 2188 | static void prealloc_protection_domains(void) |
c432f3df JR |
2189 | { |
2190 | struct pci_dev *dev = NULL; | |
2191 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2192 | u16 devid; |
c432f3df | 2193 | |
d18c69d3 | 2194 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2195 | |
2196 | /* Do we handle this device? */ | |
2197 | if (!check_device(&dev->dev)) | |
c432f3df | 2198 | continue; |
98fc5a69 JR |
2199 | |
2200 | /* Is there already any domain for it? */ | |
15898bbc | 2201 | if (domain_for_device(&dev->dev)) |
c432f3df | 2202 | continue; |
98fc5a69 JR |
2203 | |
2204 | devid = get_device_id(&dev->dev); | |
2205 | ||
87a64d52 | 2206 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2207 | if (!dma_dom) |
2208 | continue; | |
2209 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2210 | dma_dom->target_dev = devid; |
2211 | ||
15898bbc | 2212 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2213 | |
bd60b735 | 2214 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2215 | } |
2216 | } | |
2217 | ||
160c1d8e | 2218 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2219 | .alloc_coherent = alloc_coherent, |
2220 | .free_coherent = free_coherent, | |
51491367 FT |
2221 | .map_page = map_page, |
2222 | .unmap_page = unmap_page, | |
6631ee9d JR |
2223 | .map_sg = map_sg, |
2224 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2225 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2226 | }; |
2227 | ||
431b2a20 JR |
2228 | /* |
2229 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2230 | */ | |
f5325094 JR |
2231 | |
2232 | void __init amd_iommu_init_api(void) | |
2233 | { | |
2234 | register_iommu(&amd_iommu_ops); | |
2235 | } | |
2236 | ||
6631ee9d JR |
2237 | int __init amd_iommu_init_dma_ops(void) |
2238 | { | |
2239 | struct amd_iommu *iommu; | |
6631ee9d JR |
2240 | int ret; |
2241 | ||
431b2a20 JR |
2242 | /* |
2243 | * first allocate a default protection domain for every IOMMU we | |
2244 | * found in the system. Devices not assigned to any other | |
2245 | * protection domain will be assigned to the default one. | |
2246 | */ | |
3bd22172 | 2247 | for_each_iommu(iommu) { |
87a64d52 | 2248 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2249 | if (iommu->default_dom == NULL) |
2250 | return -ENOMEM; | |
e2dc14a2 | 2251 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2252 | ret = iommu_init_unity_mappings(iommu); |
2253 | if (ret) | |
2254 | goto free_domains; | |
2255 | } | |
2256 | ||
431b2a20 | 2257 | /* |
8793abeb | 2258 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2259 | */ |
8793abeb | 2260 | prealloc_protection_domains(); |
6631ee9d JR |
2261 | |
2262 | iommu_detected = 1; | |
75f1cdf1 | 2263 | swiotlb = 0; |
6631ee9d | 2264 | |
431b2a20 | 2265 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2266 | dma_ops = &amd_iommu_dma_ops; |
2267 | ||
7f26508b JR |
2268 | amd_iommu_stats_init(); |
2269 | ||
6631ee9d JR |
2270 | return 0; |
2271 | ||
2272 | free_domains: | |
2273 | ||
3bd22172 | 2274 | for_each_iommu(iommu) { |
6631ee9d JR |
2275 | if (iommu->default_dom) |
2276 | dma_ops_domain_free(iommu->default_dom); | |
2277 | } | |
2278 | ||
2279 | return ret; | |
2280 | } | |
6d98cd80 JR |
2281 | |
2282 | /***************************************************************************** | |
2283 | * | |
2284 | * The following functions belong to the exported interface of AMD IOMMU | |
2285 | * | |
2286 | * This interface allows access to lower level functions of the IOMMU | |
2287 | * like protection domain handling and assignement of devices to domains | |
2288 | * which is not possible with the dma_ops interface. | |
2289 | * | |
2290 | *****************************************************************************/ | |
2291 | ||
6d98cd80 JR |
2292 | static void cleanup_domain(struct protection_domain *domain) |
2293 | { | |
492667da | 2294 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2295 | unsigned long flags; |
6d98cd80 JR |
2296 | |
2297 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2298 | ||
492667da JR |
2299 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2300 | struct device *dev = dev_data->dev; | |
2301 | ||
04e856c0 | 2302 | __detach_device(dev); |
492667da JR |
2303 | atomic_set(&dev_data->bind, 0); |
2304 | } | |
6d98cd80 JR |
2305 | |
2306 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2307 | } | |
2308 | ||
2650815f JR |
2309 | static void protection_domain_free(struct protection_domain *domain) |
2310 | { | |
2311 | if (!domain) | |
2312 | return; | |
2313 | ||
aeb26f55 JR |
2314 | del_domain_from_list(domain); |
2315 | ||
2650815f JR |
2316 | if (domain->id) |
2317 | domain_id_free(domain->id); | |
2318 | ||
2319 | kfree(domain); | |
2320 | } | |
2321 | ||
2322 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2323 | { |
2324 | struct protection_domain *domain; | |
2325 | ||
2326 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2327 | if (!domain) | |
2650815f | 2328 | return NULL; |
c156e347 JR |
2329 | |
2330 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2331 | mutex_init(&domain->api_lock); |
c156e347 JR |
2332 | domain->id = domain_id_alloc(); |
2333 | if (!domain->id) | |
2650815f | 2334 | goto out_err; |
7c392cbe | 2335 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2336 | |
aeb26f55 JR |
2337 | add_domain_to_list(domain); |
2338 | ||
2650815f JR |
2339 | return domain; |
2340 | ||
2341 | out_err: | |
2342 | kfree(domain); | |
2343 | ||
2344 | return NULL; | |
2345 | } | |
2346 | ||
2347 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2348 | { | |
2349 | struct protection_domain *domain; | |
2350 | ||
2351 | domain = protection_domain_alloc(); | |
2352 | if (!domain) | |
c156e347 | 2353 | goto out_free; |
2650815f JR |
2354 | |
2355 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2356 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2357 | if (!domain->pt_root) | |
2358 | goto out_free; | |
2359 | ||
2360 | dom->priv = domain; | |
2361 | ||
2362 | return 0; | |
2363 | ||
2364 | out_free: | |
2650815f | 2365 | protection_domain_free(domain); |
c156e347 JR |
2366 | |
2367 | return -ENOMEM; | |
2368 | } | |
2369 | ||
98383fc3 JR |
2370 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2371 | { | |
2372 | struct protection_domain *domain = dom->priv; | |
2373 | ||
2374 | if (!domain) | |
2375 | return; | |
2376 | ||
2377 | if (domain->dev_cnt > 0) | |
2378 | cleanup_domain(domain); | |
2379 | ||
2380 | BUG_ON(domain->dev_cnt != 0); | |
2381 | ||
2382 | free_pagetable(domain); | |
2383 | ||
8b408fe4 | 2384 | protection_domain_free(domain); |
98383fc3 JR |
2385 | |
2386 | dom->priv = NULL; | |
2387 | } | |
2388 | ||
684f2888 JR |
2389 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2390 | struct device *dev) | |
2391 | { | |
657cbb6b | 2392 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2393 | struct amd_iommu *iommu; |
684f2888 JR |
2394 | u16 devid; |
2395 | ||
98fc5a69 | 2396 | if (!check_device(dev)) |
684f2888 JR |
2397 | return; |
2398 | ||
98fc5a69 | 2399 | devid = get_device_id(dev); |
684f2888 | 2400 | |
657cbb6b | 2401 | if (dev_data->domain != NULL) |
15898bbc | 2402 | detach_device(dev); |
684f2888 JR |
2403 | |
2404 | iommu = amd_iommu_rlookup_table[devid]; | |
2405 | if (!iommu) | |
2406 | return; | |
2407 | ||
3fa43655 | 2408 | iommu_flush_device(dev); |
684f2888 JR |
2409 | iommu_completion_wait(iommu); |
2410 | } | |
2411 | ||
01106066 JR |
2412 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2413 | struct device *dev) | |
2414 | { | |
2415 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2416 | struct iommu_dev_data *dev_data; |
01106066 | 2417 | struct amd_iommu *iommu; |
15898bbc | 2418 | int ret; |
01106066 JR |
2419 | u16 devid; |
2420 | ||
98fc5a69 | 2421 | if (!check_device(dev)) |
01106066 JR |
2422 | return -EINVAL; |
2423 | ||
657cbb6b JR |
2424 | dev_data = dev->archdata.iommu; |
2425 | ||
98fc5a69 | 2426 | devid = get_device_id(dev); |
01106066 JR |
2427 | |
2428 | iommu = amd_iommu_rlookup_table[devid]; | |
2429 | if (!iommu) | |
2430 | return -EINVAL; | |
2431 | ||
657cbb6b | 2432 | if (dev_data->domain) |
15898bbc | 2433 | detach_device(dev); |
01106066 | 2434 | |
15898bbc | 2435 | ret = attach_device(dev, domain); |
01106066 JR |
2436 | |
2437 | iommu_completion_wait(iommu); | |
2438 | ||
15898bbc | 2439 | return ret; |
01106066 JR |
2440 | } |
2441 | ||
468e2366 JR |
2442 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2443 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2444 | { |
468e2366 | 2445 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2446 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2447 | int prot = 0; |
2448 | int ret; | |
2449 | ||
2450 | if (iommu_prot & IOMMU_READ) | |
2451 | prot |= IOMMU_PROT_IR; | |
2452 | if (iommu_prot & IOMMU_WRITE) | |
2453 | prot |= IOMMU_PROT_IW; | |
2454 | ||
5d214fe6 | 2455 | mutex_lock(&domain->api_lock); |
795e74f7 | 2456 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2457 | mutex_unlock(&domain->api_lock); |
2458 | ||
795e74f7 | 2459 | return ret; |
c6229ca6 JR |
2460 | } |
2461 | ||
468e2366 JR |
2462 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2463 | int gfp_order) | |
eb74ff6c | 2464 | { |
eb74ff6c | 2465 | struct protection_domain *domain = dom->priv; |
468e2366 | 2466 | unsigned long page_size, unmap_size; |
eb74ff6c | 2467 | |
468e2366 | 2468 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2469 | |
5d214fe6 | 2470 | mutex_lock(&domain->api_lock); |
468e2366 | 2471 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2472 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2473 | |
601367d7 | 2474 | iommu_flush_tlb_pde(domain); |
5d214fe6 | 2475 | |
468e2366 | 2476 | return get_order(unmap_size); |
eb74ff6c JR |
2477 | } |
2478 | ||
645c4c8d JR |
2479 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2480 | unsigned long iova) | |
2481 | { | |
2482 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2483 | unsigned long offset_mask; |
645c4c8d | 2484 | phys_addr_t paddr; |
f03152bb | 2485 | u64 *pte, __pte; |
645c4c8d | 2486 | |
24cd7723 | 2487 | pte = fetch_pte(domain, iova); |
645c4c8d | 2488 | |
a6d41a40 | 2489 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2490 | return 0; |
2491 | ||
f03152bb JR |
2492 | if (PM_PTE_LEVEL(*pte) == 0) |
2493 | offset_mask = PAGE_SIZE - 1; | |
2494 | else | |
2495 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2496 | ||
2497 | __pte = *pte & PM_ADDR_MASK; | |
2498 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2499 | |
2500 | return paddr; | |
2501 | } | |
2502 | ||
dbb9fd86 SY |
2503 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2504 | unsigned long cap) | |
2505 | { | |
80a506b8 JR |
2506 | switch (cap) { |
2507 | case IOMMU_CAP_CACHE_COHERENCY: | |
2508 | return 1; | |
2509 | } | |
2510 | ||
dbb9fd86 SY |
2511 | return 0; |
2512 | } | |
2513 | ||
26961efe JR |
2514 | static struct iommu_ops amd_iommu_ops = { |
2515 | .domain_init = amd_iommu_domain_init, | |
2516 | .domain_destroy = amd_iommu_domain_destroy, | |
2517 | .attach_dev = amd_iommu_attach_device, | |
2518 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2519 | .map = amd_iommu_map, |
2520 | .unmap = amd_iommu_unmap, | |
26961efe | 2521 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2522 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2523 | }; |
2524 | ||
0feae533 JR |
2525 | /***************************************************************************** |
2526 | * | |
2527 | * The next functions do a basic initialization of IOMMU for pass through | |
2528 | * mode | |
2529 | * | |
2530 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2531 | * DMA-API translation. | |
2532 | * | |
2533 | *****************************************************************************/ | |
2534 | ||
2535 | int __init amd_iommu_init_passthrough(void) | |
2536 | { | |
15898bbc | 2537 | struct amd_iommu *iommu; |
0feae533 | 2538 | struct pci_dev *dev = NULL; |
15898bbc | 2539 | u16 devid; |
0feae533 | 2540 | |
af901ca1 | 2541 | /* allocate passthrough domain */ |
0feae533 JR |
2542 | pt_domain = protection_domain_alloc(); |
2543 | if (!pt_domain) | |
2544 | return -ENOMEM; | |
2545 | ||
2546 | pt_domain->mode |= PAGE_MODE_NONE; | |
2547 | ||
6c54aabd | 2548 | for_each_pci_dev(dev) { |
98fc5a69 | 2549 | if (!check_device(&dev->dev)) |
0feae533 JR |
2550 | continue; |
2551 | ||
98fc5a69 JR |
2552 | devid = get_device_id(&dev->dev); |
2553 | ||
15898bbc | 2554 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2555 | if (!iommu) |
2556 | continue; | |
2557 | ||
15898bbc | 2558 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2559 | } |
2560 | ||
2561 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2562 | ||
2563 | return 0; | |
2564 | } |