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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
bd0e5211 | 61 | |
7f26508b JR |
62 | #ifdef CONFIG_AMD_IOMMU_STATS |
63 | ||
64 | /* | |
65 | * Initialization code for statistics collection | |
66 | */ | |
67 | ||
da49f6df | 68 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 69 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 70 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 71 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 72 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 73 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 74 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 75 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 76 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 77 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 78 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 79 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 80 | |
7f26508b JR |
81 | static struct dentry *stats_dir; |
82 | static struct dentry *de_isolate; | |
83 | static struct dentry *de_fflush; | |
84 | ||
85 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
86 | { | |
87 | if (stats_dir == NULL) | |
88 | return; | |
89 | ||
90 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
91 | &cnt->value); | |
92 | } | |
93 | ||
94 | static void amd_iommu_stats_init(void) | |
95 | { | |
96 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
97 | if (stats_dir == NULL) | |
98 | return; | |
99 | ||
100 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
101 | (u32 *)&amd_iommu_isolate); | |
102 | ||
103 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
104 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
105 | |
106 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 107 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 108 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 109 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 110 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 111 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 112 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 113 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 114 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 115 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 116 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 117 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
118 | } |
119 | ||
120 | #endif | |
121 | ||
431b2a20 | 122 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
123 | static int iommu_has_npcache(struct amd_iommu *iommu) |
124 | { | |
ae9b9403 | 125 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
126 | } |
127 | ||
a80dc3e0 JR |
128 | /**************************************************************************** |
129 | * | |
130 | * Interrupt handling functions | |
131 | * | |
132 | ****************************************************************************/ | |
133 | ||
90008ee4 JR |
134 | static void iommu_print_event(void *__evt) |
135 | { | |
136 | u32 *event = __evt; | |
137 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
138 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
139 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
140 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
141 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
142 | ||
143 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
144 | ||
145 | switch (type) { | |
146 | case EVENT_TYPE_ILL_DEV: | |
147 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
148 | "address=0x%016llx flags=0x%04x]\n", | |
149 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
150 | address, flags); | |
151 | break; | |
152 | case EVENT_TYPE_IO_FAULT: | |
153 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
154 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
155 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
156 | domid, address, flags); | |
157 | break; | |
158 | case EVENT_TYPE_DEV_TAB_ERR: | |
159 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
160 | "address=0x%016llx flags=0x%04x]\n", | |
161 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
162 | address, flags); | |
163 | break; | |
164 | case EVENT_TYPE_PAGE_TAB_ERR: | |
165 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
166 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
167 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
168 | domid, address, flags); | |
169 | break; | |
170 | case EVENT_TYPE_ILL_CMD: | |
171 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
172 | break; | |
173 | case EVENT_TYPE_CMD_HARD_ERR: | |
174 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
175 | "flags=0x%04x]\n", address, flags); | |
176 | break; | |
177 | case EVENT_TYPE_IOTLB_INV_TO: | |
178 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
179 | "address=0x%016llx]\n", | |
180 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
181 | address); | |
182 | break; | |
183 | case EVENT_TYPE_INV_DEV_REQ: | |
184 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
185 | "address=0x%016llx flags=0x%04x]\n", | |
186 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
187 | address, flags); | |
188 | break; | |
189 | default: | |
190 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
191 | } | |
192 | } | |
193 | ||
194 | static void iommu_poll_events(struct amd_iommu *iommu) | |
195 | { | |
196 | u32 head, tail; | |
197 | unsigned long flags; | |
198 | ||
199 | spin_lock_irqsave(&iommu->lock, flags); | |
200 | ||
201 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
202 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
203 | ||
204 | while (head != tail) { | |
205 | iommu_print_event(iommu->evt_buf + head); | |
206 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
207 | } | |
208 | ||
209 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
210 | ||
211 | spin_unlock_irqrestore(&iommu->lock, flags); | |
212 | } | |
213 | ||
a80dc3e0 JR |
214 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
215 | { | |
90008ee4 JR |
216 | struct amd_iommu *iommu; |
217 | ||
218 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
219 | iommu_poll_events(iommu); | |
220 | ||
221 | return IRQ_HANDLED; | |
a80dc3e0 JR |
222 | } |
223 | ||
431b2a20 JR |
224 | /**************************************************************************** |
225 | * | |
226 | * IOMMU command queuing functions | |
227 | * | |
228 | ****************************************************************************/ | |
229 | ||
230 | /* | |
231 | * Writes the command to the IOMMUs command buffer and informs the | |
232 | * hardware about the new command. Must be called with iommu->lock held. | |
233 | */ | |
d6449536 | 234 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
235 | { |
236 | u32 tail, head; | |
237 | u8 *target; | |
238 | ||
239 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 240 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
241 | memcpy_toio(target, cmd, sizeof(*cmd)); |
242 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
243 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
244 | if (tail == head) | |
245 | return -ENOMEM; | |
246 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
431b2a20 JR |
251 | /* |
252 | * General queuing function for commands. Takes iommu->lock and calls | |
253 | * __iommu_queue_command(). | |
254 | */ | |
d6449536 | 255 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
256 | { |
257 | unsigned long flags; | |
258 | int ret; | |
259 | ||
260 | spin_lock_irqsave(&iommu->lock, flags); | |
261 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 262 | if (!ret) |
0cfd7aa9 | 263 | iommu->need_sync = true; |
a19ae1ec JR |
264 | spin_unlock_irqrestore(&iommu->lock, flags); |
265 | ||
266 | return ret; | |
267 | } | |
268 | ||
8d201968 JR |
269 | /* |
270 | * This function waits until an IOMMU has completed a completion | |
271 | * wait command | |
272 | */ | |
273 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
274 | { | |
275 | int ready = 0; | |
276 | unsigned status = 0; | |
277 | unsigned long i = 0; | |
278 | ||
da49f6df JR |
279 | INC_STATS_COUNTER(compl_wait); |
280 | ||
8d201968 JR |
281 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
282 | ++i; | |
283 | /* wait for the bit to become one */ | |
284 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
285 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
286 | } | |
287 | ||
288 | /* set bit back to zero */ | |
289 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
290 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
291 | ||
292 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
293 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
294 | } | |
295 | ||
296 | /* | |
297 | * This function queues a completion wait command into the command | |
298 | * buffer of an IOMMU | |
299 | */ | |
300 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
301 | { | |
302 | struct iommu_cmd cmd; | |
303 | ||
304 | memset(&cmd, 0, sizeof(cmd)); | |
305 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
306 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
307 | ||
308 | return __iommu_queue_command(iommu, &cmd); | |
309 | } | |
310 | ||
431b2a20 JR |
311 | /* |
312 | * This function is called whenever we need to ensure that the IOMMU has | |
313 | * completed execution of all commands we sent. It sends a | |
314 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
315 | * us about that by writing a value to a physical address we pass with | |
316 | * the command. | |
317 | */ | |
a19ae1ec JR |
318 | static int iommu_completion_wait(struct amd_iommu *iommu) |
319 | { | |
8d201968 JR |
320 | int ret = 0; |
321 | unsigned long flags; | |
a19ae1ec | 322 | |
7e4f88da JR |
323 | spin_lock_irqsave(&iommu->lock, flags); |
324 | ||
09ee17eb JR |
325 | if (!iommu->need_sync) |
326 | goto out; | |
327 | ||
8d201968 | 328 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 329 | |
0cfd7aa9 | 330 | iommu->need_sync = false; |
a19ae1ec JR |
331 | |
332 | if (ret) | |
7e4f88da | 333 | goto out; |
a19ae1ec | 334 | |
8d201968 | 335 | __iommu_wait_for_completion(iommu); |
84df8175 | 336 | |
7e4f88da JR |
337 | out: |
338 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
339 | |
340 | return 0; | |
341 | } | |
342 | ||
431b2a20 JR |
343 | /* |
344 | * Command send function for invalidating a device table entry | |
345 | */ | |
a19ae1ec JR |
346 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
347 | { | |
d6449536 | 348 | struct iommu_cmd cmd; |
ee2fa743 | 349 | int ret; |
a19ae1ec JR |
350 | |
351 | BUG_ON(iommu == NULL); | |
352 | ||
353 | memset(&cmd, 0, sizeof(cmd)); | |
354 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
355 | cmd.data[0] = devid; | |
356 | ||
ee2fa743 JR |
357 | ret = iommu_queue_command(iommu, &cmd); |
358 | ||
ee2fa743 | 359 | return ret; |
a19ae1ec JR |
360 | } |
361 | ||
237b6f33 JR |
362 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
363 | u16 domid, int pde, int s) | |
364 | { | |
365 | memset(cmd, 0, sizeof(*cmd)); | |
366 | address &= PAGE_MASK; | |
367 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
368 | cmd->data[1] |= domid; | |
369 | cmd->data[2] = lower_32_bits(address); | |
370 | cmd->data[3] = upper_32_bits(address); | |
371 | if (s) /* size bit - we flush more than one 4kb page */ | |
372 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
373 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
374 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
375 | } | |
376 | ||
431b2a20 JR |
377 | /* |
378 | * Generic command send function for invalidaing TLB entries | |
379 | */ | |
a19ae1ec JR |
380 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
381 | u64 address, u16 domid, int pde, int s) | |
382 | { | |
d6449536 | 383 | struct iommu_cmd cmd; |
ee2fa743 | 384 | int ret; |
a19ae1ec | 385 | |
237b6f33 | 386 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 387 | |
ee2fa743 JR |
388 | ret = iommu_queue_command(iommu, &cmd); |
389 | ||
ee2fa743 | 390 | return ret; |
a19ae1ec JR |
391 | } |
392 | ||
431b2a20 JR |
393 | /* |
394 | * TLB invalidation function which is called from the mapping functions. | |
395 | * It invalidates a single PTE if the range to flush is within a single | |
396 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
397 | */ | |
a19ae1ec JR |
398 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
399 | u64 address, size_t size) | |
400 | { | |
999ba417 | 401 | int s = 0; |
e3c449f5 | 402 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
403 | |
404 | address &= PAGE_MASK; | |
405 | ||
999ba417 JR |
406 | if (pages > 1) { |
407 | /* | |
408 | * If we have to flush more than one page, flush all | |
409 | * TLB entries for this domain | |
410 | */ | |
411 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
412 | s = 1; | |
a19ae1ec JR |
413 | } |
414 | ||
999ba417 JR |
415 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
416 | ||
a19ae1ec JR |
417 | return 0; |
418 | } | |
b6c02715 | 419 | |
1c655773 JR |
420 | /* Flush the whole IO/TLB for a given protection domain */ |
421 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
422 | { | |
423 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
424 | ||
f57d98ae JR |
425 | INC_STATS_COUNTER(domain_flush_single); |
426 | ||
1c655773 JR |
427 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
428 | } | |
429 | ||
43f49609 JR |
430 | /* |
431 | * This function is used to flush the IO/TLB for a given protection domain | |
432 | * on every IOMMU in the system | |
433 | */ | |
434 | static void iommu_flush_domain(u16 domid) | |
435 | { | |
436 | unsigned long flags; | |
437 | struct amd_iommu *iommu; | |
438 | struct iommu_cmd cmd; | |
439 | ||
18811f55 JR |
440 | INC_STATS_COUNTER(domain_flush_all); |
441 | ||
43f49609 JR |
442 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
443 | domid, 1, 1); | |
444 | ||
445 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
446 | spin_lock_irqsave(&iommu->lock, flags); | |
447 | __iommu_queue_command(iommu, &cmd); | |
448 | __iommu_completion_wait(iommu); | |
449 | __iommu_wait_for_completion(iommu); | |
450 | spin_unlock_irqrestore(&iommu->lock, flags); | |
451 | } | |
452 | } | |
43f49609 | 453 | |
431b2a20 JR |
454 | /**************************************************************************** |
455 | * | |
456 | * The functions below are used the create the page table mappings for | |
457 | * unity mapped regions. | |
458 | * | |
459 | ****************************************************************************/ | |
460 | ||
461 | /* | |
462 | * Generic mapping functions. It maps a physical address into a DMA | |
463 | * address space. It allocates the page table pages if necessary. | |
464 | * In the future it can be extended to a generic mapping function | |
465 | * supporting all features of AMD IOMMU page tables like level skipping | |
466 | * and full 64 bit address spaces. | |
467 | */ | |
38e817fe JR |
468 | static int iommu_map_page(struct protection_domain *dom, |
469 | unsigned long bus_addr, | |
470 | unsigned long phys_addr, | |
471 | int prot) | |
bd0e5211 | 472 | { |
8bda3092 | 473 | u64 __pte, *pte; |
bd0e5211 JR |
474 | |
475 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 476 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
477 | |
478 | /* only support 512GB address spaces for now */ | |
479 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
480 | return -EINVAL; | |
481 | ||
8bda3092 | 482 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
483 | |
484 | if (IOMMU_PTE_PRESENT(*pte)) | |
485 | return -EBUSY; | |
486 | ||
487 | __pte = phys_addr | IOMMU_PTE_P; | |
488 | if (prot & IOMMU_PROT_IR) | |
489 | __pte |= IOMMU_PTE_IR; | |
490 | if (prot & IOMMU_PROT_IW) | |
491 | __pte |= IOMMU_PTE_IW; | |
492 | ||
493 | *pte = __pte; | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
eb74ff6c JR |
498 | static void iommu_unmap_page(struct protection_domain *dom, |
499 | unsigned long bus_addr) | |
500 | { | |
501 | u64 *pte; | |
502 | ||
503 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
504 | ||
505 | if (!IOMMU_PTE_PRESENT(*pte)) | |
506 | return; | |
507 | ||
508 | pte = IOMMU_PTE_PAGE(*pte); | |
509 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
510 | ||
511 | if (!IOMMU_PTE_PRESENT(*pte)) | |
512 | return; | |
513 | ||
514 | pte = IOMMU_PTE_PAGE(*pte); | |
515 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
516 | ||
517 | *pte = 0; | |
518 | } | |
eb74ff6c | 519 | |
431b2a20 JR |
520 | /* |
521 | * This function checks if a specific unity mapping entry is needed for | |
522 | * this specific IOMMU. | |
523 | */ | |
bd0e5211 JR |
524 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
525 | struct unity_map_entry *entry) | |
526 | { | |
527 | u16 bdf, i; | |
528 | ||
529 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
530 | bdf = amd_iommu_alias_table[i]; | |
531 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
532 | return 1; | |
533 | } | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
431b2a20 JR |
538 | /* |
539 | * Init the unity mappings for a specific IOMMU in the system | |
540 | * | |
541 | * Basically iterates over all unity mapping entries and applies them to | |
542 | * the default domain DMA of that IOMMU if necessary. | |
543 | */ | |
bd0e5211 JR |
544 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
545 | { | |
546 | struct unity_map_entry *entry; | |
547 | int ret; | |
548 | ||
549 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
550 | if (!iommu_for_unity_map(iommu, entry)) | |
551 | continue; | |
552 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
553 | if (ret) | |
554 | return ret; | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
431b2a20 JR |
560 | /* |
561 | * This function actually applies the mapping to the page table of the | |
562 | * dma_ops domain. | |
563 | */ | |
bd0e5211 JR |
564 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
565 | struct unity_map_entry *e) | |
566 | { | |
567 | u64 addr; | |
568 | int ret; | |
569 | ||
570 | for (addr = e->address_start; addr < e->address_end; | |
571 | addr += PAGE_SIZE) { | |
38e817fe | 572 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
573 | if (ret) |
574 | return ret; | |
575 | /* | |
576 | * if unity mapping is in aperture range mark the page | |
577 | * as allocated in the aperture | |
578 | */ | |
579 | if (addr < dma_dom->aperture_size) | |
c3239567 | 580 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 581 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
582 | } |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
431b2a20 JR |
587 | /* |
588 | * Inits the unity mappings required for a specific device | |
589 | */ | |
bd0e5211 JR |
590 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
591 | u16 devid) | |
592 | { | |
593 | struct unity_map_entry *e; | |
594 | int ret; | |
595 | ||
596 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
597 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
598 | continue; | |
599 | ret = dma_ops_unity_map(dma_dom, e); | |
600 | if (ret) | |
601 | return ret; | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
431b2a20 JR |
607 | /**************************************************************************** |
608 | * | |
609 | * The next functions belong to the address allocator for the dma_ops | |
610 | * interface functions. They work like the allocators in the other IOMMU | |
611 | * drivers. Its basically a bitmap which marks the allocated pages in | |
612 | * the aperture. Maybe it could be enhanced in the future to a more | |
613 | * efficient allocator. | |
614 | * | |
615 | ****************************************************************************/ | |
d3086444 | 616 | |
431b2a20 | 617 | /* |
384de729 | 618 | * The address allocator core functions. |
431b2a20 JR |
619 | * |
620 | * called with domain->lock held | |
621 | */ | |
384de729 JR |
622 | |
623 | static unsigned long dma_ops_area_alloc(struct device *dev, | |
624 | struct dma_ops_domain *dom, | |
625 | unsigned int pages, | |
626 | unsigned long align_mask, | |
627 | u64 dma_mask, | |
628 | unsigned long start) | |
629 | { | |
803b8cb4 | 630 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
631 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
632 | int i = start >> APERTURE_RANGE_SHIFT; | |
633 | unsigned long boundary_size; | |
634 | unsigned long address = -1; | |
635 | unsigned long limit; | |
636 | ||
803b8cb4 JR |
637 | next_bit >>= PAGE_SHIFT; |
638 | ||
384de729 JR |
639 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
640 | PAGE_SIZE) >> PAGE_SHIFT; | |
641 | ||
642 | for (;i < max_index; ++i) { | |
643 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
644 | ||
645 | if (dom->aperture[i]->offset >= dma_mask) | |
646 | break; | |
647 | ||
648 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
649 | dma_mask >> PAGE_SHIFT); | |
650 | ||
651 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
652 | limit, next_bit, pages, 0, | |
653 | boundary_size, align_mask); | |
654 | if (address != -1) { | |
655 | address = dom->aperture[i]->offset + | |
656 | (address << PAGE_SHIFT); | |
803b8cb4 | 657 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
658 | break; |
659 | } | |
660 | ||
661 | next_bit = 0; | |
662 | } | |
663 | ||
664 | return address; | |
665 | } | |
666 | ||
d3086444 JR |
667 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
668 | struct dma_ops_domain *dom, | |
6d4f343f | 669 | unsigned int pages, |
832a90c3 JR |
670 | unsigned long align_mask, |
671 | u64 dma_mask) | |
d3086444 | 672 | { |
d3086444 | 673 | unsigned long address; |
d3086444 | 674 | |
384de729 | 675 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 676 | dma_mask, dom->next_address); |
d3086444 | 677 | |
1c655773 | 678 | if (address == -1) { |
803b8cb4 | 679 | dom->next_address = 0; |
384de729 JR |
680 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
681 | dma_mask, 0); | |
1c655773 JR |
682 | dom->need_flush = true; |
683 | } | |
d3086444 | 684 | |
384de729 | 685 | if (unlikely(address == -1)) |
d3086444 JR |
686 | address = bad_dma_address; |
687 | ||
688 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
689 | ||
690 | return address; | |
691 | } | |
692 | ||
431b2a20 JR |
693 | /* |
694 | * The address free function. | |
695 | * | |
696 | * called with domain->lock held | |
697 | */ | |
d3086444 JR |
698 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
699 | unsigned long address, | |
700 | unsigned int pages) | |
701 | { | |
384de729 JR |
702 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
703 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 704 | |
384de729 JR |
705 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
706 | ||
803b8cb4 | 707 | if (address >= dom->next_address) |
80be308d | 708 | dom->need_flush = true; |
384de729 JR |
709 | |
710 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 711 | |
384de729 JR |
712 | iommu_area_free(range->bitmap, address, pages); |
713 | ||
d3086444 JR |
714 | } |
715 | ||
431b2a20 JR |
716 | /**************************************************************************** |
717 | * | |
718 | * The next functions belong to the domain allocation. A domain is | |
719 | * allocated for every IOMMU as the default domain. If device isolation | |
720 | * is enabled, every device get its own domain. The most important thing | |
721 | * about domains is the page table mapping the DMA address space they | |
722 | * contain. | |
723 | * | |
724 | ****************************************************************************/ | |
725 | ||
ec487d1a JR |
726 | static u16 domain_id_alloc(void) |
727 | { | |
728 | unsigned long flags; | |
729 | int id; | |
730 | ||
731 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
732 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
733 | BUG_ON(id == 0); | |
734 | if (id > 0 && id < MAX_DOMAIN_ID) | |
735 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
736 | else | |
737 | id = 0; | |
738 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
739 | ||
740 | return id; | |
741 | } | |
742 | ||
a2acfb75 JR |
743 | static void domain_id_free(int id) |
744 | { | |
745 | unsigned long flags; | |
746 | ||
747 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
748 | if (id > 0 && id < MAX_DOMAIN_ID) | |
749 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
750 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
751 | } | |
a2acfb75 | 752 | |
431b2a20 JR |
753 | /* |
754 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
755 | * ranges. | |
756 | */ | |
ec487d1a JR |
757 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
758 | unsigned long start_page, | |
759 | unsigned int pages) | |
760 | { | |
384de729 | 761 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
762 | |
763 | if (start_page + pages > last_page) | |
764 | pages = last_page - start_page; | |
765 | ||
384de729 JR |
766 | for (i = start_page; i < start_page + pages; ++i) { |
767 | int index = i / APERTURE_RANGE_PAGES; | |
768 | int page = i % APERTURE_RANGE_PAGES; | |
769 | __set_bit(page, dom->aperture[index]->bitmap); | |
770 | } | |
ec487d1a JR |
771 | } |
772 | ||
86db2e5d | 773 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
774 | { |
775 | int i, j; | |
776 | u64 *p1, *p2, *p3; | |
777 | ||
86db2e5d | 778 | p1 = domain->pt_root; |
ec487d1a JR |
779 | |
780 | if (!p1) | |
781 | return; | |
782 | ||
783 | for (i = 0; i < 512; ++i) { | |
784 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
785 | continue; | |
786 | ||
787 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 788 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
789 | if (!IOMMU_PTE_PRESENT(p2[j])) |
790 | continue; | |
791 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
792 | free_page((unsigned long)p3); | |
793 | } | |
794 | ||
795 | free_page((unsigned long)p2); | |
796 | } | |
797 | ||
798 | free_page((unsigned long)p1); | |
86db2e5d JR |
799 | |
800 | domain->pt_root = NULL; | |
ec487d1a JR |
801 | } |
802 | ||
431b2a20 JR |
803 | /* |
804 | * Free a domain, only used if something went wrong in the | |
805 | * allocation path and we need to free an already allocated page table | |
806 | */ | |
ec487d1a JR |
807 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
808 | { | |
384de729 JR |
809 | int i; |
810 | ||
ec487d1a JR |
811 | if (!dom) |
812 | return; | |
813 | ||
86db2e5d | 814 | free_pagetable(&dom->domain); |
ec487d1a | 815 | |
384de729 JR |
816 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
817 | if (!dom->aperture[i]) | |
818 | continue; | |
819 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
820 | kfree(dom->aperture[i]); | |
821 | } | |
ec487d1a JR |
822 | |
823 | kfree(dom); | |
824 | } | |
825 | ||
431b2a20 JR |
826 | /* |
827 | * Allocates a new protection domain usable for the dma_ops functions. | |
828 | * It also intializes the page table and the address allocator data | |
829 | * structures required for the dma_ops interface | |
830 | */ | |
ec487d1a JR |
831 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
832 | unsigned order) | |
833 | { | |
834 | struct dma_ops_domain *dma_dom; | |
835 | unsigned i, num_pte_pages; | |
836 | u64 *l2_pde; | |
837 | u64 address; | |
838 | ||
839 | /* | |
840 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
841 | */ | |
842 | if ((order < 25) || (order > 30)) | |
843 | return NULL; | |
844 | ||
845 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
846 | if (!dma_dom) | |
847 | return NULL; | |
848 | ||
384de729 JR |
849 | dma_dom->aperture[0] = kzalloc(sizeof(struct aperture_range), |
850 | GFP_KERNEL); | |
851 | if (!dma_dom->aperture[0]) | |
852 | goto free_dma_dom; | |
853 | ||
ec487d1a JR |
854 | spin_lock_init(&dma_dom->domain.lock); |
855 | ||
856 | dma_dom->domain.id = domain_id_alloc(); | |
857 | if (dma_dom->domain.id == 0) | |
858 | goto free_dma_dom; | |
859 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
860 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 861 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
862 | dma_dom->domain.priv = dma_dom; |
863 | if (!dma_dom->domain.pt_root) | |
864 | goto free_dma_dom; | |
c3239567 | 865 | dma_dom->aperture_size = APERTURE_RANGE_SIZE; |
384de729 JR |
866 | dma_dom->aperture[0]->bitmap = (void *)get_zeroed_page(GFP_KERNEL); |
867 | if (!dma_dom->aperture[0]->bitmap) | |
ec487d1a JR |
868 | goto free_dma_dom; |
869 | /* | |
870 | * mark the first page as allocated so we never return 0 as | |
871 | * a valid dma-address. So we can use 0 as error value | |
872 | */ | |
384de729 | 873 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 874 | dma_dom->next_address = 0; |
ec487d1a | 875 | |
1c655773 | 876 | dma_dom->need_flush = false; |
bd60b735 | 877 | dma_dom->target_dev = 0xffff; |
1c655773 | 878 | |
431b2a20 | 879 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
880 | if (iommu->exclusion_start && |
881 | iommu->exclusion_start < dma_dom->aperture_size) { | |
882 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
883 | int pages = iommu_num_pages(iommu->exclusion_start, |
884 | iommu->exclusion_length, | |
885 | PAGE_SIZE); | |
ec487d1a JR |
886 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
887 | } | |
888 | ||
431b2a20 JR |
889 | /* |
890 | * At the last step, build the page tables so we don't need to | |
891 | * allocate page table pages in the dma_ops mapping/unmapping | |
c3239567 | 892 | * path for the first 128MB of dma address space. |
431b2a20 | 893 | */ |
ec487d1a | 894 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
ec487d1a JR |
895 | |
896 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
897 | if (l2_pde == NULL) | |
898 | goto free_dma_dom; | |
899 | ||
900 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
901 | ||
902 | for (i = 0; i < num_pte_pages; ++i) { | |
384de729 | 903 | u64 **pte_page = &dma_dom->aperture[0]->pte_pages[i]; |
c3239567 JR |
904 | *pte_page = (u64 *)get_zeroed_page(GFP_KERNEL); |
905 | if (!*pte_page) | |
ec487d1a | 906 | goto free_dma_dom; |
c3239567 | 907 | address = virt_to_phys(*pte_page); |
ec487d1a JR |
908 | l2_pde[i] = IOMMU_L1_PDE(address); |
909 | } | |
910 | ||
911 | return dma_dom; | |
912 | ||
913 | free_dma_dom: | |
914 | dma_ops_domain_free(dma_dom); | |
915 | ||
916 | return NULL; | |
917 | } | |
918 | ||
5b28df6f JR |
919 | /* |
920 | * little helper function to check whether a given protection domain is a | |
921 | * dma_ops domain | |
922 | */ | |
923 | static bool dma_ops_domain(struct protection_domain *domain) | |
924 | { | |
925 | return domain->flags & PD_DMA_OPS_MASK; | |
926 | } | |
927 | ||
431b2a20 JR |
928 | /* |
929 | * Find out the protection domain structure for a given PCI device. This | |
930 | * will give us the pointer to the page table root for example. | |
931 | */ | |
b20ac0d4 JR |
932 | static struct protection_domain *domain_for_device(u16 devid) |
933 | { | |
934 | struct protection_domain *dom; | |
935 | unsigned long flags; | |
936 | ||
937 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
938 | dom = amd_iommu_pd_table[devid]; | |
939 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
940 | ||
941 | return dom; | |
942 | } | |
943 | ||
431b2a20 JR |
944 | /* |
945 | * If a device is not yet associated with a domain, this function does | |
946 | * assigns it visible for the hardware | |
947 | */ | |
f1179dc0 JR |
948 | static void attach_device(struct amd_iommu *iommu, |
949 | struct protection_domain *domain, | |
950 | u16 devid) | |
b20ac0d4 JR |
951 | { |
952 | unsigned long flags; | |
b20ac0d4 JR |
953 | u64 pte_root = virt_to_phys(domain->pt_root); |
954 | ||
863c74eb JR |
955 | domain->dev_cnt += 1; |
956 | ||
38ddf41b JR |
957 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
958 | << DEV_ENTRY_MODE_SHIFT; | |
959 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
960 | |
961 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
962 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
963 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
964 | amd_iommu_dev_table[devid].data[2] = domain->id; |
965 | ||
966 | amd_iommu_pd_table[devid] = domain; | |
967 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
968 | ||
969 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
970 | } |
971 | ||
355bf553 JR |
972 | /* |
973 | * Removes a device from a protection domain (unlocked) | |
974 | */ | |
975 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
976 | { | |
977 | ||
978 | /* lock domain */ | |
979 | spin_lock(&domain->lock); | |
980 | ||
981 | /* remove domain from the lookup table */ | |
982 | amd_iommu_pd_table[devid] = NULL; | |
983 | ||
984 | /* remove entry from the device table seen by the hardware */ | |
985 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
986 | amd_iommu_dev_table[devid].data[1] = 0; | |
987 | amd_iommu_dev_table[devid].data[2] = 0; | |
988 | ||
989 | /* decrease reference counter */ | |
990 | domain->dev_cnt -= 1; | |
991 | ||
992 | /* ready */ | |
993 | spin_unlock(&domain->lock); | |
994 | } | |
995 | ||
996 | /* | |
997 | * Removes a device from a protection domain (with devtable_lock held) | |
998 | */ | |
999 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1000 | { | |
1001 | unsigned long flags; | |
1002 | ||
1003 | /* lock device table */ | |
1004 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1005 | __detach_device(domain, devid); | |
1006 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1007 | } | |
e275a2a0 JR |
1008 | |
1009 | static int device_change_notifier(struct notifier_block *nb, | |
1010 | unsigned long action, void *data) | |
1011 | { | |
1012 | struct device *dev = data; | |
1013 | struct pci_dev *pdev = to_pci_dev(dev); | |
1014 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1015 | struct protection_domain *domain; | |
1016 | struct dma_ops_domain *dma_domain; | |
1017 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
1018 | int order = amd_iommu_aperture_order; |
1019 | unsigned long flags; | |
e275a2a0 JR |
1020 | |
1021 | if (devid > amd_iommu_last_bdf) | |
1022 | goto out; | |
1023 | ||
1024 | devid = amd_iommu_alias_table[devid]; | |
1025 | ||
1026 | iommu = amd_iommu_rlookup_table[devid]; | |
1027 | if (iommu == NULL) | |
1028 | goto out; | |
1029 | ||
1030 | domain = domain_for_device(devid); | |
1031 | ||
1032 | if (domain && !dma_ops_domain(domain)) | |
1033 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1034 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1035 | ||
1036 | switch (action) { | |
1037 | case BUS_NOTIFY_BOUND_DRIVER: | |
1038 | if (domain) | |
1039 | goto out; | |
1040 | dma_domain = find_protection_domain(devid); | |
1041 | if (!dma_domain) | |
1042 | dma_domain = iommu->default_dom; | |
1043 | attach_device(iommu, &dma_domain->domain, devid); | |
1044 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1045 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1046 | break; | |
1047 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1048 | if (!domain) | |
1049 | goto out; | |
1050 | detach_device(domain, devid); | |
1ac4cbbc JR |
1051 | break; |
1052 | case BUS_NOTIFY_ADD_DEVICE: | |
1053 | /* allocate a protection domain if a device is added */ | |
1054 | dma_domain = find_protection_domain(devid); | |
1055 | if (dma_domain) | |
1056 | goto out; | |
1057 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1058 | if (!dma_domain) | |
1059 | goto out; | |
1060 | dma_domain->target_dev = devid; | |
1061 | ||
1062 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1063 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1064 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1065 | ||
e275a2a0 JR |
1066 | break; |
1067 | default: | |
1068 | goto out; | |
1069 | } | |
1070 | ||
1071 | iommu_queue_inv_dev_entry(iommu, devid); | |
1072 | iommu_completion_wait(iommu); | |
1073 | ||
1074 | out: | |
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | struct notifier_block device_nb = { | |
1079 | .notifier_call = device_change_notifier, | |
1080 | }; | |
355bf553 | 1081 | |
431b2a20 JR |
1082 | /***************************************************************************** |
1083 | * | |
1084 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1085 | * | |
1086 | *****************************************************************************/ | |
1087 | ||
dbcc112e JR |
1088 | /* |
1089 | * This function checks if the driver got a valid device from the caller to | |
1090 | * avoid dereferencing invalid pointers. | |
1091 | */ | |
1092 | static bool check_device(struct device *dev) | |
1093 | { | |
1094 | if (!dev || !dev->dma_mask) | |
1095 | return false; | |
1096 | ||
1097 | return true; | |
1098 | } | |
1099 | ||
bd60b735 JR |
1100 | /* |
1101 | * In this function the list of preallocated protection domains is traversed to | |
1102 | * find the domain for a specific device | |
1103 | */ | |
1104 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1105 | { | |
1106 | struct dma_ops_domain *entry, *ret = NULL; | |
1107 | unsigned long flags; | |
1108 | ||
1109 | if (list_empty(&iommu_pd_list)) | |
1110 | return NULL; | |
1111 | ||
1112 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1113 | ||
1114 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1115 | if (entry->target_dev == devid) { | |
1116 | ret = entry; | |
bd60b735 JR |
1117 | break; |
1118 | } | |
1119 | } | |
1120 | ||
1121 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1122 | ||
1123 | return ret; | |
1124 | } | |
1125 | ||
431b2a20 JR |
1126 | /* |
1127 | * In the dma_ops path we only have the struct device. This function | |
1128 | * finds the corresponding IOMMU, the protection domain and the | |
1129 | * requestor id for a given device. | |
1130 | * If the device is not yet associated with a domain this is also done | |
1131 | * in this function. | |
1132 | */ | |
b20ac0d4 JR |
1133 | static int get_device_resources(struct device *dev, |
1134 | struct amd_iommu **iommu, | |
1135 | struct protection_domain **domain, | |
1136 | u16 *bdf) | |
1137 | { | |
1138 | struct dma_ops_domain *dma_dom; | |
1139 | struct pci_dev *pcidev; | |
1140 | u16 _bdf; | |
1141 | ||
dbcc112e JR |
1142 | *iommu = NULL; |
1143 | *domain = NULL; | |
1144 | *bdf = 0xffff; | |
1145 | ||
1146 | if (dev->bus != &pci_bus_type) | |
1147 | return 0; | |
b20ac0d4 JR |
1148 | |
1149 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1150 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1151 | |
431b2a20 | 1152 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1153 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1154 | return 0; |
b20ac0d4 JR |
1155 | |
1156 | *bdf = amd_iommu_alias_table[_bdf]; | |
1157 | ||
1158 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1159 | if (*iommu == NULL) | |
1160 | return 0; | |
b20ac0d4 JR |
1161 | *domain = domain_for_device(*bdf); |
1162 | if (*domain == NULL) { | |
bd60b735 JR |
1163 | dma_dom = find_protection_domain(*bdf); |
1164 | if (!dma_dom) | |
1165 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1166 | *domain = &dma_dom->domain; |
f1179dc0 | 1167 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1168 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1169 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1170 | } |
1171 | ||
f91ba190 | 1172 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1173 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1174 | |
b20ac0d4 JR |
1175 | return 1; |
1176 | } | |
1177 | ||
8bda3092 JR |
1178 | /* |
1179 | * If the pte_page is not yet allocated this function is called | |
1180 | */ | |
1181 | static u64* alloc_pte(struct protection_domain *dom, | |
1182 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1183 | { | |
1184 | u64 *pte, *page; | |
1185 | ||
1186 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1187 | ||
1188 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1189 | page = (u64 *)get_zeroed_page(gfp); | |
1190 | if (!page) | |
1191 | return NULL; | |
1192 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1193 | } | |
1194 | ||
1195 | pte = IOMMU_PTE_PAGE(*pte); | |
1196 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1197 | ||
1198 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1199 | page = (u64 *)get_zeroed_page(gfp); | |
1200 | if (!page) | |
1201 | return NULL; | |
1202 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1203 | } | |
1204 | ||
1205 | pte = IOMMU_PTE_PAGE(*pte); | |
1206 | ||
1207 | if (pte_page) | |
1208 | *pte_page = pte; | |
1209 | ||
1210 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1211 | ||
1212 | return pte; | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * This function fetches the PTE for a given address in the aperture | |
1217 | */ | |
1218 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1219 | unsigned long address) | |
1220 | { | |
384de729 | 1221 | struct aperture_range *aperture; |
8bda3092 JR |
1222 | u64 *pte, *pte_page; |
1223 | ||
384de729 JR |
1224 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1225 | if (!aperture) | |
1226 | return NULL; | |
1227 | ||
1228 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1229 | if (!pte) { |
1230 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1231 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1232 | } else | |
1233 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1234 | |
1235 | return pte; | |
1236 | } | |
1237 | ||
431b2a20 JR |
1238 | /* |
1239 | * This is the generic map function. It maps one 4kb page at paddr to | |
1240 | * the given address in the DMA address space for the domain. | |
1241 | */ | |
cb76c322 JR |
1242 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1243 | struct dma_ops_domain *dom, | |
1244 | unsigned long address, | |
1245 | phys_addr_t paddr, | |
1246 | int direction) | |
1247 | { | |
1248 | u64 *pte, __pte; | |
1249 | ||
1250 | WARN_ON(address > dom->aperture_size); | |
1251 | ||
1252 | paddr &= PAGE_MASK; | |
1253 | ||
8bda3092 | 1254 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1255 | if (!pte) |
1256 | return bad_dma_address; | |
cb76c322 JR |
1257 | |
1258 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1259 | ||
1260 | if (direction == DMA_TO_DEVICE) | |
1261 | __pte |= IOMMU_PTE_IR; | |
1262 | else if (direction == DMA_FROM_DEVICE) | |
1263 | __pte |= IOMMU_PTE_IW; | |
1264 | else if (direction == DMA_BIDIRECTIONAL) | |
1265 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1266 | ||
1267 | WARN_ON(*pte); | |
1268 | ||
1269 | *pte = __pte; | |
1270 | ||
1271 | return (dma_addr_t)address; | |
1272 | } | |
1273 | ||
431b2a20 JR |
1274 | /* |
1275 | * The generic unmapping function for on page in the DMA address space. | |
1276 | */ | |
cb76c322 JR |
1277 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1278 | struct dma_ops_domain *dom, | |
1279 | unsigned long address) | |
1280 | { | |
384de729 | 1281 | struct aperture_range *aperture; |
cb76c322 JR |
1282 | u64 *pte; |
1283 | ||
1284 | if (address >= dom->aperture_size) | |
1285 | return; | |
1286 | ||
384de729 JR |
1287 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1288 | if (!aperture) | |
1289 | return; | |
1290 | ||
1291 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1292 | if (!pte) | |
1293 | return; | |
cb76c322 | 1294 | |
cb76c322 JR |
1295 | pte += IOMMU_PTE_L0_INDEX(address); |
1296 | ||
1297 | WARN_ON(!*pte); | |
1298 | ||
1299 | *pte = 0ULL; | |
1300 | } | |
1301 | ||
431b2a20 JR |
1302 | /* |
1303 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1304 | * contiguous memory region into DMA address space. It is used by all |
1305 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1306 | * Must be called with the domain lock held. |
1307 | */ | |
cb76c322 JR |
1308 | static dma_addr_t __map_single(struct device *dev, |
1309 | struct amd_iommu *iommu, | |
1310 | struct dma_ops_domain *dma_dom, | |
1311 | phys_addr_t paddr, | |
1312 | size_t size, | |
6d4f343f | 1313 | int dir, |
832a90c3 JR |
1314 | bool align, |
1315 | u64 dma_mask) | |
cb76c322 JR |
1316 | { |
1317 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1318 | dma_addr_t address, start, ret; |
cb76c322 | 1319 | unsigned int pages; |
6d4f343f | 1320 | unsigned long align_mask = 0; |
cb76c322 JR |
1321 | int i; |
1322 | ||
e3c449f5 | 1323 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1324 | paddr &= PAGE_MASK; |
1325 | ||
8ecaf8f1 JR |
1326 | INC_STATS_COUNTER(total_map_requests); |
1327 | ||
c1858976 JR |
1328 | if (pages > 1) |
1329 | INC_STATS_COUNTER(cross_page); | |
1330 | ||
6d4f343f JR |
1331 | if (align) |
1332 | align_mask = (1UL << get_order(size)) - 1; | |
1333 | ||
832a90c3 JR |
1334 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1335 | dma_mask); | |
cb76c322 JR |
1336 | if (unlikely(address == bad_dma_address)) |
1337 | goto out; | |
1338 | ||
1339 | start = address; | |
1340 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1341 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1342 | if (ret == bad_dma_address) | |
1343 | goto out_unmap; | |
1344 | ||
cb76c322 JR |
1345 | paddr += PAGE_SIZE; |
1346 | start += PAGE_SIZE; | |
1347 | } | |
1348 | address += offset; | |
1349 | ||
5774f7c5 JR |
1350 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1351 | ||
afa9fdc2 | 1352 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1353 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1354 | dma_dom->need_flush = false; | |
1355 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1356 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1357 | ||
cb76c322 JR |
1358 | out: |
1359 | return address; | |
53812c11 JR |
1360 | |
1361 | out_unmap: | |
1362 | ||
1363 | for (--i; i >= 0; --i) { | |
1364 | start -= PAGE_SIZE; | |
1365 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1366 | } | |
1367 | ||
1368 | dma_ops_free_addresses(dma_dom, address, pages); | |
1369 | ||
1370 | return bad_dma_address; | |
cb76c322 JR |
1371 | } |
1372 | ||
431b2a20 JR |
1373 | /* |
1374 | * Does the reverse of the __map_single function. Must be called with | |
1375 | * the domain lock held too | |
1376 | */ | |
cb76c322 JR |
1377 | static void __unmap_single(struct amd_iommu *iommu, |
1378 | struct dma_ops_domain *dma_dom, | |
1379 | dma_addr_t dma_addr, | |
1380 | size_t size, | |
1381 | int dir) | |
1382 | { | |
1383 | dma_addr_t i, start; | |
1384 | unsigned int pages; | |
1385 | ||
b8d9905d JR |
1386 | if ((dma_addr == bad_dma_address) || |
1387 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1388 | return; |
1389 | ||
e3c449f5 | 1390 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1391 | dma_addr &= PAGE_MASK; |
1392 | start = dma_addr; | |
1393 | ||
1394 | for (i = 0; i < pages; ++i) { | |
1395 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1396 | start += PAGE_SIZE; | |
1397 | } | |
1398 | ||
5774f7c5 JR |
1399 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1400 | ||
cb76c322 | 1401 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1402 | |
80be308d | 1403 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1404 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1405 | dma_dom->need_flush = false; |
1406 | } | |
cb76c322 JR |
1407 | } |
1408 | ||
431b2a20 JR |
1409 | /* |
1410 | * The exported map_single function for dma_ops. | |
1411 | */ | |
51491367 FT |
1412 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1413 | unsigned long offset, size_t size, | |
1414 | enum dma_data_direction dir, | |
1415 | struct dma_attrs *attrs) | |
4da70b9e JR |
1416 | { |
1417 | unsigned long flags; | |
1418 | struct amd_iommu *iommu; | |
1419 | struct protection_domain *domain; | |
1420 | u16 devid; | |
1421 | dma_addr_t addr; | |
832a90c3 | 1422 | u64 dma_mask; |
51491367 | 1423 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1424 | |
0f2a86f2 JR |
1425 | INC_STATS_COUNTER(cnt_map_single); |
1426 | ||
dbcc112e JR |
1427 | if (!check_device(dev)) |
1428 | return bad_dma_address; | |
1429 | ||
832a90c3 | 1430 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1431 | |
1432 | get_device_resources(dev, &iommu, &domain, &devid); | |
1433 | ||
1434 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1435 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1436 | return (dma_addr_t)paddr; |
1437 | ||
5b28df6f JR |
1438 | if (!dma_ops_domain(domain)) |
1439 | return bad_dma_address; | |
1440 | ||
4da70b9e | 1441 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1442 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1443 | dma_mask); | |
4da70b9e JR |
1444 | if (addr == bad_dma_address) |
1445 | goto out; | |
1446 | ||
09ee17eb | 1447 | iommu_completion_wait(iommu); |
4da70b9e JR |
1448 | |
1449 | out: | |
1450 | spin_unlock_irqrestore(&domain->lock, flags); | |
1451 | ||
1452 | return addr; | |
1453 | } | |
1454 | ||
431b2a20 JR |
1455 | /* |
1456 | * The exported unmap_single function for dma_ops. | |
1457 | */ | |
51491367 FT |
1458 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1459 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1460 | { |
1461 | unsigned long flags; | |
1462 | struct amd_iommu *iommu; | |
1463 | struct protection_domain *domain; | |
1464 | u16 devid; | |
1465 | ||
146a6917 JR |
1466 | INC_STATS_COUNTER(cnt_unmap_single); |
1467 | ||
dbcc112e JR |
1468 | if (!check_device(dev) || |
1469 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1470 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1471 | return; |
1472 | ||
5b28df6f JR |
1473 | if (!dma_ops_domain(domain)) |
1474 | return; | |
1475 | ||
4da70b9e JR |
1476 | spin_lock_irqsave(&domain->lock, flags); |
1477 | ||
1478 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1479 | ||
09ee17eb | 1480 | iommu_completion_wait(iommu); |
4da70b9e JR |
1481 | |
1482 | spin_unlock_irqrestore(&domain->lock, flags); | |
1483 | } | |
1484 | ||
431b2a20 JR |
1485 | /* |
1486 | * This is a special map_sg function which is used if we should map a | |
1487 | * device which is not handled by an AMD IOMMU in the system. | |
1488 | */ | |
65b050ad JR |
1489 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1490 | int nelems, int dir) | |
1491 | { | |
1492 | struct scatterlist *s; | |
1493 | int i; | |
1494 | ||
1495 | for_each_sg(sglist, s, nelems, i) { | |
1496 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1497 | s->dma_length = s->length; | |
1498 | } | |
1499 | ||
1500 | return nelems; | |
1501 | } | |
1502 | ||
431b2a20 JR |
1503 | /* |
1504 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1505 | * lists). | |
1506 | */ | |
65b050ad | 1507 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1508 | int nelems, enum dma_data_direction dir, |
1509 | struct dma_attrs *attrs) | |
65b050ad JR |
1510 | { |
1511 | unsigned long flags; | |
1512 | struct amd_iommu *iommu; | |
1513 | struct protection_domain *domain; | |
1514 | u16 devid; | |
1515 | int i; | |
1516 | struct scatterlist *s; | |
1517 | phys_addr_t paddr; | |
1518 | int mapped_elems = 0; | |
832a90c3 | 1519 | u64 dma_mask; |
65b050ad | 1520 | |
d03f067a JR |
1521 | INC_STATS_COUNTER(cnt_map_sg); |
1522 | ||
dbcc112e JR |
1523 | if (!check_device(dev)) |
1524 | return 0; | |
1525 | ||
832a90c3 | 1526 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1527 | |
1528 | get_device_resources(dev, &iommu, &domain, &devid); | |
1529 | ||
1530 | if (!iommu || !domain) | |
1531 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1532 | ||
5b28df6f JR |
1533 | if (!dma_ops_domain(domain)) |
1534 | return 0; | |
1535 | ||
65b050ad JR |
1536 | spin_lock_irqsave(&domain->lock, flags); |
1537 | ||
1538 | for_each_sg(sglist, s, nelems, i) { | |
1539 | paddr = sg_phys(s); | |
1540 | ||
1541 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1542 | paddr, s->length, dir, false, |
1543 | dma_mask); | |
65b050ad JR |
1544 | |
1545 | if (s->dma_address) { | |
1546 | s->dma_length = s->length; | |
1547 | mapped_elems++; | |
1548 | } else | |
1549 | goto unmap; | |
65b050ad JR |
1550 | } |
1551 | ||
09ee17eb | 1552 | iommu_completion_wait(iommu); |
65b050ad JR |
1553 | |
1554 | out: | |
1555 | spin_unlock_irqrestore(&domain->lock, flags); | |
1556 | ||
1557 | return mapped_elems; | |
1558 | unmap: | |
1559 | for_each_sg(sglist, s, mapped_elems, i) { | |
1560 | if (s->dma_address) | |
1561 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1562 | s->dma_length, dir); | |
1563 | s->dma_address = s->dma_length = 0; | |
1564 | } | |
1565 | ||
1566 | mapped_elems = 0; | |
1567 | ||
1568 | goto out; | |
1569 | } | |
1570 | ||
431b2a20 JR |
1571 | /* |
1572 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1573 | * lists). | |
1574 | */ | |
65b050ad | 1575 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1576 | int nelems, enum dma_data_direction dir, |
1577 | struct dma_attrs *attrs) | |
65b050ad JR |
1578 | { |
1579 | unsigned long flags; | |
1580 | struct amd_iommu *iommu; | |
1581 | struct protection_domain *domain; | |
1582 | struct scatterlist *s; | |
1583 | u16 devid; | |
1584 | int i; | |
1585 | ||
55877a6b JR |
1586 | INC_STATS_COUNTER(cnt_unmap_sg); |
1587 | ||
dbcc112e JR |
1588 | if (!check_device(dev) || |
1589 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1590 | return; |
1591 | ||
5b28df6f JR |
1592 | if (!dma_ops_domain(domain)) |
1593 | return; | |
1594 | ||
65b050ad JR |
1595 | spin_lock_irqsave(&domain->lock, flags); |
1596 | ||
1597 | for_each_sg(sglist, s, nelems, i) { | |
1598 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1599 | s->dma_length, dir); | |
65b050ad JR |
1600 | s->dma_address = s->dma_length = 0; |
1601 | } | |
1602 | ||
09ee17eb | 1603 | iommu_completion_wait(iommu); |
65b050ad JR |
1604 | |
1605 | spin_unlock_irqrestore(&domain->lock, flags); | |
1606 | } | |
1607 | ||
431b2a20 JR |
1608 | /* |
1609 | * The exported alloc_coherent function for dma_ops. | |
1610 | */ | |
5d8b53cf JR |
1611 | static void *alloc_coherent(struct device *dev, size_t size, |
1612 | dma_addr_t *dma_addr, gfp_t flag) | |
1613 | { | |
1614 | unsigned long flags; | |
1615 | void *virt_addr; | |
1616 | struct amd_iommu *iommu; | |
1617 | struct protection_domain *domain; | |
1618 | u16 devid; | |
1619 | phys_addr_t paddr; | |
832a90c3 | 1620 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1621 | |
c8f0fb36 JR |
1622 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1623 | ||
dbcc112e JR |
1624 | if (!check_device(dev)) |
1625 | return NULL; | |
5d8b53cf | 1626 | |
13d9fead FT |
1627 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1628 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1629 | |
c97ac535 | 1630 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1631 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1632 | if (!virt_addr) | |
1633 | return 0; | |
1634 | ||
5d8b53cf JR |
1635 | paddr = virt_to_phys(virt_addr); |
1636 | ||
5d8b53cf JR |
1637 | if (!iommu || !domain) { |
1638 | *dma_addr = (dma_addr_t)paddr; | |
1639 | return virt_addr; | |
1640 | } | |
1641 | ||
5b28df6f JR |
1642 | if (!dma_ops_domain(domain)) |
1643 | goto out_free; | |
1644 | ||
832a90c3 JR |
1645 | if (!dma_mask) |
1646 | dma_mask = *dev->dma_mask; | |
1647 | ||
5d8b53cf JR |
1648 | spin_lock_irqsave(&domain->lock, flags); |
1649 | ||
1650 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1651 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1652 | |
5b28df6f JR |
1653 | if (*dma_addr == bad_dma_address) |
1654 | goto out_free; | |
5d8b53cf | 1655 | |
09ee17eb | 1656 | iommu_completion_wait(iommu); |
5d8b53cf | 1657 | |
5d8b53cf JR |
1658 | spin_unlock_irqrestore(&domain->lock, flags); |
1659 | ||
1660 | return virt_addr; | |
5b28df6f JR |
1661 | |
1662 | out_free: | |
1663 | ||
1664 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1665 | ||
1666 | return NULL; | |
5d8b53cf JR |
1667 | } |
1668 | ||
431b2a20 JR |
1669 | /* |
1670 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1671 | */ |
5d8b53cf JR |
1672 | static void free_coherent(struct device *dev, size_t size, |
1673 | void *virt_addr, dma_addr_t dma_addr) | |
1674 | { | |
1675 | unsigned long flags; | |
1676 | struct amd_iommu *iommu; | |
1677 | struct protection_domain *domain; | |
1678 | u16 devid; | |
1679 | ||
5d31ee7e JR |
1680 | INC_STATS_COUNTER(cnt_free_coherent); |
1681 | ||
dbcc112e JR |
1682 | if (!check_device(dev)) |
1683 | return; | |
1684 | ||
5d8b53cf JR |
1685 | get_device_resources(dev, &iommu, &domain, &devid); |
1686 | ||
1687 | if (!iommu || !domain) | |
1688 | goto free_mem; | |
1689 | ||
5b28df6f JR |
1690 | if (!dma_ops_domain(domain)) |
1691 | goto free_mem; | |
1692 | ||
5d8b53cf JR |
1693 | spin_lock_irqsave(&domain->lock, flags); |
1694 | ||
1695 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1696 | |
09ee17eb | 1697 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1698 | |
1699 | spin_unlock_irqrestore(&domain->lock, flags); | |
1700 | ||
1701 | free_mem: | |
1702 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1703 | } | |
1704 | ||
b39ba6ad JR |
1705 | /* |
1706 | * This function is called by the DMA layer to find out if we can handle a | |
1707 | * particular device. It is part of the dma_ops. | |
1708 | */ | |
1709 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1710 | { | |
1711 | u16 bdf; | |
1712 | struct pci_dev *pcidev; | |
1713 | ||
1714 | /* No device or no PCI device */ | |
1715 | if (!dev || dev->bus != &pci_bus_type) | |
1716 | return 0; | |
1717 | ||
1718 | pcidev = to_pci_dev(dev); | |
1719 | ||
1720 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1721 | ||
1722 | /* Out of our scope? */ | |
1723 | if (bdf > amd_iommu_last_bdf) | |
1724 | return 0; | |
1725 | ||
1726 | return 1; | |
1727 | } | |
1728 | ||
c432f3df | 1729 | /* |
431b2a20 JR |
1730 | * The function for pre-allocating protection domains. |
1731 | * | |
c432f3df JR |
1732 | * If the driver core informs the DMA layer if a driver grabs a device |
1733 | * we don't need to preallocate the protection domains anymore. | |
1734 | * For now we have to. | |
1735 | */ | |
0e93dd88 | 1736 | static void prealloc_protection_domains(void) |
c432f3df JR |
1737 | { |
1738 | struct pci_dev *dev = NULL; | |
1739 | struct dma_ops_domain *dma_dom; | |
1740 | struct amd_iommu *iommu; | |
1741 | int order = amd_iommu_aperture_order; | |
1742 | u16 devid; | |
1743 | ||
1744 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1745 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1746 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1747 | continue; |
1748 | devid = amd_iommu_alias_table[devid]; | |
1749 | if (domain_for_device(devid)) | |
1750 | continue; | |
1751 | iommu = amd_iommu_rlookup_table[devid]; | |
1752 | if (!iommu) | |
1753 | continue; | |
1754 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1755 | if (!dma_dom) | |
1756 | continue; | |
1757 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1758 | dma_dom->target_dev = devid; |
1759 | ||
1760 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1761 | } |
1762 | } | |
1763 | ||
160c1d8e | 1764 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1765 | .alloc_coherent = alloc_coherent, |
1766 | .free_coherent = free_coherent, | |
51491367 FT |
1767 | .map_page = map_page, |
1768 | .unmap_page = unmap_page, | |
6631ee9d JR |
1769 | .map_sg = map_sg, |
1770 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1771 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1772 | }; |
1773 | ||
431b2a20 JR |
1774 | /* |
1775 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1776 | */ | |
6631ee9d JR |
1777 | int __init amd_iommu_init_dma_ops(void) |
1778 | { | |
1779 | struct amd_iommu *iommu; | |
1780 | int order = amd_iommu_aperture_order; | |
1781 | int ret; | |
1782 | ||
431b2a20 JR |
1783 | /* |
1784 | * first allocate a default protection domain for every IOMMU we | |
1785 | * found in the system. Devices not assigned to any other | |
1786 | * protection domain will be assigned to the default one. | |
1787 | */ | |
6631ee9d JR |
1788 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1789 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1790 | if (iommu->default_dom == NULL) | |
1791 | return -ENOMEM; | |
e2dc14a2 | 1792 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1793 | ret = iommu_init_unity_mappings(iommu); |
1794 | if (ret) | |
1795 | goto free_domains; | |
1796 | } | |
1797 | ||
431b2a20 JR |
1798 | /* |
1799 | * If device isolation is enabled, pre-allocate the protection | |
1800 | * domains for each device. | |
1801 | */ | |
6631ee9d JR |
1802 | if (amd_iommu_isolate) |
1803 | prealloc_protection_domains(); | |
1804 | ||
1805 | iommu_detected = 1; | |
1806 | force_iommu = 1; | |
1807 | bad_dma_address = 0; | |
92af4e29 | 1808 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1809 | gart_iommu_aperture_disabled = 1; |
1810 | gart_iommu_aperture = 0; | |
92af4e29 | 1811 | #endif |
6631ee9d | 1812 | |
431b2a20 | 1813 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1814 | dma_ops = &amd_iommu_dma_ops; |
1815 | ||
26961efe | 1816 | register_iommu(&amd_iommu_ops); |
26961efe | 1817 | |
e275a2a0 JR |
1818 | bus_register_notifier(&pci_bus_type, &device_nb); |
1819 | ||
7f26508b JR |
1820 | amd_iommu_stats_init(); |
1821 | ||
6631ee9d JR |
1822 | return 0; |
1823 | ||
1824 | free_domains: | |
1825 | ||
1826 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1827 | if (iommu->default_dom) | |
1828 | dma_ops_domain_free(iommu->default_dom); | |
1829 | } | |
1830 | ||
1831 | return ret; | |
1832 | } | |
6d98cd80 JR |
1833 | |
1834 | /***************************************************************************** | |
1835 | * | |
1836 | * The following functions belong to the exported interface of AMD IOMMU | |
1837 | * | |
1838 | * This interface allows access to lower level functions of the IOMMU | |
1839 | * like protection domain handling and assignement of devices to domains | |
1840 | * which is not possible with the dma_ops interface. | |
1841 | * | |
1842 | *****************************************************************************/ | |
1843 | ||
6d98cd80 JR |
1844 | static void cleanup_domain(struct protection_domain *domain) |
1845 | { | |
1846 | unsigned long flags; | |
1847 | u16 devid; | |
1848 | ||
1849 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1850 | ||
1851 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1852 | if (amd_iommu_pd_table[devid] == domain) | |
1853 | __detach_device(domain, devid); | |
1854 | ||
1855 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1856 | } | |
1857 | ||
c156e347 JR |
1858 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1859 | { | |
1860 | struct protection_domain *domain; | |
1861 | ||
1862 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1863 | if (!domain) | |
1864 | return -ENOMEM; | |
1865 | ||
1866 | spin_lock_init(&domain->lock); | |
1867 | domain->mode = PAGE_MODE_3_LEVEL; | |
1868 | domain->id = domain_id_alloc(); | |
1869 | if (!domain->id) | |
1870 | goto out_free; | |
1871 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1872 | if (!domain->pt_root) | |
1873 | goto out_free; | |
1874 | ||
1875 | dom->priv = domain; | |
1876 | ||
1877 | return 0; | |
1878 | ||
1879 | out_free: | |
1880 | kfree(domain); | |
1881 | ||
1882 | return -ENOMEM; | |
1883 | } | |
1884 | ||
98383fc3 JR |
1885 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1886 | { | |
1887 | struct protection_domain *domain = dom->priv; | |
1888 | ||
1889 | if (!domain) | |
1890 | return; | |
1891 | ||
1892 | if (domain->dev_cnt > 0) | |
1893 | cleanup_domain(domain); | |
1894 | ||
1895 | BUG_ON(domain->dev_cnt != 0); | |
1896 | ||
1897 | free_pagetable(domain); | |
1898 | ||
1899 | domain_id_free(domain->id); | |
1900 | ||
1901 | kfree(domain); | |
1902 | ||
1903 | dom->priv = NULL; | |
1904 | } | |
1905 | ||
684f2888 JR |
1906 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1907 | struct device *dev) | |
1908 | { | |
1909 | struct protection_domain *domain = dom->priv; | |
1910 | struct amd_iommu *iommu; | |
1911 | struct pci_dev *pdev; | |
1912 | u16 devid; | |
1913 | ||
1914 | if (dev->bus != &pci_bus_type) | |
1915 | return; | |
1916 | ||
1917 | pdev = to_pci_dev(dev); | |
1918 | ||
1919 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1920 | ||
1921 | if (devid > 0) | |
1922 | detach_device(domain, devid); | |
1923 | ||
1924 | iommu = amd_iommu_rlookup_table[devid]; | |
1925 | if (!iommu) | |
1926 | return; | |
1927 | ||
1928 | iommu_queue_inv_dev_entry(iommu, devid); | |
1929 | iommu_completion_wait(iommu); | |
1930 | } | |
1931 | ||
01106066 JR |
1932 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1933 | struct device *dev) | |
1934 | { | |
1935 | struct protection_domain *domain = dom->priv; | |
1936 | struct protection_domain *old_domain; | |
1937 | struct amd_iommu *iommu; | |
1938 | struct pci_dev *pdev; | |
1939 | u16 devid; | |
1940 | ||
1941 | if (dev->bus != &pci_bus_type) | |
1942 | return -EINVAL; | |
1943 | ||
1944 | pdev = to_pci_dev(dev); | |
1945 | ||
1946 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1947 | ||
1948 | if (devid >= amd_iommu_last_bdf || | |
1949 | devid != amd_iommu_alias_table[devid]) | |
1950 | return -EINVAL; | |
1951 | ||
1952 | iommu = amd_iommu_rlookup_table[devid]; | |
1953 | if (!iommu) | |
1954 | return -EINVAL; | |
1955 | ||
1956 | old_domain = domain_for_device(devid); | |
1957 | if (old_domain) | |
1958 | return -EBUSY; | |
1959 | ||
1960 | attach_device(iommu, domain, devid); | |
1961 | ||
1962 | iommu_completion_wait(iommu); | |
1963 | ||
1964 | return 0; | |
1965 | } | |
1966 | ||
c6229ca6 JR |
1967 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1968 | unsigned long iova, phys_addr_t paddr, | |
1969 | size_t size, int iommu_prot) | |
1970 | { | |
1971 | struct protection_domain *domain = dom->priv; | |
1972 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1973 | int prot = 0; | |
1974 | int ret; | |
1975 | ||
1976 | if (iommu_prot & IOMMU_READ) | |
1977 | prot |= IOMMU_PROT_IR; | |
1978 | if (iommu_prot & IOMMU_WRITE) | |
1979 | prot |= IOMMU_PROT_IW; | |
1980 | ||
1981 | iova &= PAGE_MASK; | |
1982 | paddr &= PAGE_MASK; | |
1983 | ||
1984 | for (i = 0; i < npages; ++i) { | |
1985 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1986 | if (ret) | |
1987 | return ret; | |
1988 | ||
1989 | iova += PAGE_SIZE; | |
1990 | paddr += PAGE_SIZE; | |
1991 | } | |
1992 | ||
1993 | return 0; | |
1994 | } | |
1995 | ||
eb74ff6c JR |
1996 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1997 | unsigned long iova, size_t size) | |
1998 | { | |
1999 | ||
2000 | struct protection_domain *domain = dom->priv; | |
2001 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2002 | ||
2003 | iova &= PAGE_MASK; | |
2004 | ||
2005 | for (i = 0; i < npages; ++i) { | |
2006 | iommu_unmap_page(domain, iova); | |
2007 | iova += PAGE_SIZE; | |
2008 | } | |
2009 | ||
2010 | iommu_flush_domain(domain->id); | |
2011 | } | |
2012 | ||
645c4c8d JR |
2013 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2014 | unsigned long iova) | |
2015 | { | |
2016 | struct protection_domain *domain = dom->priv; | |
2017 | unsigned long offset = iova & ~PAGE_MASK; | |
2018 | phys_addr_t paddr; | |
2019 | u64 *pte; | |
2020 | ||
2021 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2022 | ||
2023 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2024 | return 0; | |
2025 | ||
2026 | pte = IOMMU_PTE_PAGE(*pte); | |
2027 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2028 | ||
2029 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2030 | return 0; | |
2031 | ||
2032 | pte = IOMMU_PTE_PAGE(*pte); | |
2033 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2034 | ||
2035 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2036 | return 0; | |
2037 | ||
2038 | paddr = *pte & IOMMU_PAGE_MASK; | |
2039 | paddr |= offset; | |
2040 | ||
2041 | return paddr; | |
2042 | } | |
2043 | ||
dbb9fd86 SY |
2044 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2045 | unsigned long cap) | |
2046 | { | |
2047 | return 0; | |
2048 | } | |
2049 | ||
26961efe JR |
2050 | static struct iommu_ops amd_iommu_ops = { |
2051 | .domain_init = amd_iommu_domain_init, | |
2052 | .domain_destroy = amd_iommu_domain_destroy, | |
2053 | .attach_dev = amd_iommu_attach_device, | |
2054 | .detach_dev = amd_iommu_detach_device, | |
2055 | .map = amd_iommu_map_range, | |
2056 | .unmap = amd_iommu_unmap_range, | |
2057 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2058 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2059 | }; |
2060 |