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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
25 | #include <asm/proto.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
b6c02715 | 27 | #include <asm/amd_iommu_types.h> |
c6da992e | 28 | #include <asm/amd_iommu.h> |
b6c02715 JR |
29 | |
30 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
31 | ||
136f78a1 JR |
32 | #define EXIT_LOOP_COUNT 10000000 |
33 | ||
b6c02715 JR |
34 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
35 | ||
bd60b735 JR |
36 | /* A list of preallocated protection domains */ |
37 | static LIST_HEAD(iommu_pd_list); | |
38 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
39 | ||
431b2a20 JR |
40 | /* |
41 | * general struct to manage commands send to an IOMMU | |
42 | */ | |
d6449536 | 43 | struct iommu_cmd { |
b6c02715 JR |
44 | u32 data[4]; |
45 | }; | |
46 | ||
bd0e5211 JR |
47 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
48 | struct unity_map_entry *e); | |
49 | ||
431b2a20 | 50 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
51 | static int iommu_has_npcache(struct amd_iommu *iommu) |
52 | { | |
ae9b9403 | 53 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
54 | } |
55 | ||
a80dc3e0 JR |
56 | /**************************************************************************** |
57 | * | |
58 | * Interrupt handling functions | |
59 | * | |
60 | ****************************************************************************/ | |
61 | ||
90008ee4 JR |
62 | static void iommu_print_event(void *__evt) |
63 | { | |
64 | u32 *event = __evt; | |
65 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
66 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
67 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
68 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
69 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
70 | ||
71 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
72 | ||
73 | switch (type) { | |
74 | case EVENT_TYPE_ILL_DEV: | |
75 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
76 | "address=0x%016llx flags=0x%04x]\n", | |
77 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
78 | address, flags); | |
79 | break; | |
80 | case EVENT_TYPE_IO_FAULT: | |
81 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
82 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
83 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
84 | domid, address, flags); | |
85 | break; | |
86 | case EVENT_TYPE_DEV_TAB_ERR: | |
87 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
88 | "address=0x%016llx flags=0x%04x]\n", | |
89 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
90 | address, flags); | |
91 | break; | |
92 | case EVENT_TYPE_PAGE_TAB_ERR: | |
93 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
94 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
95 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
96 | domid, address, flags); | |
97 | break; | |
98 | case EVENT_TYPE_ILL_CMD: | |
99 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
100 | break; | |
101 | case EVENT_TYPE_CMD_HARD_ERR: | |
102 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
103 | "flags=0x%04x]\n", address, flags); | |
104 | break; | |
105 | case EVENT_TYPE_IOTLB_INV_TO: | |
106 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
107 | "address=0x%016llx]\n", | |
108 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
109 | address); | |
110 | break; | |
111 | case EVENT_TYPE_INV_DEV_REQ: | |
112 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
113 | "address=0x%016llx flags=0x%04x]\n", | |
114 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
115 | address, flags); | |
116 | break; | |
117 | default: | |
118 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
119 | } | |
120 | } | |
121 | ||
122 | static void iommu_poll_events(struct amd_iommu *iommu) | |
123 | { | |
124 | u32 head, tail; | |
125 | unsigned long flags; | |
126 | ||
127 | spin_lock_irqsave(&iommu->lock, flags); | |
128 | ||
129 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
130 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
131 | ||
132 | while (head != tail) { | |
133 | iommu_print_event(iommu->evt_buf + head); | |
134 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
135 | } | |
136 | ||
137 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
138 | ||
139 | spin_unlock_irqrestore(&iommu->lock, flags); | |
140 | } | |
141 | ||
a80dc3e0 JR |
142 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
143 | { | |
90008ee4 JR |
144 | struct amd_iommu *iommu; |
145 | ||
146 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
147 | iommu_poll_events(iommu); | |
148 | ||
149 | return IRQ_HANDLED; | |
a80dc3e0 JR |
150 | } |
151 | ||
431b2a20 JR |
152 | /**************************************************************************** |
153 | * | |
154 | * IOMMU command queuing functions | |
155 | * | |
156 | ****************************************************************************/ | |
157 | ||
158 | /* | |
159 | * Writes the command to the IOMMUs command buffer and informs the | |
160 | * hardware about the new command. Must be called with iommu->lock held. | |
161 | */ | |
d6449536 | 162 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
163 | { |
164 | u32 tail, head; | |
165 | u8 *target; | |
166 | ||
167 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 168 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
169 | memcpy_toio(target, cmd, sizeof(*cmd)); |
170 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
171 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
172 | if (tail == head) | |
173 | return -ENOMEM; | |
174 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
431b2a20 JR |
179 | /* |
180 | * General queuing function for commands. Takes iommu->lock and calls | |
181 | * __iommu_queue_command(). | |
182 | */ | |
d6449536 | 183 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
184 | { |
185 | unsigned long flags; | |
186 | int ret; | |
187 | ||
188 | spin_lock_irqsave(&iommu->lock, flags); | |
189 | ret = __iommu_queue_command(iommu, cmd); | |
190 | spin_unlock_irqrestore(&iommu->lock, flags); | |
191 | ||
192 | return ret; | |
193 | } | |
194 | ||
431b2a20 JR |
195 | /* |
196 | * This function is called whenever we need to ensure that the IOMMU has | |
197 | * completed execution of all commands we sent. It sends a | |
198 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
199 | * us about that by writing a value to a physical address we pass with | |
200 | * the command. | |
201 | */ | |
a19ae1ec JR |
202 | static int iommu_completion_wait(struct amd_iommu *iommu) |
203 | { | |
7e4f88da | 204 | int ret = 0, ready = 0; |
519c31ba | 205 | unsigned status = 0; |
d6449536 | 206 | struct iommu_cmd cmd; |
7e4f88da | 207 | unsigned long flags, i = 0; |
a19ae1ec JR |
208 | |
209 | memset(&cmd, 0, sizeof(cmd)); | |
519c31ba | 210 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; |
a19ae1ec JR |
211 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); |
212 | ||
213 | iommu->need_sync = 0; | |
214 | ||
7e4f88da JR |
215 | spin_lock_irqsave(&iommu->lock, flags); |
216 | ||
217 | ret = __iommu_queue_command(iommu, &cmd); | |
a19ae1ec JR |
218 | |
219 | if (ret) | |
7e4f88da | 220 | goto out; |
a19ae1ec | 221 | |
136f78a1 JR |
222 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
223 | ++i; | |
519c31ba JR |
224 | /* wait for the bit to become one */ |
225 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
226 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
136f78a1 JR |
227 | } |
228 | ||
519c31ba JR |
229 | /* set bit back to zero */ |
230 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
231 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
232 | ||
136f78a1 JR |
233 | if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit())) |
234 | printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n"); | |
7e4f88da JR |
235 | out: |
236 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
237 | |
238 | return 0; | |
239 | } | |
240 | ||
431b2a20 JR |
241 | /* |
242 | * Command send function for invalidating a device table entry | |
243 | */ | |
a19ae1ec JR |
244 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
245 | { | |
d6449536 | 246 | struct iommu_cmd cmd; |
ee2fa743 | 247 | int ret; |
a19ae1ec JR |
248 | |
249 | BUG_ON(iommu == NULL); | |
250 | ||
251 | memset(&cmd, 0, sizeof(cmd)); | |
252 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
253 | cmd.data[0] = devid; | |
254 | ||
ee2fa743 JR |
255 | ret = iommu_queue_command(iommu, &cmd); |
256 | ||
a19ae1ec JR |
257 | iommu->need_sync = 1; |
258 | ||
ee2fa743 | 259 | return ret; |
a19ae1ec JR |
260 | } |
261 | ||
431b2a20 JR |
262 | /* |
263 | * Generic command send function for invalidaing TLB entries | |
264 | */ | |
a19ae1ec JR |
265 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
266 | u64 address, u16 domid, int pde, int s) | |
267 | { | |
d6449536 | 268 | struct iommu_cmd cmd; |
ee2fa743 | 269 | int ret; |
a19ae1ec JR |
270 | |
271 | memset(&cmd, 0, sizeof(cmd)); | |
272 | address &= PAGE_MASK; | |
273 | CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES); | |
274 | cmd.data[1] |= domid; | |
8a456695 | 275 | cmd.data[2] = lower_32_bits(address); |
8ea80d78 | 276 | cmd.data[3] = upper_32_bits(address); |
431b2a20 | 277 | if (s) /* size bit - we flush more than one 4kb page */ |
a19ae1ec | 278 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
431b2a20 | 279 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ |
a19ae1ec JR |
280 | cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
281 | ||
ee2fa743 JR |
282 | ret = iommu_queue_command(iommu, &cmd); |
283 | ||
a19ae1ec JR |
284 | iommu->need_sync = 1; |
285 | ||
ee2fa743 | 286 | return ret; |
a19ae1ec JR |
287 | } |
288 | ||
431b2a20 JR |
289 | /* |
290 | * TLB invalidation function which is called from the mapping functions. | |
291 | * It invalidates a single PTE if the range to flush is within a single | |
292 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
293 | */ | |
a19ae1ec JR |
294 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
295 | u64 address, size_t size) | |
296 | { | |
999ba417 | 297 | int s = 0; |
e3c449f5 | 298 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
299 | |
300 | address &= PAGE_MASK; | |
301 | ||
999ba417 JR |
302 | if (pages > 1) { |
303 | /* | |
304 | * If we have to flush more than one page, flush all | |
305 | * TLB entries for this domain | |
306 | */ | |
307 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
308 | s = 1; | |
a19ae1ec JR |
309 | } |
310 | ||
999ba417 JR |
311 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
312 | ||
a19ae1ec JR |
313 | return 0; |
314 | } | |
b6c02715 | 315 | |
1c655773 JR |
316 | /* Flush the whole IO/TLB for a given protection domain */ |
317 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
318 | { | |
319 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
320 | ||
321 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
322 | } | |
323 | ||
431b2a20 JR |
324 | /**************************************************************************** |
325 | * | |
326 | * The functions below are used the create the page table mappings for | |
327 | * unity mapped regions. | |
328 | * | |
329 | ****************************************************************************/ | |
330 | ||
331 | /* | |
332 | * Generic mapping functions. It maps a physical address into a DMA | |
333 | * address space. It allocates the page table pages if necessary. | |
334 | * In the future it can be extended to a generic mapping function | |
335 | * supporting all features of AMD IOMMU page tables like level skipping | |
336 | * and full 64 bit address spaces. | |
337 | */ | |
bd0e5211 JR |
338 | static int iommu_map(struct protection_domain *dom, |
339 | unsigned long bus_addr, | |
340 | unsigned long phys_addr, | |
341 | int prot) | |
342 | { | |
343 | u64 __pte, *pte, *page; | |
344 | ||
345 | bus_addr = PAGE_ALIGN(bus_addr); | |
346 | phys_addr = PAGE_ALIGN(bus_addr); | |
347 | ||
348 | /* only support 512GB address spaces for now */ | |
349 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
350 | return -EINVAL; | |
351 | ||
352 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
353 | ||
354 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
355 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
356 | if (!page) | |
357 | return -ENOMEM; | |
358 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
359 | } | |
360 | ||
361 | pte = IOMMU_PTE_PAGE(*pte); | |
362 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
363 | ||
364 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
365 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
366 | if (!page) | |
367 | return -ENOMEM; | |
368 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
369 | } | |
370 | ||
371 | pte = IOMMU_PTE_PAGE(*pte); | |
372 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
373 | ||
374 | if (IOMMU_PTE_PRESENT(*pte)) | |
375 | return -EBUSY; | |
376 | ||
377 | __pte = phys_addr | IOMMU_PTE_P; | |
378 | if (prot & IOMMU_PROT_IR) | |
379 | __pte |= IOMMU_PTE_IR; | |
380 | if (prot & IOMMU_PROT_IW) | |
381 | __pte |= IOMMU_PTE_IW; | |
382 | ||
383 | *pte = __pte; | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
431b2a20 JR |
388 | /* |
389 | * This function checks if a specific unity mapping entry is needed for | |
390 | * this specific IOMMU. | |
391 | */ | |
bd0e5211 JR |
392 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
393 | struct unity_map_entry *entry) | |
394 | { | |
395 | u16 bdf, i; | |
396 | ||
397 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
398 | bdf = amd_iommu_alias_table[i]; | |
399 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
400 | return 1; | |
401 | } | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
431b2a20 JR |
406 | /* |
407 | * Init the unity mappings for a specific IOMMU in the system | |
408 | * | |
409 | * Basically iterates over all unity mapping entries and applies them to | |
410 | * the default domain DMA of that IOMMU if necessary. | |
411 | */ | |
bd0e5211 JR |
412 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
413 | { | |
414 | struct unity_map_entry *entry; | |
415 | int ret; | |
416 | ||
417 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
418 | if (!iommu_for_unity_map(iommu, entry)) | |
419 | continue; | |
420 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
421 | if (ret) | |
422 | return ret; | |
423 | } | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
431b2a20 JR |
428 | /* |
429 | * This function actually applies the mapping to the page table of the | |
430 | * dma_ops domain. | |
431 | */ | |
bd0e5211 JR |
432 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
433 | struct unity_map_entry *e) | |
434 | { | |
435 | u64 addr; | |
436 | int ret; | |
437 | ||
438 | for (addr = e->address_start; addr < e->address_end; | |
439 | addr += PAGE_SIZE) { | |
440 | ret = iommu_map(&dma_dom->domain, addr, addr, e->prot); | |
441 | if (ret) | |
442 | return ret; | |
443 | /* | |
444 | * if unity mapping is in aperture range mark the page | |
445 | * as allocated in the aperture | |
446 | */ | |
447 | if (addr < dma_dom->aperture_size) | |
448 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
431b2a20 JR |
454 | /* |
455 | * Inits the unity mappings required for a specific device | |
456 | */ | |
bd0e5211 JR |
457 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
458 | u16 devid) | |
459 | { | |
460 | struct unity_map_entry *e; | |
461 | int ret; | |
462 | ||
463 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
464 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
465 | continue; | |
466 | ret = dma_ops_unity_map(dma_dom, e); | |
467 | if (ret) | |
468 | return ret; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
431b2a20 JR |
474 | /**************************************************************************** |
475 | * | |
476 | * The next functions belong to the address allocator for the dma_ops | |
477 | * interface functions. They work like the allocators in the other IOMMU | |
478 | * drivers. Its basically a bitmap which marks the allocated pages in | |
479 | * the aperture. Maybe it could be enhanced in the future to a more | |
480 | * efficient allocator. | |
481 | * | |
482 | ****************************************************************************/ | |
d3086444 | 483 | |
431b2a20 JR |
484 | /* |
485 | * The address allocator core function. | |
486 | * | |
487 | * called with domain->lock held | |
488 | */ | |
d3086444 JR |
489 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
490 | struct dma_ops_domain *dom, | |
6d4f343f | 491 | unsigned int pages, |
832a90c3 JR |
492 | unsigned long align_mask, |
493 | u64 dma_mask) | |
d3086444 | 494 | { |
40becd8d | 495 | unsigned long limit; |
d3086444 | 496 | unsigned long address; |
d3086444 JR |
497 | unsigned long boundary_size; |
498 | ||
499 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
500 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
501 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
502 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 503 | |
1c655773 | 504 | if (dom->next_bit >= limit) { |
d3086444 | 505 | dom->next_bit = 0; |
1c655773 JR |
506 | dom->need_flush = true; |
507 | } | |
d3086444 JR |
508 | |
509 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 510 | 0 , boundary_size, align_mask); |
1c655773 | 511 | if (address == -1) { |
d3086444 | 512 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 513 | 0, boundary_size, align_mask); |
1c655773 JR |
514 | dom->need_flush = true; |
515 | } | |
d3086444 JR |
516 | |
517 | if (likely(address != -1)) { | |
d3086444 JR |
518 | dom->next_bit = address + pages; |
519 | address <<= PAGE_SHIFT; | |
520 | } else | |
521 | address = bad_dma_address; | |
522 | ||
523 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
524 | ||
525 | return address; | |
526 | } | |
527 | ||
431b2a20 JR |
528 | /* |
529 | * The address free function. | |
530 | * | |
531 | * called with domain->lock held | |
532 | */ | |
d3086444 JR |
533 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
534 | unsigned long address, | |
535 | unsigned int pages) | |
536 | { | |
537 | address >>= PAGE_SHIFT; | |
538 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d JR |
539 | |
540 | if (address + pages >= dom->next_bit) | |
541 | dom->need_flush = true; | |
d3086444 JR |
542 | } |
543 | ||
431b2a20 JR |
544 | /**************************************************************************** |
545 | * | |
546 | * The next functions belong to the domain allocation. A domain is | |
547 | * allocated for every IOMMU as the default domain. If device isolation | |
548 | * is enabled, every device get its own domain. The most important thing | |
549 | * about domains is the page table mapping the DMA address space they | |
550 | * contain. | |
551 | * | |
552 | ****************************************************************************/ | |
553 | ||
ec487d1a JR |
554 | static u16 domain_id_alloc(void) |
555 | { | |
556 | unsigned long flags; | |
557 | int id; | |
558 | ||
559 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
560 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
561 | BUG_ON(id == 0); | |
562 | if (id > 0 && id < MAX_DOMAIN_ID) | |
563 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
564 | else | |
565 | id = 0; | |
566 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
567 | ||
568 | return id; | |
569 | } | |
570 | ||
431b2a20 JR |
571 | /* |
572 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
573 | * ranges. | |
574 | */ | |
ec487d1a JR |
575 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
576 | unsigned long start_page, | |
577 | unsigned int pages) | |
578 | { | |
579 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
580 | ||
581 | if (start_page + pages > last_page) | |
582 | pages = last_page - start_page; | |
583 | ||
d26dbc5c | 584 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
585 | } |
586 | ||
587 | static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom) | |
588 | { | |
589 | int i, j; | |
590 | u64 *p1, *p2, *p3; | |
591 | ||
592 | p1 = dma_dom->domain.pt_root; | |
593 | ||
594 | if (!p1) | |
595 | return; | |
596 | ||
597 | for (i = 0; i < 512; ++i) { | |
598 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
599 | continue; | |
600 | ||
601 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
602 | for (j = 0; j < 512; ++i) { | |
603 | if (!IOMMU_PTE_PRESENT(p2[j])) | |
604 | continue; | |
605 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
606 | free_page((unsigned long)p3); | |
607 | } | |
608 | ||
609 | free_page((unsigned long)p2); | |
610 | } | |
611 | ||
612 | free_page((unsigned long)p1); | |
613 | } | |
614 | ||
431b2a20 JR |
615 | /* |
616 | * Free a domain, only used if something went wrong in the | |
617 | * allocation path and we need to free an already allocated page table | |
618 | */ | |
ec487d1a JR |
619 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
620 | { | |
621 | if (!dom) | |
622 | return; | |
623 | ||
624 | dma_ops_free_pagetable(dom); | |
625 | ||
626 | kfree(dom->pte_pages); | |
627 | ||
628 | kfree(dom->bitmap); | |
629 | ||
630 | kfree(dom); | |
631 | } | |
632 | ||
431b2a20 JR |
633 | /* |
634 | * Allocates a new protection domain usable for the dma_ops functions. | |
635 | * It also intializes the page table and the address allocator data | |
636 | * structures required for the dma_ops interface | |
637 | */ | |
ec487d1a JR |
638 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
639 | unsigned order) | |
640 | { | |
641 | struct dma_ops_domain *dma_dom; | |
642 | unsigned i, num_pte_pages; | |
643 | u64 *l2_pde; | |
644 | u64 address; | |
645 | ||
646 | /* | |
647 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
648 | */ | |
649 | if ((order < 25) || (order > 30)) | |
650 | return NULL; | |
651 | ||
652 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
653 | if (!dma_dom) | |
654 | return NULL; | |
655 | ||
656 | spin_lock_init(&dma_dom->domain.lock); | |
657 | ||
658 | dma_dom->domain.id = domain_id_alloc(); | |
659 | if (dma_dom->domain.id == 0) | |
660 | goto free_dma_dom; | |
661 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
662 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
663 | dma_dom->domain.priv = dma_dom; | |
664 | if (!dma_dom->domain.pt_root) | |
665 | goto free_dma_dom; | |
666 | dma_dom->aperture_size = (1ULL << order); | |
667 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
668 | GFP_KERNEL); | |
669 | if (!dma_dom->bitmap) | |
670 | goto free_dma_dom; | |
671 | /* | |
672 | * mark the first page as allocated so we never return 0 as | |
673 | * a valid dma-address. So we can use 0 as error value | |
674 | */ | |
675 | dma_dom->bitmap[0] = 1; | |
676 | dma_dom->next_bit = 0; | |
677 | ||
1c655773 | 678 | dma_dom->need_flush = false; |
bd60b735 | 679 | dma_dom->target_dev = 0xffff; |
1c655773 | 680 | |
431b2a20 | 681 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
682 | if (iommu->exclusion_start && |
683 | iommu->exclusion_start < dma_dom->aperture_size) { | |
684 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
685 | int pages = iommu_num_pages(iommu->exclusion_start, |
686 | iommu->exclusion_length, | |
687 | PAGE_SIZE); | |
ec487d1a JR |
688 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
689 | } | |
690 | ||
431b2a20 JR |
691 | /* |
692 | * At the last step, build the page tables so we don't need to | |
693 | * allocate page table pages in the dma_ops mapping/unmapping | |
694 | * path. | |
695 | */ | |
ec487d1a JR |
696 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
697 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
698 | GFP_KERNEL); | |
699 | if (!dma_dom->pte_pages) | |
700 | goto free_dma_dom; | |
701 | ||
702 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
703 | if (l2_pde == NULL) | |
704 | goto free_dma_dom; | |
705 | ||
706 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
707 | ||
708 | for (i = 0; i < num_pte_pages; ++i) { | |
709 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
710 | if (!dma_dom->pte_pages[i]) | |
711 | goto free_dma_dom; | |
712 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
713 | l2_pde[i] = IOMMU_L1_PDE(address); | |
714 | } | |
715 | ||
716 | return dma_dom; | |
717 | ||
718 | free_dma_dom: | |
719 | dma_ops_domain_free(dma_dom); | |
720 | ||
721 | return NULL; | |
722 | } | |
723 | ||
431b2a20 JR |
724 | /* |
725 | * Find out the protection domain structure for a given PCI device. This | |
726 | * will give us the pointer to the page table root for example. | |
727 | */ | |
b20ac0d4 JR |
728 | static struct protection_domain *domain_for_device(u16 devid) |
729 | { | |
730 | struct protection_domain *dom; | |
731 | unsigned long flags; | |
732 | ||
733 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
734 | dom = amd_iommu_pd_table[devid]; | |
735 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
736 | ||
737 | return dom; | |
738 | } | |
739 | ||
431b2a20 JR |
740 | /* |
741 | * If a device is not yet associated with a domain, this function does | |
742 | * assigns it visible for the hardware | |
743 | */ | |
b20ac0d4 JR |
744 | static void set_device_domain(struct amd_iommu *iommu, |
745 | struct protection_domain *domain, | |
746 | u16 devid) | |
747 | { | |
748 | unsigned long flags; | |
749 | ||
750 | u64 pte_root = virt_to_phys(domain->pt_root); | |
751 | ||
38ddf41b JR |
752 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
753 | << DEV_ENTRY_MODE_SHIFT; | |
754 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
755 | |
756 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
757 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
758 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
759 | amd_iommu_dev_table[devid].data[2] = domain->id; |
760 | ||
761 | amd_iommu_pd_table[devid] = domain; | |
762 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
763 | ||
764 | iommu_queue_inv_dev_entry(iommu, devid); | |
765 | ||
766 | iommu->need_sync = 1; | |
767 | } | |
768 | ||
431b2a20 JR |
769 | /***************************************************************************** |
770 | * | |
771 | * The next functions belong to the dma_ops mapping/unmapping code. | |
772 | * | |
773 | *****************************************************************************/ | |
774 | ||
dbcc112e JR |
775 | /* |
776 | * This function checks if the driver got a valid device from the caller to | |
777 | * avoid dereferencing invalid pointers. | |
778 | */ | |
779 | static bool check_device(struct device *dev) | |
780 | { | |
781 | if (!dev || !dev->dma_mask) | |
782 | return false; | |
783 | ||
784 | return true; | |
785 | } | |
786 | ||
bd60b735 JR |
787 | /* |
788 | * In this function the list of preallocated protection domains is traversed to | |
789 | * find the domain for a specific device | |
790 | */ | |
791 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
792 | { | |
793 | struct dma_ops_domain *entry, *ret = NULL; | |
794 | unsigned long flags; | |
795 | ||
796 | if (list_empty(&iommu_pd_list)) | |
797 | return NULL; | |
798 | ||
799 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
800 | ||
801 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
802 | if (entry->target_dev == devid) { | |
803 | ret = entry; | |
804 | list_del(&ret->list); | |
805 | break; | |
806 | } | |
807 | } | |
808 | ||
809 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
810 | ||
811 | return ret; | |
812 | } | |
813 | ||
431b2a20 JR |
814 | /* |
815 | * In the dma_ops path we only have the struct device. This function | |
816 | * finds the corresponding IOMMU, the protection domain and the | |
817 | * requestor id for a given device. | |
818 | * If the device is not yet associated with a domain this is also done | |
819 | * in this function. | |
820 | */ | |
b20ac0d4 JR |
821 | static int get_device_resources(struct device *dev, |
822 | struct amd_iommu **iommu, | |
823 | struct protection_domain **domain, | |
824 | u16 *bdf) | |
825 | { | |
826 | struct dma_ops_domain *dma_dom; | |
827 | struct pci_dev *pcidev; | |
828 | u16 _bdf; | |
829 | ||
dbcc112e JR |
830 | *iommu = NULL; |
831 | *domain = NULL; | |
832 | *bdf = 0xffff; | |
833 | ||
834 | if (dev->bus != &pci_bus_type) | |
835 | return 0; | |
b20ac0d4 JR |
836 | |
837 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 838 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 839 | |
431b2a20 | 840 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 841 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 842 | return 0; |
b20ac0d4 JR |
843 | |
844 | *bdf = amd_iommu_alias_table[_bdf]; | |
845 | ||
846 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
847 | if (*iommu == NULL) | |
848 | return 0; | |
b20ac0d4 JR |
849 | *domain = domain_for_device(*bdf); |
850 | if (*domain == NULL) { | |
bd60b735 JR |
851 | dma_dom = find_protection_domain(*bdf); |
852 | if (!dma_dom) | |
853 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 JR |
854 | *domain = &dma_dom->domain; |
855 | set_device_domain(*iommu, *domain, *bdf); | |
856 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
857 | "device ", (*domain)->id); | |
858 | print_devid(_bdf, 1); | |
859 | } | |
860 | ||
861 | return 1; | |
862 | } | |
863 | ||
431b2a20 JR |
864 | /* |
865 | * This is the generic map function. It maps one 4kb page at paddr to | |
866 | * the given address in the DMA address space for the domain. | |
867 | */ | |
cb76c322 JR |
868 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
869 | struct dma_ops_domain *dom, | |
870 | unsigned long address, | |
871 | phys_addr_t paddr, | |
872 | int direction) | |
873 | { | |
874 | u64 *pte, __pte; | |
875 | ||
876 | WARN_ON(address > dom->aperture_size); | |
877 | ||
878 | paddr &= PAGE_MASK; | |
879 | ||
880 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
881 | pte += IOMMU_PTE_L0_INDEX(address); | |
882 | ||
883 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
884 | ||
885 | if (direction == DMA_TO_DEVICE) | |
886 | __pte |= IOMMU_PTE_IR; | |
887 | else if (direction == DMA_FROM_DEVICE) | |
888 | __pte |= IOMMU_PTE_IW; | |
889 | else if (direction == DMA_BIDIRECTIONAL) | |
890 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
891 | ||
892 | WARN_ON(*pte); | |
893 | ||
894 | *pte = __pte; | |
895 | ||
896 | return (dma_addr_t)address; | |
897 | } | |
898 | ||
431b2a20 JR |
899 | /* |
900 | * The generic unmapping function for on page in the DMA address space. | |
901 | */ | |
cb76c322 JR |
902 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
903 | struct dma_ops_domain *dom, | |
904 | unsigned long address) | |
905 | { | |
906 | u64 *pte; | |
907 | ||
908 | if (address >= dom->aperture_size) | |
909 | return; | |
910 | ||
911 | WARN_ON(address & 0xfffULL || address > dom->aperture_size); | |
912 | ||
913 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
914 | pte += IOMMU_PTE_L0_INDEX(address); | |
915 | ||
916 | WARN_ON(!*pte); | |
917 | ||
918 | *pte = 0ULL; | |
919 | } | |
920 | ||
431b2a20 JR |
921 | /* |
922 | * This function contains common code for mapping of a physically | |
923 | * contiguous memory region into DMA address space. It is uses by all | |
924 | * mapping functions provided by this IOMMU driver. | |
925 | * Must be called with the domain lock held. | |
926 | */ | |
cb76c322 JR |
927 | static dma_addr_t __map_single(struct device *dev, |
928 | struct amd_iommu *iommu, | |
929 | struct dma_ops_domain *dma_dom, | |
930 | phys_addr_t paddr, | |
931 | size_t size, | |
6d4f343f | 932 | int dir, |
832a90c3 JR |
933 | bool align, |
934 | u64 dma_mask) | |
cb76c322 JR |
935 | { |
936 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
937 | dma_addr_t address, start; | |
938 | unsigned int pages; | |
6d4f343f | 939 | unsigned long align_mask = 0; |
cb76c322 JR |
940 | int i; |
941 | ||
e3c449f5 | 942 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
943 | paddr &= PAGE_MASK; |
944 | ||
6d4f343f JR |
945 | if (align) |
946 | align_mask = (1UL << get_order(size)) - 1; | |
947 | ||
832a90c3 JR |
948 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
949 | dma_mask); | |
cb76c322 JR |
950 | if (unlikely(address == bad_dma_address)) |
951 | goto out; | |
952 | ||
953 | start = address; | |
954 | for (i = 0; i < pages; ++i) { | |
955 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
956 | paddr += PAGE_SIZE; | |
957 | start += PAGE_SIZE; | |
958 | } | |
959 | address += offset; | |
960 | ||
afa9fdc2 | 961 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
962 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
963 | dma_dom->need_flush = false; | |
964 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
965 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
966 | ||
cb76c322 JR |
967 | out: |
968 | return address; | |
969 | } | |
970 | ||
431b2a20 JR |
971 | /* |
972 | * Does the reverse of the __map_single function. Must be called with | |
973 | * the domain lock held too | |
974 | */ | |
cb76c322 JR |
975 | static void __unmap_single(struct amd_iommu *iommu, |
976 | struct dma_ops_domain *dma_dom, | |
977 | dma_addr_t dma_addr, | |
978 | size_t size, | |
979 | int dir) | |
980 | { | |
981 | dma_addr_t i, start; | |
982 | unsigned int pages; | |
983 | ||
984 | if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) | |
985 | return; | |
986 | ||
e3c449f5 | 987 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
988 | dma_addr &= PAGE_MASK; |
989 | start = dma_addr; | |
990 | ||
991 | for (i = 0; i < pages; ++i) { | |
992 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
993 | start += PAGE_SIZE; | |
994 | } | |
995 | ||
996 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 997 | |
80be308d | 998 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 999 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1000 | dma_dom->need_flush = false; |
1001 | } | |
cb76c322 JR |
1002 | } |
1003 | ||
431b2a20 JR |
1004 | /* |
1005 | * The exported map_single function for dma_ops. | |
1006 | */ | |
4da70b9e JR |
1007 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1008 | size_t size, int dir) | |
1009 | { | |
1010 | unsigned long flags; | |
1011 | struct amd_iommu *iommu; | |
1012 | struct protection_domain *domain; | |
1013 | u16 devid; | |
1014 | dma_addr_t addr; | |
832a90c3 | 1015 | u64 dma_mask; |
4da70b9e | 1016 | |
dbcc112e JR |
1017 | if (!check_device(dev)) |
1018 | return bad_dma_address; | |
1019 | ||
832a90c3 | 1020 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1021 | |
1022 | get_device_resources(dev, &iommu, &domain, &devid); | |
1023 | ||
1024 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1025 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1026 | return (dma_addr_t)paddr; |
1027 | ||
1028 | spin_lock_irqsave(&domain->lock, flags); | |
832a90c3 JR |
1029 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1030 | dma_mask); | |
4da70b9e JR |
1031 | if (addr == bad_dma_address) |
1032 | goto out; | |
1033 | ||
5507eef8 | 1034 | if (unlikely(iommu->need_sync)) |
4da70b9e JR |
1035 | iommu_completion_wait(iommu); |
1036 | ||
1037 | out: | |
1038 | spin_unlock_irqrestore(&domain->lock, flags); | |
1039 | ||
1040 | return addr; | |
1041 | } | |
1042 | ||
431b2a20 JR |
1043 | /* |
1044 | * The exported unmap_single function for dma_ops. | |
1045 | */ | |
4da70b9e JR |
1046 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1047 | size_t size, int dir) | |
1048 | { | |
1049 | unsigned long flags; | |
1050 | struct amd_iommu *iommu; | |
1051 | struct protection_domain *domain; | |
1052 | u16 devid; | |
1053 | ||
dbcc112e JR |
1054 | if (!check_device(dev) || |
1055 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1056 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1057 | return; |
1058 | ||
1059 | spin_lock_irqsave(&domain->lock, flags); | |
1060 | ||
1061 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1062 | ||
5507eef8 | 1063 | if (unlikely(iommu->need_sync)) |
4da70b9e JR |
1064 | iommu_completion_wait(iommu); |
1065 | ||
1066 | spin_unlock_irqrestore(&domain->lock, flags); | |
1067 | } | |
1068 | ||
431b2a20 JR |
1069 | /* |
1070 | * This is a special map_sg function which is used if we should map a | |
1071 | * device which is not handled by an AMD IOMMU in the system. | |
1072 | */ | |
65b050ad JR |
1073 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1074 | int nelems, int dir) | |
1075 | { | |
1076 | struct scatterlist *s; | |
1077 | int i; | |
1078 | ||
1079 | for_each_sg(sglist, s, nelems, i) { | |
1080 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1081 | s->dma_length = s->length; | |
1082 | } | |
1083 | ||
1084 | return nelems; | |
1085 | } | |
1086 | ||
431b2a20 JR |
1087 | /* |
1088 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1089 | * lists). | |
1090 | */ | |
65b050ad JR |
1091 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1092 | int nelems, int dir) | |
1093 | { | |
1094 | unsigned long flags; | |
1095 | struct amd_iommu *iommu; | |
1096 | struct protection_domain *domain; | |
1097 | u16 devid; | |
1098 | int i; | |
1099 | struct scatterlist *s; | |
1100 | phys_addr_t paddr; | |
1101 | int mapped_elems = 0; | |
832a90c3 | 1102 | u64 dma_mask; |
65b050ad | 1103 | |
dbcc112e JR |
1104 | if (!check_device(dev)) |
1105 | return 0; | |
1106 | ||
832a90c3 | 1107 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1108 | |
1109 | get_device_resources(dev, &iommu, &domain, &devid); | |
1110 | ||
1111 | if (!iommu || !domain) | |
1112 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1113 | ||
1114 | spin_lock_irqsave(&domain->lock, flags); | |
1115 | ||
1116 | for_each_sg(sglist, s, nelems, i) { | |
1117 | paddr = sg_phys(s); | |
1118 | ||
1119 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1120 | paddr, s->length, dir, false, |
1121 | dma_mask); | |
65b050ad JR |
1122 | |
1123 | if (s->dma_address) { | |
1124 | s->dma_length = s->length; | |
1125 | mapped_elems++; | |
1126 | } else | |
1127 | goto unmap; | |
65b050ad JR |
1128 | } |
1129 | ||
5507eef8 | 1130 | if (unlikely(iommu->need_sync)) |
65b050ad JR |
1131 | iommu_completion_wait(iommu); |
1132 | ||
1133 | out: | |
1134 | spin_unlock_irqrestore(&domain->lock, flags); | |
1135 | ||
1136 | return mapped_elems; | |
1137 | unmap: | |
1138 | for_each_sg(sglist, s, mapped_elems, i) { | |
1139 | if (s->dma_address) | |
1140 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1141 | s->dma_length, dir); | |
1142 | s->dma_address = s->dma_length = 0; | |
1143 | } | |
1144 | ||
1145 | mapped_elems = 0; | |
1146 | ||
1147 | goto out; | |
1148 | } | |
1149 | ||
431b2a20 JR |
1150 | /* |
1151 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1152 | * lists). | |
1153 | */ | |
65b050ad JR |
1154 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1155 | int nelems, int dir) | |
1156 | { | |
1157 | unsigned long flags; | |
1158 | struct amd_iommu *iommu; | |
1159 | struct protection_domain *domain; | |
1160 | struct scatterlist *s; | |
1161 | u16 devid; | |
1162 | int i; | |
1163 | ||
dbcc112e JR |
1164 | if (!check_device(dev) || |
1165 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1166 | return; |
1167 | ||
1168 | spin_lock_irqsave(&domain->lock, flags); | |
1169 | ||
1170 | for_each_sg(sglist, s, nelems, i) { | |
1171 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1172 | s->dma_length, dir); | |
65b050ad JR |
1173 | s->dma_address = s->dma_length = 0; |
1174 | } | |
1175 | ||
5507eef8 | 1176 | if (unlikely(iommu->need_sync)) |
65b050ad JR |
1177 | iommu_completion_wait(iommu); |
1178 | ||
1179 | spin_unlock_irqrestore(&domain->lock, flags); | |
1180 | } | |
1181 | ||
431b2a20 JR |
1182 | /* |
1183 | * The exported alloc_coherent function for dma_ops. | |
1184 | */ | |
5d8b53cf JR |
1185 | static void *alloc_coherent(struct device *dev, size_t size, |
1186 | dma_addr_t *dma_addr, gfp_t flag) | |
1187 | { | |
1188 | unsigned long flags; | |
1189 | void *virt_addr; | |
1190 | struct amd_iommu *iommu; | |
1191 | struct protection_domain *domain; | |
1192 | u16 devid; | |
1193 | phys_addr_t paddr; | |
832a90c3 | 1194 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1195 | |
dbcc112e JR |
1196 | if (!check_device(dev)) |
1197 | return NULL; | |
5d8b53cf | 1198 | |
13d9fead FT |
1199 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1200 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1201 | |
c97ac535 | 1202 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1203 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1204 | if (!virt_addr) | |
1205 | return 0; | |
1206 | ||
5d8b53cf JR |
1207 | paddr = virt_to_phys(virt_addr); |
1208 | ||
5d8b53cf JR |
1209 | if (!iommu || !domain) { |
1210 | *dma_addr = (dma_addr_t)paddr; | |
1211 | return virt_addr; | |
1212 | } | |
1213 | ||
832a90c3 JR |
1214 | if (!dma_mask) |
1215 | dma_mask = *dev->dma_mask; | |
1216 | ||
5d8b53cf JR |
1217 | spin_lock_irqsave(&domain->lock, flags); |
1218 | ||
1219 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1220 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf JR |
1221 | |
1222 | if (*dma_addr == bad_dma_address) { | |
1223 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1224 | virt_addr = NULL; | |
1225 | goto out; | |
1226 | } | |
1227 | ||
5507eef8 | 1228 | if (unlikely(iommu->need_sync)) |
5d8b53cf JR |
1229 | iommu_completion_wait(iommu); |
1230 | ||
1231 | out: | |
1232 | spin_unlock_irqrestore(&domain->lock, flags); | |
1233 | ||
1234 | return virt_addr; | |
1235 | } | |
1236 | ||
431b2a20 JR |
1237 | /* |
1238 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1239 | */ |
5d8b53cf JR |
1240 | static void free_coherent(struct device *dev, size_t size, |
1241 | void *virt_addr, dma_addr_t dma_addr) | |
1242 | { | |
1243 | unsigned long flags; | |
1244 | struct amd_iommu *iommu; | |
1245 | struct protection_domain *domain; | |
1246 | u16 devid; | |
1247 | ||
dbcc112e JR |
1248 | if (!check_device(dev)) |
1249 | return; | |
1250 | ||
5d8b53cf JR |
1251 | get_device_resources(dev, &iommu, &domain, &devid); |
1252 | ||
1253 | if (!iommu || !domain) | |
1254 | goto free_mem; | |
1255 | ||
1256 | spin_lock_irqsave(&domain->lock, flags); | |
1257 | ||
1258 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1259 | |
5507eef8 | 1260 | if (unlikely(iommu->need_sync)) |
5d8b53cf JR |
1261 | iommu_completion_wait(iommu); |
1262 | ||
1263 | spin_unlock_irqrestore(&domain->lock, flags); | |
1264 | ||
1265 | free_mem: | |
1266 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1267 | } | |
1268 | ||
b39ba6ad JR |
1269 | /* |
1270 | * This function is called by the DMA layer to find out if we can handle a | |
1271 | * particular device. It is part of the dma_ops. | |
1272 | */ | |
1273 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1274 | { | |
1275 | u16 bdf; | |
1276 | struct pci_dev *pcidev; | |
1277 | ||
1278 | /* No device or no PCI device */ | |
1279 | if (!dev || dev->bus != &pci_bus_type) | |
1280 | return 0; | |
1281 | ||
1282 | pcidev = to_pci_dev(dev); | |
1283 | ||
1284 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1285 | ||
1286 | /* Out of our scope? */ | |
1287 | if (bdf > amd_iommu_last_bdf) | |
1288 | return 0; | |
1289 | ||
1290 | return 1; | |
1291 | } | |
1292 | ||
c432f3df | 1293 | /* |
431b2a20 JR |
1294 | * The function for pre-allocating protection domains. |
1295 | * | |
c432f3df JR |
1296 | * If the driver core informs the DMA layer if a driver grabs a device |
1297 | * we don't need to preallocate the protection domains anymore. | |
1298 | * For now we have to. | |
1299 | */ | |
1300 | void prealloc_protection_domains(void) | |
1301 | { | |
1302 | struct pci_dev *dev = NULL; | |
1303 | struct dma_ops_domain *dma_dom; | |
1304 | struct amd_iommu *iommu; | |
1305 | int order = amd_iommu_aperture_order; | |
1306 | u16 devid; | |
1307 | ||
1308 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1309 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1310 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1311 | continue; |
1312 | devid = amd_iommu_alias_table[devid]; | |
1313 | if (domain_for_device(devid)) | |
1314 | continue; | |
1315 | iommu = amd_iommu_rlookup_table[devid]; | |
1316 | if (!iommu) | |
1317 | continue; | |
1318 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1319 | if (!dma_dom) | |
1320 | continue; | |
1321 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1322 | dma_dom->target_dev = devid; |
1323 | ||
1324 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1325 | } |
1326 | } | |
1327 | ||
6631ee9d JR |
1328 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1329 | .alloc_coherent = alloc_coherent, | |
1330 | .free_coherent = free_coherent, | |
1331 | .map_single = map_single, | |
1332 | .unmap_single = unmap_single, | |
1333 | .map_sg = map_sg, | |
1334 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1335 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1336 | }; |
1337 | ||
431b2a20 JR |
1338 | /* |
1339 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1340 | */ | |
6631ee9d JR |
1341 | int __init amd_iommu_init_dma_ops(void) |
1342 | { | |
1343 | struct amd_iommu *iommu; | |
1344 | int order = amd_iommu_aperture_order; | |
1345 | int ret; | |
1346 | ||
431b2a20 JR |
1347 | /* |
1348 | * first allocate a default protection domain for every IOMMU we | |
1349 | * found in the system. Devices not assigned to any other | |
1350 | * protection domain will be assigned to the default one. | |
1351 | */ | |
6631ee9d JR |
1352 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1353 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1354 | if (iommu->default_dom == NULL) | |
1355 | return -ENOMEM; | |
1356 | ret = iommu_init_unity_mappings(iommu); | |
1357 | if (ret) | |
1358 | goto free_domains; | |
1359 | } | |
1360 | ||
431b2a20 JR |
1361 | /* |
1362 | * If device isolation is enabled, pre-allocate the protection | |
1363 | * domains for each device. | |
1364 | */ | |
6631ee9d JR |
1365 | if (amd_iommu_isolate) |
1366 | prealloc_protection_domains(); | |
1367 | ||
1368 | iommu_detected = 1; | |
1369 | force_iommu = 1; | |
1370 | bad_dma_address = 0; | |
92af4e29 | 1371 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1372 | gart_iommu_aperture_disabled = 1; |
1373 | gart_iommu_aperture = 0; | |
92af4e29 | 1374 | #endif |
6631ee9d | 1375 | |
431b2a20 | 1376 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1377 | dma_ops = &amd_iommu_dma_ops; |
1378 | ||
1379 | return 0; | |
1380 | ||
1381 | free_domains: | |
1382 | ||
1383 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1384 | if (iommu->default_dom) | |
1385 | dma_ops_domain_free(iommu->default_dom); | |
1386 | } | |
1387 | ||
1388 | return ret; | |
1389 | } |