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Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
0feae533 JR |
44 | /* |
45 | * Domain for untranslated devices - only allocated | |
46 | * if iommu=pt passed on kernel cmd line. | |
47 | */ | |
48 | static struct protection_domain *pt_domain; | |
49 | ||
26961efe JR |
50 | #ifdef CONFIG_IOMMU_API |
51 | static struct iommu_ops amd_iommu_ops; | |
52 | #endif | |
53 | ||
431b2a20 JR |
54 | /* |
55 | * general struct to manage commands send to an IOMMU | |
56 | */ | |
d6449536 | 57 | struct iommu_cmd { |
b6c02715 JR |
58 | u32 data[4]; |
59 | }; | |
60 | ||
bd0e5211 JR |
61 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
62 | struct unity_map_entry *e); | |
e275a2a0 | 63 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
64 | static u64* alloc_pte(struct protection_domain *dom, |
65 | unsigned long address, u64 | |
66 | **pte_page, gfp_t gfp); | |
00cd122a JR |
67 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
68 | unsigned long start_page, | |
69 | unsigned int pages); | |
bd0e5211 | 70 | |
c1eee67b CW |
71 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
72 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
73 | #endif | |
74 | ||
7f26508b JR |
75 | #ifdef CONFIG_AMD_IOMMU_STATS |
76 | ||
77 | /* | |
78 | * Initialization code for statistics collection | |
79 | */ | |
80 | ||
da49f6df | 81 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 82 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 83 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 84 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 85 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 86 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 87 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 88 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 89 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 90 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 91 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 92 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 93 | |
7f26508b JR |
94 | static struct dentry *stats_dir; |
95 | static struct dentry *de_isolate; | |
96 | static struct dentry *de_fflush; | |
97 | ||
98 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
99 | { | |
100 | if (stats_dir == NULL) | |
101 | return; | |
102 | ||
103 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
104 | &cnt->value); | |
105 | } | |
106 | ||
107 | static void amd_iommu_stats_init(void) | |
108 | { | |
109 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
110 | if (stats_dir == NULL) | |
111 | return; | |
112 | ||
113 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
114 | (u32 *)&amd_iommu_isolate); | |
115 | ||
116 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
117 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
118 | |
119 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 120 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 121 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 122 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 123 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 124 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 125 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 126 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 127 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 128 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 129 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 130 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
131 | } |
132 | ||
133 | #endif | |
134 | ||
431b2a20 | 135 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
136 | static int iommu_has_npcache(struct amd_iommu *iommu) |
137 | { | |
ae9b9403 | 138 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
139 | } |
140 | ||
a80dc3e0 JR |
141 | /**************************************************************************** |
142 | * | |
143 | * Interrupt handling functions | |
144 | * | |
145 | ****************************************************************************/ | |
146 | ||
90008ee4 JR |
147 | static void iommu_print_event(void *__evt) |
148 | { | |
149 | u32 *event = __evt; | |
150 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
151 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
152 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
153 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
154 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
155 | ||
156 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
157 | ||
158 | switch (type) { | |
159 | case EVENT_TYPE_ILL_DEV: | |
160 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
161 | "address=0x%016llx flags=0x%04x]\n", | |
162 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
163 | address, flags); | |
164 | break; | |
165 | case EVENT_TYPE_IO_FAULT: | |
166 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
167 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
168 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
169 | domid, address, flags); | |
170 | break; | |
171 | case EVENT_TYPE_DEV_TAB_ERR: | |
172 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
173 | "address=0x%016llx flags=0x%04x]\n", | |
174 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
175 | address, flags); | |
176 | break; | |
177 | case EVENT_TYPE_PAGE_TAB_ERR: | |
178 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
179 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
180 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
181 | domid, address, flags); | |
182 | break; | |
183 | case EVENT_TYPE_ILL_CMD: | |
184 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
185 | break; | |
186 | case EVENT_TYPE_CMD_HARD_ERR: | |
187 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
188 | "flags=0x%04x]\n", address, flags); | |
189 | break; | |
190 | case EVENT_TYPE_IOTLB_INV_TO: | |
191 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
192 | "address=0x%016llx]\n", | |
193 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
194 | address); | |
195 | break; | |
196 | case EVENT_TYPE_INV_DEV_REQ: | |
197 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
198 | "address=0x%016llx flags=0x%04x]\n", | |
199 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
200 | address, flags); | |
201 | break; | |
202 | default: | |
203 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
204 | } | |
205 | } | |
206 | ||
207 | static void iommu_poll_events(struct amd_iommu *iommu) | |
208 | { | |
209 | u32 head, tail; | |
210 | unsigned long flags; | |
211 | ||
212 | spin_lock_irqsave(&iommu->lock, flags); | |
213 | ||
214 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
215 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
216 | ||
217 | while (head != tail) { | |
218 | iommu_print_event(iommu->evt_buf + head); | |
219 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
220 | } | |
221 | ||
222 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
223 | ||
224 | spin_unlock_irqrestore(&iommu->lock, flags); | |
225 | } | |
226 | ||
a80dc3e0 JR |
227 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
228 | { | |
90008ee4 JR |
229 | struct amd_iommu *iommu; |
230 | ||
3bd22172 | 231 | for_each_iommu(iommu) |
90008ee4 JR |
232 | iommu_poll_events(iommu); |
233 | ||
234 | return IRQ_HANDLED; | |
a80dc3e0 JR |
235 | } |
236 | ||
431b2a20 JR |
237 | /**************************************************************************** |
238 | * | |
239 | * IOMMU command queuing functions | |
240 | * | |
241 | ****************************************************************************/ | |
242 | ||
243 | /* | |
244 | * Writes the command to the IOMMUs command buffer and informs the | |
245 | * hardware about the new command. Must be called with iommu->lock held. | |
246 | */ | |
d6449536 | 247 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
248 | { |
249 | u32 tail, head; | |
250 | u8 *target; | |
251 | ||
252 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 253 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
254 | memcpy_toio(target, cmd, sizeof(*cmd)); |
255 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
256 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
257 | if (tail == head) | |
258 | return -ENOMEM; | |
259 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
431b2a20 JR |
264 | /* |
265 | * General queuing function for commands. Takes iommu->lock and calls | |
266 | * __iommu_queue_command(). | |
267 | */ | |
d6449536 | 268 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
269 | { |
270 | unsigned long flags; | |
271 | int ret; | |
272 | ||
273 | spin_lock_irqsave(&iommu->lock, flags); | |
274 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 275 | if (!ret) |
0cfd7aa9 | 276 | iommu->need_sync = true; |
a19ae1ec JR |
277 | spin_unlock_irqrestore(&iommu->lock, flags); |
278 | ||
279 | return ret; | |
280 | } | |
281 | ||
8d201968 JR |
282 | /* |
283 | * This function waits until an IOMMU has completed a completion | |
284 | * wait command | |
285 | */ | |
286 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
287 | { | |
288 | int ready = 0; | |
289 | unsigned status = 0; | |
290 | unsigned long i = 0; | |
291 | ||
da49f6df JR |
292 | INC_STATS_COUNTER(compl_wait); |
293 | ||
8d201968 JR |
294 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
295 | ++i; | |
296 | /* wait for the bit to become one */ | |
297 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
298 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
299 | } | |
300 | ||
301 | /* set bit back to zero */ | |
302 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
303 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
304 | ||
305 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
306 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
307 | } | |
308 | ||
309 | /* | |
310 | * This function queues a completion wait command into the command | |
311 | * buffer of an IOMMU | |
312 | */ | |
313 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
314 | { | |
315 | struct iommu_cmd cmd; | |
316 | ||
317 | memset(&cmd, 0, sizeof(cmd)); | |
318 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
319 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
320 | ||
321 | return __iommu_queue_command(iommu, &cmd); | |
322 | } | |
323 | ||
431b2a20 JR |
324 | /* |
325 | * This function is called whenever we need to ensure that the IOMMU has | |
326 | * completed execution of all commands we sent. It sends a | |
327 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
328 | * us about that by writing a value to a physical address we pass with | |
329 | * the command. | |
330 | */ | |
a19ae1ec JR |
331 | static int iommu_completion_wait(struct amd_iommu *iommu) |
332 | { | |
8d201968 JR |
333 | int ret = 0; |
334 | unsigned long flags; | |
a19ae1ec | 335 | |
7e4f88da JR |
336 | spin_lock_irqsave(&iommu->lock, flags); |
337 | ||
09ee17eb JR |
338 | if (!iommu->need_sync) |
339 | goto out; | |
340 | ||
8d201968 | 341 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 342 | |
0cfd7aa9 | 343 | iommu->need_sync = false; |
a19ae1ec JR |
344 | |
345 | if (ret) | |
7e4f88da | 346 | goto out; |
a19ae1ec | 347 | |
8d201968 | 348 | __iommu_wait_for_completion(iommu); |
84df8175 | 349 | |
7e4f88da JR |
350 | out: |
351 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
431b2a20 JR |
356 | /* |
357 | * Command send function for invalidating a device table entry | |
358 | */ | |
a19ae1ec JR |
359 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
360 | { | |
d6449536 | 361 | struct iommu_cmd cmd; |
ee2fa743 | 362 | int ret; |
a19ae1ec JR |
363 | |
364 | BUG_ON(iommu == NULL); | |
365 | ||
366 | memset(&cmd, 0, sizeof(cmd)); | |
367 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
368 | cmd.data[0] = devid; | |
369 | ||
ee2fa743 JR |
370 | ret = iommu_queue_command(iommu, &cmd); |
371 | ||
ee2fa743 | 372 | return ret; |
a19ae1ec JR |
373 | } |
374 | ||
237b6f33 JR |
375 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
376 | u16 domid, int pde, int s) | |
377 | { | |
378 | memset(cmd, 0, sizeof(*cmd)); | |
379 | address &= PAGE_MASK; | |
380 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
381 | cmd->data[1] |= domid; | |
382 | cmd->data[2] = lower_32_bits(address); | |
383 | cmd->data[3] = upper_32_bits(address); | |
384 | if (s) /* size bit - we flush more than one 4kb page */ | |
385 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
386 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
387 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
388 | } | |
389 | ||
431b2a20 JR |
390 | /* |
391 | * Generic command send function for invalidaing TLB entries | |
392 | */ | |
a19ae1ec JR |
393 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
394 | u64 address, u16 domid, int pde, int s) | |
395 | { | |
d6449536 | 396 | struct iommu_cmd cmd; |
ee2fa743 | 397 | int ret; |
a19ae1ec | 398 | |
237b6f33 | 399 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 400 | |
ee2fa743 JR |
401 | ret = iommu_queue_command(iommu, &cmd); |
402 | ||
ee2fa743 | 403 | return ret; |
a19ae1ec JR |
404 | } |
405 | ||
431b2a20 JR |
406 | /* |
407 | * TLB invalidation function which is called from the mapping functions. | |
408 | * It invalidates a single PTE if the range to flush is within a single | |
409 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
410 | */ | |
a19ae1ec JR |
411 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
412 | u64 address, size_t size) | |
413 | { | |
999ba417 | 414 | int s = 0; |
e3c449f5 | 415 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
416 | |
417 | address &= PAGE_MASK; | |
418 | ||
999ba417 JR |
419 | if (pages > 1) { |
420 | /* | |
421 | * If we have to flush more than one page, flush all | |
422 | * TLB entries for this domain | |
423 | */ | |
424 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
425 | s = 1; | |
a19ae1ec JR |
426 | } |
427 | ||
999ba417 JR |
428 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
429 | ||
a19ae1ec JR |
430 | return 0; |
431 | } | |
b6c02715 | 432 | |
1c655773 JR |
433 | /* Flush the whole IO/TLB for a given protection domain */ |
434 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
435 | { | |
436 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
437 | ||
f57d98ae JR |
438 | INC_STATS_COUNTER(domain_flush_single); |
439 | ||
1c655773 JR |
440 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
441 | } | |
442 | ||
42a49f96 CW |
443 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
444 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
445 | { | |
446 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
447 | ||
448 | INC_STATS_COUNTER(domain_flush_single); | |
449 | ||
450 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
451 | } | |
452 | ||
43f49609 JR |
453 | /* |
454 | * This function is used to flush the IO/TLB for a given protection domain | |
455 | * on every IOMMU in the system | |
456 | */ | |
457 | static void iommu_flush_domain(u16 domid) | |
458 | { | |
459 | unsigned long flags; | |
460 | struct amd_iommu *iommu; | |
461 | struct iommu_cmd cmd; | |
462 | ||
18811f55 JR |
463 | INC_STATS_COUNTER(domain_flush_all); |
464 | ||
43f49609 JR |
465 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
466 | domid, 1, 1); | |
467 | ||
3bd22172 | 468 | for_each_iommu(iommu) { |
43f49609 JR |
469 | spin_lock_irqsave(&iommu->lock, flags); |
470 | __iommu_queue_command(iommu, &cmd); | |
471 | __iommu_completion_wait(iommu); | |
472 | __iommu_wait_for_completion(iommu); | |
473 | spin_unlock_irqrestore(&iommu->lock, flags); | |
474 | } | |
475 | } | |
43f49609 | 476 | |
bfd1be18 JR |
477 | void amd_iommu_flush_all_domains(void) |
478 | { | |
479 | int i; | |
480 | ||
481 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
482 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
483 | continue; | |
484 | iommu_flush_domain(i); | |
485 | } | |
486 | } | |
487 | ||
7d7a110c JR |
488 | void amd_iommu_flush_all_devices(void) |
489 | { | |
490 | struct amd_iommu *iommu; | |
491 | int i; | |
492 | ||
493 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
494 | if (amd_iommu_pd_table[i] == NULL) | |
495 | continue; | |
496 | ||
497 | iommu = amd_iommu_rlookup_table[i]; | |
498 | if (!iommu) | |
499 | continue; | |
500 | ||
501 | iommu_queue_inv_dev_entry(iommu, i); | |
502 | iommu_completion_wait(iommu); | |
503 | } | |
504 | } | |
505 | ||
431b2a20 JR |
506 | /**************************************************************************** |
507 | * | |
508 | * The functions below are used the create the page table mappings for | |
509 | * unity mapped regions. | |
510 | * | |
511 | ****************************************************************************/ | |
512 | ||
513 | /* | |
514 | * Generic mapping functions. It maps a physical address into a DMA | |
515 | * address space. It allocates the page table pages if necessary. | |
516 | * In the future it can be extended to a generic mapping function | |
517 | * supporting all features of AMD IOMMU page tables like level skipping | |
518 | * and full 64 bit address spaces. | |
519 | */ | |
38e817fe JR |
520 | static int iommu_map_page(struct protection_domain *dom, |
521 | unsigned long bus_addr, | |
522 | unsigned long phys_addr, | |
523 | int prot) | |
bd0e5211 | 524 | { |
8bda3092 | 525 | u64 __pte, *pte; |
bd0e5211 JR |
526 | |
527 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 528 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
529 | |
530 | /* only support 512GB address spaces for now */ | |
531 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
532 | return -EINVAL; | |
533 | ||
8bda3092 | 534 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
535 | |
536 | if (IOMMU_PTE_PRESENT(*pte)) | |
537 | return -EBUSY; | |
538 | ||
539 | __pte = phys_addr | IOMMU_PTE_P; | |
540 | if (prot & IOMMU_PROT_IR) | |
541 | __pte |= IOMMU_PTE_IR; | |
542 | if (prot & IOMMU_PROT_IW) | |
543 | __pte |= IOMMU_PTE_IW; | |
544 | ||
545 | *pte = __pte; | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
eb74ff6c JR |
550 | static void iommu_unmap_page(struct protection_domain *dom, |
551 | unsigned long bus_addr) | |
552 | { | |
553 | u64 *pte; | |
554 | ||
555 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
556 | ||
557 | if (!IOMMU_PTE_PRESENT(*pte)) | |
558 | return; | |
559 | ||
560 | pte = IOMMU_PTE_PAGE(*pte); | |
561 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
562 | ||
563 | if (!IOMMU_PTE_PRESENT(*pte)) | |
564 | return; | |
565 | ||
566 | pte = IOMMU_PTE_PAGE(*pte); | |
567 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
568 | ||
569 | *pte = 0; | |
570 | } | |
eb74ff6c | 571 | |
431b2a20 JR |
572 | /* |
573 | * This function checks if a specific unity mapping entry is needed for | |
574 | * this specific IOMMU. | |
575 | */ | |
bd0e5211 JR |
576 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
577 | struct unity_map_entry *entry) | |
578 | { | |
579 | u16 bdf, i; | |
580 | ||
581 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
582 | bdf = amd_iommu_alias_table[i]; | |
583 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
584 | return 1; | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
431b2a20 JR |
590 | /* |
591 | * Init the unity mappings for a specific IOMMU in the system | |
592 | * | |
593 | * Basically iterates over all unity mapping entries and applies them to | |
594 | * the default domain DMA of that IOMMU if necessary. | |
595 | */ | |
bd0e5211 JR |
596 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
597 | { | |
598 | struct unity_map_entry *entry; | |
599 | int ret; | |
600 | ||
601 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
602 | if (!iommu_for_unity_map(iommu, entry)) | |
603 | continue; | |
604 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
605 | if (ret) | |
606 | return ret; | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
431b2a20 JR |
612 | /* |
613 | * This function actually applies the mapping to the page table of the | |
614 | * dma_ops domain. | |
615 | */ | |
bd0e5211 JR |
616 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
617 | struct unity_map_entry *e) | |
618 | { | |
619 | u64 addr; | |
620 | int ret; | |
621 | ||
622 | for (addr = e->address_start; addr < e->address_end; | |
623 | addr += PAGE_SIZE) { | |
38e817fe | 624 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
625 | if (ret) |
626 | return ret; | |
627 | /* | |
628 | * if unity mapping is in aperture range mark the page | |
629 | * as allocated in the aperture | |
630 | */ | |
631 | if (addr < dma_dom->aperture_size) | |
c3239567 | 632 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 633 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
634 | } |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
431b2a20 JR |
639 | /* |
640 | * Inits the unity mappings required for a specific device | |
641 | */ | |
bd0e5211 JR |
642 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
643 | u16 devid) | |
644 | { | |
645 | struct unity_map_entry *e; | |
646 | int ret; | |
647 | ||
648 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
649 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
650 | continue; | |
651 | ret = dma_ops_unity_map(dma_dom, e); | |
652 | if (ret) | |
653 | return ret; | |
654 | } | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
431b2a20 JR |
659 | /**************************************************************************** |
660 | * | |
661 | * The next functions belong to the address allocator for the dma_ops | |
662 | * interface functions. They work like the allocators in the other IOMMU | |
663 | * drivers. Its basically a bitmap which marks the allocated pages in | |
664 | * the aperture. Maybe it could be enhanced in the future to a more | |
665 | * efficient allocator. | |
666 | * | |
667 | ****************************************************************************/ | |
d3086444 | 668 | |
431b2a20 | 669 | /* |
384de729 | 670 | * The address allocator core functions. |
431b2a20 JR |
671 | * |
672 | * called with domain->lock held | |
673 | */ | |
384de729 | 674 | |
00cd122a JR |
675 | /* |
676 | * This function checks if there is a PTE for a given dma address. If | |
677 | * there is one, it returns the pointer to it. | |
678 | */ | |
679 | static u64* fetch_pte(struct protection_domain *domain, | |
680 | unsigned long address) | |
681 | { | |
682 | u64 *pte; | |
683 | ||
684 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
685 | ||
686 | if (!IOMMU_PTE_PRESENT(*pte)) | |
687 | return NULL; | |
688 | ||
689 | pte = IOMMU_PTE_PAGE(*pte); | |
690 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
691 | ||
692 | if (!IOMMU_PTE_PRESENT(*pte)) | |
693 | return NULL; | |
694 | ||
695 | pte = IOMMU_PTE_PAGE(*pte); | |
696 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
697 | ||
698 | return pte; | |
699 | } | |
700 | ||
9cabe89b JR |
701 | /* |
702 | * This function is used to add a new aperture range to an existing | |
703 | * aperture in case of dma_ops domain allocation or address allocation | |
704 | * failure. | |
705 | */ | |
00cd122a JR |
706 | static int alloc_new_range(struct amd_iommu *iommu, |
707 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
708 | bool populate, gfp_t gfp) |
709 | { | |
710 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 711 | int i; |
9cabe89b | 712 | |
f5e9705c JR |
713 | #ifdef CONFIG_IOMMU_STRESS |
714 | populate = false; | |
715 | #endif | |
716 | ||
9cabe89b JR |
717 | if (index >= APERTURE_MAX_RANGES) |
718 | return -ENOMEM; | |
719 | ||
720 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
721 | if (!dma_dom->aperture[index]) | |
722 | return -ENOMEM; | |
723 | ||
724 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
725 | if (!dma_dom->aperture[index]->bitmap) | |
726 | goto out_free; | |
727 | ||
728 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
729 | ||
730 | if (populate) { | |
731 | unsigned long address = dma_dom->aperture_size; | |
732 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
733 | u64 *pte, *pte_page; | |
734 | ||
735 | for (i = 0; i < num_ptes; ++i) { | |
736 | pte = alloc_pte(&dma_dom->domain, address, | |
737 | &pte_page, gfp); | |
738 | if (!pte) | |
739 | goto out_free; | |
740 | ||
741 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
742 | ||
743 | address += APERTURE_RANGE_SIZE / 64; | |
744 | } | |
745 | } | |
746 | ||
747 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
748 | ||
00cd122a JR |
749 | /* Intialize the exclusion range if necessary */ |
750 | if (iommu->exclusion_start && | |
751 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
752 | iommu->exclusion_start < dma_dom->aperture_size) { | |
753 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
754 | int pages = iommu_num_pages(iommu->exclusion_start, | |
755 | iommu->exclusion_length, | |
756 | PAGE_SIZE); | |
757 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
758 | } | |
759 | ||
760 | /* | |
761 | * Check for areas already mapped as present in the new aperture | |
762 | * range and mark those pages as reserved in the allocator. Such | |
763 | * mappings may already exist as a result of requested unity | |
764 | * mappings for devices. | |
765 | */ | |
766 | for (i = dma_dom->aperture[index]->offset; | |
767 | i < dma_dom->aperture_size; | |
768 | i += PAGE_SIZE) { | |
769 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
770 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
771 | continue; | |
772 | ||
773 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
774 | } | |
775 | ||
9cabe89b JR |
776 | return 0; |
777 | ||
778 | out_free: | |
779 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
780 | ||
781 | kfree(dma_dom->aperture[index]); | |
782 | dma_dom->aperture[index] = NULL; | |
783 | ||
784 | return -ENOMEM; | |
785 | } | |
786 | ||
384de729 JR |
787 | static unsigned long dma_ops_area_alloc(struct device *dev, |
788 | struct dma_ops_domain *dom, | |
789 | unsigned int pages, | |
790 | unsigned long align_mask, | |
791 | u64 dma_mask, | |
792 | unsigned long start) | |
793 | { | |
803b8cb4 | 794 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
795 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
796 | int i = start >> APERTURE_RANGE_SHIFT; | |
797 | unsigned long boundary_size; | |
798 | unsigned long address = -1; | |
799 | unsigned long limit; | |
800 | ||
803b8cb4 JR |
801 | next_bit >>= PAGE_SHIFT; |
802 | ||
384de729 JR |
803 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
804 | PAGE_SIZE) >> PAGE_SHIFT; | |
805 | ||
806 | for (;i < max_index; ++i) { | |
807 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
808 | ||
809 | if (dom->aperture[i]->offset >= dma_mask) | |
810 | break; | |
811 | ||
812 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
813 | dma_mask >> PAGE_SHIFT); | |
814 | ||
815 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
816 | limit, next_bit, pages, 0, | |
817 | boundary_size, align_mask); | |
818 | if (address != -1) { | |
819 | address = dom->aperture[i]->offset + | |
820 | (address << PAGE_SHIFT); | |
803b8cb4 | 821 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
822 | break; |
823 | } | |
824 | ||
825 | next_bit = 0; | |
826 | } | |
827 | ||
828 | return address; | |
829 | } | |
830 | ||
d3086444 JR |
831 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
832 | struct dma_ops_domain *dom, | |
6d4f343f | 833 | unsigned int pages, |
832a90c3 JR |
834 | unsigned long align_mask, |
835 | u64 dma_mask) | |
d3086444 | 836 | { |
d3086444 | 837 | unsigned long address; |
d3086444 | 838 | |
fe16f088 JR |
839 | #ifdef CONFIG_IOMMU_STRESS |
840 | dom->next_address = 0; | |
841 | dom->need_flush = true; | |
842 | #endif | |
d3086444 | 843 | |
384de729 | 844 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 845 | dma_mask, dom->next_address); |
d3086444 | 846 | |
1c655773 | 847 | if (address == -1) { |
803b8cb4 | 848 | dom->next_address = 0; |
384de729 JR |
849 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
850 | dma_mask, 0); | |
1c655773 JR |
851 | dom->need_flush = true; |
852 | } | |
d3086444 | 853 | |
384de729 | 854 | if (unlikely(address == -1)) |
d3086444 JR |
855 | address = bad_dma_address; |
856 | ||
857 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
858 | ||
859 | return address; | |
860 | } | |
861 | ||
431b2a20 JR |
862 | /* |
863 | * The address free function. | |
864 | * | |
865 | * called with domain->lock held | |
866 | */ | |
d3086444 JR |
867 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
868 | unsigned long address, | |
869 | unsigned int pages) | |
870 | { | |
384de729 JR |
871 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
872 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 873 | |
384de729 JR |
874 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
875 | ||
47bccd6b JR |
876 | #ifdef CONFIG_IOMMU_STRESS |
877 | if (i < 4) | |
878 | return; | |
879 | #endif | |
80be308d | 880 | |
803b8cb4 | 881 | if (address >= dom->next_address) |
80be308d | 882 | dom->need_flush = true; |
384de729 JR |
883 | |
884 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 885 | |
384de729 JR |
886 | iommu_area_free(range->bitmap, address, pages); |
887 | ||
d3086444 JR |
888 | } |
889 | ||
431b2a20 JR |
890 | /**************************************************************************** |
891 | * | |
892 | * The next functions belong to the domain allocation. A domain is | |
893 | * allocated for every IOMMU as the default domain. If device isolation | |
894 | * is enabled, every device get its own domain. The most important thing | |
895 | * about domains is the page table mapping the DMA address space they | |
896 | * contain. | |
897 | * | |
898 | ****************************************************************************/ | |
899 | ||
ec487d1a JR |
900 | static u16 domain_id_alloc(void) |
901 | { | |
902 | unsigned long flags; | |
903 | int id; | |
904 | ||
905 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
906 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
907 | BUG_ON(id == 0); | |
908 | if (id > 0 && id < MAX_DOMAIN_ID) | |
909 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
910 | else | |
911 | id = 0; | |
912 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
913 | ||
914 | return id; | |
915 | } | |
916 | ||
a2acfb75 JR |
917 | static void domain_id_free(int id) |
918 | { | |
919 | unsigned long flags; | |
920 | ||
921 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
922 | if (id > 0 && id < MAX_DOMAIN_ID) | |
923 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
924 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
925 | } | |
a2acfb75 | 926 | |
431b2a20 JR |
927 | /* |
928 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
929 | * ranges. | |
930 | */ | |
ec487d1a JR |
931 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
932 | unsigned long start_page, | |
933 | unsigned int pages) | |
934 | { | |
384de729 | 935 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
936 | |
937 | if (start_page + pages > last_page) | |
938 | pages = last_page - start_page; | |
939 | ||
384de729 JR |
940 | for (i = start_page; i < start_page + pages; ++i) { |
941 | int index = i / APERTURE_RANGE_PAGES; | |
942 | int page = i % APERTURE_RANGE_PAGES; | |
943 | __set_bit(page, dom->aperture[index]->bitmap); | |
944 | } | |
ec487d1a JR |
945 | } |
946 | ||
86db2e5d | 947 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
948 | { |
949 | int i, j; | |
950 | u64 *p1, *p2, *p3; | |
951 | ||
86db2e5d | 952 | p1 = domain->pt_root; |
ec487d1a JR |
953 | |
954 | if (!p1) | |
955 | return; | |
956 | ||
957 | for (i = 0; i < 512; ++i) { | |
958 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
959 | continue; | |
960 | ||
961 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 962 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
963 | if (!IOMMU_PTE_PRESENT(p2[j])) |
964 | continue; | |
965 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
966 | free_page((unsigned long)p3); | |
967 | } | |
968 | ||
969 | free_page((unsigned long)p2); | |
970 | } | |
971 | ||
972 | free_page((unsigned long)p1); | |
86db2e5d JR |
973 | |
974 | domain->pt_root = NULL; | |
ec487d1a JR |
975 | } |
976 | ||
431b2a20 JR |
977 | /* |
978 | * Free a domain, only used if something went wrong in the | |
979 | * allocation path and we need to free an already allocated page table | |
980 | */ | |
ec487d1a JR |
981 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
982 | { | |
384de729 JR |
983 | int i; |
984 | ||
ec487d1a JR |
985 | if (!dom) |
986 | return; | |
987 | ||
86db2e5d | 988 | free_pagetable(&dom->domain); |
ec487d1a | 989 | |
384de729 JR |
990 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
991 | if (!dom->aperture[i]) | |
992 | continue; | |
993 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
994 | kfree(dom->aperture[i]); | |
995 | } | |
ec487d1a JR |
996 | |
997 | kfree(dom); | |
998 | } | |
999 | ||
431b2a20 JR |
1000 | /* |
1001 | * Allocates a new protection domain usable for the dma_ops functions. | |
1002 | * It also intializes the page table and the address allocator data | |
1003 | * structures required for the dma_ops interface | |
1004 | */ | |
d9cfed92 | 1005 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1006 | { |
1007 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1008 | |
1009 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1010 | if (!dma_dom) | |
1011 | return NULL; | |
1012 | ||
1013 | spin_lock_init(&dma_dom->domain.lock); | |
1014 | ||
1015 | dma_dom->domain.id = domain_id_alloc(); | |
1016 | if (dma_dom->domain.id == 0) | |
1017 | goto free_dma_dom; | |
1018 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1019 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1020 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1021 | dma_dom->domain.priv = dma_dom; |
1022 | if (!dma_dom->domain.pt_root) | |
1023 | goto free_dma_dom; | |
ec487d1a | 1024 | |
1c655773 | 1025 | dma_dom->need_flush = false; |
bd60b735 | 1026 | dma_dom->target_dev = 0xffff; |
1c655773 | 1027 | |
00cd122a | 1028 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1029 | goto free_dma_dom; |
ec487d1a | 1030 | |
431b2a20 | 1031 | /* |
ec487d1a JR |
1032 | * mark the first page as allocated so we never return 0 as |
1033 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1034 | */ |
384de729 | 1035 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1036 | dma_dom->next_address = 0; |
ec487d1a | 1037 | |
ec487d1a JR |
1038 | |
1039 | return dma_dom; | |
1040 | ||
1041 | free_dma_dom: | |
1042 | dma_ops_domain_free(dma_dom); | |
1043 | ||
1044 | return NULL; | |
1045 | } | |
1046 | ||
5b28df6f JR |
1047 | /* |
1048 | * little helper function to check whether a given protection domain is a | |
1049 | * dma_ops domain | |
1050 | */ | |
1051 | static bool dma_ops_domain(struct protection_domain *domain) | |
1052 | { | |
1053 | return domain->flags & PD_DMA_OPS_MASK; | |
1054 | } | |
1055 | ||
431b2a20 JR |
1056 | /* |
1057 | * Find out the protection domain structure for a given PCI device. This | |
1058 | * will give us the pointer to the page table root for example. | |
1059 | */ | |
b20ac0d4 JR |
1060 | static struct protection_domain *domain_for_device(u16 devid) |
1061 | { | |
1062 | struct protection_domain *dom; | |
1063 | unsigned long flags; | |
1064 | ||
1065 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1066 | dom = amd_iommu_pd_table[devid]; | |
1067 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1068 | ||
1069 | return dom; | |
1070 | } | |
1071 | ||
431b2a20 JR |
1072 | /* |
1073 | * If a device is not yet associated with a domain, this function does | |
1074 | * assigns it visible for the hardware | |
1075 | */ | |
0feae533 JR |
1076 | static void __attach_device(struct amd_iommu *iommu, |
1077 | struct protection_domain *domain, | |
1078 | u16 devid) | |
b20ac0d4 JR |
1079 | { |
1080 | unsigned long flags; | |
b20ac0d4 JR |
1081 | u64 pte_root = virt_to_phys(domain->pt_root); |
1082 | ||
863c74eb JR |
1083 | domain->dev_cnt += 1; |
1084 | ||
38ddf41b JR |
1085 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1086 | << DEV_ENTRY_MODE_SHIFT; | |
1087 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1088 | |
1089 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
b20ac0d4 | 1090 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1091 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1092 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1093 | |
1094 | amd_iommu_pd_table[devid] = domain; | |
1095 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
0feae533 | 1096 | } |
b20ac0d4 | 1097 | |
0feae533 JR |
1098 | static void attach_device(struct amd_iommu *iommu, |
1099 | struct protection_domain *domain, | |
1100 | u16 devid) | |
1101 | { | |
1102 | __attach_device(iommu, domain, devid); | |
1103 | ||
1104 | /* | |
1105 | * We might boot into a crash-kernel here. The crashed kernel | |
1106 | * left the caches in the IOMMU dirty. So we have to flush | |
1107 | * here to evict all dirty stuff. | |
1108 | */ | |
b20ac0d4 | 1109 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1110 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1111 | } |
1112 | ||
355bf553 JR |
1113 | /* |
1114 | * Removes a device from a protection domain (unlocked) | |
1115 | */ | |
1116 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1117 | { | |
1118 | ||
1119 | /* lock domain */ | |
1120 | spin_lock(&domain->lock); | |
1121 | ||
1122 | /* remove domain from the lookup table */ | |
1123 | amd_iommu_pd_table[devid] = NULL; | |
1124 | ||
1125 | /* remove entry from the device table seen by the hardware */ | |
1126 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1127 | amd_iommu_dev_table[devid].data[1] = 0; | |
1128 | amd_iommu_dev_table[devid].data[2] = 0; | |
1129 | ||
1130 | /* decrease reference counter */ | |
1131 | domain->dev_cnt -= 1; | |
1132 | ||
1133 | /* ready */ | |
1134 | spin_unlock(&domain->lock); | |
1135 | } | |
1136 | ||
1137 | /* | |
1138 | * Removes a device from a protection domain (with devtable_lock held) | |
1139 | */ | |
1140 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1141 | { | |
1142 | unsigned long flags; | |
1143 | ||
1144 | /* lock device table */ | |
1145 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1146 | __detach_device(domain, devid); | |
1147 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1148 | } | |
e275a2a0 JR |
1149 | |
1150 | static int device_change_notifier(struct notifier_block *nb, | |
1151 | unsigned long action, void *data) | |
1152 | { | |
1153 | struct device *dev = data; | |
1154 | struct pci_dev *pdev = to_pci_dev(dev); | |
1155 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1156 | struct protection_domain *domain; | |
1157 | struct dma_ops_domain *dma_domain; | |
1158 | struct amd_iommu *iommu; | |
1ac4cbbc | 1159 | unsigned long flags; |
e275a2a0 JR |
1160 | |
1161 | if (devid > amd_iommu_last_bdf) | |
1162 | goto out; | |
1163 | ||
1164 | devid = amd_iommu_alias_table[devid]; | |
1165 | ||
1166 | iommu = amd_iommu_rlookup_table[devid]; | |
1167 | if (iommu == NULL) | |
1168 | goto out; | |
1169 | ||
1170 | domain = domain_for_device(devid); | |
1171 | ||
1172 | if (domain && !dma_ops_domain(domain)) | |
1173 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1174 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1175 | ||
1176 | switch (action) { | |
c1eee67b | 1177 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1178 | if (!domain) |
1179 | goto out; | |
1180 | detach_device(domain, devid); | |
1ac4cbbc JR |
1181 | break; |
1182 | case BUS_NOTIFY_ADD_DEVICE: | |
1183 | /* allocate a protection domain if a device is added */ | |
1184 | dma_domain = find_protection_domain(devid); | |
1185 | if (dma_domain) | |
1186 | goto out; | |
d9cfed92 | 1187 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1188 | if (!dma_domain) |
1189 | goto out; | |
1190 | dma_domain->target_dev = devid; | |
1191 | ||
1192 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1193 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1194 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1195 | ||
e275a2a0 JR |
1196 | break; |
1197 | default: | |
1198 | goto out; | |
1199 | } | |
1200 | ||
1201 | iommu_queue_inv_dev_entry(iommu, devid); | |
1202 | iommu_completion_wait(iommu); | |
1203 | ||
1204 | out: | |
1205 | return 0; | |
1206 | } | |
1207 | ||
b25ae679 | 1208 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1209 | .notifier_call = device_change_notifier, |
1210 | }; | |
355bf553 | 1211 | |
431b2a20 JR |
1212 | /***************************************************************************** |
1213 | * | |
1214 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1215 | * | |
1216 | *****************************************************************************/ | |
1217 | ||
dbcc112e JR |
1218 | /* |
1219 | * This function checks if the driver got a valid device from the caller to | |
1220 | * avoid dereferencing invalid pointers. | |
1221 | */ | |
1222 | static bool check_device(struct device *dev) | |
1223 | { | |
1224 | if (!dev || !dev->dma_mask) | |
1225 | return false; | |
1226 | ||
1227 | return true; | |
1228 | } | |
1229 | ||
bd60b735 JR |
1230 | /* |
1231 | * In this function the list of preallocated protection domains is traversed to | |
1232 | * find the domain for a specific device | |
1233 | */ | |
1234 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1235 | { | |
1236 | struct dma_ops_domain *entry, *ret = NULL; | |
1237 | unsigned long flags; | |
1238 | ||
1239 | if (list_empty(&iommu_pd_list)) | |
1240 | return NULL; | |
1241 | ||
1242 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1243 | ||
1244 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1245 | if (entry->target_dev == devid) { | |
1246 | ret = entry; | |
bd60b735 JR |
1247 | break; |
1248 | } | |
1249 | } | |
1250 | ||
1251 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1252 | ||
1253 | return ret; | |
1254 | } | |
1255 | ||
431b2a20 JR |
1256 | /* |
1257 | * In the dma_ops path we only have the struct device. This function | |
1258 | * finds the corresponding IOMMU, the protection domain and the | |
1259 | * requestor id for a given device. | |
1260 | * If the device is not yet associated with a domain this is also done | |
1261 | * in this function. | |
1262 | */ | |
b20ac0d4 JR |
1263 | static int get_device_resources(struct device *dev, |
1264 | struct amd_iommu **iommu, | |
1265 | struct protection_domain **domain, | |
1266 | u16 *bdf) | |
1267 | { | |
1268 | struct dma_ops_domain *dma_dom; | |
1269 | struct pci_dev *pcidev; | |
1270 | u16 _bdf; | |
1271 | ||
dbcc112e JR |
1272 | *iommu = NULL; |
1273 | *domain = NULL; | |
1274 | *bdf = 0xffff; | |
1275 | ||
1276 | if (dev->bus != &pci_bus_type) | |
1277 | return 0; | |
b20ac0d4 JR |
1278 | |
1279 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1280 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1281 | |
431b2a20 | 1282 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1283 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1284 | return 0; |
b20ac0d4 JR |
1285 | |
1286 | *bdf = amd_iommu_alias_table[_bdf]; | |
1287 | ||
1288 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1289 | if (*iommu == NULL) | |
1290 | return 0; | |
b20ac0d4 JR |
1291 | *domain = domain_for_device(*bdf); |
1292 | if (*domain == NULL) { | |
bd60b735 JR |
1293 | dma_dom = find_protection_domain(*bdf); |
1294 | if (!dma_dom) | |
1295 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1296 | *domain = &dma_dom->domain; |
f1179dc0 | 1297 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1298 | DUMP_printk("Using protection domain %d for device %s\n", |
1299 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1300 | } |
1301 | ||
f91ba190 | 1302 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1303 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1304 | |
b20ac0d4 JR |
1305 | return 1; |
1306 | } | |
1307 | ||
8bda3092 JR |
1308 | /* |
1309 | * If the pte_page is not yet allocated this function is called | |
1310 | */ | |
1311 | static u64* alloc_pte(struct protection_domain *dom, | |
1312 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1313 | { | |
1314 | u64 *pte, *page; | |
1315 | ||
1316 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1317 | ||
1318 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1319 | page = (u64 *)get_zeroed_page(gfp); | |
1320 | if (!page) | |
1321 | return NULL; | |
1322 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1323 | } | |
1324 | ||
1325 | pte = IOMMU_PTE_PAGE(*pte); | |
1326 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1327 | ||
1328 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1329 | page = (u64 *)get_zeroed_page(gfp); | |
1330 | if (!page) | |
1331 | return NULL; | |
1332 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1333 | } | |
1334 | ||
1335 | pte = IOMMU_PTE_PAGE(*pte); | |
1336 | ||
1337 | if (pte_page) | |
1338 | *pte_page = pte; | |
1339 | ||
1340 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1341 | ||
1342 | return pte; | |
1343 | } | |
1344 | ||
1345 | /* | |
1346 | * This function fetches the PTE for a given address in the aperture | |
1347 | */ | |
1348 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1349 | unsigned long address) | |
1350 | { | |
384de729 | 1351 | struct aperture_range *aperture; |
8bda3092 JR |
1352 | u64 *pte, *pte_page; |
1353 | ||
384de729 JR |
1354 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1355 | if (!aperture) | |
1356 | return NULL; | |
1357 | ||
1358 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1359 | if (!pte) { |
1360 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1361 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1362 | } else | |
1363 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1364 | |
1365 | return pte; | |
1366 | } | |
1367 | ||
431b2a20 JR |
1368 | /* |
1369 | * This is the generic map function. It maps one 4kb page at paddr to | |
1370 | * the given address in the DMA address space for the domain. | |
1371 | */ | |
cb76c322 JR |
1372 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1373 | struct dma_ops_domain *dom, | |
1374 | unsigned long address, | |
1375 | phys_addr_t paddr, | |
1376 | int direction) | |
1377 | { | |
1378 | u64 *pte, __pte; | |
1379 | ||
1380 | WARN_ON(address > dom->aperture_size); | |
1381 | ||
1382 | paddr &= PAGE_MASK; | |
1383 | ||
8bda3092 | 1384 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1385 | if (!pte) |
1386 | return bad_dma_address; | |
cb76c322 JR |
1387 | |
1388 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1389 | ||
1390 | if (direction == DMA_TO_DEVICE) | |
1391 | __pte |= IOMMU_PTE_IR; | |
1392 | else if (direction == DMA_FROM_DEVICE) | |
1393 | __pte |= IOMMU_PTE_IW; | |
1394 | else if (direction == DMA_BIDIRECTIONAL) | |
1395 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1396 | ||
1397 | WARN_ON(*pte); | |
1398 | ||
1399 | *pte = __pte; | |
1400 | ||
1401 | return (dma_addr_t)address; | |
1402 | } | |
1403 | ||
431b2a20 JR |
1404 | /* |
1405 | * The generic unmapping function for on page in the DMA address space. | |
1406 | */ | |
cb76c322 JR |
1407 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1408 | struct dma_ops_domain *dom, | |
1409 | unsigned long address) | |
1410 | { | |
384de729 | 1411 | struct aperture_range *aperture; |
cb76c322 JR |
1412 | u64 *pte; |
1413 | ||
1414 | if (address >= dom->aperture_size) | |
1415 | return; | |
1416 | ||
384de729 JR |
1417 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1418 | if (!aperture) | |
1419 | return; | |
1420 | ||
1421 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1422 | if (!pte) | |
1423 | return; | |
cb76c322 | 1424 | |
cb76c322 JR |
1425 | pte += IOMMU_PTE_L0_INDEX(address); |
1426 | ||
1427 | WARN_ON(!*pte); | |
1428 | ||
1429 | *pte = 0ULL; | |
1430 | } | |
1431 | ||
431b2a20 JR |
1432 | /* |
1433 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1434 | * contiguous memory region into DMA address space. It is used by all |
1435 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1436 | * Must be called with the domain lock held. |
1437 | */ | |
cb76c322 JR |
1438 | static dma_addr_t __map_single(struct device *dev, |
1439 | struct amd_iommu *iommu, | |
1440 | struct dma_ops_domain *dma_dom, | |
1441 | phys_addr_t paddr, | |
1442 | size_t size, | |
6d4f343f | 1443 | int dir, |
832a90c3 JR |
1444 | bool align, |
1445 | u64 dma_mask) | |
cb76c322 JR |
1446 | { |
1447 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1448 | dma_addr_t address, start, ret; |
cb76c322 | 1449 | unsigned int pages; |
6d4f343f | 1450 | unsigned long align_mask = 0; |
cb76c322 JR |
1451 | int i; |
1452 | ||
e3c449f5 | 1453 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1454 | paddr &= PAGE_MASK; |
1455 | ||
8ecaf8f1 JR |
1456 | INC_STATS_COUNTER(total_map_requests); |
1457 | ||
c1858976 JR |
1458 | if (pages > 1) |
1459 | INC_STATS_COUNTER(cross_page); | |
1460 | ||
6d4f343f JR |
1461 | if (align) |
1462 | align_mask = (1UL << get_order(size)) - 1; | |
1463 | ||
11b83888 | 1464 | retry: |
832a90c3 JR |
1465 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1466 | dma_mask); | |
11b83888 JR |
1467 | if (unlikely(address == bad_dma_address)) { |
1468 | /* | |
1469 | * setting next_address here will let the address | |
1470 | * allocator only scan the new allocated range in the | |
1471 | * first run. This is a small optimization. | |
1472 | */ | |
1473 | dma_dom->next_address = dma_dom->aperture_size; | |
1474 | ||
1475 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1476 | goto out; | |
1477 | ||
1478 | /* | |
1479 | * aperture was sucessfully enlarged by 128 MB, try | |
1480 | * allocation again | |
1481 | */ | |
1482 | goto retry; | |
1483 | } | |
cb76c322 JR |
1484 | |
1485 | start = address; | |
1486 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1487 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1488 | if (ret == bad_dma_address) | |
1489 | goto out_unmap; | |
1490 | ||
cb76c322 JR |
1491 | paddr += PAGE_SIZE; |
1492 | start += PAGE_SIZE; | |
1493 | } | |
1494 | address += offset; | |
1495 | ||
5774f7c5 JR |
1496 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1497 | ||
afa9fdc2 | 1498 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1499 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1500 | dma_dom->need_flush = false; | |
1501 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1502 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1503 | ||
cb76c322 JR |
1504 | out: |
1505 | return address; | |
53812c11 JR |
1506 | |
1507 | out_unmap: | |
1508 | ||
1509 | for (--i; i >= 0; --i) { | |
1510 | start -= PAGE_SIZE; | |
1511 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1512 | } | |
1513 | ||
1514 | dma_ops_free_addresses(dma_dom, address, pages); | |
1515 | ||
1516 | return bad_dma_address; | |
cb76c322 JR |
1517 | } |
1518 | ||
431b2a20 JR |
1519 | /* |
1520 | * Does the reverse of the __map_single function. Must be called with | |
1521 | * the domain lock held too | |
1522 | */ | |
cb76c322 JR |
1523 | static void __unmap_single(struct amd_iommu *iommu, |
1524 | struct dma_ops_domain *dma_dom, | |
1525 | dma_addr_t dma_addr, | |
1526 | size_t size, | |
1527 | int dir) | |
1528 | { | |
1529 | dma_addr_t i, start; | |
1530 | unsigned int pages; | |
1531 | ||
b8d9905d JR |
1532 | if ((dma_addr == bad_dma_address) || |
1533 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1534 | return; |
1535 | ||
e3c449f5 | 1536 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1537 | dma_addr &= PAGE_MASK; |
1538 | start = dma_addr; | |
1539 | ||
1540 | for (i = 0; i < pages; ++i) { | |
1541 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1542 | start += PAGE_SIZE; | |
1543 | } | |
1544 | ||
5774f7c5 JR |
1545 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1546 | ||
cb76c322 | 1547 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1548 | |
80be308d | 1549 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1550 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1551 | dma_dom->need_flush = false; |
1552 | } | |
cb76c322 JR |
1553 | } |
1554 | ||
431b2a20 JR |
1555 | /* |
1556 | * The exported map_single function for dma_ops. | |
1557 | */ | |
51491367 FT |
1558 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1559 | unsigned long offset, size_t size, | |
1560 | enum dma_data_direction dir, | |
1561 | struct dma_attrs *attrs) | |
4da70b9e JR |
1562 | { |
1563 | unsigned long flags; | |
1564 | struct amd_iommu *iommu; | |
1565 | struct protection_domain *domain; | |
1566 | u16 devid; | |
1567 | dma_addr_t addr; | |
832a90c3 | 1568 | u64 dma_mask; |
51491367 | 1569 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1570 | |
0f2a86f2 JR |
1571 | INC_STATS_COUNTER(cnt_map_single); |
1572 | ||
dbcc112e JR |
1573 | if (!check_device(dev)) |
1574 | return bad_dma_address; | |
1575 | ||
832a90c3 | 1576 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1577 | |
1578 | get_device_resources(dev, &iommu, &domain, &devid); | |
1579 | ||
1580 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1581 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1582 | return (dma_addr_t)paddr; |
1583 | ||
5b28df6f JR |
1584 | if (!dma_ops_domain(domain)) |
1585 | return bad_dma_address; | |
1586 | ||
4da70b9e | 1587 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1588 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1589 | dma_mask); | |
4da70b9e JR |
1590 | if (addr == bad_dma_address) |
1591 | goto out; | |
1592 | ||
09ee17eb | 1593 | iommu_completion_wait(iommu); |
4da70b9e JR |
1594 | |
1595 | out: | |
1596 | spin_unlock_irqrestore(&domain->lock, flags); | |
1597 | ||
1598 | return addr; | |
1599 | } | |
1600 | ||
431b2a20 JR |
1601 | /* |
1602 | * The exported unmap_single function for dma_ops. | |
1603 | */ | |
51491367 FT |
1604 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1605 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1606 | { |
1607 | unsigned long flags; | |
1608 | struct amd_iommu *iommu; | |
1609 | struct protection_domain *domain; | |
1610 | u16 devid; | |
1611 | ||
146a6917 JR |
1612 | INC_STATS_COUNTER(cnt_unmap_single); |
1613 | ||
dbcc112e JR |
1614 | if (!check_device(dev) || |
1615 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1616 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1617 | return; |
1618 | ||
5b28df6f JR |
1619 | if (!dma_ops_domain(domain)) |
1620 | return; | |
1621 | ||
4da70b9e JR |
1622 | spin_lock_irqsave(&domain->lock, flags); |
1623 | ||
1624 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1625 | ||
09ee17eb | 1626 | iommu_completion_wait(iommu); |
4da70b9e JR |
1627 | |
1628 | spin_unlock_irqrestore(&domain->lock, flags); | |
1629 | } | |
1630 | ||
431b2a20 JR |
1631 | /* |
1632 | * This is a special map_sg function which is used if we should map a | |
1633 | * device which is not handled by an AMD IOMMU in the system. | |
1634 | */ | |
65b050ad JR |
1635 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1636 | int nelems, int dir) | |
1637 | { | |
1638 | struct scatterlist *s; | |
1639 | int i; | |
1640 | ||
1641 | for_each_sg(sglist, s, nelems, i) { | |
1642 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1643 | s->dma_length = s->length; | |
1644 | } | |
1645 | ||
1646 | return nelems; | |
1647 | } | |
1648 | ||
431b2a20 JR |
1649 | /* |
1650 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1651 | * lists). | |
1652 | */ | |
65b050ad | 1653 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1654 | int nelems, enum dma_data_direction dir, |
1655 | struct dma_attrs *attrs) | |
65b050ad JR |
1656 | { |
1657 | unsigned long flags; | |
1658 | struct amd_iommu *iommu; | |
1659 | struct protection_domain *domain; | |
1660 | u16 devid; | |
1661 | int i; | |
1662 | struct scatterlist *s; | |
1663 | phys_addr_t paddr; | |
1664 | int mapped_elems = 0; | |
832a90c3 | 1665 | u64 dma_mask; |
65b050ad | 1666 | |
d03f067a JR |
1667 | INC_STATS_COUNTER(cnt_map_sg); |
1668 | ||
dbcc112e JR |
1669 | if (!check_device(dev)) |
1670 | return 0; | |
1671 | ||
832a90c3 | 1672 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1673 | |
1674 | get_device_resources(dev, &iommu, &domain, &devid); | |
1675 | ||
1676 | if (!iommu || !domain) | |
1677 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1678 | ||
5b28df6f JR |
1679 | if (!dma_ops_domain(domain)) |
1680 | return 0; | |
1681 | ||
65b050ad JR |
1682 | spin_lock_irqsave(&domain->lock, flags); |
1683 | ||
1684 | for_each_sg(sglist, s, nelems, i) { | |
1685 | paddr = sg_phys(s); | |
1686 | ||
1687 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1688 | paddr, s->length, dir, false, |
1689 | dma_mask); | |
65b050ad JR |
1690 | |
1691 | if (s->dma_address) { | |
1692 | s->dma_length = s->length; | |
1693 | mapped_elems++; | |
1694 | } else | |
1695 | goto unmap; | |
65b050ad JR |
1696 | } |
1697 | ||
09ee17eb | 1698 | iommu_completion_wait(iommu); |
65b050ad JR |
1699 | |
1700 | out: | |
1701 | spin_unlock_irqrestore(&domain->lock, flags); | |
1702 | ||
1703 | return mapped_elems; | |
1704 | unmap: | |
1705 | for_each_sg(sglist, s, mapped_elems, i) { | |
1706 | if (s->dma_address) | |
1707 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1708 | s->dma_length, dir); | |
1709 | s->dma_address = s->dma_length = 0; | |
1710 | } | |
1711 | ||
1712 | mapped_elems = 0; | |
1713 | ||
1714 | goto out; | |
1715 | } | |
1716 | ||
431b2a20 JR |
1717 | /* |
1718 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1719 | * lists). | |
1720 | */ | |
65b050ad | 1721 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1722 | int nelems, enum dma_data_direction dir, |
1723 | struct dma_attrs *attrs) | |
65b050ad JR |
1724 | { |
1725 | unsigned long flags; | |
1726 | struct amd_iommu *iommu; | |
1727 | struct protection_domain *domain; | |
1728 | struct scatterlist *s; | |
1729 | u16 devid; | |
1730 | int i; | |
1731 | ||
55877a6b JR |
1732 | INC_STATS_COUNTER(cnt_unmap_sg); |
1733 | ||
dbcc112e JR |
1734 | if (!check_device(dev) || |
1735 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1736 | return; |
1737 | ||
5b28df6f JR |
1738 | if (!dma_ops_domain(domain)) |
1739 | return; | |
1740 | ||
65b050ad JR |
1741 | spin_lock_irqsave(&domain->lock, flags); |
1742 | ||
1743 | for_each_sg(sglist, s, nelems, i) { | |
1744 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1745 | s->dma_length, dir); | |
65b050ad JR |
1746 | s->dma_address = s->dma_length = 0; |
1747 | } | |
1748 | ||
09ee17eb | 1749 | iommu_completion_wait(iommu); |
65b050ad JR |
1750 | |
1751 | spin_unlock_irqrestore(&domain->lock, flags); | |
1752 | } | |
1753 | ||
431b2a20 JR |
1754 | /* |
1755 | * The exported alloc_coherent function for dma_ops. | |
1756 | */ | |
5d8b53cf JR |
1757 | static void *alloc_coherent(struct device *dev, size_t size, |
1758 | dma_addr_t *dma_addr, gfp_t flag) | |
1759 | { | |
1760 | unsigned long flags; | |
1761 | void *virt_addr; | |
1762 | struct amd_iommu *iommu; | |
1763 | struct protection_domain *domain; | |
1764 | u16 devid; | |
1765 | phys_addr_t paddr; | |
832a90c3 | 1766 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1767 | |
c8f0fb36 JR |
1768 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1769 | ||
dbcc112e JR |
1770 | if (!check_device(dev)) |
1771 | return NULL; | |
5d8b53cf | 1772 | |
13d9fead FT |
1773 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1774 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1775 | |
c97ac535 | 1776 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1777 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1778 | if (!virt_addr) | |
b25ae679 | 1779 | return NULL; |
5d8b53cf | 1780 | |
5d8b53cf JR |
1781 | paddr = virt_to_phys(virt_addr); |
1782 | ||
5d8b53cf JR |
1783 | if (!iommu || !domain) { |
1784 | *dma_addr = (dma_addr_t)paddr; | |
1785 | return virt_addr; | |
1786 | } | |
1787 | ||
5b28df6f JR |
1788 | if (!dma_ops_domain(domain)) |
1789 | goto out_free; | |
1790 | ||
832a90c3 JR |
1791 | if (!dma_mask) |
1792 | dma_mask = *dev->dma_mask; | |
1793 | ||
5d8b53cf JR |
1794 | spin_lock_irqsave(&domain->lock, flags); |
1795 | ||
1796 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1797 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1798 | |
367d04c4 JS |
1799 | if (*dma_addr == bad_dma_address) { |
1800 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1801 | goto out_free; |
367d04c4 | 1802 | } |
5d8b53cf | 1803 | |
09ee17eb | 1804 | iommu_completion_wait(iommu); |
5d8b53cf | 1805 | |
5d8b53cf JR |
1806 | spin_unlock_irqrestore(&domain->lock, flags); |
1807 | ||
1808 | return virt_addr; | |
5b28df6f JR |
1809 | |
1810 | out_free: | |
1811 | ||
1812 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1813 | ||
1814 | return NULL; | |
5d8b53cf JR |
1815 | } |
1816 | ||
431b2a20 JR |
1817 | /* |
1818 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1819 | */ |
5d8b53cf JR |
1820 | static void free_coherent(struct device *dev, size_t size, |
1821 | void *virt_addr, dma_addr_t dma_addr) | |
1822 | { | |
1823 | unsigned long flags; | |
1824 | struct amd_iommu *iommu; | |
1825 | struct protection_domain *domain; | |
1826 | u16 devid; | |
1827 | ||
5d31ee7e JR |
1828 | INC_STATS_COUNTER(cnt_free_coherent); |
1829 | ||
dbcc112e JR |
1830 | if (!check_device(dev)) |
1831 | return; | |
1832 | ||
5d8b53cf JR |
1833 | get_device_resources(dev, &iommu, &domain, &devid); |
1834 | ||
1835 | if (!iommu || !domain) | |
1836 | goto free_mem; | |
1837 | ||
5b28df6f JR |
1838 | if (!dma_ops_domain(domain)) |
1839 | goto free_mem; | |
1840 | ||
5d8b53cf JR |
1841 | spin_lock_irqsave(&domain->lock, flags); |
1842 | ||
1843 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1844 | |
09ee17eb | 1845 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1846 | |
1847 | spin_unlock_irqrestore(&domain->lock, flags); | |
1848 | ||
1849 | free_mem: | |
1850 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1851 | } | |
1852 | ||
b39ba6ad JR |
1853 | /* |
1854 | * This function is called by the DMA layer to find out if we can handle a | |
1855 | * particular device. It is part of the dma_ops. | |
1856 | */ | |
1857 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1858 | { | |
1859 | u16 bdf; | |
1860 | struct pci_dev *pcidev; | |
1861 | ||
1862 | /* No device or no PCI device */ | |
1863 | if (!dev || dev->bus != &pci_bus_type) | |
1864 | return 0; | |
1865 | ||
1866 | pcidev = to_pci_dev(dev); | |
1867 | ||
1868 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1869 | ||
1870 | /* Out of our scope? */ | |
1871 | if (bdf > amd_iommu_last_bdf) | |
1872 | return 0; | |
1873 | ||
1874 | return 1; | |
1875 | } | |
1876 | ||
c432f3df | 1877 | /* |
431b2a20 JR |
1878 | * The function for pre-allocating protection domains. |
1879 | * | |
c432f3df JR |
1880 | * If the driver core informs the DMA layer if a driver grabs a device |
1881 | * we don't need to preallocate the protection domains anymore. | |
1882 | * For now we have to. | |
1883 | */ | |
0e93dd88 | 1884 | static void prealloc_protection_domains(void) |
c432f3df JR |
1885 | { |
1886 | struct pci_dev *dev = NULL; | |
1887 | struct dma_ops_domain *dma_dom; | |
1888 | struct amd_iommu *iommu; | |
c432f3df JR |
1889 | u16 devid; |
1890 | ||
1891 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1892 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1893 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1894 | continue; |
1895 | devid = amd_iommu_alias_table[devid]; | |
1896 | if (domain_for_device(devid)) | |
1897 | continue; | |
1898 | iommu = amd_iommu_rlookup_table[devid]; | |
1899 | if (!iommu) | |
1900 | continue; | |
d9cfed92 | 1901 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1902 | if (!dma_dom) |
1903 | continue; | |
1904 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1905 | dma_dom->target_dev = devid; |
1906 | ||
1907 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1908 | } |
1909 | } | |
1910 | ||
160c1d8e | 1911 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1912 | .alloc_coherent = alloc_coherent, |
1913 | .free_coherent = free_coherent, | |
51491367 FT |
1914 | .map_page = map_page, |
1915 | .unmap_page = unmap_page, | |
6631ee9d JR |
1916 | .map_sg = map_sg, |
1917 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1918 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1919 | }; |
1920 | ||
431b2a20 JR |
1921 | /* |
1922 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1923 | */ | |
6631ee9d JR |
1924 | int __init amd_iommu_init_dma_ops(void) |
1925 | { | |
1926 | struct amd_iommu *iommu; | |
6631ee9d JR |
1927 | int ret; |
1928 | ||
431b2a20 JR |
1929 | /* |
1930 | * first allocate a default protection domain for every IOMMU we | |
1931 | * found in the system. Devices not assigned to any other | |
1932 | * protection domain will be assigned to the default one. | |
1933 | */ | |
3bd22172 | 1934 | for_each_iommu(iommu) { |
d9cfed92 | 1935 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1936 | if (iommu->default_dom == NULL) |
1937 | return -ENOMEM; | |
e2dc14a2 | 1938 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1939 | ret = iommu_init_unity_mappings(iommu); |
1940 | if (ret) | |
1941 | goto free_domains; | |
1942 | } | |
1943 | ||
431b2a20 JR |
1944 | /* |
1945 | * If device isolation is enabled, pre-allocate the protection | |
1946 | * domains for each device. | |
1947 | */ | |
6631ee9d JR |
1948 | if (amd_iommu_isolate) |
1949 | prealloc_protection_domains(); | |
1950 | ||
1951 | iommu_detected = 1; | |
1952 | force_iommu = 1; | |
1953 | bad_dma_address = 0; | |
92af4e29 | 1954 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1955 | gart_iommu_aperture_disabled = 1; |
1956 | gart_iommu_aperture = 0; | |
92af4e29 | 1957 | #endif |
6631ee9d | 1958 | |
431b2a20 | 1959 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1960 | dma_ops = &amd_iommu_dma_ops; |
1961 | ||
26961efe | 1962 | register_iommu(&amd_iommu_ops); |
26961efe | 1963 | |
e275a2a0 JR |
1964 | bus_register_notifier(&pci_bus_type, &device_nb); |
1965 | ||
7f26508b JR |
1966 | amd_iommu_stats_init(); |
1967 | ||
6631ee9d JR |
1968 | return 0; |
1969 | ||
1970 | free_domains: | |
1971 | ||
3bd22172 | 1972 | for_each_iommu(iommu) { |
6631ee9d JR |
1973 | if (iommu->default_dom) |
1974 | dma_ops_domain_free(iommu->default_dom); | |
1975 | } | |
1976 | ||
1977 | return ret; | |
1978 | } | |
6d98cd80 JR |
1979 | |
1980 | /***************************************************************************** | |
1981 | * | |
1982 | * The following functions belong to the exported interface of AMD IOMMU | |
1983 | * | |
1984 | * This interface allows access to lower level functions of the IOMMU | |
1985 | * like protection domain handling and assignement of devices to domains | |
1986 | * which is not possible with the dma_ops interface. | |
1987 | * | |
1988 | *****************************************************************************/ | |
1989 | ||
6d98cd80 JR |
1990 | static void cleanup_domain(struct protection_domain *domain) |
1991 | { | |
1992 | unsigned long flags; | |
1993 | u16 devid; | |
1994 | ||
1995 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1996 | ||
1997 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1998 | if (amd_iommu_pd_table[devid] == domain) | |
1999 | __detach_device(domain, devid); | |
2000 | ||
2001 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2002 | } | |
2003 | ||
2650815f JR |
2004 | static void protection_domain_free(struct protection_domain *domain) |
2005 | { | |
2006 | if (!domain) | |
2007 | return; | |
2008 | ||
2009 | if (domain->id) | |
2010 | domain_id_free(domain->id); | |
2011 | ||
2012 | kfree(domain); | |
2013 | } | |
2014 | ||
2015 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2016 | { |
2017 | struct protection_domain *domain; | |
2018 | ||
2019 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2020 | if (!domain) | |
2650815f | 2021 | return NULL; |
c156e347 JR |
2022 | |
2023 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2024 | domain->id = domain_id_alloc(); |
2025 | if (!domain->id) | |
2650815f JR |
2026 | goto out_err; |
2027 | ||
2028 | return domain; | |
2029 | ||
2030 | out_err: | |
2031 | kfree(domain); | |
2032 | ||
2033 | return NULL; | |
2034 | } | |
2035 | ||
2036 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2037 | { | |
2038 | struct protection_domain *domain; | |
2039 | ||
2040 | domain = protection_domain_alloc(); | |
2041 | if (!domain) | |
c156e347 | 2042 | goto out_free; |
2650815f JR |
2043 | |
2044 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2045 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2046 | if (!domain->pt_root) | |
2047 | goto out_free; | |
2048 | ||
2049 | dom->priv = domain; | |
2050 | ||
2051 | return 0; | |
2052 | ||
2053 | out_free: | |
2650815f | 2054 | protection_domain_free(domain); |
c156e347 JR |
2055 | |
2056 | return -ENOMEM; | |
2057 | } | |
2058 | ||
98383fc3 JR |
2059 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2060 | { | |
2061 | struct protection_domain *domain = dom->priv; | |
2062 | ||
2063 | if (!domain) | |
2064 | return; | |
2065 | ||
2066 | if (domain->dev_cnt > 0) | |
2067 | cleanup_domain(domain); | |
2068 | ||
2069 | BUG_ON(domain->dev_cnt != 0); | |
2070 | ||
2071 | free_pagetable(domain); | |
2072 | ||
2073 | domain_id_free(domain->id); | |
2074 | ||
2075 | kfree(domain); | |
2076 | ||
2077 | dom->priv = NULL; | |
2078 | } | |
2079 | ||
684f2888 JR |
2080 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2081 | struct device *dev) | |
2082 | { | |
2083 | struct protection_domain *domain = dom->priv; | |
2084 | struct amd_iommu *iommu; | |
2085 | struct pci_dev *pdev; | |
2086 | u16 devid; | |
2087 | ||
2088 | if (dev->bus != &pci_bus_type) | |
2089 | return; | |
2090 | ||
2091 | pdev = to_pci_dev(dev); | |
2092 | ||
2093 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2094 | ||
2095 | if (devid > 0) | |
2096 | detach_device(domain, devid); | |
2097 | ||
2098 | iommu = amd_iommu_rlookup_table[devid]; | |
2099 | if (!iommu) | |
2100 | return; | |
2101 | ||
2102 | iommu_queue_inv_dev_entry(iommu, devid); | |
2103 | iommu_completion_wait(iommu); | |
2104 | } | |
2105 | ||
01106066 JR |
2106 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2107 | struct device *dev) | |
2108 | { | |
2109 | struct protection_domain *domain = dom->priv; | |
2110 | struct protection_domain *old_domain; | |
2111 | struct amd_iommu *iommu; | |
2112 | struct pci_dev *pdev; | |
2113 | u16 devid; | |
2114 | ||
2115 | if (dev->bus != &pci_bus_type) | |
2116 | return -EINVAL; | |
2117 | ||
2118 | pdev = to_pci_dev(dev); | |
2119 | ||
2120 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2121 | ||
2122 | if (devid >= amd_iommu_last_bdf || | |
2123 | devid != amd_iommu_alias_table[devid]) | |
2124 | return -EINVAL; | |
2125 | ||
2126 | iommu = amd_iommu_rlookup_table[devid]; | |
2127 | if (!iommu) | |
2128 | return -EINVAL; | |
2129 | ||
2130 | old_domain = domain_for_device(devid); | |
2131 | if (old_domain) | |
71ff3bca | 2132 | detach_device(old_domain, devid); |
01106066 JR |
2133 | |
2134 | attach_device(iommu, domain, devid); | |
2135 | ||
2136 | iommu_completion_wait(iommu); | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
c6229ca6 JR |
2141 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2142 | unsigned long iova, phys_addr_t paddr, | |
2143 | size_t size, int iommu_prot) | |
2144 | { | |
2145 | struct protection_domain *domain = dom->priv; | |
2146 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2147 | int prot = 0; | |
2148 | int ret; | |
2149 | ||
2150 | if (iommu_prot & IOMMU_READ) | |
2151 | prot |= IOMMU_PROT_IR; | |
2152 | if (iommu_prot & IOMMU_WRITE) | |
2153 | prot |= IOMMU_PROT_IW; | |
2154 | ||
2155 | iova &= PAGE_MASK; | |
2156 | paddr &= PAGE_MASK; | |
2157 | ||
2158 | for (i = 0; i < npages; ++i) { | |
2159 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2160 | if (ret) | |
2161 | return ret; | |
2162 | ||
2163 | iova += PAGE_SIZE; | |
2164 | paddr += PAGE_SIZE; | |
2165 | } | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | ||
eb74ff6c JR |
2170 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2171 | unsigned long iova, size_t size) | |
2172 | { | |
2173 | ||
2174 | struct protection_domain *domain = dom->priv; | |
2175 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2176 | ||
2177 | iova &= PAGE_MASK; | |
2178 | ||
2179 | for (i = 0; i < npages; ++i) { | |
2180 | iommu_unmap_page(domain, iova); | |
2181 | iova += PAGE_SIZE; | |
2182 | } | |
2183 | ||
2184 | iommu_flush_domain(domain->id); | |
2185 | } | |
2186 | ||
645c4c8d JR |
2187 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2188 | unsigned long iova) | |
2189 | { | |
2190 | struct protection_domain *domain = dom->priv; | |
2191 | unsigned long offset = iova & ~PAGE_MASK; | |
2192 | phys_addr_t paddr; | |
2193 | u64 *pte; | |
2194 | ||
2195 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2196 | ||
2197 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2198 | return 0; | |
2199 | ||
2200 | pte = IOMMU_PTE_PAGE(*pte); | |
2201 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2202 | ||
2203 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2204 | return 0; | |
2205 | ||
2206 | pte = IOMMU_PTE_PAGE(*pte); | |
2207 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2208 | ||
2209 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2210 | return 0; | |
2211 | ||
2212 | paddr = *pte & IOMMU_PAGE_MASK; | |
2213 | paddr |= offset; | |
2214 | ||
2215 | return paddr; | |
2216 | } | |
2217 | ||
dbb9fd86 SY |
2218 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2219 | unsigned long cap) | |
2220 | { | |
2221 | return 0; | |
2222 | } | |
2223 | ||
26961efe JR |
2224 | static struct iommu_ops amd_iommu_ops = { |
2225 | .domain_init = amd_iommu_domain_init, | |
2226 | .domain_destroy = amd_iommu_domain_destroy, | |
2227 | .attach_dev = amd_iommu_attach_device, | |
2228 | .detach_dev = amd_iommu_detach_device, | |
2229 | .map = amd_iommu_map_range, | |
2230 | .unmap = amd_iommu_unmap_range, | |
2231 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2232 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2233 | }; |
2234 | ||
0feae533 JR |
2235 | /***************************************************************************** |
2236 | * | |
2237 | * The next functions do a basic initialization of IOMMU for pass through | |
2238 | * mode | |
2239 | * | |
2240 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2241 | * DMA-API translation. | |
2242 | * | |
2243 | *****************************************************************************/ | |
2244 | ||
2245 | int __init amd_iommu_init_passthrough(void) | |
2246 | { | |
2247 | struct pci_dev *dev = NULL; | |
2248 | u16 devid, devid2; | |
2249 | ||
2250 | /* allocate passthroug domain */ | |
2251 | pt_domain = protection_domain_alloc(); | |
2252 | if (!pt_domain) | |
2253 | return -ENOMEM; | |
2254 | ||
2255 | pt_domain->mode |= PAGE_MODE_NONE; | |
2256 | ||
2257 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2258 | struct amd_iommu *iommu; | |
2259 | ||
2260 | devid = calc_devid(dev->bus->number, dev->devfn); | |
2261 | if (devid > amd_iommu_last_bdf) | |
2262 | continue; | |
2263 | ||
2264 | devid2 = amd_iommu_alias_table[devid]; | |
2265 | ||
2266 | iommu = amd_iommu_rlookup_table[devid2]; | |
2267 | if (!iommu) | |
2268 | continue; | |
2269 | ||
2270 | __attach_device(iommu, pt_domain, devid); | |
2271 | __attach_device(iommu, pt_domain, devid2); | |
2272 | } | |
2273 | ||
2274 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2275 | ||
2276 | return 0; | |
2277 | } |