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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 JR |
57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
58 | ||
bd0e5211 | 59 | |
c1eee67b CW |
60 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
61 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
62 | #endif | |
63 | ||
7f26508b JR |
64 | #ifdef CONFIG_AMD_IOMMU_STATS |
65 | ||
66 | /* | |
67 | * Initialization code for statistics collection | |
68 | */ | |
69 | ||
da49f6df | 70 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 71 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 72 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 73 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 74 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 75 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 76 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 77 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 78 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 79 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 80 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 81 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 82 | |
7f26508b JR |
83 | static struct dentry *stats_dir; |
84 | static struct dentry *de_isolate; | |
85 | static struct dentry *de_fflush; | |
86 | ||
87 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
88 | { | |
89 | if (stats_dir == NULL) | |
90 | return; | |
91 | ||
92 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
93 | &cnt->value); | |
94 | } | |
95 | ||
96 | static void amd_iommu_stats_init(void) | |
97 | { | |
98 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
99 | if (stats_dir == NULL) | |
100 | return; | |
101 | ||
102 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
103 | (u32 *)&amd_iommu_isolate); | |
104 | ||
105 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
106 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
107 | |
108 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 109 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 110 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 111 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 112 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 113 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 114 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 115 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 116 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 117 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 118 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 119 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
120 | } |
121 | ||
122 | #endif | |
123 | ||
431b2a20 | 124 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
125 | static int iommu_has_npcache(struct amd_iommu *iommu) |
126 | { | |
ae9b9403 | 127 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
128 | } |
129 | ||
a80dc3e0 JR |
130 | /**************************************************************************** |
131 | * | |
132 | * Interrupt handling functions | |
133 | * | |
134 | ****************************************************************************/ | |
135 | ||
90008ee4 JR |
136 | static void iommu_print_event(void *__evt) |
137 | { | |
138 | u32 *event = __evt; | |
139 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
140 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
141 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
142 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
143 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
144 | ||
145 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
146 | ||
147 | switch (type) { | |
148 | case EVENT_TYPE_ILL_DEV: | |
149 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
150 | "address=0x%016llx flags=0x%04x]\n", | |
151 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
152 | address, flags); | |
153 | break; | |
154 | case EVENT_TYPE_IO_FAULT: | |
155 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
156 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
157 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
158 | domid, address, flags); | |
159 | break; | |
160 | case EVENT_TYPE_DEV_TAB_ERR: | |
161 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
162 | "address=0x%016llx flags=0x%04x]\n", | |
163 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
164 | address, flags); | |
165 | break; | |
166 | case EVENT_TYPE_PAGE_TAB_ERR: | |
167 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
168 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
169 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
170 | domid, address, flags); | |
171 | break; | |
172 | case EVENT_TYPE_ILL_CMD: | |
173 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
174 | break; | |
175 | case EVENT_TYPE_CMD_HARD_ERR: | |
176 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
177 | "flags=0x%04x]\n", address, flags); | |
178 | break; | |
179 | case EVENT_TYPE_IOTLB_INV_TO: | |
180 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
181 | "address=0x%016llx]\n", | |
182 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
183 | address); | |
184 | break; | |
185 | case EVENT_TYPE_INV_DEV_REQ: | |
186 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
187 | "address=0x%016llx flags=0x%04x]\n", | |
188 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
189 | address, flags); | |
190 | break; | |
191 | default: | |
192 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
193 | } | |
194 | } | |
195 | ||
196 | static void iommu_poll_events(struct amd_iommu *iommu) | |
197 | { | |
198 | u32 head, tail; | |
199 | unsigned long flags; | |
200 | ||
201 | spin_lock_irqsave(&iommu->lock, flags); | |
202 | ||
203 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
204 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
205 | ||
206 | while (head != tail) { | |
207 | iommu_print_event(iommu->evt_buf + head); | |
208 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
209 | } | |
210 | ||
211 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
212 | ||
213 | spin_unlock_irqrestore(&iommu->lock, flags); | |
214 | } | |
215 | ||
a80dc3e0 JR |
216 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
217 | { | |
90008ee4 JR |
218 | struct amd_iommu *iommu; |
219 | ||
220 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
221 | iommu_poll_events(iommu); | |
222 | ||
223 | return IRQ_HANDLED; | |
a80dc3e0 JR |
224 | } |
225 | ||
431b2a20 JR |
226 | /**************************************************************************** |
227 | * | |
228 | * IOMMU command queuing functions | |
229 | * | |
230 | ****************************************************************************/ | |
231 | ||
232 | /* | |
233 | * Writes the command to the IOMMUs command buffer and informs the | |
234 | * hardware about the new command. Must be called with iommu->lock held. | |
235 | */ | |
d6449536 | 236 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
237 | { |
238 | u32 tail, head; | |
239 | u8 *target; | |
240 | ||
241 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 242 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
243 | memcpy_toio(target, cmd, sizeof(*cmd)); |
244 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
245 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
246 | if (tail == head) | |
247 | return -ENOMEM; | |
248 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
431b2a20 JR |
253 | /* |
254 | * General queuing function for commands. Takes iommu->lock and calls | |
255 | * __iommu_queue_command(). | |
256 | */ | |
d6449536 | 257 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
258 | { |
259 | unsigned long flags; | |
260 | int ret; | |
261 | ||
262 | spin_lock_irqsave(&iommu->lock, flags); | |
263 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 264 | if (!ret) |
0cfd7aa9 | 265 | iommu->need_sync = true; |
a19ae1ec JR |
266 | spin_unlock_irqrestore(&iommu->lock, flags); |
267 | ||
268 | return ret; | |
269 | } | |
270 | ||
8d201968 JR |
271 | /* |
272 | * This function waits until an IOMMU has completed a completion | |
273 | * wait command | |
274 | */ | |
275 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
276 | { | |
277 | int ready = 0; | |
278 | unsigned status = 0; | |
279 | unsigned long i = 0; | |
280 | ||
da49f6df JR |
281 | INC_STATS_COUNTER(compl_wait); |
282 | ||
8d201968 JR |
283 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
284 | ++i; | |
285 | /* wait for the bit to become one */ | |
286 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
287 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
288 | } | |
289 | ||
290 | /* set bit back to zero */ | |
291 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
292 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
293 | ||
294 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
295 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
296 | } | |
297 | ||
298 | /* | |
299 | * This function queues a completion wait command into the command | |
300 | * buffer of an IOMMU | |
301 | */ | |
302 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
303 | { | |
304 | struct iommu_cmd cmd; | |
305 | ||
306 | memset(&cmd, 0, sizeof(cmd)); | |
307 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
308 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
309 | ||
310 | return __iommu_queue_command(iommu, &cmd); | |
311 | } | |
312 | ||
431b2a20 JR |
313 | /* |
314 | * This function is called whenever we need to ensure that the IOMMU has | |
315 | * completed execution of all commands we sent. It sends a | |
316 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
317 | * us about that by writing a value to a physical address we pass with | |
318 | * the command. | |
319 | */ | |
a19ae1ec JR |
320 | static int iommu_completion_wait(struct amd_iommu *iommu) |
321 | { | |
8d201968 JR |
322 | int ret = 0; |
323 | unsigned long flags; | |
a19ae1ec | 324 | |
7e4f88da JR |
325 | spin_lock_irqsave(&iommu->lock, flags); |
326 | ||
09ee17eb JR |
327 | if (!iommu->need_sync) |
328 | goto out; | |
329 | ||
8d201968 | 330 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 331 | |
0cfd7aa9 | 332 | iommu->need_sync = false; |
a19ae1ec JR |
333 | |
334 | if (ret) | |
7e4f88da | 335 | goto out; |
a19ae1ec | 336 | |
8d201968 | 337 | __iommu_wait_for_completion(iommu); |
84df8175 | 338 | |
7e4f88da JR |
339 | out: |
340 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
341 | |
342 | return 0; | |
343 | } | |
344 | ||
431b2a20 JR |
345 | /* |
346 | * Command send function for invalidating a device table entry | |
347 | */ | |
a19ae1ec JR |
348 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
349 | { | |
d6449536 | 350 | struct iommu_cmd cmd; |
ee2fa743 | 351 | int ret; |
a19ae1ec JR |
352 | |
353 | BUG_ON(iommu == NULL); | |
354 | ||
355 | memset(&cmd, 0, sizeof(cmd)); | |
356 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
357 | cmd.data[0] = devid; | |
358 | ||
ee2fa743 JR |
359 | ret = iommu_queue_command(iommu, &cmd); |
360 | ||
ee2fa743 | 361 | return ret; |
a19ae1ec JR |
362 | } |
363 | ||
237b6f33 JR |
364 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
365 | u16 domid, int pde, int s) | |
366 | { | |
367 | memset(cmd, 0, sizeof(*cmd)); | |
368 | address &= PAGE_MASK; | |
369 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
370 | cmd->data[1] |= domid; | |
371 | cmd->data[2] = lower_32_bits(address); | |
372 | cmd->data[3] = upper_32_bits(address); | |
373 | if (s) /* size bit - we flush more than one 4kb page */ | |
374 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
375 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
376 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
377 | } | |
378 | ||
431b2a20 JR |
379 | /* |
380 | * Generic command send function for invalidaing TLB entries | |
381 | */ | |
a19ae1ec JR |
382 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
383 | u64 address, u16 domid, int pde, int s) | |
384 | { | |
d6449536 | 385 | struct iommu_cmd cmd; |
ee2fa743 | 386 | int ret; |
a19ae1ec | 387 | |
237b6f33 | 388 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 389 | |
ee2fa743 JR |
390 | ret = iommu_queue_command(iommu, &cmd); |
391 | ||
ee2fa743 | 392 | return ret; |
a19ae1ec JR |
393 | } |
394 | ||
431b2a20 JR |
395 | /* |
396 | * TLB invalidation function which is called from the mapping functions. | |
397 | * It invalidates a single PTE if the range to flush is within a single | |
398 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
399 | */ | |
a19ae1ec JR |
400 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
401 | u64 address, size_t size) | |
402 | { | |
999ba417 | 403 | int s = 0; |
e3c449f5 | 404 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
405 | |
406 | address &= PAGE_MASK; | |
407 | ||
999ba417 JR |
408 | if (pages > 1) { |
409 | /* | |
410 | * If we have to flush more than one page, flush all | |
411 | * TLB entries for this domain | |
412 | */ | |
413 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
414 | s = 1; | |
a19ae1ec JR |
415 | } |
416 | ||
999ba417 JR |
417 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
418 | ||
a19ae1ec JR |
419 | return 0; |
420 | } | |
b6c02715 | 421 | |
1c655773 JR |
422 | /* Flush the whole IO/TLB for a given protection domain */ |
423 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
424 | { | |
425 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
426 | ||
f57d98ae JR |
427 | INC_STATS_COUNTER(domain_flush_single); |
428 | ||
1c655773 JR |
429 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
430 | } | |
431 | ||
43f49609 JR |
432 | /* |
433 | * This function is used to flush the IO/TLB for a given protection domain | |
434 | * on every IOMMU in the system | |
435 | */ | |
436 | static void iommu_flush_domain(u16 domid) | |
437 | { | |
438 | unsigned long flags; | |
439 | struct amd_iommu *iommu; | |
440 | struct iommu_cmd cmd; | |
441 | ||
18811f55 JR |
442 | INC_STATS_COUNTER(domain_flush_all); |
443 | ||
43f49609 JR |
444 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
445 | domid, 1, 1); | |
446 | ||
447 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
448 | spin_lock_irqsave(&iommu->lock, flags); | |
449 | __iommu_queue_command(iommu, &cmd); | |
450 | __iommu_completion_wait(iommu); | |
451 | __iommu_wait_for_completion(iommu); | |
452 | spin_unlock_irqrestore(&iommu->lock, flags); | |
453 | } | |
454 | } | |
43f49609 | 455 | |
431b2a20 JR |
456 | /**************************************************************************** |
457 | * | |
458 | * The functions below are used the create the page table mappings for | |
459 | * unity mapped regions. | |
460 | * | |
461 | ****************************************************************************/ | |
462 | ||
463 | /* | |
464 | * Generic mapping functions. It maps a physical address into a DMA | |
465 | * address space. It allocates the page table pages if necessary. | |
466 | * In the future it can be extended to a generic mapping function | |
467 | * supporting all features of AMD IOMMU page tables like level skipping | |
468 | * and full 64 bit address spaces. | |
469 | */ | |
38e817fe JR |
470 | static int iommu_map_page(struct protection_domain *dom, |
471 | unsigned long bus_addr, | |
472 | unsigned long phys_addr, | |
473 | int prot) | |
bd0e5211 JR |
474 | { |
475 | u64 __pte, *pte, *page; | |
476 | ||
477 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 478 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
479 | |
480 | /* only support 512GB address spaces for now */ | |
481 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
482 | return -EINVAL; | |
483 | ||
484 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
485 | ||
486 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
487 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
488 | if (!page) | |
489 | return -ENOMEM; | |
490 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
491 | } | |
492 | ||
493 | pte = IOMMU_PTE_PAGE(*pte); | |
494 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
495 | ||
496 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
497 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
498 | if (!page) | |
499 | return -ENOMEM; | |
500 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
501 | } | |
502 | ||
503 | pte = IOMMU_PTE_PAGE(*pte); | |
504 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
505 | ||
506 | if (IOMMU_PTE_PRESENT(*pte)) | |
507 | return -EBUSY; | |
508 | ||
509 | __pte = phys_addr | IOMMU_PTE_P; | |
510 | if (prot & IOMMU_PROT_IR) | |
511 | __pte |= IOMMU_PTE_IR; | |
512 | if (prot & IOMMU_PROT_IW) | |
513 | __pte |= IOMMU_PTE_IW; | |
514 | ||
515 | *pte = __pte; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
eb74ff6c JR |
520 | static void iommu_unmap_page(struct protection_domain *dom, |
521 | unsigned long bus_addr) | |
522 | { | |
523 | u64 *pte; | |
524 | ||
525 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
526 | ||
527 | if (!IOMMU_PTE_PRESENT(*pte)) | |
528 | return; | |
529 | ||
530 | pte = IOMMU_PTE_PAGE(*pte); | |
531 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
532 | ||
533 | if (!IOMMU_PTE_PRESENT(*pte)) | |
534 | return; | |
535 | ||
536 | pte = IOMMU_PTE_PAGE(*pte); | |
537 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
538 | ||
539 | *pte = 0; | |
540 | } | |
eb74ff6c | 541 | |
431b2a20 JR |
542 | /* |
543 | * This function checks if a specific unity mapping entry is needed for | |
544 | * this specific IOMMU. | |
545 | */ | |
bd0e5211 JR |
546 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
547 | struct unity_map_entry *entry) | |
548 | { | |
549 | u16 bdf, i; | |
550 | ||
551 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
552 | bdf = amd_iommu_alias_table[i]; | |
553 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
554 | return 1; | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
431b2a20 JR |
560 | /* |
561 | * Init the unity mappings for a specific IOMMU in the system | |
562 | * | |
563 | * Basically iterates over all unity mapping entries and applies them to | |
564 | * the default domain DMA of that IOMMU if necessary. | |
565 | */ | |
bd0e5211 JR |
566 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
567 | { | |
568 | struct unity_map_entry *entry; | |
569 | int ret; | |
570 | ||
571 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
572 | if (!iommu_for_unity_map(iommu, entry)) | |
573 | continue; | |
574 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
575 | if (ret) | |
576 | return ret; | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
431b2a20 JR |
582 | /* |
583 | * This function actually applies the mapping to the page table of the | |
584 | * dma_ops domain. | |
585 | */ | |
bd0e5211 JR |
586 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
587 | struct unity_map_entry *e) | |
588 | { | |
589 | u64 addr; | |
590 | int ret; | |
591 | ||
592 | for (addr = e->address_start; addr < e->address_end; | |
593 | addr += PAGE_SIZE) { | |
38e817fe | 594 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
595 | if (ret) |
596 | return ret; | |
597 | /* | |
598 | * if unity mapping is in aperture range mark the page | |
599 | * as allocated in the aperture | |
600 | */ | |
601 | if (addr < dma_dom->aperture_size) | |
602 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
603 | } | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
431b2a20 JR |
608 | /* |
609 | * Inits the unity mappings required for a specific device | |
610 | */ | |
bd0e5211 JR |
611 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
612 | u16 devid) | |
613 | { | |
614 | struct unity_map_entry *e; | |
615 | int ret; | |
616 | ||
617 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
618 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
619 | continue; | |
620 | ret = dma_ops_unity_map(dma_dom, e); | |
621 | if (ret) | |
622 | return ret; | |
623 | } | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
431b2a20 JR |
628 | /**************************************************************************** |
629 | * | |
630 | * The next functions belong to the address allocator for the dma_ops | |
631 | * interface functions. They work like the allocators in the other IOMMU | |
632 | * drivers. Its basically a bitmap which marks the allocated pages in | |
633 | * the aperture. Maybe it could be enhanced in the future to a more | |
634 | * efficient allocator. | |
635 | * | |
636 | ****************************************************************************/ | |
d3086444 | 637 | |
431b2a20 JR |
638 | /* |
639 | * The address allocator core function. | |
640 | * | |
641 | * called with domain->lock held | |
642 | */ | |
d3086444 JR |
643 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
644 | struct dma_ops_domain *dom, | |
6d4f343f | 645 | unsigned int pages, |
832a90c3 JR |
646 | unsigned long align_mask, |
647 | u64 dma_mask) | |
d3086444 | 648 | { |
40becd8d | 649 | unsigned long limit; |
d3086444 | 650 | unsigned long address; |
d3086444 JR |
651 | unsigned long boundary_size; |
652 | ||
653 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
654 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
655 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
656 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 657 | |
1c655773 | 658 | if (dom->next_bit >= limit) { |
d3086444 | 659 | dom->next_bit = 0; |
1c655773 JR |
660 | dom->need_flush = true; |
661 | } | |
d3086444 JR |
662 | |
663 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 664 | 0 , boundary_size, align_mask); |
1c655773 | 665 | if (address == -1) { |
d3086444 | 666 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 667 | 0, boundary_size, align_mask); |
1c655773 JR |
668 | dom->need_flush = true; |
669 | } | |
d3086444 JR |
670 | |
671 | if (likely(address != -1)) { | |
d3086444 JR |
672 | dom->next_bit = address + pages; |
673 | address <<= PAGE_SHIFT; | |
674 | } else | |
675 | address = bad_dma_address; | |
676 | ||
677 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
678 | ||
679 | return address; | |
680 | } | |
681 | ||
431b2a20 JR |
682 | /* |
683 | * The address free function. | |
684 | * | |
685 | * called with domain->lock held | |
686 | */ | |
d3086444 JR |
687 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
688 | unsigned long address, | |
689 | unsigned int pages) | |
690 | { | |
691 | address >>= PAGE_SHIFT; | |
692 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 693 | |
8501c45c | 694 | if (address >= dom->next_bit) |
80be308d | 695 | dom->need_flush = true; |
d3086444 JR |
696 | } |
697 | ||
431b2a20 JR |
698 | /**************************************************************************** |
699 | * | |
700 | * The next functions belong to the domain allocation. A domain is | |
701 | * allocated for every IOMMU as the default domain. If device isolation | |
702 | * is enabled, every device get its own domain. The most important thing | |
703 | * about domains is the page table mapping the DMA address space they | |
704 | * contain. | |
705 | * | |
706 | ****************************************************************************/ | |
707 | ||
ec487d1a JR |
708 | static u16 domain_id_alloc(void) |
709 | { | |
710 | unsigned long flags; | |
711 | int id; | |
712 | ||
713 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
714 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
715 | BUG_ON(id == 0); | |
716 | if (id > 0 && id < MAX_DOMAIN_ID) | |
717 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
718 | else | |
719 | id = 0; | |
720 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
721 | ||
722 | return id; | |
723 | } | |
724 | ||
a2acfb75 JR |
725 | static void domain_id_free(int id) |
726 | { | |
727 | unsigned long flags; | |
728 | ||
729 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
730 | if (id > 0 && id < MAX_DOMAIN_ID) | |
731 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
732 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
733 | } | |
a2acfb75 | 734 | |
431b2a20 JR |
735 | /* |
736 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
737 | * ranges. | |
738 | */ | |
ec487d1a JR |
739 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
740 | unsigned long start_page, | |
741 | unsigned int pages) | |
742 | { | |
743 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
744 | ||
745 | if (start_page + pages > last_page) | |
746 | pages = last_page - start_page; | |
747 | ||
d26dbc5c | 748 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
749 | } |
750 | ||
86db2e5d | 751 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
752 | { |
753 | int i, j; | |
754 | u64 *p1, *p2, *p3; | |
755 | ||
86db2e5d | 756 | p1 = domain->pt_root; |
ec487d1a JR |
757 | |
758 | if (!p1) | |
759 | return; | |
760 | ||
761 | for (i = 0; i < 512; ++i) { | |
762 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
763 | continue; | |
764 | ||
765 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 766 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
767 | if (!IOMMU_PTE_PRESENT(p2[j])) |
768 | continue; | |
769 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
770 | free_page((unsigned long)p3); | |
771 | } | |
772 | ||
773 | free_page((unsigned long)p2); | |
774 | } | |
775 | ||
776 | free_page((unsigned long)p1); | |
86db2e5d JR |
777 | |
778 | domain->pt_root = NULL; | |
ec487d1a JR |
779 | } |
780 | ||
431b2a20 JR |
781 | /* |
782 | * Free a domain, only used if something went wrong in the | |
783 | * allocation path and we need to free an already allocated page table | |
784 | */ | |
ec487d1a JR |
785 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
786 | { | |
787 | if (!dom) | |
788 | return; | |
789 | ||
86db2e5d | 790 | free_pagetable(&dom->domain); |
ec487d1a JR |
791 | |
792 | kfree(dom->pte_pages); | |
793 | ||
794 | kfree(dom->bitmap); | |
795 | ||
796 | kfree(dom); | |
797 | } | |
798 | ||
431b2a20 JR |
799 | /* |
800 | * Allocates a new protection domain usable for the dma_ops functions. | |
801 | * It also intializes the page table and the address allocator data | |
802 | * structures required for the dma_ops interface | |
803 | */ | |
ec487d1a JR |
804 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
805 | unsigned order) | |
806 | { | |
807 | struct dma_ops_domain *dma_dom; | |
808 | unsigned i, num_pte_pages; | |
809 | u64 *l2_pde; | |
810 | u64 address; | |
811 | ||
812 | /* | |
813 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
814 | */ | |
815 | if ((order < 25) || (order > 30)) | |
816 | return NULL; | |
817 | ||
818 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
819 | if (!dma_dom) | |
820 | return NULL; | |
821 | ||
822 | spin_lock_init(&dma_dom->domain.lock); | |
823 | ||
824 | dma_dom->domain.id = domain_id_alloc(); | |
825 | if (dma_dom->domain.id == 0) | |
826 | goto free_dma_dom; | |
827 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
828 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 829 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
830 | dma_dom->domain.priv = dma_dom; |
831 | if (!dma_dom->domain.pt_root) | |
832 | goto free_dma_dom; | |
833 | dma_dom->aperture_size = (1ULL << order); | |
834 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
835 | GFP_KERNEL); | |
836 | if (!dma_dom->bitmap) | |
837 | goto free_dma_dom; | |
838 | /* | |
839 | * mark the first page as allocated so we never return 0 as | |
840 | * a valid dma-address. So we can use 0 as error value | |
841 | */ | |
842 | dma_dom->bitmap[0] = 1; | |
843 | dma_dom->next_bit = 0; | |
844 | ||
1c655773 | 845 | dma_dom->need_flush = false; |
bd60b735 | 846 | dma_dom->target_dev = 0xffff; |
1c655773 | 847 | |
431b2a20 | 848 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
849 | if (iommu->exclusion_start && |
850 | iommu->exclusion_start < dma_dom->aperture_size) { | |
851 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
852 | int pages = iommu_num_pages(iommu->exclusion_start, |
853 | iommu->exclusion_length, | |
854 | PAGE_SIZE); | |
ec487d1a JR |
855 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
856 | } | |
857 | ||
431b2a20 JR |
858 | /* |
859 | * At the last step, build the page tables so we don't need to | |
860 | * allocate page table pages in the dma_ops mapping/unmapping | |
861 | * path. | |
862 | */ | |
ec487d1a JR |
863 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
864 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
865 | GFP_KERNEL); | |
866 | if (!dma_dom->pte_pages) | |
867 | goto free_dma_dom; | |
868 | ||
869 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
870 | if (l2_pde == NULL) | |
871 | goto free_dma_dom; | |
872 | ||
873 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
874 | ||
875 | for (i = 0; i < num_pte_pages; ++i) { | |
876 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
877 | if (!dma_dom->pte_pages[i]) | |
878 | goto free_dma_dom; | |
879 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
880 | l2_pde[i] = IOMMU_L1_PDE(address); | |
881 | } | |
882 | ||
883 | return dma_dom; | |
884 | ||
885 | free_dma_dom: | |
886 | dma_ops_domain_free(dma_dom); | |
887 | ||
888 | return NULL; | |
889 | } | |
890 | ||
5b28df6f JR |
891 | /* |
892 | * little helper function to check whether a given protection domain is a | |
893 | * dma_ops domain | |
894 | */ | |
895 | static bool dma_ops_domain(struct protection_domain *domain) | |
896 | { | |
897 | return domain->flags & PD_DMA_OPS_MASK; | |
898 | } | |
899 | ||
431b2a20 JR |
900 | /* |
901 | * Find out the protection domain structure for a given PCI device. This | |
902 | * will give us the pointer to the page table root for example. | |
903 | */ | |
b20ac0d4 JR |
904 | static struct protection_domain *domain_for_device(u16 devid) |
905 | { | |
906 | struct protection_domain *dom; | |
907 | unsigned long flags; | |
908 | ||
909 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
910 | dom = amd_iommu_pd_table[devid]; | |
911 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
912 | ||
913 | return dom; | |
914 | } | |
915 | ||
431b2a20 JR |
916 | /* |
917 | * If a device is not yet associated with a domain, this function does | |
918 | * assigns it visible for the hardware | |
919 | */ | |
f1179dc0 JR |
920 | static void attach_device(struct amd_iommu *iommu, |
921 | struct protection_domain *domain, | |
922 | u16 devid) | |
b20ac0d4 JR |
923 | { |
924 | unsigned long flags; | |
b20ac0d4 JR |
925 | u64 pte_root = virt_to_phys(domain->pt_root); |
926 | ||
863c74eb JR |
927 | domain->dev_cnt += 1; |
928 | ||
38ddf41b JR |
929 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
930 | << DEV_ENTRY_MODE_SHIFT; | |
931 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
932 | |
933 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
934 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
935 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
936 | amd_iommu_dev_table[devid].data[2] = domain->id; |
937 | ||
938 | amd_iommu_pd_table[devid] = domain; | |
939 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
940 | ||
941 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
942 | } |
943 | ||
355bf553 JR |
944 | /* |
945 | * Removes a device from a protection domain (unlocked) | |
946 | */ | |
947 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
948 | { | |
949 | ||
950 | /* lock domain */ | |
951 | spin_lock(&domain->lock); | |
952 | ||
953 | /* remove domain from the lookup table */ | |
954 | amd_iommu_pd_table[devid] = NULL; | |
955 | ||
956 | /* remove entry from the device table seen by the hardware */ | |
957 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
958 | amd_iommu_dev_table[devid].data[1] = 0; | |
959 | amd_iommu_dev_table[devid].data[2] = 0; | |
960 | ||
961 | /* decrease reference counter */ | |
962 | domain->dev_cnt -= 1; | |
963 | ||
964 | /* ready */ | |
965 | spin_unlock(&domain->lock); | |
966 | } | |
967 | ||
968 | /* | |
969 | * Removes a device from a protection domain (with devtable_lock held) | |
970 | */ | |
971 | static void detach_device(struct protection_domain *domain, u16 devid) | |
972 | { | |
973 | unsigned long flags; | |
974 | ||
975 | /* lock device table */ | |
976 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
977 | __detach_device(domain, devid); | |
978 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
979 | } | |
e275a2a0 JR |
980 | |
981 | static int device_change_notifier(struct notifier_block *nb, | |
982 | unsigned long action, void *data) | |
983 | { | |
984 | struct device *dev = data; | |
985 | struct pci_dev *pdev = to_pci_dev(dev); | |
986 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
987 | struct protection_domain *domain; | |
988 | struct dma_ops_domain *dma_domain; | |
989 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
990 | int order = amd_iommu_aperture_order; |
991 | unsigned long flags; | |
e275a2a0 JR |
992 | |
993 | if (devid > amd_iommu_last_bdf) | |
994 | goto out; | |
995 | ||
996 | devid = amd_iommu_alias_table[devid]; | |
997 | ||
998 | iommu = amd_iommu_rlookup_table[devid]; | |
999 | if (iommu == NULL) | |
1000 | goto out; | |
1001 | ||
1002 | domain = domain_for_device(devid); | |
1003 | ||
1004 | if (domain && !dma_ops_domain(domain)) | |
1005 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1006 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1007 | ||
1008 | switch (action) { | |
1009 | case BUS_NOTIFY_BOUND_DRIVER: | |
1010 | if (domain) | |
1011 | goto out; | |
1012 | dma_domain = find_protection_domain(devid); | |
1013 | if (!dma_domain) | |
1014 | dma_domain = iommu->default_dom; | |
1015 | attach_device(iommu, &dma_domain->domain, devid); | |
1016 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1017 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1018 | break; | |
c1eee67b | 1019 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1020 | if (!domain) |
1021 | goto out; | |
1022 | detach_device(domain, devid); | |
1ac4cbbc JR |
1023 | break; |
1024 | case BUS_NOTIFY_ADD_DEVICE: | |
1025 | /* allocate a protection domain if a device is added */ | |
1026 | dma_domain = find_protection_domain(devid); | |
1027 | if (dma_domain) | |
1028 | goto out; | |
1029 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1030 | if (!dma_domain) | |
1031 | goto out; | |
1032 | dma_domain->target_dev = devid; | |
1033 | ||
1034 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1035 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1036 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1037 | ||
e275a2a0 JR |
1038 | break; |
1039 | default: | |
1040 | goto out; | |
1041 | } | |
1042 | ||
1043 | iommu_queue_inv_dev_entry(iommu, devid); | |
1044 | iommu_completion_wait(iommu); | |
1045 | ||
1046 | out: | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | struct notifier_block device_nb = { | |
1051 | .notifier_call = device_change_notifier, | |
1052 | }; | |
355bf553 | 1053 | |
431b2a20 JR |
1054 | /***************************************************************************** |
1055 | * | |
1056 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1057 | * | |
1058 | *****************************************************************************/ | |
1059 | ||
dbcc112e JR |
1060 | /* |
1061 | * This function checks if the driver got a valid device from the caller to | |
1062 | * avoid dereferencing invalid pointers. | |
1063 | */ | |
1064 | static bool check_device(struct device *dev) | |
1065 | { | |
1066 | if (!dev || !dev->dma_mask) | |
1067 | return false; | |
1068 | ||
1069 | return true; | |
1070 | } | |
1071 | ||
bd60b735 JR |
1072 | /* |
1073 | * In this function the list of preallocated protection domains is traversed to | |
1074 | * find the domain for a specific device | |
1075 | */ | |
1076 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1077 | { | |
1078 | struct dma_ops_domain *entry, *ret = NULL; | |
1079 | unsigned long flags; | |
1080 | ||
1081 | if (list_empty(&iommu_pd_list)) | |
1082 | return NULL; | |
1083 | ||
1084 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1085 | ||
1086 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1087 | if (entry->target_dev == devid) { | |
1088 | ret = entry; | |
bd60b735 JR |
1089 | break; |
1090 | } | |
1091 | } | |
1092 | ||
1093 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1094 | ||
1095 | return ret; | |
1096 | } | |
1097 | ||
431b2a20 JR |
1098 | /* |
1099 | * In the dma_ops path we only have the struct device. This function | |
1100 | * finds the corresponding IOMMU, the protection domain and the | |
1101 | * requestor id for a given device. | |
1102 | * If the device is not yet associated with a domain this is also done | |
1103 | * in this function. | |
1104 | */ | |
b20ac0d4 JR |
1105 | static int get_device_resources(struct device *dev, |
1106 | struct amd_iommu **iommu, | |
1107 | struct protection_domain **domain, | |
1108 | u16 *bdf) | |
1109 | { | |
1110 | struct dma_ops_domain *dma_dom; | |
1111 | struct pci_dev *pcidev; | |
1112 | u16 _bdf; | |
1113 | ||
dbcc112e JR |
1114 | *iommu = NULL; |
1115 | *domain = NULL; | |
1116 | *bdf = 0xffff; | |
1117 | ||
1118 | if (dev->bus != &pci_bus_type) | |
1119 | return 0; | |
b20ac0d4 JR |
1120 | |
1121 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1122 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1123 | |
431b2a20 | 1124 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1125 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1126 | return 0; |
b20ac0d4 JR |
1127 | |
1128 | *bdf = amd_iommu_alias_table[_bdf]; | |
1129 | ||
1130 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1131 | if (*iommu == NULL) | |
1132 | return 0; | |
b20ac0d4 JR |
1133 | *domain = domain_for_device(*bdf); |
1134 | if (*domain == NULL) { | |
bd60b735 JR |
1135 | dma_dom = find_protection_domain(*bdf); |
1136 | if (!dma_dom) | |
1137 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1138 | *domain = &dma_dom->domain; |
f1179dc0 | 1139 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1140 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1141 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1142 | } |
1143 | ||
f91ba190 | 1144 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1145 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1146 | |
b20ac0d4 JR |
1147 | return 1; |
1148 | } | |
1149 | ||
431b2a20 JR |
1150 | /* |
1151 | * This is the generic map function. It maps one 4kb page at paddr to | |
1152 | * the given address in the DMA address space for the domain. | |
1153 | */ | |
cb76c322 JR |
1154 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1155 | struct dma_ops_domain *dom, | |
1156 | unsigned long address, | |
1157 | phys_addr_t paddr, | |
1158 | int direction) | |
1159 | { | |
1160 | u64 *pte, __pte; | |
1161 | ||
1162 | WARN_ON(address > dom->aperture_size); | |
1163 | ||
1164 | paddr &= PAGE_MASK; | |
1165 | ||
1166 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1167 | pte += IOMMU_PTE_L0_INDEX(address); | |
1168 | ||
1169 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1170 | ||
1171 | if (direction == DMA_TO_DEVICE) | |
1172 | __pte |= IOMMU_PTE_IR; | |
1173 | else if (direction == DMA_FROM_DEVICE) | |
1174 | __pte |= IOMMU_PTE_IW; | |
1175 | else if (direction == DMA_BIDIRECTIONAL) | |
1176 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1177 | ||
1178 | WARN_ON(*pte); | |
1179 | ||
1180 | *pte = __pte; | |
1181 | ||
1182 | return (dma_addr_t)address; | |
1183 | } | |
1184 | ||
431b2a20 JR |
1185 | /* |
1186 | * The generic unmapping function for on page in the DMA address space. | |
1187 | */ | |
cb76c322 JR |
1188 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1189 | struct dma_ops_domain *dom, | |
1190 | unsigned long address) | |
1191 | { | |
1192 | u64 *pte; | |
1193 | ||
1194 | if (address >= dom->aperture_size) | |
1195 | return; | |
1196 | ||
8ad909c4 | 1197 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1198 | |
1199 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1200 | pte += IOMMU_PTE_L0_INDEX(address); | |
1201 | ||
1202 | WARN_ON(!*pte); | |
1203 | ||
1204 | *pte = 0ULL; | |
1205 | } | |
1206 | ||
431b2a20 JR |
1207 | /* |
1208 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1209 | * contiguous memory region into DMA address space. It is used by all |
1210 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1211 | * Must be called with the domain lock held. |
1212 | */ | |
cb76c322 JR |
1213 | static dma_addr_t __map_single(struct device *dev, |
1214 | struct amd_iommu *iommu, | |
1215 | struct dma_ops_domain *dma_dom, | |
1216 | phys_addr_t paddr, | |
1217 | size_t size, | |
6d4f343f | 1218 | int dir, |
832a90c3 JR |
1219 | bool align, |
1220 | u64 dma_mask) | |
cb76c322 JR |
1221 | { |
1222 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1223 | dma_addr_t address, start; | |
1224 | unsigned int pages; | |
6d4f343f | 1225 | unsigned long align_mask = 0; |
cb76c322 JR |
1226 | int i; |
1227 | ||
e3c449f5 | 1228 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1229 | paddr &= PAGE_MASK; |
1230 | ||
8ecaf8f1 JR |
1231 | INC_STATS_COUNTER(total_map_requests); |
1232 | ||
c1858976 JR |
1233 | if (pages > 1) |
1234 | INC_STATS_COUNTER(cross_page); | |
1235 | ||
6d4f343f JR |
1236 | if (align) |
1237 | align_mask = (1UL << get_order(size)) - 1; | |
1238 | ||
832a90c3 JR |
1239 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1240 | dma_mask); | |
cb76c322 JR |
1241 | if (unlikely(address == bad_dma_address)) |
1242 | goto out; | |
1243 | ||
1244 | start = address; | |
1245 | for (i = 0; i < pages; ++i) { | |
1246 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1247 | paddr += PAGE_SIZE; | |
1248 | start += PAGE_SIZE; | |
1249 | } | |
1250 | address += offset; | |
1251 | ||
5774f7c5 JR |
1252 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1253 | ||
afa9fdc2 | 1254 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1255 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1256 | dma_dom->need_flush = false; | |
1257 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1258 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1259 | ||
cb76c322 JR |
1260 | out: |
1261 | return address; | |
1262 | } | |
1263 | ||
431b2a20 JR |
1264 | /* |
1265 | * Does the reverse of the __map_single function. Must be called with | |
1266 | * the domain lock held too | |
1267 | */ | |
cb76c322 JR |
1268 | static void __unmap_single(struct amd_iommu *iommu, |
1269 | struct dma_ops_domain *dma_dom, | |
1270 | dma_addr_t dma_addr, | |
1271 | size_t size, | |
1272 | int dir) | |
1273 | { | |
1274 | dma_addr_t i, start; | |
1275 | unsigned int pages; | |
1276 | ||
b8d9905d JR |
1277 | if ((dma_addr == bad_dma_address) || |
1278 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1279 | return; |
1280 | ||
e3c449f5 | 1281 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1282 | dma_addr &= PAGE_MASK; |
1283 | start = dma_addr; | |
1284 | ||
1285 | for (i = 0; i < pages; ++i) { | |
1286 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1287 | start += PAGE_SIZE; | |
1288 | } | |
1289 | ||
5774f7c5 JR |
1290 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1291 | ||
cb76c322 | 1292 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1293 | |
80be308d | 1294 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1295 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1296 | dma_dom->need_flush = false; |
1297 | } | |
cb76c322 JR |
1298 | } |
1299 | ||
431b2a20 JR |
1300 | /* |
1301 | * The exported map_single function for dma_ops. | |
1302 | */ | |
51491367 FT |
1303 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1304 | unsigned long offset, size_t size, | |
1305 | enum dma_data_direction dir, | |
1306 | struct dma_attrs *attrs) | |
4da70b9e JR |
1307 | { |
1308 | unsigned long flags; | |
1309 | struct amd_iommu *iommu; | |
1310 | struct protection_domain *domain; | |
1311 | u16 devid; | |
1312 | dma_addr_t addr; | |
832a90c3 | 1313 | u64 dma_mask; |
51491367 | 1314 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1315 | |
0f2a86f2 JR |
1316 | INC_STATS_COUNTER(cnt_map_single); |
1317 | ||
dbcc112e JR |
1318 | if (!check_device(dev)) |
1319 | return bad_dma_address; | |
1320 | ||
832a90c3 | 1321 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1322 | |
1323 | get_device_resources(dev, &iommu, &domain, &devid); | |
1324 | ||
1325 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1326 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1327 | return (dma_addr_t)paddr; |
1328 | ||
5b28df6f JR |
1329 | if (!dma_ops_domain(domain)) |
1330 | return bad_dma_address; | |
1331 | ||
4da70b9e | 1332 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1333 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1334 | dma_mask); | |
4da70b9e JR |
1335 | if (addr == bad_dma_address) |
1336 | goto out; | |
1337 | ||
09ee17eb | 1338 | iommu_completion_wait(iommu); |
4da70b9e JR |
1339 | |
1340 | out: | |
1341 | spin_unlock_irqrestore(&domain->lock, flags); | |
1342 | ||
1343 | return addr; | |
1344 | } | |
1345 | ||
431b2a20 JR |
1346 | /* |
1347 | * The exported unmap_single function for dma_ops. | |
1348 | */ | |
51491367 FT |
1349 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1350 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1351 | { |
1352 | unsigned long flags; | |
1353 | struct amd_iommu *iommu; | |
1354 | struct protection_domain *domain; | |
1355 | u16 devid; | |
1356 | ||
146a6917 JR |
1357 | INC_STATS_COUNTER(cnt_unmap_single); |
1358 | ||
dbcc112e JR |
1359 | if (!check_device(dev) || |
1360 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1361 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1362 | return; |
1363 | ||
5b28df6f JR |
1364 | if (!dma_ops_domain(domain)) |
1365 | return; | |
1366 | ||
4da70b9e JR |
1367 | spin_lock_irqsave(&domain->lock, flags); |
1368 | ||
1369 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1370 | ||
09ee17eb | 1371 | iommu_completion_wait(iommu); |
4da70b9e JR |
1372 | |
1373 | spin_unlock_irqrestore(&domain->lock, flags); | |
1374 | } | |
1375 | ||
431b2a20 JR |
1376 | /* |
1377 | * This is a special map_sg function which is used if we should map a | |
1378 | * device which is not handled by an AMD IOMMU in the system. | |
1379 | */ | |
65b050ad JR |
1380 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1381 | int nelems, int dir) | |
1382 | { | |
1383 | struct scatterlist *s; | |
1384 | int i; | |
1385 | ||
1386 | for_each_sg(sglist, s, nelems, i) { | |
1387 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1388 | s->dma_length = s->length; | |
1389 | } | |
1390 | ||
1391 | return nelems; | |
1392 | } | |
1393 | ||
431b2a20 JR |
1394 | /* |
1395 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1396 | * lists). | |
1397 | */ | |
65b050ad | 1398 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1399 | int nelems, enum dma_data_direction dir, |
1400 | struct dma_attrs *attrs) | |
65b050ad JR |
1401 | { |
1402 | unsigned long flags; | |
1403 | struct amd_iommu *iommu; | |
1404 | struct protection_domain *domain; | |
1405 | u16 devid; | |
1406 | int i; | |
1407 | struct scatterlist *s; | |
1408 | phys_addr_t paddr; | |
1409 | int mapped_elems = 0; | |
832a90c3 | 1410 | u64 dma_mask; |
65b050ad | 1411 | |
d03f067a JR |
1412 | INC_STATS_COUNTER(cnt_map_sg); |
1413 | ||
dbcc112e JR |
1414 | if (!check_device(dev)) |
1415 | return 0; | |
1416 | ||
832a90c3 | 1417 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1418 | |
1419 | get_device_resources(dev, &iommu, &domain, &devid); | |
1420 | ||
1421 | if (!iommu || !domain) | |
1422 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1423 | ||
5b28df6f JR |
1424 | if (!dma_ops_domain(domain)) |
1425 | return 0; | |
1426 | ||
65b050ad JR |
1427 | spin_lock_irqsave(&domain->lock, flags); |
1428 | ||
1429 | for_each_sg(sglist, s, nelems, i) { | |
1430 | paddr = sg_phys(s); | |
1431 | ||
1432 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1433 | paddr, s->length, dir, false, |
1434 | dma_mask); | |
65b050ad JR |
1435 | |
1436 | if (s->dma_address) { | |
1437 | s->dma_length = s->length; | |
1438 | mapped_elems++; | |
1439 | } else | |
1440 | goto unmap; | |
65b050ad JR |
1441 | } |
1442 | ||
09ee17eb | 1443 | iommu_completion_wait(iommu); |
65b050ad JR |
1444 | |
1445 | out: | |
1446 | spin_unlock_irqrestore(&domain->lock, flags); | |
1447 | ||
1448 | return mapped_elems; | |
1449 | unmap: | |
1450 | for_each_sg(sglist, s, mapped_elems, i) { | |
1451 | if (s->dma_address) | |
1452 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1453 | s->dma_length, dir); | |
1454 | s->dma_address = s->dma_length = 0; | |
1455 | } | |
1456 | ||
1457 | mapped_elems = 0; | |
1458 | ||
1459 | goto out; | |
1460 | } | |
1461 | ||
431b2a20 JR |
1462 | /* |
1463 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1464 | * lists). | |
1465 | */ | |
65b050ad | 1466 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1467 | int nelems, enum dma_data_direction dir, |
1468 | struct dma_attrs *attrs) | |
65b050ad JR |
1469 | { |
1470 | unsigned long flags; | |
1471 | struct amd_iommu *iommu; | |
1472 | struct protection_domain *domain; | |
1473 | struct scatterlist *s; | |
1474 | u16 devid; | |
1475 | int i; | |
1476 | ||
55877a6b JR |
1477 | INC_STATS_COUNTER(cnt_unmap_sg); |
1478 | ||
dbcc112e JR |
1479 | if (!check_device(dev) || |
1480 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1481 | return; |
1482 | ||
5b28df6f JR |
1483 | if (!dma_ops_domain(domain)) |
1484 | return; | |
1485 | ||
65b050ad JR |
1486 | spin_lock_irqsave(&domain->lock, flags); |
1487 | ||
1488 | for_each_sg(sglist, s, nelems, i) { | |
1489 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1490 | s->dma_length, dir); | |
65b050ad JR |
1491 | s->dma_address = s->dma_length = 0; |
1492 | } | |
1493 | ||
09ee17eb | 1494 | iommu_completion_wait(iommu); |
65b050ad JR |
1495 | |
1496 | spin_unlock_irqrestore(&domain->lock, flags); | |
1497 | } | |
1498 | ||
431b2a20 JR |
1499 | /* |
1500 | * The exported alloc_coherent function for dma_ops. | |
1501 | */ | |
5d8b53cf JR |
1502 | static void *alloc_coherent(struct device *dev, size_t size, |
1503 | dma_addr_t *dma_addr, gfp_t flag) | |
1504 | { | |
1505 | unsigned long flags; | |
1506 | void *virt_addr; | |
1507 | struct amd_iommu *iommu; | |
1508 | struct protection_domain *domain; | |
1509 | u16 devid; | |
1510 | phys_addr_t paddr; | |
832a90c3 | 1511 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1512 | |
c8f0fb36 JR |
1513 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1514 | ||
dbcc112e JR |
1515 | if (!check_device(dev)) |
1516 | return NULL; | |
5d8b53cf | 1517 | |
13d9fead FT |
1518 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1519 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1520 | |
c97ac535 | 1521 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1522 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1523 | if (!virt_addr) | |
1524 | return 0; | |
1525 | ||
5d8b53cf JR |
1526 | paddr = virt_to_phys(virt_addr); |
1527 | ||
5d8b53cf JR |
1528 | if (!iommu || !domain) { |
1529 | *dma_addr = (dma_addr_t)paddr; | |
1530 | return virt_addr; | |
1531 | } | |
1532 | ||
5b28df6f JR |
1533 | if (!dma_ops_domain(domain)) |
1534 | goto out_free; | |
1535 | ||
832a90c3 JR |
1536 | if (!dma_mask) |
1537 | dma_mask = *dev->dma_mask; | |
1538 | ||
5d8b53cf JR |
1539 | spin_lock_irqsave(&domain->lock, flags); |
1540 | ||
1541 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1542 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1543 | |
5b28df6f JR |
1544 | if (*dma_addr == bad_dma_address) |
1545 | goto out_free; | |
5d8b53cf | 1546 | |
09ee17eb | 1547 | iommu_completion_wait(iommu); |
5d8b53cf | 1548 | |
5d8b53cf JR |
1549 | spin_unlock_irqrestore(&domain->lock, flags); |
1550 | ||
1551 | return virt_addr; | |
5b28df6f JR |
1552 | |
1553 | out_free: | |
1554 | ||
1555 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1556 | ||
1557 | return NULL; | |
5d8b53cf JR |
1558 | } |
1559 | ||
431b2a20 JR |
1560 | /* |
1561 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1562 | */ |
5d8b53cf JR |
1563 | static void free_coherent(struct device *dev, size_t size, |
1564 | void *virt_addr, dma_addr_t dma_addr) | |
1565 | { | |
1566 | unsigned long flags; | |
1567 | struct amd_iommu *iommu; | |
1568 | struct protection_domain *domain; | |
1569 | u16 devid; | |
1570 | ||
5d31ee7e JR |
1571 | INC_STATS_COUNTER(cnt_free_coherent); |
1572 | ||
dbcc112e JR |
1573 | if (!check_device(dev)) |
1574 | return; | |
1575 | ||
5d8b53cf JR |
1576 | get_device_resources(dev, &iommu, &domain, &devid); |
1577 | ||
1578 | if (!iommu || !domain) | |
1579 | goto free_mem; | |
1580 | ||
5b28df6f JR |
1581 | if (!dma_ops_domain(domain)) |
1582 | goto free_mem; | |
1583 | ||
5d8b53cf JR |
1584 | spin_lock_irqsave(&domain->lock, flags); |
1585 | ||
1586 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1587 | |
09ee17eb | 1588 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1589 | |
1590 | spin_unlock_irqrestore(&domain->lock, flags); | |
1591 | ||
1592 | free_mem: | |
1593 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1594 | } | |
1595 | ||
b39ba6ad JR |
1596 | /* |
1597 | * This function is called by the DMA layer to find out if we can handle a | |
1598 | * particular device. It is part of the dma_ops. | |
1599 | */ | |
1600 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1601 | { | |
1602 | u16 bdf; | |
1603 | struct pci_dev *pcidev; | |
1604 | ||
1605 | /* No device or no PCI device */ | |
1606 | if (!dev || dev->bus != &pci_bus_type) | |
1607 | return 0; | |
1608 | ||
1609 | pcidev = to_pci_dev(dev); | |
1610 | ||
1611 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1612 | ||
1613 | /* Out of our scope? */ | |
1614 | if (bdf > amd_iommu_last_bdf) | |
1615 | return 0; | |
1616 | ||
1617 | return 1; | |
1618 | } | |
1619 | ||
c432f3df | 1620 | /* |
431b2a20 JR |
1621 | * The function for pre-allocating protection domains. |
1622 | * | |
c432f3df JR |
1623 | * If the driver core informs the DMA layer if a driver grabs a device |
1624 | * we don't need to preallocate the protection domains anymore. | |
1625 | * For now we have to. | |
1626 | */ | |
0e93dd88 | 1627 | static void prealloc_protection_domains(void) |
c432f3df JR |
1628 | { |
1629 | struct pci_dev *dev = NULL; | |
1630 | struct dma_ops_domain *dma_dom; | |
1631 | struct amd_iommu *iommu; | |
1632 | int order = amd_iommu_aperture_order; | |
1633 | u16 devid; | |
1634 | ||
1635 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1636 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1637 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1638 | continue; |
1639 | devid = amd_iommu_alias_table[devid]; | |
1640 | if (domain_for_device(devid)) | |
1641 | continue; | |
1642 | iommu = amd_iommu_rlookup_table[devid]; | |
1643 | if (!iommu) | |
1644 | continue; | |
1645 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1646 | if (!dma_dom) | |
1647 | continue; | |
1648 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1649 | dma_dom->target_dev = devid; |
1650 | ||
1651 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1652 | } |
1653 | } | |
1654 | ||
160c1d8e | 1655 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1656 | .alloc_coherent = alloc_coherent, |
1657 | .free_coherent = free_coherent, | |
51491367 FT |
1658 | .map_page = map_page, |
1659 | .unmap_page = unmap_page, | |
6631ee9d JR |
1660 | .map_sg = map_sg, |
1661 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1662 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1663 | }; |
1664 | ||
431b2a20 JR |
1665 | /* |
1666 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1667 | */ | |
6631ee9d JR |
1668 | int __init amd_iommu_init_dma_ops(void) |
1669 | { | |
1670 | struct amd_iommu *iommu; | |
1671 | int order = amd_iommu_aperture_order; | |
1672 | int ret; | |
1673 | ||
431b2a20 JR |
1674 | /* |
1675 | * first allocate a default protection domain for every IOMMU we | |
1676 | * found in the system. Devices not assigned to any other | |
1677 | * protection domain will be assigned to the default one. | |
1678 | */ | |
6631ee9d JR |
1679 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1680 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1681 | if (iommu->default_dom == NULL) | |
1682 | return -ENOMEM; | |
e2dc14a2 | 1683 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1684 | ret = iommu_init_unity_mappings(iommu); |
1685 | if (ret) | |
1686 | goto free_domains; | |
1687 | } | |
1688 | ||
431b2a20 JR |
1689 | /* |
1690 | * If device isolation is enabled, pre-allocate the protection | |
1691 | * domains for each device. | |
1692 | */ | |
6631ee9d JR |
1693 | if (amd_iommu_isolate) |
1694 | prealloc_protection_domains(); | |
1695 | ||
1696 | iommu_detected = 1; | |
1697 | force_iommu = 1; | |
1698 | bad_dma_address = 0; | |
92af4e29 | 1699 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1700 | gart_iommu_aperture_disabled = 1; |
1701 | gart_iommu_aperture = 0; | |
92af4e29 | 1702 | #endif |
6631ee9d | 1703 | |
431b2a20 | 1704 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1705 | dma_ops = &amd_iommu_dma_ops; |
1706 | ||
26961efe | 1707 | register_iommu(&amd_iommu_ops); |
26961efe | 1708 | |
e275a2a0 JR |
1709 | bus_register_notifier(&pci_bus_type, &device_nb); |
1710 | ||
7f26508b JR |
1711 | amd_iommu_stats_init(); |
1712 | ||
6631ee9d JR |
1713 | return 0; |
1714 | ||
1715 | free_domains: | |
1716 | ||
1717 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1718 | if (iommu->default_dom) | |
1719 | dma_ops_domain_free(iommu->default_dom); | |
1720 | } | |
1721 | ||
1722 | return ret; | |
1723 | } | |
6d98cd80 JR |
1724 | |
1725 | /***************************************************************************** | |
1726 | * | |
1727 | * The following functions belong to the exported interface of AMD IOMMU | |
1728 | * | |
1729 | * This interface allows access to lower level functions of the IOMMU | |
1730 | * like protection domain handling and assignement of devices to domains | |
1731 | * which is not possible with the dma_ops interface. | |
1732 | * | |
1733 | *****************************************************************************/ | |
1734 | ||
6d98cd80 JR |
1735 | static void cleanup_domain(struct protection_domain *domain) |
1736 | { | |
1737 | unsigned long flags; | |
1738 | u16 devid; | |
1739 | ||
1740 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1741 | ||
1742 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1743 | if (amd_iommu_pd_table[devid] == domain) | |
1744 | __detach_device(domain, devid); | |
1745 | ||
1746 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1747 | } | |
1748 | ||
c156e347 JR |
1749 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1750 | { | |
1751 | struct protection_domain *domain; | |
1752 | ||
1753 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1754 | if (!domain) | |
1755 | return -ENOMEM; | |
1756 | ||
1757 | spin_lock_init(&domain->lock); | |
1758 | domain->mode = PAGE_MODE_3_LEVEL; | |
1759 | domain->id = domain_id_alloc(); | |
1760 | if (!domain->id) | |
1761 | goto out_free; | |
1762 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1763 | if (!domain->pt_root) | |
1764 | goto out_free; | |
1765 | ||
1766 | dom->priv = domain; | |
1767 | ||
1768 | return 0; | |
1769 | ||
1770 | out_free: | |
1771 | kfree(domain); | |
1772 | ||
1773 | return -ENOMEM; | |
1774 | } | |
1775 | ||
98383fc3 JR |
1776 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1777 | { | |
1778 | struct protection_domain *domain = dom->priv; | |
1779 | ||
1780 | if (!domain) | |
1781 | return; | |
1782 | ||
1783 | if (domain->dev_cnt > 0) | |
1784 | cleanup_domain(domain); | |
1785 | ||
1786 | BUG_ON(domain->dev_cnt != 0); | |
1787 | ||
1788 | free_pagetable(domain); | |
1789 | ||
1790 | domain_id_free(domain->id); | |
1791 | ||
1792 | kfree(domain); | |
1793 | ||
1794 | dom->priv = NULL; | |
1795 | } | |
1796 | ||
684f2888 JR |
1797 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1798 | struct device *dev) | |
1799 | { | |
1800 | struct protection_domain *domain = dom->priv; | |
1801 | struct amd_iommu *iommu; | |
1802 | struct pci_dev *pdev; | |
1803 | u16 devid; | |
1804 | ||
1805 | if (dev->bus != &pci_bus_type) | |
1806 | return; | |
1807 | ||
1808 | pdev = to_pci_dev(dev); | |
1809 | ||
1810 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1811 | ||
1812 | if (devid > 0) | |
1813 | detach_device(domain, devid); | |
1814 | ||
1815 | iommu = amd_iommu_rlookup_table[devid]; | |
1816 | if (!iommu) | |
1817 | return; | |
1818 | ||
1819 | iommu_queue_inv_dev_entry(iommu, devid); | |
1820 | iommu_completion_wait(iommu); | |
1821 | } | |
1822 | ||
01106066 JR |
1823 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1824 | struct device *dev) | |
1825 | { | |
1826 | struct protection_domain *domain = dom->priv; | |
1827 | struct protection_domain *old_domain; | |
1828 | struct amd_iommu *iommu; | |
1829 | struct pci_dev *pdev; | |
1830 | u16 devid; | |
1831 | ||
1832 | if (dev->bus != &pci_bus_type) | |
1833 | return -EINVAL; | |
1834 | ||
1835 | pdev = to_pci_dev(dev); | |
1836 | ||
1837 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1838 | ||
1839 | if (devid >= amd_iommu_last_bdf || | |
1840 | devid != amd_iommu_alias_table[devid]) | |
1841 | return -EINVAL; | |
1842 | ||
1843 | iommu = amd_iommu_rlookup_table[devid]; | |
1844 | if (!iommu) | |
1845 | return -EINVAL; | |
1846 | ||
1847 | old_domain = domain_for_device(devid); | |
1848 | if (old_domain) | |
1849 | return -EBUSY; | |
1850 | ||
1851 | attach_device(iommu, domain, devid); | |
1852 | ||
1853 | iommu_completion_wait(iommu); | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | ||
c6229ca6 JR |
1858 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1859 | unsigned long iova, phys_addr_t paddr, | |
1860 | size_t size, int iommu_prot) | |
1861 | { | |
1862 | struct protection_domain *domain = dom->priv; | |
1863 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1864 | int prot = 0; | |
1865 | int ret; | |
1866 | ||
1867 | if (iommu_prot & IOMMU_READ) | |
1868 | prot |= IOMMU_PROT_IR; | |
1869 | if (iommu_prot & IOMMU_WRITE) | |
1870 | prot |= IOMMU_PROT_IW; | |
1871 | ||
1872 | iova &= PAGE_MASK; | |
1873 | paddr &= PAGE_MASK; | |
1874 | ||
1875 | for (i = 0; i < npages; ++i) { | |
1876 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1877 | if (ret) | |
1878 | return ret; | |
1879 | ||
1880 | iova += PAGE_SIZE; | |
1881 | paddr += PAGE_SIZE; | |
1882 | } | |
1883 | ||
1884 | return 0; | |
1885 | } | |
1886 | ||
eb74ff6c JR |
1887 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1888 | unsigned long iova, size_t size) | |
1889 | { | |
1890 | ||
1891 | struct protection_domain *domain = dom->priv; | |
1892 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1893 | ||
1894 | iova &= PAGE_MASK; | |
1895 | ||
1896 | for (i = 0; i < npages; ++i) { | |
1897 | iommu_unmap_page(domain, iova); | |
1898 | iova += PAGE_SIZE; | |
1899 | } | |
1900 | ||
1901 | iommu_flush_domain(domain->id); | |
1902 | } | |
1903 | ||
645c4c8d JR |
1904 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1905 | unsigned long iova) | |
1906 | { | |
1907 | struct protection_domain *domain = dom->priv; | |
1908 | unsigned long offset = iova & ~PAGE_MASK; | |
1909 | phys_addr_t paddr; | |
1910 | u64 *pte; | |
1911 | ||
1912 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1913 | ||
1914 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1915 | return 0; | |
1916 | ||
1917 | pte = IOMMU_PTE_PAGE(*pte); | |
1918 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1919 | ||
1920 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1921 | return 0; | |
1922 | ||
1923 | pte = IOMMU_PTE_PAGE(*pte); | |
1924 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1925 | ||
1926 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1927 | return 0; | |
1928 | ||
1929 | paddr = *pte & IOMMU_PAGE_MASK; | |
1930 | paddr |= offset; | |
1931 | ||
1932 | return paddr; | |
1933 | } | |
1934 | ||
dbb9fd86 SY |
1935 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
1936 | unsigned long cap) | |
1937 | { | |
1938 | return 0; | |
1939 | } | |
1940 | ||
26961efe JR |
1941 | static struct iommu_ops amd_iommu_ops = { |
1942 | .domain_init = amd_iommu_domain_init, | |
1943 | .domain_destroy = amd_iommu_domain_destroy, | |
1944 | .attach_dev = amd_iommu_attach_device, | |
1945 | .detach_dev = amd_iommu_detach_device, | |
1946 | .map = amd_iommu_map_range, | |
1947 | .unmap = amd_iommu_unmap_range, | |
1948 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 1949 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
1950 | }; |
1951 |