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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 JR |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/iommu-helper.h> | |
c156e347 JR |
26 | #ifdef CONFIG_IOMMU_API |
27 | #include <linux/iommu.h> | |
28 | #endif | |
b6c02715 | 29 | #include <asm/proto.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
26961efe JR |
45 | #ifdef CONFIG_IOMMU_API |
46 | static struct iommu_ops amd_iommu_ops; | |
47 | #endif | |
48 | ||
431b2a20 JR |
49 | /* |
50 | * general struct to manage commands send to an IOMMU | |
51 | */ | |
d6449536 | 52 | struct iommu_cmd { |
b6c02715 JR |
53 | u32 data[4]; |
54 | }; | |
55 | ||
bd0e5211 JR |
56 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
57 | struct unity_map_entry *e); | |
e275a2a0 JR |
58 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
59 | ||
bd0e5211 | 60 | |
7f26508b JR |
61 | #ifdef CONFIG_AMD_IOMMU_STATS |
62 | ||
63 | /* | |
64 | * Initialization code for statistics collection | |
65 | */ | |
66 | ||
da49f6df | 67 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 68 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 69 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 70 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 71 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 72 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
da49f6df | 73 | |
7f26508b JR |
74 | static struct dentry *stats_dir; |
75 | static struct dentry *de_isolate; | |
76 | static struct dentry *de_fflush; | |
77 | ||
78 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
79 | { | |
80 | if (stats_dir == NULL) | |
81 | return; | |
82 | ||
83 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
84 | &cnt->value); | |
85 | } | |
86 | ||
87 | static void amd_iommu_stats_init(void) | |
88 | { | |
89 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
90 | if (stats_dir == NULL) | |
91 | return; | |
92 | ||
93 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
94 | (u32 *)&amd_iommu_isolate); | |
95 | ||
96 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
97 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
98 | |
99 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 100 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 101 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 102 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 103 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 104 | amd_iommu_stats_add(&cnt_alloc_coherent); |
7f26508b JR |
105 | } |
106 | ||
107 | #endif | |
108 | ||
431b2a20 | 109 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
110 | static int iommu_has_npcache(struct amd_iommu *iommu) |
111 | { | |
ae9b9403 | 112 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
113 | } |
114 | ||
a80dc3e0 JR |
115 | /**************************************************************************** |
116 | * | |
117 | * Interrupt handling functions | |
118 | * | |
119 | ****************************************************************************/ | |
120 | ||
90008ee4 JR |
121 | static void iommu_print_event(void *__evt) |
122 | { | |
123 | u32 *event = __evt; | |
124 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
125 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
126 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
127 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
128 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
129 | ||
130 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
131 | ||
132 | switch (type) { | |
133 | case EVENT_TYPE_ILL_DEV: | |
134 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
135 | "address=0x%016llx flags=0x%04x]\n", | |
136 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
137 | address, flags); | |
138 | break; | |
139 | case EVENT_TYPE_IO_FAULT: | |
140 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
141 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
142 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
143 | domid, address, flags); | |
144 | break; | |
145 | case EVENT_TYPE_DEV_TAB_ERR: | |
146 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
147 | "address=0x%016llx flags=0x%04x]\n", | |
148 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
149 | address, flags); | |
150 | break; | |
151 | case EVENT_TYPE_PAGE_TAB_ERR: | |
152 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
153 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
154 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
155 | domid, address, flags); | |
156 | break; | |
157 | case EVENT_TYPE_ILL_CMD: | |
158 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
159 | break; | |
160 | case EVENT_TYPE_CMD_HARD_ERR: | |
161 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
162 | "flags=0x%04x]\n", address, flags); | |
163 | break; | |
164 | case EVENT_TYPE_IOTLB_INV_TO: | |
165 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
166 | "address=0x%016llx]\n", | |
167 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
168 | address); | |
169 | break; | |
170 | case EVENT_TYPE_INV_DEV_REQ: | |
171 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
172 | "address=0x%016llx flags=0x%04x]\n", | |
173 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
174 | address, flags); | |
175 | break; | |
176 | default: | |
177 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
178 | } | |
179 | } | |
180 | ||
181 | static void iommu_poll_events(struct amd_iommu *iommu) | |
182 | { | |
183 | u32 head, tail; | |
184 | unsigned long flags; | |
185 | ||
186 | spin_lock_irqsave(&iommu->lock, flags); | |
187 | ||
188 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
189 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
190 | ||
191 | while (head != tail) { | |
192 | iommu_print_event(iommu->evt_buf + head); | |
193 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
194 | } | |
195 | ||
196 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
197 | ||
198 | spin_unlock_irqrestore(&iommu->lock, flags); | |
199 | } | |
200 | ||
a80dc3e0 JR |
201 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
202 | { | |
90008ee4 JR |
203 | struct amd_iommu *iommu; |
204 | ||
205 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
206 | iommu_poll_events(iommu); | |
207 | ||
208 | return IRQ_HANDLED; | |
a80dc3e0 JR |
209 | } |
210 | ||
431b2a20 JR |
211 | /**************************************************************************** |
212 | * | |
213 | * IOMMU command queuing functions | |
214 | * | |
215 | ****************************************************************************/ | |
216 | ||
217 | /* | |
218 | * Writes the command to the IOMMUs command buffer and informs the | |
219 | * hardware about the new command. Must be called with iommu->lock held. | |
220 | */ | |
d6449536 | 221 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
222 | { |
223 | u32 tail, head; | |
224 | u8 *target; | |
225 | ||
226 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 227 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
228 | memcpy_toio(target, cmd, sizeof(*cmd)); |
229 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
230 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
231 | if (tail == head) | |
232 | return -ENOMEM; | |
233 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
431b2a20 JR |
238 | /* |
239 | * General queuing function for commands. Takes iommu->lock and calls | |
240 | * __iommu_queue_command(). | |
241 | */ | |
d6449536 | 242 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
243 | { |
244 | unsigned long flags; | |
245 | int ret; | |
246 | ||
247 | spin_lock_irqsave(&iommu->lock, flags); | |
248 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 249 | if (!ret) |
0cfd7aa9 | 250 | iommu->need_sync = true; |
a19ae1ec JR |
251 | spin_unlock_irqrestore(&iommu->lock, flags); |
252 | ||
253 | return ret; | |
254 | } | |
255 | ||
8d201968 JR |
256 | /* |
257 | * This function waits until an IOMMU has completed a completion | |
258 | * wait command | |
259 | */ | |
260 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
261 | { | |
262 | int ready = 0; | |
263 | unsigned status = 0; | |
264 | unsigned long i = 0; | |
265 | ||
da49f6df JR |
266 | INC_STATS_COUNTER(compl_wait); |
267 | ||
8d201968 JR |
268 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
269 | ++i; | |
270 | /* wait for the bit to become one */ | |
271 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
272 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
273 | } | |
274 | ||
275 | /* set bit back to zero */ | |
276 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
277 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
278 | ||
279 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
280 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
281 | } | |
282 | ||
283 | /* | |
284 | * This function queues a completion wait command into the command | |
285 | * buffer of an IOMMU | |
286 | */ | |
287 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
288 | { | |
289 | struct iommu_cmd cmd; | |
290 | ||
291 | memset(&cmd, 0, sizeof(cmd)); | |
292 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
293 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
294 | ||
295 | return __iommu_queue_command(iommu, &cmd); | |
296 | } | |
297 | ||
431b2a20 JR |
298 | /* |
299 | * This function is called whenever we need to ensure that the IOMMU has | |
300 | * completed execution of all commands we sent. It sends a | |
301 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
302 | * us about that by writing a value to a physical address we pass with | |
303 | * the command. | |
304 | */ | |
a19ae1ec JR |
305 | static int iommu_completion_wait(struct amd_iommu *iommu) |
306 | { | |
8d201968 JR |
307 | int ret = 0; |
308 | unsigned long flags; | |
a19ae1ec | 309 | |
7e4f88da JR |
310 | spin_lock_irqsave(&iommu->lock, flags); |
311 | ||
09ee17eb JR |
312 | if (!iommu->need_sync) |
313 | goto out; | |
314 | ||
8d201968 | 315 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 316 | |
0cfd7aa9 | 317 | iommu->need_sync = false; |
a19ae1ec JR |
318 | |
319 | if (ret) | |
7e4f88da | 320 | goto out; |
a19ae1ec | 321 | |
8d201968 | 322 | __iommu_wait_for_completion(iommu); |
84df8175 | 323 | |
7e4f88da JR |
324 | out: |
325 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
431b2a20 JR |
330 | /* |
331 | * Command send function for invalidating a device table entry | |
332 | */ | |
a19ae1ec JR |
333 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
334 | { | |
d6449536 | 335 | struct iommu_cmd cmd; |
ee2fa743 | 336 | int ret; |
a19ae1ec JR |
337 | |
338 | BUG_ON(iommu == NULL); | |
339 | ||
340 | memset(&cmd, 0, sizeof(cmd)); | |
341 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
342 | cmd.data[0] = devid; | |
343 | ||
ee2fa743 JR |
344 | ret = iommu_queue_command(iommu, &cmd); |
345 | ||
ee2fa743 | 346 | return ret; |
a19ae1ec JR |
347 | } |
348 | ||
237b6f33 JR |
349 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
350 | u16 domid, int pde, int s) | |
351 | { | |
352 | memset(cmd, 0, sizeof(*cmd)); | |
353 | address &= PAGE_MASK; | |
354 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
355 | cmd->data[1] |= domid; | |
356 | cmd->data[2] = lower_32_bits(address); | |
357 | cmd->data[3] = upper_32_bits(address); | |
358 | if (s) /* size bit - we flush more than one 4kb page */ | |
359 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
360 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
361 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
362 | } | |
363 | ||
431b2a20 JR |
364 | /* |
365 | * Generic command send function for invalidaing TLB entries | |
366 | */ | |
a19ae1ec JR |
367 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
368 | u64 address, u16 domid, int pde, int s) | |
369 | { | |
d6449536 | 370 | struct iommu_cmd cmd; |
ee2fa743 | 371 | int ret; |
a19ae1ec | 372 | |
237b6f33 | 373 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 374 | |
ee2fa743 JR |
375 | ret = iommu_queue_command(iommu, &cmd); |
376 | ||
ee2fa743 | 377 | return ret; |
a19ae1ec JR |
378 | } |
379 | ||
431b2a20 JR |
380 | /* |
381 | * TLB invalidation function which is called from the mapping functions. | |
382 | * It invalidates a single PTE if the range to flush is within a single | |
383 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
384 | */ | |
a19ae1ec JR |
385 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
386 | u64 address, size_t size) | |
387 | { | |
999ba417 | 388 | int s = 0; |
e3c449f5 | 389 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
390 | |
391 | address &= PAGE_MASK; | |
392 | ||
999ba417 JR |
393 | if (pages > 1) { |
394 | /* | |
395 | * If we have to flush more than one page, flush all | |
396 | * TLB entries for this domain | |
397 | */ | |
398 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
399 | s = 1; | |
a19ae1ec JR |
400 | } |
401 | ||
999ba417 JR |
402 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
403 | ||
a19ae1ec JR |
404 | return 0; |
405 | } | |
b6c02715 | 406 | |
1c655773 JR |
407 | /* Flush the whole IO/TLB for a given protection domain */ |
408 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
409 | { | |
410 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
411 | ||
412 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
413 | } | |
414 | ||
43f49609 JR |
415 | #ifdef CONFIG_IOMMU_API |
416 | /* | |
417 | * This function is used to flush the IO/TLB for a given protection domain | |
418 | * on every IOMMU in the system | |
419 | */ | |
420 | static void iommu_flush_domain(u16 domid) | |
421 | { | |
422 | unsigned long flags; | |
423 | struct amd_iommu *iommu; | |
424 | struct iommu_cmd cmd; | |
425 | ||
426 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
427 | domid, 1, 1); | |
428 | ||
429 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
430 | spin_lock_irqsave(&iommu->lock, flags); | |
431 | __iommu_queue_command(iommu, &cmd); | |
432 | __iommu_completion_wait(iommu); | |
433 | __iommu_wait_for_completion(iommu); | |
434 | spin_unlock_irqrestore(&iommu->lock, flags); | |
435 | } | |
436 | } | |
437 | #endif | |
438 | ||
431b2a20 JR |
439 | /**************************************************************************** |
440 | * | |
441 | * The functions below are used the create the page table mappings for | |
442 | * unity mapped regions. | |
443 | * | |
444 | ****************************************************************************/ | |
445 | ||
446 | /* | |
447 | * Generic mapping functions. It maps a physical address into a DMA | |
448 | * address space. It allocates the page table pages if necessary. | |
449 | * In the future it can be extended to a generic mapping function | |
450 | * supporting all features of AMD IOMMU page tables like level skipping | |
451 | * and full 64 bit address spaces. | |
452 | */ | |
38e817fe JR |
453 | static int iommu_map_page(struct protection_domain *dom, |
454 | unsigned long bus_addr, | |
455 | unsigned long phys_addr, | |
456 | int prot) | |
bd0e5211 JR |
457 | { |
458 | u64 __pte, *pte, *page; | |
459 | ||
460 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 461 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
462 | |
463 | /* only support 512GB address spaces for now */ | |
464 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
465 | return -EINVAL; | |
466 | ||
467 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
468 | ||
469 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
470 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
471 | if (!page) | |
472 | return -ENOMEM; | |
473 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
474 | } | |
475 | ||
476 | pte = IOMMU_PTE_PAGE(*pte); | |
477 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
478 | ||
479 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
480 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
481 | if (!page) | |
482 | return -ENOMEM; | |
483 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
484 | } | |
485 | ||
486 | pte = IOMMU_PTE_PAGE(*pte); | |
487 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
488 | ||
489 | if (IOMMU_PTE_PRESENT(*pte)) | |
490 | return -EBUSY; | |
491 | ||
492 | __pte = phys_addr | IOMMU_PTE_P; | |
493 | if (prot & IOMMU_PROT_IR) | |
494 | __pte |= IOMMU_PTE_IR; | |
495 | if (prot & IOMMU_PROT_IW) | |
496 | __pte |= IOMMU_PTE_IW; | |
497 | ||
498 | *pte = __pte; | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
eb74ff6c JR |
503 | #ifdef CONFIG_IOMMU_API |
504 | static void iommu_unmap_page(struct protection_domain *dom, | |
505 | unsigned long bus_addr) | |
506 | { | |
507 | u64 *pte; | |
508 | ||
509 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
510 | ||
511 | if (!IOMMU_PTE_PRESENT(*pte)) | |
512 | return; | |
513 | ||
514 | pte = IOMMU_PTE_PAGE(*pte); | |
515 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
516 | ||
517 | if (!IOMMU_PTE_PRESENT(*pte)) | |
518 | return; | |
519 | ||
520 | pte = IOMMU_PTE_PAGE(*pte); | |
521 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
522 | ||
523 | *pte = 0; | |
524 | } | |
525 | #endif | |
526 | ||
431b2a20 JR |
527 | /* |
528 | * This function checks if a specific unity mapping entry is needed for | |
529 | * this specific IOMMU. | |
530 | */ | |
bd0e5211 JR |
531 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
532 | struct unity_map_entry *entry) | |
533 | { | |
534 | u16 bdf, i; | |
535 | ||
536 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
537 | bdf = amd_iommu_alias_table[i]; | |
538 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
539 | return 1; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
431b2a20 JR |
545 | /* |
546 | * Init the unity mappings for a specific IOMMU in the system | |
547 | * | |
548 | * Basically iterates over all unity mapping entries and applies them to | |
549 | * the default domain DMA of that IOMMU if necessary. | |
550 | */ | |
bd0e5211 JR |
551 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
552 | { | |
553 | struct unity_map_entry *entry; | |
554 | int ret; | |
555 | ||
556 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
557 | if (!iommu_for_unity_map(iommu, entry)) | |
558 | continue; | |
559 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
560 | if (ret) | |
561 | return ret; | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
431b2a20 JR |
567 | /* |
568 | * This function actually applies the mapping to the page table of the | |
569 | * dma_ops domain. | |
570 | */ | |
bd0e5211 JR |
571 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
572 | struct unity_map_entry *e) | |
573 | { | |
574 | u64 addr; | |
575 | int ret; | |
576 | ||
577 | for (addr = e->address_start; addr < e->address_end; | |
578 | addr += PAGE_SIZE) { | |
38e817fe | 579 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
580 | if (ret) |
581 | return ret; | |
582 | /* | |
583 | * if unity mapping is in aperture range mark the page | |
584 | * as allocated in the aperture | |
585 | */ | |
586 | if (addr < dma_dom->aperture_size) | |
587 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
588 | } | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
431b2a20 JR |
593 | /* |
594 | * Inits the unity mappings required for a specific device | |
595 | */ | |
bd0e5211 JR |
596 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
597 | u16 devid) | |
598 | { | |
599 | struct unity_map_entry *e; | |
600 | int ret; | |
601 | ||
602 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
603 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
604 | continue; | |
605 | ret = dma_ops_unity_map(dma_dom, e); | |
606 | if (ret) | |
607 | return ret; | |
608 | } | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
431b2a20 JR |
613 | /**************************************************************************** |
614 | * | |
615 | * The next functions belong to the address allocator for the dma_ops | |
616 | * interface functions. They work like the allocators in the other IOMMU | |
617 | * drivers. Its basically a bitmap which marks the allocated pages in | |
618 | * the aperture. Maybe it could be enhanced in the future to a more | |
619 | * efficient allocator. | |
620 | * | |
621 | ****************************************************************************/ | |
d3086444 | 622 | |
431b2a20 JR |
623 | /* |
624 | * The address allocator core function. | |
625 | * | |
626 | * called with domain->lock held | |
627 | */ | |
d3086444 JR |
628 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
629 | struct dma_ops_domain *dom, | |
6d4f343f | 630 | unsigned int pages, |
832a90c3 JR |
631 | unsigned long align_mask, |
632 | u64 dma_mask) | |
d3086444 | 633 | { |
40becd8d | 634 | unsigned long limit; |
d3086444 | 635 | unsigned long address; |
d3086444 JR |
636 | unsigned long boundary_size; |
637 | ||
638 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
639 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
640 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
641 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 642 | |
1c655773 | 643 | if (dom->next_bit >= limit) { |
d3086444 | 644 | dom->next_bit = 0; |
1c655773 JR |
645 | dom->need_flush = true; |
646 | } | |
d3086444 JR |
647 | |
648 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 649 | 0 , boundary_size, align_mask); |
1c655773 | 650 | if (address == -1) { |
d3086444 | 651 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 652 | 0, boundary_size, align_mask); |
1c655773 JR |
653 | dom->need_flush = true; |
654 | } | |
d3086444 JR |
655 | |
656 | if (likely(address != -1)) { | |
d3086444 JR |
657 | dom->next_bit = address + pages; |
658 | address <<= PAGE_SHIFT; | |
659 | } else | |
660 | address = bad_dma_address; | |
661 | ||
662 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
663 | ||
664 | return address; | |
665 | } | |
666 | ||
431b2a20 JR |
667 | /* |
668 | * The address free function. | |
669 | * | |
670 | * called with domain->lock held | |
671 | */ | |
d3086444 JR |
672 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
673 | unsigned long address, | |
674 | unsigned int pages) | |
675 | { | |
676 | address >>= PAGE_SHIFT; | |
677 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 678 | |
8501c45c | 679 | if (address >= dom->next_bit) |
80be308d | 680 | dom->need_flush = true; |
d3086444 JR |
681 | } |
682 | ||
431b2a20 JR |
683 | /**************************************************************************** |
684 | * | |
685 | * The next functions belong to the domain allocation. A domain is | |
686 | * allocated for every IOMMU as the default domain. If device isolation | |
687 | * is enabled, every device get its own domain. The most important thing | |
688 | * about domains is the page table mapping the DMA address space they | |
689 | * contain. | |
690 | * | |
691 | ****************************************************************************/ | |
692 | ||
ec487d1a JR |
693 | static u16 domain_id_alloc(void) |
694 | { | |
695 | unsigned long flags; | |
696 | int id; | |
697 | ||
698 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
699 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
700 | BUG_ON(id == 0); | |
701 | if (id > 0 && id < MAX_DOMAIN_ID) | |
702 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
703 | else | |
704 | id = 0; | |
705 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
706 | ||
707 | return id; | |
708 | } | |
709 | ||
a2acfb75 JR |
710 | #ifdef CONFIG_IOMMU_API |
711 | static void domain_id_free(int id) | |
712 | { | |
713 | unsigned long flags; | |
714 | ||
715 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
716 | if (id > 0 && id < MAX_DOMAIN_ID) | |
717 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
718 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
719 | } | |
720 | #endif | |
721 | ||
431b2a20 JR |
722 | /* |
723 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
724 | * ranges. | |
725 | */ | |
ec487d1a JR |
726 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
727 | unsigned long start_page, | |
728 | unsigned int pages) | |
729 | { | |
730 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
731 | ||
732 | if (start_page + pages > last_page) | |
733 | pages = last_page - start_page; | |
734 | ||
d26dbc5c | 735 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
736 | } |
737 | ||
86db2e5d | 738 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
739 | { |
740 | int i, j; | |
741 | u64 *p1, *p2, *p3; | |
742 | ||
86db2e5d | 743 | p1 = domain->pt_root; |
ec487d1a JR |
744 | |
745 | if (!p1) | |
746 | return; | |
747 | ||
748 | for (i = 0; i < 512; ++i) { | |
749 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
750 | continue; | |
751 | ||
752 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 753 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
754 | if (!IOMMU_PTE_PRESENT(p2[j])) |
755 | continue; | |
756 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
757 | free_page((unsigned long)p3); | |
758 | } | |
759 | ||
760 | free_page((unsigned long)p2); | |
761 | } | |
762 | ||
763 | free_page((unsigned long)p1); | |
86db2e5d JR |
764 | |
765 | domain->pt_root = NULL; | |
ec487d1a JR |
766 | } |
767 | ||
431b2a20 JR |
768 | /* |
769 | * Free a domain, only used if something went wrong in the | |
770 | * allocation path and we need to free an already allocated page table | |
771 | */ | |
ec487d1a JR |
772 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
773 | { | |
774 | if (!dom) | |
775 | return; | |
776 | ||
86db2e5d | 777 | free_pagetable(&dom->domain); |
ec487d1a JR |
778 | |
779 | kfree(dom->pte_pages); | |
780 | ||
781 | kfree(dom->bitmap); | |
782 | ||
783 | kfree(dom); | |
784 | } | |
785 | ||
431b2a20 JR |
786 | /* |
787 | * Allocates a new protection domain usable for the dma_ops functions. | |
788 | * It also intializes the page table and the address allocator data | |
789 | * structures required for the dma_ops interface | |
790 | */ | |
ec487d1a JR |
791 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
792 | unsigned order) | |
793 | { | |
794 | struct dma_ops_domain *dma_dom; | |
795 | unsigned i, num_pte_pages; | |
796 | u64 *l2_pde; | |
797 | u64 address; | |
798 | ||
799 | /* | |
800 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
801 | */ | |
802 | if ((order < 25) || (order > 30)) | |
803 | return NULL; | |
804 | ||
805 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
806 | if (!dma_dom) | |
807 | return NULL; | |
808 | ||
809 | spin_lock_init(&dma_dom->domain.lock); | |
810 | ||
811 | dma_dom->domain.id = domain_id_alloc(); | |
812 | if (dma_dom->domain.id == 0) | |
813 | goto free_dma_dom; | |
814 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
815 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 816 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
817 | dma_dom->domain.priv = dma_dom; |
818 | if (!dma_dom->domain.pt_root) | |
819 | goto free_dma_dom; | |
820 | dma_dom->aperture_size = (1ULL << order); | |
821 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
822 | GFP_KERNEL); | |
823 | if (!dma_dom->bitmap) | |
824 | goto free_dma_dom; | |
825 | /* | |
826 | * mark the first page as allocated so we never return 0 as | |
827 | * a valid dma-address. So we can use 0 as error value | |
828 | */ | |
829 | dma_dom->bitmap[0] = 1; | |
830 | dma_dom->next_bit = 0; | |
831 | ||
1c655773 | 832 | dma_dom->need_flush = false; |
bd60b735 | 833 | dma_dom->target_dev = 0xffff; |
1c655773 | 834 | |
431b2a20 | 835 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
836 | if (iommu->exclusion_start && |
837 | iommu->exclusion_start < dma_dom->aperture_size) { | |
838 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
839 | int pages = iommu_num_pages(iommu->exclusion_start, |
840 | iommu->exclusion_length, | |
841 | PAGE_SIZE); | |
ec487d1a JR |
842 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
843 | } | |
844 | ||
431b2a20 JR |
845 | /* |
846 | * At the last step, build the page tables so we don't need to | |
847 | * allocate page table pages in the dma_ops mapping/unmapping | |
848 | * path. | |
849 | */ | |
ec487d1a JR |
850 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
851 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
852 | GFP_KERNEL); | |
853 | if (!dma_dom->pte_pages) | |
854 | goto free_dma_dom; | |
855 | ||
856 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
857 | if (l2_pde == NULL) | |
858 | goto free_dma_dom; | |
859 | ||
860 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
861 | ||
862 | for (i = 0; i < num_pte_pages; ++i) { | |
863 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
864 | if (!dma_dom->pte_pages[i]) | |
865 | goto free_dma_dom; | |
866 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
867 | l2_pde[i] = IOMMU_L1_PDE(address); | |
868 | } | |
869 | ||
870 | return dma_dom; | |
871 | ||
872 | free_dma_dom: | |
873 | dma_ops_domain_free(dma_dom); | |
874 | ||
875 | return NULL; | |
876 | } | |
877 | ||
5b28df6f JR |
878 | /* |
879 | * little helper function to check whether a given protection domain is a | |
880 | * dma_ops domain | |
881 | */ | |
882 | static bool dma_ops_domain(struct protection_domain *domain) | |
883 | { | |
884 | return domain->flags & PD_DMA_OPS_MASK; | |
885 | } | |
886 | ||
431b2a20 JR |
887 | /* |
888 | * Find out the protection domain structure for a given PCI device. This | |
889 | * will give us the pointer to the page table root for example. | |
890 | */ | |
b20ac0d4 JR |
891 | static struct protection_domain *domain_for_device(u16 devid) |
892 | { | |
893 | struct protection_domain *dom; | |
894 | unsigned long flags; | |
895 | ||
896 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
897 | dom = amd_iommu_pd_table[devid]; | |
898 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
899 | ||
900 | return dom; | |
901 | } | |
902 | ||
431b2a20 JR |
903 | /* |
904 | * If a device is not yet associated with a domain, this function does | |
905 | * assigns it visible for the hardware | |
906 | */ | |
f1179dc0 JR |
907 | static void attach_device(struct amd_iommu *iommu, |
908 | struct protection_domain *domain, | |
909 | u16 devid) | |
b20ac0d4 JR |
910 | { |
911 | unsigned long flags; | |
b20ac0d4 JR |
912 | u64 pte_root = virt_to_phys(domain->pt_root); |
913 | ||
863c74eb JR |
914 | domain->dev_cnt += 1; |
915 | ||
38ddf41b JR |
916 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
917 | << DEV_ENTRY_MODE_SHIFT; | |
918 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
919 | |
920 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
921 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
922 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
923 | amd_iommu_dev_table[devid].data[2] = domain->id; |
924 | ||
925 | amd_iommu_pd_table[devid] = domain; | |
926 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
927 | ||
928 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
929 | } |
930 | ||
355bf553 JR |
931 | /* |
932 | * Removes a device from a protection domain (unlocked) | |
933 | */ | |
934 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
935 | { | |
936 | ||
937 | /* lock domain */ | |
938 | spin_lock(&domain->lock); | |
939 | ||
940 | /* remove domain from the lookup table */ | |
941 | amd_iommu_pd_table[devid] = NULL; | |
942 | ||
943 | /* remove entry from the device table seen by the hardware */ | |
944 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
945 | amd_iommu_dev_table[devid].data[1] = 0; | |
946 | amd_iommu_dev_table[devid].data[2] = 0; | |
947 | ||
948 | /* decrease reference counter */ | |
949 | domain->dev_cnt -= 1; | |
950 | ||
951 | /* ready */ | |
952 | spin_unlock(&domain->lock); | |
953 | } | |
954 | ||
955 | /* | |
956 | * Removes a device from a protection domain (with devtable_lock held) | |
957 | */ | |
958 | static void detach_device(struct protection_domain *domain, u16 devid) | |
959 | { | |
960 | unsigned long flags; | |
961 | ||
962 | /* lock device table */ | |
963 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
964 | __detach_device(domain, devid); | |
965 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
966 | } | |
e275a2a0 JR |
967 | |
968 | static int device_change_notifier(struct notifier_block *nb, | |
969 | unsigned long action, void *data) | |
970 | { | |
971 | struct device *dev = data; | |
972 | struct pci_dev *pdev = to_pci_dev(dev); | |
973 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
974 | struct protection_domain *domain; | |
975 | struct dma_ops_domain *dma_domain; | |
976 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
977 | int order = amd_iommu_aperture_order; |
978 | unsigned long flags; | |
e275a2a0 JR |
979 | |
980 | if (devid > amd_iommu_last_bdf) | |
981 | goto out; | |
982 | ||
983 | devid = amd_iommu_alias_table[devid]; | |
984 | ||
985 | iommu = amd_iommu_rlookup_table[devid]; | |
986 | if (iommu == NULL) | |
987 | goto out; | |
988 | ||
989 | domain = domain_for_device(devid); | |
990 | ||
991 | if (domain && !dma_ops_domain(domain)) | |
992 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
993 | "to a non-dma-ops domain\n", dev_name(dev)); | |
994 | ||
995 | switch (action) { | |
996 | case BUS_NOTIFY_BOUND_DRIVER: | |
997 | if (domain) | |
998 | goto out; | |
999 | dma_domain = find_protection_domain(devid); | |
1000 | if (!dma_domain) | |
1001 | dma_domain = iommu->default_dom; | |
1002 | attach_device(iommu, &dma_domain->domain, devid); | |
1003 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1004 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1005 | break; | |
1006 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1007 | if (!domain) | |
1008 | goto out; | |
1009 | detach_device(domain, devid); | |
1ac4cbbc JR |
1010 | break; |
1011 | case BUS_NOTIFY_ADD_DEVICE: | |
1012 | /* allocate a protection domain if a device is added */ | |
1013 | dma_domain = find_protection_domain(devid); | |
1014 | if (dma_domain) | |
1015 | goto out; | |
1016 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1017 | if (!dma_domain) | |
1018 | goto out; | |
1019 | dma_domain->target_dev = devid; | |
1020 | ||
1021 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1022 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1023 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1024 | ||
e275a2a0 JR |
1025 | break; |
1026 | default: | |
1027 | goto out; | |
1028 | } | |
1029 | ||
1030 | iommu_queue_inv_dev_entry(iommu, devid); | |
1031 | iommu_completion_wait(iommu); | |
1032 | ||
1033 | out: | |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | struct notifier_block device_nb = { | |
1038 | .notifier_call = device_change_notifier, | |
1039 | }; | |
355bf553 | 1040 | |
431b2a20 JR |
1041 | /***************************************************************************** |
1042 | * | |
1043 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1044 | * | |
1045 | *****************************************************************************/ | |
1046 | ||
dbcc112e JR |
1047 | /* |
1048 | * This function checks if the driver got a valid device from the caller to | |
1049 | * avoid dereferencing invalid pointers. | |
1050 | */ | |
1051 | static bool check_device(struct device *dev) | |
1052 | { | |
1053 | if (!dev || !dev->dma_mask) | |
1054 | return false; | |
1055 | ||
1056 | return true; | |
1057 | } | |
1058 | ||
bd60b735 JR |
1059 | /* |
1060 | * In this function the list of preallocated protection domains is traversed to | |
1061 | * find the domain for a specific device | |
1062 | */ | |
1063 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1064 | { | |
1065 | struct dma_ops_domain *entry, *ret = NULL; | |
1066 | unsigned long flags; | |
1067 | ||
1068 | if (list_empty(&iommu_pd_list)) | |
1069 | return NULL; | |
1070 | ||
1071 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1072 | ||
1073 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1074 | if (entry->target_dev == devid) { | |
1075 | ret = entry; | |
bd60b735 JR |
1076 | break; |
1077 | } | |
1078 | } | |
1079 | ||
1080 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1081 | ||
1082 | return ret; | |
1083 | } | |
1084 | ||
431b2a20 JR |
1085 | /* |
1086 | * In the dma_ops path we only have the struct device. This function | |
1087 | * finds the corresponding IOMMU, the protection domain and the | |
1088 | * requestor id for a given device. | |
1089 | * If the device is not yet associated with a domain this is also done | |
1090 | * in this function. | |
1091 | */ | |
b20ac0d4 JR |
1092 | static int get_device_resources(struct device *dev, |
1093 | struct amd_iommu **iommu, | |
1094 | struct protection_domain **domain, | |
1095 | u16 *bdf) | |
1096 | { | |
1097 | struct dma_ops_domain *dma_dom; | |
1098 | struct pci_dev *pcidev; | |
1099 | u16 _bdf; | |
1100 | ||
dbcc112e JR |
1101 | *iommu = NULL; |
1102 | *domain = NULL; | |
1103 | *bdf = 0xffff; | |
1104 | ||
1105 | if (dev->bus != &pci_bus_type) | |
1106 | return 0; | |
b20ac0d4 JR |
1107 | |
1108 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1109 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1110 | |
431b2a20 | 1111 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1112 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1113 | return 0; |
b20ac0d4 JR |
1114 | |
1115 | *bdf = amd_iommu_alias_table[_bdf]; | |
1116 | ||
1117 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1118 | if (*iommu == NULL) | |
1119 | return 0; | |
b20ac0d4 JR |
1120 | *domain = domain_for_device(*bdf); |
1121 | if (*domain == NULL) { | |
bd60b735 JR |
1122 | dma_dom = find_protection_domain(*bdf); |
1123 | if (!dma_dom) | |
1124 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1125 | *domain = &dma_dom->domain; |
f1179dc0 | 1126 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1127 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1128 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1129 | } |
1130 | ||
f91ba190 | 1131 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1132 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1133 | |
b20ac0d4 JR |
1134 | return 1; |
1135 | } | |
1136 | ||
431b2a20 JR |
1137 | /* |
1138 | * This is the generic map function. It maps one 4kb page at paddr to | |
1139 | * the given address in the DMA address space for the domain. | |
1140 | */ | |
cb76c322 JR |
1141 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1142 | struct dma_ops_domain *dom, | |
1143 | unsigned long address, | |
1144 | phys_addr_t paddr, | |
1145 | int direction) | |
1146 | { | |
1147 | u64 *pte, __pte; | |
1148 | ||
1149 | WARN_ON(address > dom->aperture_size); | |
1150 | ||
1151 | paddr &= PAGE_MASK; | |
1152 | ||
1153 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1154 | pte += IOMMU_PTE_L0_INDEX(address); | |
1155 | ||
1156 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1157 | ||
1158 | if (direction == DMA_TO_DEVICE) | |
1159 | __pte |= IOMMU_PTE_IR; | |
1160 | else if (direction == DMA_FROM_DEVICE) | |
1161 | __pte |= IOMMU_PTE_IW; | |
1162 | else if (direction == DMA_BIDIRECTIONAL) | |
1163 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1164 | ||
1165 | WARN_ON(*pte); | |
1166 | ||
1167 | *pte = __pte; | |
1168 | ||
1169 | return (dma_addr_t)address; | |
1170 | } | |
1171 | ||
431b2a20 JR |
1172 | /* |
1173 | * The generic unmapping function for on page in the DMA address space. | |
1174 | */ | |
cb76c322 JR |
1175 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1176 | struct dma_ops_domain *dom, | |
1177 | unsigned long address) | |
1178 | { | |
1179 | u64 *pte; | |
1180 | ||
1181 | if (address >= dom->aperture_size) | |
1182 | return; | |
1183 | ||
8ad909c4 | 1184 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1185 | |
1186 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1187 | pte += IOMMU_PTE_L0_INDEX(address); | |
1188 | ||
1189 | WARN_ON(!*pte); | |
1190 | ||
1191 | *pte = 0ULL; | |
1192 | } | |
1193 | ||
431b2a20 JR |
1194 | /* |
1195 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1196 | * contiguous memory region into DMA address space. It is used by all |
1197 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1198 | * Must be called with the domain lock held. |
1199 | */ | |
cb76c322 JR |
1200 | static dma_addr_t __map_single(struct device *dev, |
1201 | struct amd_iommu *iommu, | |
1202 | struct dma_ops_domain *dma_dom, | |
1203 | phys_addr_t paddr, | |
1204 | size_t size, | |
6d4f343f | 1205 | int dir, |
832a90c3 JR |
1206 | bool align, |
1207 | u64 dma_mask) | |
cb76c322 JR |
1208 | { |
1209 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1210 | dma_addr_t address, start; | |
1211 | unsigned int pages; | |
6d4f343f | 1212 | unsigned long align_mask = 0; |
cb76c322 JR |
1213 | int i; |
1214 | ||
e3c449f5 | 1215 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1216 | paddr &= PAGE_MASK; |
1217 | ||
6d4f343f JR |
1218 | if (align) |
1219 | align_mask = (1UL << get_order(size)) - 1; | |
1220 | ||
832a90c3 JR |
1221 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1222 | dma_mask); | |
cb76c322 JR |
1223 | if (unlikely(address == bad_dma_address)) |
1224 | goto out; | |
1225 | ||
1226 | start = address; | |
1227 | for (i = 0; i < pages; ++i) { | |
1228 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1229 | paddr += PAGE_SIZE; | |
1230 | start += PAGE_SIZE; | |
1231 | } | |
1232 | address += offset; | |
1233 | ||
afa9fdc2 | 1234 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1235 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1236 | dma_dom->need_flush = false; | |
1237 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1238 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1239 | ||
cb76c322 JR |
1240 | out: |
1241 | return address; | |
1242 | } | |
1243 | ||
431b2a20 JR |
1244 | /* |
1245 | * Does the reverse of the __map_single function. Must be called with | |
1246 | * the domain lock held too | |
1247 | */ | |
cb76c322 JR |
1248 | static void __unmap_single(struct amd_iommu *iommu, |
1249 | struct dma_ops_domain *dma_dom, | |
1250 | dma_addr_t dma_addr, | |
1251 | size_t size, | |
1252 | int dir) | |
1253 | { | |
1254 | dma_addr_t i, start; | |
1255 | unsigned int pages; | |
1256 | ||
b8d9905d JR |
1257 | if ((dma_addr == bad_dma_address) || |
1258 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1259 | return; |
1260 | ||
e3c449f5 | 1261 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1262 | dma_addr &= PAGE_MASK; |
1263 | start = dma_addr; | |
1264 | ||
1265 | for (i = 0; i < pages; ++i) { | |
1266 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1267 | start += PAGE_SIZE; | |
1268 | } | |
1269 | ||
1270 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 1271 | |
80be308d | 1272 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1273 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1274 | dma_dom->need_flush = false; |
1275 | } | |
cb76c322 JR |
1276 | } |
1277 | ||
431b2a20 JR |
1278 | /* |
1279 | * The exported map_single function for dma_ops. | |
1280 | */ | |
4da70b9e JR |
1281 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1282 | size_t size, int dir) | |
1283 | { | |
1284 | unsigned long flags; | |
1285 | struct amd_iommu *iommu; | |
1286 | struct protection_domain *domain; | |
1287 | u16 devid; | |
1288 | dma_addr_t addr; | |
832a90c3 | 1289 | u64 dma_mask; |
4da70b9e | 1290 | |
0f2a86f2 JR |
1291 | INC_STATS_COUNTER(cnt_map_single); |
1292 | ||
dbcc112e JR |
1293 | if (!check_device(dev)) |
1294 | return bad_dma_address; | |
1295 | ||
832a90c3 | 1296 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1297 | |
1298 | get_device_resources(dev, &iommu, &domain, &devid); | |
1299 | ||
1300 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1301 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1302 | return (dma_addr_t)paddr; |
1303 | ||
5b28df6f JR |
1304 | if (!dma_ops_domain(domain)) |
1305 | return bad_dma_address; | |
1306 | ||
4da70b9e | 1307 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1308 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1309 | dma_mask); | |
4da70b9e JR |
1310 | if (addr == bad_dma_address) |
1311 | goto out; | |
1312 | ||
09ee17eb | 1313 | iommu_completion_wait(iommu); |
4da70b9e JR |
1314 | |
1315 | out: | |
1316 | spin_unlock_irqrestore(&domain->lock, flags); | |
1317 | ||
1318 | return addr; | |
1319 | } | |
1320 | ||
431b2a20 JR |
1321 | /* |
1322 | * The exported unmap_single function for dma_ops. | |
1323 | */ | |
4da70b9e JR |
1324 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1325 | size_t size, int dir) | |
1326 | { | |
1327 | unsigned long flags; | |
1328 | struct amd_iommu *iommu; | |
1329 | struct protection_domain *domain; | |
1330 | u16 devid; | |
1331 | ||
146a6917 JR |
1332 | INC_STATS_COUNTER(cnt_unmap_single); |
1333 | ||
dbcc112e JR |
1334 | if (!check_device(dev) || |
1335 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1336 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1337 | return; |
1338 | ||
5b28df6f JR |
1339 | if (!dma_ops_domain(domain)) |
1340 | return; | |
1341 | ||
4da70b9e JR |
1342 | spin_lock_irqsave(&domain->lock, flags); |
1343 | ||
1344 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1345 | ||
09ee17eb | 1346 | iommu_completion_wait(iommu); |
4da70b9e JR |
1347 | |
1348 | spin_unlock_irqrestore(&domain->lock, flags); | |
1349 | } | |
1350 | ||
431b2a20 JR |
1351 | /* |
1352 | * This is a special map_sg function which is used if we should map a | |
1353 | * device which is not handled by an AMD IOMMU in the system. | |
1354 | */ | |
65b050ad JR |
1355 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1356 | int nelems, int dir) | |
1357 | { | |
1358 | struct scatterlist *s; | |
1359 | int i; | |
1360 | ||
1361 | for_each_sg(sglist, s, nelems, i) { | |
1362 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1363 | s->dma_length = s->length; | |
1364 | } | |
1365 | ||
1366 | return nelems; | |
1367 | } | |
1368 | ||
431b2a20 JR |
1369 | /* |
1370 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1371 | * lists). | |
1372 | */ | |
65b050ad JR |
1373 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1374 | int nelems, int dir) | |
1375 | { | |
1376 | unsigned long flags; | |
1377 | struct amd_iommu *iommu; | |
1378 | struct protection_domain *domain; | |
1379 | u16 devid; | |
1380 | int i; | |
1381 | struct scatterlist *s; | |
1382 | phys_addr_t paddr; | |
1383 | int mapped_elems = 0; | |
832a90c3 | 1384 | u64 dma_mask; |
65b050ad | 1385 | |
d03f067a JR |
1386 | INC_STATS_COUNTER(cnt_map_sg); |
1387 | ||
dbcc112e JR |
1388 | if (!check_device(dev)) |
1389 | return 0; | |
1390 | ||
832a90c3 | 1391 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1392 | |
1393 | get_device_resources(dev, &iommu, &domain, &devid); | |
1394 | ||
1395 | if (!iommu || !domain) | |
1396 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1397 | ||
5b28df6f JR |
1398 | if (!dma_ops_domain(domain)) |
1399 | return 0; | |
1400 | ||
65b050ad JR |
1401 | spin_lock_irqsave(&domain->lock, flags); |
1402 | ||
1403 | for_each_sg(sglist, s, nelems, i) { | |
1404 | paddr = sg_phys(s); | |
1405 | ||
1406 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1407 | paddr, s->length, dir, false, |
1408 | dma_mask); | |
65b050ad JR |
1409 | |
1410 | if (s->dma_address) { | |
1411 | s->dma_length = s->length; | |
1412 | mapped_elems++; | |
1413 | } else | |
1414 | goto unmap; | |
65b050ad JR |
1415 | } |
1416 | ||
09ee17eb | 1417 | iommu_completion_wait(iommu); |
65b050ad JR |
1418 | |
1419 | out: | |
1420 | spin_unlock_irqrestore(&domain->lock, flags); | |
1421 | ||
1422 | return mapped_elems; | |
1423 | unmap: | |
1424 | for_each_sg(sglist, s, mapped_elems, i) { | |
1425 | if (s->dma_address) | |
1426 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1427 | s->dma_length, dir); | |
1428 | s->dma_address = s->dma_length = 0; | |
1429 | } | |
1430 | ||
1431 | mapped_elems = 0; | |
1432 | ||
1433 | goto out; | |
1434 | } | |
1435 | ||
431b2a20 JR |
1436 | /* |
1437 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1438 | * lists). | |
1439 | */ | |
65b050ad JR |
1440 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1441 | int nelems, int dir) | |
1442 | { | |
1443 | unsigned long flags; | |
1444 | struct amd_iommu *iommu; | |
1445 | struct protection_domain *domain; | |
1446 | struct scatterlist *s; | |
1447 | u16 devid; | |
1448 | int i; | |
1449 | ||
55877a6b JR |
1450 | INC_STATS_COUNTER(cnt_unmap_sg); |
1451 | ||
dbcc112e JR |
1452 | if (!check_device(dev) || |
1453 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1454 | return; |
1455 | ||
5b28df6f JR |
1456 | if (!dma_ops_domain(domain)) |
1457 | return; | |
1458 | ||
65b050ad JR |
1459 | spin_lock_irqsave(&domain->lock, flags); |
1460 | ||
1461 | for_each_sg(sglist, s, nelems, i) { | |
1462 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1463 | s->dma_length, dir); | |
65b050ad JR |
1464 | s->dma_address = s->dma_length = 0; |
1465 | } | |
1466 | ||
09ee17eb | 1467 | iommu_completion_wait(iommu); |
65b050ad JR |
1468 | |
1469 | spin_unlock_irqrestore(&domain->lock, flags); | |
1470 | } | |
1471 | ||
431b2a20 JR |
1472 | /* |
1473 | * The exported alloc_coherent function for dma_ops. | |
1474 | */ | |
5d8b53cf JR |
1475 | static void *alloc_coherent(struct device *dev, size_t size, |
1476 | dma_addr_t *dma_addr, gfp_t flag) | |
1477 | { | |
1478 | unsigned long flags; | |
1479 | void *virt_addr; | |
1480 | struct amd_iommu *iommu; | |
1481 | struct protection_domain *domain; | |
1482 | u16 devid; | |
1483 | phys_addr_t paddr; | |
832a90c3 | 1484 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1485 | |
c8f0fb36 JR |
1486 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1487 | ||
dbcc112e JR |
1488 | if (!check_device(dev)) |
1489 | return NULL; | |
5d8b53cf | 1490 | |
13d9fead FT |
1491 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1492 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1493 | |
c97ac535 | 1494 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1495 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1496 | if (!virt_addr) | |
1497 | return 0; | |
1498 | ||
5d8b53cf JR |
1499 | paddr = virt_to_phys(virt_addr); |
1500 | ||
5d8b53cf JR |
1501 | if (!iommu || !domain) { |
1502 | *dma_addr = (dma_addr_t)paddr; | |
1503 | return virt_addr; | |
1504 | } | |
1505 | ||
5b28df6f JR |
1506 | if (!dma_ops_domain(domain)) |
1507 | goto out_free; | |
1508 | ||
832a90c3 JR |
1509 | if (!dma_mask) |
1510 | dma_mask = *dev->dma_mask; | |
1511 | ||
5d8b53cf JR |
1512 | spin_lock_irqsave(&domain->lock, flags); |
1513 | ||
1514 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1515 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1516 | |
5b28df6f JR |
1517 | if (*dma_addr == bad_dma_address) |
1518 | goto out_free; | |
5d8b53cf | 1519 | |
09ee17eb | 1520 | iommu_completion_wait(iommu); |
5d8b53cf | 1521 | |
5d8b53cf JR |
1522 | spin_unlock_irqrestore(&domain->lock, flags); |
1523 | ||
1524 | return virt_addr; | |
5b28df6f JR |
1525 | |
1526 | out_free: | |
1527 | ||
1528 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1529 | ||
1530 | return NULL; | |
5d8b53cf JR |
1531 | } |
1532 | ||
431b2a20 JR |
1533 | /* |
1534 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1535 | */ |
5d8b53cf JR |
1536 | static void free_coherent(struct device *dev, size_t size, |
1537 | void *virt_addr, dma_addr_t dma_addr) | |
1538 | { | |
1539 | unsigned long flags; | |
1540 | struct amd_iommu *iommu; | |
1541 | struct protection_domain *domain; | |
1542 | u16 devid; | |
1543 | ||
dbcc112e JR |
1544 | if (!check_device(dev)) |
1545 | return; | |
1546 | ||
5d8b53cf JR |
1547 | get_device_resources(dev, &iommu, &domain, &devid); |
1548 | ||
1549 | if (!iommu || !domain) | |
1550 | goto free_mem; | |
1551 | ||
5b28df6f JR |
1552 | if (!dma_ops_domain(domain)) |
1553 | goto free_mem; | |
1554 | ||
5d8b53cf JR |
1555 | spin_lock_irqsave(&domain->lock, flags); |
1556 | ||
1557 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1558 | |
09ee17eb | 1559 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1560 | |
1561 | spin_unlock_irqrestore(&domain->lock, flags); | |
1562 | ||
1563 | free_mem: | |
1564 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1565 | } | |
1566 | ||
b39ba6ad JR |
1567 | /* |
1568 | * This function is called by the DMA layer to find out if we can handle a | |
1569 | * particular device. It is part of the dma_ops. | |
1570 | */ | |
1571 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1572 | { | |
1573 | u16 bdf; | |
1574 | struct pci_dev *pcidev; | |
1575 | ||
1576 | /* No device or no PCI device */ | |
1577 | if (!dev || dev->bus != &pci_bus_type) | |
1578 | return 0; | |
1579 | ||
1580 | pcidev = to_pci_dev(dev); | |
1581 | ||
1582 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1583 | ||
1584 | /* Out of our scope? */ | |
1585 | if (bdf > amd_iommu_last_bdf) | |
1586 | return 0; | |
1587 | ||
1588 | return 1; | |
1589 | } | |
1590 | ||
c432f3df | 1591 | /* |
431b2a20 JR |
1592 | * The function for pre-allocating protection domains. |
1593 | * | |
c432f3df JR |
1594 | * If the driver core informs the DMA layer if a driver grabs a device |
1595 | * we don't need to preallocate the protection domains anymore. | |
1596 | * For now we have to. | |
1597 | */ | |
1598 | void prealloc_protection_domains(void) | |
1599 | { | |
1600 | struct pci_dev *dev = NULL; | |
1601 | struct dma_ops_domain *dma_dom; | |
1602 | struct amd_iommu *iommu; | |
1603 | int order = amd_iommu_aperture_order; | |
1604 | u16 devid; | |
1605 | ||
1606 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1607 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1608 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1609 | continue; |
1610 | devid = amd_iommu_alias_table[devid]; | |
1611 | if (domain_for_device(devid)) | |
1612 | continue; | |
1613 | iommu = amd_iommu_rlookup_table[devid]; | |
1614 | if (!iommu) | |
1615 | continue; | |
1616 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1617 | if (!dma_dom) | |
1618 | continue; | |
1619 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1620 | dma_dom->target_dev = devid; |
1621 | ||
1622 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1623 | } |
1624 | } | |
1625 | ||
6631ee9d JR |
1626 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1627 | .alloc_coherent = alloc_coherent, | |
1628 | .free_coherent = free_coherent, | |
1629 | .map_single = map_single, | |
1630 | .unmap_single = unmap_single, | |
1631 | .map_sg = map_sg, | |
1632 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1633 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1634 | }; |
1635 | ||
431b2a20 JR |
1636 | /* |
1637 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1638 | */ | |
6631ee9d JR |
1639 | int __init amd_iommu_init_dma_ops(void) |
1640 | { | |
1641 | struct amd_iommu *iommu; | |
1642 | int order = amd_iommu_aperture_order; | |
1643 | int ret; | |
1644 | ||
431b2a20 JR |
1645 | /* |
1646 | * first allocate a default protection domain for every IOMMU we | |
1647 | * found in the system. Devices not assigned to any other | |
1648 | * protection domain will be assigned to the default one. | |
1649 | */ | |
6631ee9d JR |
1650 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1651 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1652 | if (iommu->default_dom == NULL) | |
1653 | return -ENOMEM; | |
e2dc14a2 | 1654 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1655 | ret = iommu_init_unity_mappings(iommu); |
1656 | if (ret) | |
1657 | goto free_domains; | |
1658 | } | |
1659 | ||
431b2a20 JR |
1660 | /* |
1661 | * If device isolation is enabled, pre-allocate the protection | |
1662 | * domains for each device. | |
1663 | */ | |
6631ee9d JR |
1664 | if (amd_iommu_isolate) |
1665 | prealloc_protection_domains(); | |
1666 | ||
1667 | iommu_detected = 1; | |
1668 | force_iommu = 1; | |
1669 | bad_dma_address = 0; | |
92af4e29 | 1670 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1671 | gart_iommu_aperture_disabled = 1; |
1672 | gart_iommu_aperture = 0; | |
92af4e29 | 1673 | #endif |
6631ee9d | 1674 | |
431b2a20 | 1675 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1676 | dma_ops = &amd_iommu_dma_ops; |
1677 | ||
26961efe JR |
1678 | #ifdef CONFIG_IOMMU_API |
1679 | register_iommu(&amd_iommu_ops); | |
1680 | #endif | |
1681 | ||
e275a2a0 JR |
1682 | bus_register_notifier(&pci_bus_type, &device_nb); |
1683 | ||
7f26508b JR |
1684 | amd_iommu_stats_init(); |
1685 | ||
6631ee9d JR |
1686 | return 0; |
1687 | ||
1688 | free_domains: | |
1689 | ||
1690 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1691 | if (iommu->default_dom) | |
1692 | dma_ops_domain_free(iommu->default_dom); | |
1693 | } | |
1694 | ||
1695 | return ret; | |
1696 | } | |
6d98cd80 JR |
1697 | |
1698 | /***************************************************************************** | |
1699 | * | |
1700 | * The following functions belong to the exported interface of AMD IOMMU | |
1701 | * | |
1702 | * This interface allows access to lower level functions of the IOMMU | |
1703 | * like protection domain handling and assignement of devices to domains | |
1704 | * which is not possible with the dma_ops interface. | |
1705 | * | |
1706 | *****************************************************************************/ | |
1707 | ||
1708 | #ifdef CONFIG_IOMMU_API | |
1709 | ||
1710 | static void cleanup_domain(struct protection_domain *domain) | |
1711 | { | |
1712 | unsigned long flags; | |
1713 | u16 devid; | |
1714 | ||
1715 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1716 | ||
1717 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1718 | if (amd_iommu_pd_table[devid] == domain) | |
1719 | __detach_device(domain, devid); | |
1720 | ||
1721 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1722 | } | |
1723 | ||
c156e347 JR |
1724 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1725 | { | |
1726 | struct protection_domain *domain; | |
1727 | ||
1728 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1729 | if (!domain) | |
1730 | return -ENOMEM; | |
1731 | ||
1732 | spin_lock_init(&domain->lock); | |
1733 | domain->mode = PAGE_MODE_3_LEVEL; | |
1734 | domain->id = domain_id_alloc(); | |
1735 | if (!domain->id) | |
1736 | goto out_free; | |
1737 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1738 | if (!domain->pt_root) | |
1739 | goto out_free; | |
1740 | ||
1741 | dom->priv = domain; | |
1742 | ||
1743 | return 0; | |
1744 | ||
1745 | out_free: | |
1746 | kfree(domain); | |
1747 | ||
1748 | return -ENOMEM; | |
1749 | } | |
1750 | ||
98383fc3 JR |
1751 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1752 | { | |
1753 | struct protection_domain *domain = dom->priv; | |
1754 | ||
1755 | if (!domain) | |
1756 | return; | |
1757 | ||
1758 | if (domain->dev_cnt > 0) | |
1759 | cleanup_domain(domain); | |
1760 | ||
1761 | BUG_ON(domain->dev_cnt != 0); | |
1762 | ||
1763 | free_pagetable(domain); | |
1764 | ||
1765 | domain_id_free(domain->id); | |
1766 | ||
1767 | kfree(domain); | |
1768 | ||
1769 | dom->priv = NULL; | |
1770 | } | |
1771 | ||
684f2888 JR |
1772 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1773 | struct device *dev) | |
1774 | { | |
1775 | struct protection_domain *domain = dom->priv; | |
1776 | struct amd_iommu *iommu; | |
1777 | struct pci_dev *pdev; | |
1778 | u16 devid; | |
1779 | ||
1780 | if (dev->bus != &pci_bus_type) | |
1781 | return; | |
1782 | ||
1783 | pdev = to_pci_dev(dev); | |
1784 | ||
1785 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1786 | ||
1787 | if (devid > 0) | |
1788 | detach_device(domain, devid); | |
1789 | ||
1790 | iommu = amd_iommu_rlookup_table[devid]; | |
1791 | if (!iommu) | |
1792 | return; | |
1793 | ||
1794 | iommu_queue_inv_dev_entry(iommu, devid); | |
1795 | iommu_completion_wait(iommu); | |
1796 | } | |
1797 | ||
01106066 JR |
1798 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1799 | struct device *dev) | |
1800 | { | |
1801 | struct protection_domain *domain = dom->priv; | |
1802 | struct protection_domain *old_domain; | |
1803 | struct amd_iommu *iommu; | |
1804 | struct pci_dev *pdev; | |
1805 | u16 devid; | |
1806 | ||
1807 | if (dev->bus != &pci_bus_type) | |
1808 | return -EINVAL; | |
1809 | ||
1810 | pdev = to_pci_dev(dev); | |
1811 | ||
1812 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1813 | ||
1814 | if (devid >= amd_iommu_last_bdf || | |
1815 | devid != amd_iommu_alias_table[devid]) | |
1816 | return -EINVAL; | |
1817 | ||
1818 | iommu = amd_iommu_rlookup_table[devid]; | |
1819 | if (!iommu) | |
1820 | return -EINVAL; | |
1821 | ||
1822 | old_domain = domain_for_device(devid); | |
1823 | if (old_domain) | |
1824 | return -EBUSY; | |
1825 | ||
1826 | attach_device(iommu, domain, devid); | |
1827 | ||
1828 | iommu_completion_wait(iommu); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
1832 | ||
c6229ca6 JR |
1833 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1834 | unsigned long iova, phys_addr_t paddr, | |
1835 | size_t size, int iommu_prot) | |
1836 | { | |
1837 | struct protection_domain *domain = dom->priv; | |
1838 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1839 | int prot = 0; | |
1840 | int ret; | |
1841 | ||
1842 | if (iommu_prot & IOMMU_READ) | |
1843 | prot |= IOMMU_PROT_IR; | |
1844 | if (iommu_prot & IOMMU_WRITE) | |
1845 | prot |= IOMMU_PROT_IW; | |
1846 | ||
1847 | iova &= PAGE_MASK; | |
1848 | paddr &= PAGE_MASK; | |
1849 | ||
1850 | for (i = 0; i < npages; ++i) { | |
1851 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1852 | if (ret) | |
1853 | return ret; | |
1854 | ||
1855 | iova += PAGE_SIZE; | |
1856 | paddr += PAGE_SIZE; | |
1857 | } | |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
eb74ff6c JR |
1862 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1863 | unsigned long iova, size_t size) | |
1864 | { | |
1865 | ||
1866 | struct protection_domain *domain = dom->priv; | |
1867 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1868 | ||
1869 | iova &= PAGE_MASK; | |
1870 | ||
1871 | for (i = 0; i < npages; ++i) { | |
1872 | iommu_unmap_page(domain, iova); | |
1873 | iova += PAGE_SIZE; | |
1874 | } | |
1875 | ||
1876 | iommu_flush_domain(domain->id); | |
1877 | } | |
1878 | ||
645c4c8d JR |
1879 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1880 | unsigned long iova) | |
1881 | { | |
1882 | struct protection_domain *domain = dom->priv; | |
1883 | unsigned long offset = iova & ~PAGE_MASK; | |
1884 | phys_addr_t paddr; | |
1885 | u64 *pte; | |
1886 | ||
1887 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1888 | ||
1889 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1890 | return 0; | |
1891 | ||
1892 | pte = IOMMU_PTE_PAGE(*pte); | |
1893 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1894 | ||
1895 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1896 | return 0; | |
1897 | ||
1898 | pte = IOMMU_PTE_PAGE(*pte); | |
1899 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1900 | ||
1901 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1902 | return 0; | |
1903 | ||
1904 | paddr = *pte & IOMMU_PAGE_MASK; | |
1905 | paddr |= offset; | |
1906 | ||
1907 | return paddr; | |
1908 | } | |
1909 | ||
26961efe JR |
1910 | static struct iommu_ops amd_iommu_ops = { |
1911 | .domain_init = amd_iommu_domain_init, | |
1912 | .domain_destroy = amd_iommu_domain_destroy, | |
1913 | .attach_dev = amd_iommu_attach_device, | |
1914 | .detach_dev = amd_iommu_detach_device, | |
1915 | .map = amd_iommu_map_range, | |
1916 | .unmap = amd_iommu_unmap_range, | |
1917 | .iova_to_phys = amd_iommu_iova_to_phys, | |
1918 | }; | |
1919 | ||
6d98cd80 | 1920 | #endif |