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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/scatterlist.h> | |
24 | #include <linux/iommu-helper.h> | |
c156e347 JR |
25 | #ifdef CONFIG_IOMMU_API |
26 | #include <linux/iommu.h> | |
27 | #endif | |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 JR |
57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
58 | ||
bd0e5211 | 59 | |
431b2a20 | 60 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
61 | static int iommu_has_npcache(struct amd_iommu *iommu) |
62 | { | |
ae9b9403 | 63 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
64 | } |
65 | ||
a80dc3e0 JR |
66 | /**************************************************************************** |
67 | * | |
68 | * Interrupt handling functions | |
69 | * | |
70 | ****************************************************************************/ | |
71 | ||
90008ee4 JR |
72 | static void iommu_print_event(void *__evt) |
73 | { | |
74 | u32 *event = __evt; | |
75 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
76 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
77 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
78 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
79 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
80 | ||
81 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
82 | ||
83 | switch (type) { | |
84 | case EVENT_TYPE_ILL_DEV: | |
85 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
86 | "address=0x%016llx flags=0x%04x]\n", | |
87 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
88 | address, flags); | |
89 | break; | |
90 | case EVENT_TYPE_IO_FAULT: | |
91 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
92 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
93 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
94 | domid, address, flags); | |
95 | break; | |
96 | case EVENT_TYPE_DEV_TAB_ERR: | |
97 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
98 | "address=0x%016llx flags=0x%04x]\n", | |
99 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
100 | address, flags); | |
101 | break; | |
102 | case EVENT_TYPE_PAGE_TAB_ERR: | |
103 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
104 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
105 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
106 | domid, address, flags); | |
107 | break; | |
108 | case EVENT_TYPE_ILL_CMD: | |
109 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
110 | break; | |
111 | case EVENT_TYPE_CMD_HARD_ERR: | |
112 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
113 | "flags=0x%04x]\n", address, flags); | |
114 | break; | |
115 | case EVENT_TYPE_IOTLB_INV_TO: | |
116 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
117 | "address=0x%016llx]\n", | |
118 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
119 | address); | |
120 | break; | |
121 | case EVENT_TYPE_INV_DEV_REQ: | |
122 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
123 | "address=0x%016llx flags=0x%04x]\n", | |
124 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
125 | address, flags); | |
126 | break; | |
127 | default: | |
128 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
129 | } | |
130 | } | |
131 | ||
132 | static void iommu_poll_events(struct amd_iommu *iommu) | |
133 | { | |
134 | u32 head, tail; | |
135 | unsigned long flags; | |
136 | ||
137 | spin_lock_irqsave(&iommu->lock, flags); | |
138 | ||
139 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
140 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
141 | ||
142 | while (head != tail) { | |
143 | iommu_print_event(iommu->evt_buf + head); | |
144 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
145 | } | |
146 | ||
147 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
148 | ||
149 | spin_unlock_irqrestore(&iommu->lock, flags); | |
150 | } | |
151 | ||
a80dc3e0 JR |
152 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
153 | { | |
90008ee4 JR |
154 | struct amd_iommu *iommu; |
155 | ||
156 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
157 | iommu_poll_events(iommu); | |
158 | ||
159 | return IRQ_HANDLED; | |
a80dc3e0 JR |
160 | } |
161 | ||
431b2a20 JR |
162 | /**************************************************************************** |
163 | * | |
164 | * IOMMU command queuing functions | |
165 | * | |
166 | ****************************************************************************/ | |
167 | ||
168 | /* | |
169 | * Writes the command to the IOMMUs command buffer and informs the | |
170 | * hardware about the new command. Must be called with iommu->lock held. | |
171 | */ | |
d6449536 | 172 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
173 | { |
174 | u32 tail, head; | |
175 | u8 *target; | |
176 | ||
177 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 178 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
179 | memcpy_toio(target, cmd, sizeof(*cmd)); |
180 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
181 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
182 | if (tail == head) | |
183 | return -ENOMEM; | |
184 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
431b2a20 JR |
189 | /* |
190 | * General queuing function for commands. Takes iommu->lock and calls | |
191 | * __iommu_queue_command(). | |
192 | */ | |
d6449536 | 193 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
194 | { |
195 | unsigned long flags; | |
196 | int ret; | |
197 | ||
198 | spin_lock_irqsave(&iommu->lock, flags); | |
199 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb JR |
200 | if (!ret) |
201 | iommu->need_sync = 1; | |
a19ae1ec JR |
202 | spin_unlock_irqrestore(&iommu->lock, flags); |
203 | ||
204 | return ret; | |
205 | } | |
206 | ||
8d201968 JR |
207 | /* |
208 | * This function waits until an IOMMU has completed a completion | |
209 | * wait command | |
210 | */ | |
211 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
212 | { | |
213 | int ready = 0; | |
214 | unsigned status = 0; | |
215 | unsigned long i = 0; | |
216 | ||
217 | while (!ready && (i < EXIT_LOOP_COUNT)) { | |
218 | ++i; | |
219 | /* wait for the bit to become one */ | |
220 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
221 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
222 | } | |
223 | ||
224 | /* set bit back to zero */ | |
225 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
226 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
227 | ||
228 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
229 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
230 | } | |
231 | ||
232 | /* | |
233 | * This function queues a completion wait command into the command | |
234 | * buffer of an IOMMU | |
235 | */ | |
236 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
237 | { | |
238 | struct iommu_cmd cmd; | |
239 | ||
240 | memset(&cmd, 0, sizeof(cmd)); | |
241 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
242 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
243 | ||
244 | return __iommu_queue_command(iommu, &cmd); | |
245 | } | |
246 | ||
431b2a20 JR |
247 | /* |
248 | * This function is called whenever we need to ensure that the IOMMU has | |
249 | * completed execution of all commands we sent. It sends a | |
250 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
251 | * us about that by writing a value to a physical address we pass with | |
252 | * the command. | |
253 | */ | |
a19ae1ec JR |
254 | static int iommu_completion_wait(struct amd_iommu *iommu) |
255 | { | |
8d201968 JR |
256 | int ret = 0; |
257 | unsigned long flags; | |
a19ae1ec | 258 | |
7e4f88da JR |
259 | spin_lock_irqsave(&iommu->lock, flags); |
260 | ||
09ee17eb JR |
261 | if (!iommu->need_sync) |
262 | goto out; | |
263 | ||
8d201968 | 264 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 265 | |
8d201968 | 266 | iommu->need_sync = 0; |
a19ae1ec JR |
267 | |
268 | if (ret) | |
7e4f88da | 269 | goto out; |
a19ae1ec | 270 | |
8d201968 | 271 | __iommu_wait_for_completion(iommu); |
84df8175 | 272 | |
7e4f88da JR |
273 | out: |
274 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
275 | |
276 | return 0; | |
277 | } | |
278 | ||
431b2a20 JR |
279 | /* |
280 | * Command send function for invalidating a device table entry | |
281 | */ | |
a19ae1ec JR |
282 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
283 | { | |
d6449536 | 284 | struct iommu_cmd cmd; |
ee2fa743 | 285 | int ret; |
a19ae1ec JR |
286 | |
287 | BUG_ON(iommu == NULL); | |
288 | ||
289 | memset(&cmd, 0, sizeof(cmd)); | |
290 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
291 | cmd.data[0] = devid; | |
292 | ||
ee2fa743 JR |
293 | ret = iommu_queue_command(iommu, &cmd); |
294 | ||
ee2fa743 | 295 | return ret; |
a19ae1ec JR |
296 | } |
297 | ||
237b6f33 JR |
298 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
299 | u16 domid, int pde, int s) | |
300 | { | |
301 | memset(cmd, 0, sizeof(*cmd)); | |
302 | address &= PAGE_MASK; | |
303 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
304 | cmd->data[1] |= domid; | |
305 | cmd->data[2] = lower_32_bits(address); | |
306 | cmd->data[3] = upper_32_bits(address); | |
307 | if (s) /* size bit - we flush more than one 4kb page */ | |
308 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
309 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
310 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
311 | } | |
312 | ||
431b2a20 JR |
313 | /* |
314 | * Generic command send function for invalidaing TLB entries | |
315 | */ | |
a19ae1ec JR |
316 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
317 | u64 address, u16 domid, int pde, int s) | |
318 | { | |
d6449536 | 319 | struct iommu_cmd cmd; |
ee2fa743 | 320 | int ret; |
a19ae1ec | 321 | |
237b6f33 | 322 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 323 | |
ee2fa743 JR |
324 | ret = iommu_queue_command(iommu, &cmd); |
325 | ||
ee2fa743 | 326 | return ret; |
a19ae1ec JR |
327 | } |
328 | ||
431b2a20 JR |
329 | /* |
330 | * TLB invalidation function which is called from the mapping functions. | |
331 | * It invalidates a single PTE if the range to flush is within a single | |
332 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
333 | */ | |
a19ae1ec JR |
334 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
335 | u64 address, size_t size) | |
336 | { | |
999ba417 | 337 | int s = 0; |
e3c449f5 | 338 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
339 | |
340 | address &= PAGE_MASK; | |
341 | ||
999ba417 JR |
342 | if (pages > 1) { |
343 | /* | |
344 | * If we have to flush more than one page, flush all | |
345 | * TLB entries for this domain | |
346 | */ | |
347 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
348 | s = 1; | |
a19ae1ec JR |
349 | } |
350 | ||
999ba417 JR |
351 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
352 | ||
a19ae1ec JR |
353 | return 0; |
354 | } | |
b6c02715 | 355 | |
1c655773 JR |
356 | /* Flush the whole IO/TLB for a given protection domain */ |
357 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
358 | { | |
359 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
360 | ||
361 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); | |
362 | } | |
363 | ||
43f49609 JR |
364 | #ifdef CONFIG_IOMMU_API |
365 | /* | |
366 | * This function is used to flush the IO/TLB for a given protection domain | |
367 | * on every IOMMU in the system | |
368 | */ | |
369 | static void iommu_flush_domain(u16 domid) | |
370 | { | |
371 | unsigned long flags; | |
372 | struct amd_iommu *iommu; | |
373 | struct iommu_cmd cmd; | |
374 | ||
375 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
376 | domid, 1, 1); | |
377 | ||
378 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
379 | spin_lock_irqsave(&iommu->lock, flags); | |
380 | __iommu_queue_command(iommu, &cmd); | |
381 | __iommu_completion_wait(iommu); | |
382 | __iommu_wait_for_completion(iommu); | |
383 | spin_unlock_irqrestore(&iommu->lock, flags); | |
384 | } | |
385 | } | |
386 | #endif | |
387 | ||
431b2a20 JR |
388 | /**************************************************************************** |
389 | * | |
390 | * The functions below are used the create the page table mappings for | |
391 | * unity mapped regions. | |
392 | * | |
393 | ****************************************************************************/ | |
394 | ||
395 | /* | |
396 | * Generic mapping functions. It maps a physical address into a DMA | |
397 | * address space. It allocates the page table pages if necessary. | |
398 | * In the future it can be extended to a generic mapping function | |
399 | * supporting all features of AMD IOMMU page tables like level skipping | |
400 | * and full 64 bit address spaces. | |
401 | */ | |
38e817fe JR |
402 | static int iommu_map_page(struct protection_domain *dom, |
403 | unsigned long bus_addr, | |
404 | unsigned long phys_addr, | |
405 | int prot) | |
bd0e5211 JR |
406 | { |
407 | u64 __pte, *pte, *page; | |
408 | ||
409 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 410 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
411 | |
412 | /* only support 512GB address spaces for now */ | |
413 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
414 | return -EINVAL; | |
415 | ||
416 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
417 | ||
418 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
419 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
420 | if (!page) | |
421 | return -ENOMEM; | |
422 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
423 | } | |
424 | ||
425 | pte = IOMMU_PTE_PAGE(*pte); | |
426 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
427 | ||
428 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
429 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
430 | if (!page) | |
431 | return -ENOMEM; | |
432 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
433 | } | |
434 | ||
435 | pte = IOMMU_PTE_PAGE(*pte); | |
436 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
437 | ||
438 | if (IOMMU_PTE_PRESENT(*pte)) | |
439 | return -EBUSY; | |
440 | ||
441 | __pte = phys_addr | IOMMU_PTE_P; | |
442 | if (prot & IOMMU_PROT_IR) | |
443 | __pte |= IOMMU_PTE_IR; | |
444 | if (prot & IOMMU_PROT_IW) | |
445 | __pte |= IOMMU_PTE_IW; | |
446 | ||
447 | *pte = __pte; | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
eb74ff6c JR |
452 | #ifdef CONFIG_IOMMU_API |
453 | static void iommu_unmap_page(struct protection_domain *dom, | |
454 | unsigned long bus_addr) | |
455 | { | |
456 | u64 *pte; | |
457 | ||
458 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
459 | ||
460 | if (!IOMMU_PTE_PRESENT(*pte)) | |
461 | return; | |
462 | ||
463 | pte = IOMMU_PTE_PAGE(*pte); | |
464 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
465 | ||
466 | if (!IOMMU_PTE_PRESENT(*pte)) | |
467 | return; | |
468 | ||
469 | pte = IOMMU_PTE_PAGE(*pte); | |
470 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
471 | ||
472 | *pte = 0; | |
473 | } | |
474 | #endif | |
475 | ||
431b2a20 JR |
476 | /* |
477 | * This function checks if a specific unity mapping entry is needed for | |
478 | * this specific IOMMU. | |
479 | */ | |
bd0e5211 JR |
480 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
481 | struct unity_map_entry *entry) | |
482 | { | |
483 | u16 bdf, i; | |
484 | ||
485 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
486 | bdf = amd_iommu_alias_table[i]; | |
487 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
488 | return 1; | |
489 | } | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
431b2a20 JR |
494 | /* |
495 | * Init the unity mappings for a specific IOMMU in the system | |
496 | * | |
497 | * Basically iterates over all unity mapping entries and applies them to | |
498 | * the default domain DMA of that IOMMU if necessary. | |
499 | */ | |
bd0e5211 JR |
500 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
501 | { | |
502 | struct unity_map_entry *entry; | |
503 | int ret; | |
504 | ||
505 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
506 | if (!iommu_for_unity_map(iommu, entry)) | |
507 | continue; | |
508 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
509 | if (ret) | |
510 | return ret; | |
511 | } | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
431b2a20 JR |
516 | /* |
517 | * This function actually applies the mapping to the page table of the | |
518 | * dma_ops domain. | |
519 | */ | |
bd0e5211 JR |
520 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
521 | struct unity_map_entry *e) | |
522 | { | |
523 | u64 addr; | |
524 | int ret; | |
525 | ||
526 | for (addr = e->address_start; addr < e->address_end; | |
527 | addr += PAGE_SIZE) { | |
38e817fe | 528 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
529 | if (ret) |
530 | return ret; | |
531 | /* | |
532 | * if unity mapping is in aperture range mark the page | |
533 | * as allocated in the aperture | |
534 | */ | |
535 | if (addr < dma_dom->aperture_size) | |
536 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
537 | } | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
431b2a20 JR |
542 | /* |
543 | * Inits the unity mappings required for a specific device | |
544 | */ | |
bd0e5211 JR |
545 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
546 | u16 devid) | |
547 | { | |
548 | struct unity_map_entry *e; | |
549 | int ret; | |
550 | ||
551 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
552 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
553 | continue; | |
554 | ret = dma_ops_unity_map(dma_dom, e); | |
555 | if (ret) | |
556 | return ret; | |
557 | } | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
431b2a20 JR |
562 | /**************************************************************************** |
563 | * | |
564 | * The next functions belong to the address allocator for the dma_ops | |
565 | * interface functions. They work like the allocators in the other IOMMU | |
566 | * drivers. Its basically a bitmap which marks the allocated pages in | |
567 | * the aperture. Maybe it could be enhanced in the future to a more | |
568 | * efficient allocator. | |
569 | * | |
570 | ****************************************************************************/ | |
d3086444 | 571 | |
431b2a20 JR |
572 | /* |
573 | * The address allocator core function. | |
574 | * | |
575 | * called with domain->lock held | |
576 | */ | |
d3086444 JR |
577 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
578 | struct dma_ops_domain *dom, | |
6d4f343f | 579 | unsigned int pages, |
832a90c3 JR |
580 | unsigned long align_mask, |
581 | u64 dma_mask) | |
d3086444 | 582 | { |
40becd8d | 583 | unsigned long limit; |
d3086444 | 584 | unsigned long address; |
d3086444 JR |
585 | unsigned long boundary_size; |
586 | ||
587 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
588 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
589 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
590 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 591 | |
1c655773 | 592 | if (dom->next_bit >= limit) { |
d3086444 | 593 | dom->next_bit = 0; |
1c655773 JR |
594 | dom->need_flush = true; |
595 | } | |
d3086444 JR |
596 | |
597 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 598 | 0 , boundary_size, align_mask); |
1c655773 | 599 | if (address == -1) { |
d3086444 | 600 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 601 | 0, boundary_size, align_mask); |
1c655773 JR |
602 | dom->need_flush = true; |
603 | } | |
d3086444 JR |
604 | |
605 | if (likely(address != -1)) { | |
d3086444 JR |
606 | dom->next_bit = address + pages; |
607 | address <<= PAGE_SHIFT; | |
608 | } else | |
609 | address = bad_dma_address; | |
610 | ||
611 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
612 | ||
613 | return address; | |
614 | } | |
615 | ||
431b2a20 JR |
616 | /* |
617 | * The address free function. | |
618 | * | |
619 | * called with domain->lock held | |
620 | */ | |
d3086444 JR |
621 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
622 | unsigned long address, | |
623 | unsigned int pages) | |
624 | { | |
625 | address >>= PAGE_SHIFT; | |
626 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 627 | |
8501c45c | 628 | if (address >= dom->next_bit) |
80be308d | 629 | dom->need_flush = true; |
d3086444 JR |
630 | } |
631 | ||
431b2a20 JR |
632 | /**************************************************************************** |
633 | * | |
634 | * The next functions belong to the domain allocation. A domain is | |
635 | * allocated for every IOMMU as the default domain. If device isolation | |
636 | * is enabled, every device get its own domain. The most important thing | |
637 | * about domains is the page table mapping the DMA address space they | |
638 | * contain. | |
639 | * | |
640 | ****************************************************************************/ | |
641 | ||
ec487d1a JR |
642 | static u16 domain_id_alloc(void) |
643 | { | |
644 | unsigned long flags; | |
645 | int id; | |
646 | ||
647 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
648 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
649 | BUG_ON(id == 0); | |
650 | if (id > 0 && id < MAX_DOMAIN_ID) | |
651 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
652 | else | |
653 | id = 0; | |
654 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
655 | ||
656 | return id; | |
657 | } | |
658 | ||
a2acfb75 JR |
659 | #ifdef CONFIG_IOMMU_API |
660 | static void domain_id_free(int id) | |
661 | { | |
662 | unsigned long flags; | |
663 | ||
664 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
665 | if (id > 0 && id < MAX_DOMAIN_ID) | |
666 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
667 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
668 | } | |
669 | #endif | |
670 | ||
431b2a20 JR |
671 | /* |
672 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
673 | * ranges. | |
674 | */ | |
ec487d1a JR |
675 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
676 | unsigned long start_page, | |
677 | unsigned int pages) | |
678 | { | |
679 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
680 | ||
681 | if (start_page + pages > last_page) | |
682 | pages = last_page - start_page; | |
683 | ||
d26dbc5c | 684 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
685 | } |
686 | ||
86db2e5d | 687 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
688 | { |
689 | int i, j; | |
690 | u64 *p1, *p2, *p3; | |
691 | ||
86db2e5d | 692 | p1 = domain->pt_root; |
ec487d1a JR |
693 | |
694 | if (!p1) | |
695 | return; | |
696 | ||
697 | for (i = 0; i < 512; ++i) { | |
698 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
699 | continue; | |
700 | ||
701 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 702 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
703 | if (!IOMMU_PTE_PRESENT(p2[j])) |
704 | continue; | |
705 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
706 | free_page((unsigned long)p3); | |
707 | } | |
708 | ||
709 | free_page((unsigned long)p2); | |
710 | } | |
711 | ||
712 | free_page((unsigned long)p1); | |
86db2e5d JR |
713 | |
714 | domain->pt_root = NULL; | |
ec487d1a JR |
715 | } |
716 | ||
431b2a20 JR |
717 | /* |
718 | * Free a domain, only used if something went wrong in the | |
719 | * allocation path and we need to free an already allocated page table | |
720 | */ | |
ec487d1a JR |
721 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
722 | { | |
723 | if (!dom) | |
724 | return; | |
725 | ||
86db2e5d | 726 | free_pagetable(&dom->domain); |
ec487d1a JR |
727 | |
728 | kfree(dom->pte_pages); | |
729 | ||
730 | kfree(dom->bitmap); | |
731 | ||
732 | kfree(dom); | |
733 | } | |
734 | ||
431b2a20 JR |
735 | /* |
736 | * Allocates a new protection domain usable for the dma_ops functions. | |
737 | * It also intializes the page table and the address allocator data | |
738 | * structures required for the dma_ops interface | |
739 | */ | |
ec487d1a JR |
740 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
741 | unsigned order) | |
742 | { | |
743 | struct dma_ops_domain *dma_dom; | |
744 | unsigned i, num_pte_pages; | |
745 | u64 *l2_pde; | |
746 | u64 address; | |
747 | ||
748 | /* | |
749 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
750 | */ | |
751 | if ((order < 25) || (order > 30)) | |
752 | return NULL; | |
753 | ||
754 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
755 | if (!dma_dom) | |
756 | return NULL; | |
757 | ||
758 | spin_lock_init(&dma_dom->domain.lock); | |
759 | ||
760 | dma_dom->domain.id = domain_id_alloc(); | |
761 | if (dma_dom->domain.id == 0) | |
762 | goto free_dma_dom; | |
763 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
764 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 765 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
766 | dma_dom->domain.priv = dma_dom; |
767 | if (!dma_dom->domain.pt_root) | |
768 | goto free_dma_dom; | |
769 | dma_dom->aperture_size = (1ULL << order); | |
770 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
771 | GFP_KERNEL); | |
772 | if (!dma_dom->bitmap) | |
773 | goto free_dma_dom; | |
774 | /* | |
775 | * mark the first page as allocated so we never return 0 as | |
776 | * a valid dma-address. So we can use 0 as error value | |
777 | */ | |
778 | dma_dom->bitmap[0] = 1; | |
779 | dma_dom->next_bit = 0; | |
780 | ||
1c655773 | 781 | dma_dom->need_flush = false; |
bd60b735 | 782 | dma_dom->target_dev = 0xffff; |
1c655773 | 783 | |
431b2a20 | 784 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
785 | if (iommu->exclusion_start && |
786 | iommu->exclusion_start < dma_dom->aperture_size) { | |
787 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
788 | int pages = iommu_num_pages(iommu->exclusion_start, |
789 | iommu->exclusion_length, | |
790 | PAGE_SIZE); | |
ec487d1a JR |
791 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
792 | } | |
793 | ||
431b2a20 JR |
794 | /* |
795 | * At the last step, build the page tables so we don't need to | |
796 | * allocate page table pages in the dma_ops mapping/unmapping | |
797 | * path. | |
798 | */ | |
ec487d1a JR |
799 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
800 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
801 | GFP_KERNEL); | |
802 | if (!dma_dom->pte_pages) | |
803 | goto free_dma_dom; | |
804 | ||
805 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
806 | if (l2_pde == NULL) | |
807 | goto free_dma_dom; | |
808 | ||
809 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
810 | ||
811 | for (i = 0; i < num_pte_pages; ++i) { | |
812 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
813 | if (!dma_dom->pte_pages[i]) | |
814 | goto free_dma_dom; | |
815 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
816 | l2_pde[i] = IOMMU_L1_PDE(address); | |
817 | } | |
818 | ||
819 | return dma_dom; | |
820 | ||
821 | free_dma_dom: | |
822 | dma_ops_domain_free(dma_dom); | |
823 | ||
824 | return NULL; | |
825 | } | |
826 | ||
5b28df6f JR |
827 | /* |
828 | * little helper function to check whether a given protection domain is a | |
829 | * dma_ops domain | |
830 | */ | |
831 | static bool dma_ops_domain(struct protection_domain *domain) | |
832 | { | |
833 | return domain->flags & PD_DMA_OPS_MASK; | |
834 | } | |
835 | ||
431b2a20 JR |
836 | /* |
837 | * Find out the protection domain structure for a given PCI device. This | |
838 | * will give us the pointer to the page table root for example. | |
839 | */ | |
b20ac0d4 JR |
840 | static struct protection_domain *domain_for_device(u16 devid) |
841 | { | |
842 | struct protection_domain *dom; | |
843 | unsigned long flags; | |
844 | ||
845 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
846 | dom = amd_iommu_pd_table[devid]; | |
847 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
848 | ||
849 | return dom; | |
850 | } | |
851 | ||
431b2a20 JR |
852 | /* |
853 | * If a device is not yet associated with a domain, this function does | |
854 | * assigns it visible for the hardware | |
855 | */ | |
f1179dc0 JR |
856 | static void attach_device(struct amd_iommu *iommu, |
857 | struct protection_domain *domain, | |
858 | u16 devid) | |
b20ac0d4 JR |
859 | { |
860 | unsigned long flags; | |
b20ac0d4 JR |
861 | u64 pte_root = virt_to_phys(domain->pt_root); |
862 | ||
863c74eb JR |
863 | domain->dev_cnt += 1; |
864 | ||
38ddf41b JR |
865 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
866 | << DEV_ENTRY_MODE_SHIFT; | |
867 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
868 | |
869 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
870 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
871 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
872 | amd_iommu_dev_table[devid].data[2] = domain->id; |
873 | ||
874 | amd_iommu_pd_table[devid] = domain; | |
875 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
876 | ||
877 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
878 | } |
879 | ||
355bf553 JR |
880 | /* |
881 | * Removes a device from a protection domain (unlocked) | |
882 | */ | |
883 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
884 | { | |
885 | ||
886 | /* lock domain */ | |
887 | spin_lock(&domain->lock); | |
888 | ||
889 | /* remove domain from the lookup table */ | |
890 | amd_iommu_pd_table[devid] = NULL; | |
891 | ||
892 | /* remove entry from the device table seen by the hardware */ | |
893 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
894 | amd_iommu_dev_table[devid].data[1] = 0; | |
895 | amd_iommu_dev_table[devid].data[2] = 0; | |
896 | ||
897 | /* decrease reference counter */ | |
898 | domain->dev_cnt -= 1; | |
899 | ||
900 | /* ready */ | |
901 | spin_unlock(&domain->lock); | |
902 | } | |
903 | ||
904 | /* | |
905 | * Removes a device from a protection domain (with devtable_lock held) | |
906 | */ | |
907 | static void detach_device(struct protection_domain *domain, u16 devid) | |
908 | { | |
909 | unsigned long flags; | |
910 | ||
911 | /* lock device table */ | |
912 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
913 | __detach_device(domain, devid); | |
914 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
915 | } | |
e275a2a0 JR |
916 | |
917 | static int device_change_notifier(struct notifier_block *nb, | |
918 | unsigned long action, void *data) | |
919 | { | |
920 | struct device *dev = data; | |
921 | struct pci_dev *pdev = to_pci_dev(dev); | |
922 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
923 | struct protection_domain *domain; | |
924 | struct dma_ops_domain *dma_domain; | |
925 | struct amd_iommu *iommu; | |
926 | ||
927 | if (devid > amd_iommu_last_bdf) | |
928 | goto out; | |
929 | ||
930 | devid = amd_iommu_alias_table[devid]; | |
931 | ||
932 | iommu = amd_iommu_rlookup_table[devid]; | |
933 | if (iommu == NULL) | |
934 | goto out; | |
935 | ||
936 | domain = domain_for_device(devid); | |
937 | ||
938 | if (domain && !dma_ops_domain(domain)) | |
939 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
940 | "to a non-dma-ops domain\n", dev_name(dev)); | |
941 | ||
942 | switch (action) { | |
943 | case BUS_NOTIFY_BOUND_DRIVER: | |
944 | if (domain) | |
945 | goto out; | |
946 | dma_domain = find_protection_domain(devid); | |
947 | if (!dma_domain) | |
948 | dma_domain = iommu->default_dom; | |
949 | attach_device(iommu, &dma_domain->domain, devid); | |
950 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
951 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
952 | break; | |
953 | case BUS_NOTIFY_UNBIND_DRIVER: | |
954 | if (!domain) | |
955 | goto out; | |
956 | detach_device(domain, devid); | |
957 | break; | |
958 | default: | |
959 | goto out; | |
960 | } | |
961 | ||
962 | iommu_queue_inv_dev_entry(iommu, devid); | |
963 | iommu_completion_wait(iommu); | |
964 | ||
965 | out: | |
966 | return 0; | |
967 | } | |
968 | ||
969 | struct notifier_block device_nb = { | |
970 | .notifier_call = device_change_notifier, | |
971 | }; | |
355bf553 | 972 | |
431b2a20 JR |
973 | /***************************************************************************** |
974 | * | |
975 | * The next functions belong to the dma_ops mapping/unmapping code. | |
976 | * | |
977 | *****************************************************************************/ | |
978 | ||
dbcc112e JR |
979 | /* |
980 | * This function checks if the driver got a valid device from the caller to | |
981 | * avoid dereferencing invalid pointers. | |
982 | */ | |
983 | static bool check_device(struct device *dev) | |
984 | { | |
985 | if (!dev || !dev->dma_mask) | |
986 | return false; | |
987 | ||
988 | return true; | |
989 | } | |
990 | ||
bd60b735 JR |
991 | /* |
992 | * In this function the list of preallocated protection domains is traversed to | |
993 | * find the domain for a specific device | |
994 | */ | |
995 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
996 | { | |
997 | struct dma_ops_domain *entry, *ret = NULL; | |
998 | unsigned long flags; | |
999 | ||
1000 | if (list_empty(&iommu_pd_list)) | |
1001 | return NULL; | |
1002 | ||
1003 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1004 | ||
1005 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1006 | if (entry->target_dev == devid) { | |
1007 | ret = entry; | |
bd60b735 JR |
1008 | break; |
1009 | } | |
1010 | } | |
1011 | ||
1012 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1013 | ||
1014 | return ret; | |
1015 | } | |
1016 | ||
431b2a20 JR |
1017 | /* |
1018 | * In the dma_ops path we only have the struct device. This function | |
1019 | * finds the corresponding IOMMU, the protection domain and the | |
1020 | * requestor id for a given device. | |
1021 | * If the device is not yet associated with a domain this is also done | |
1022 | * in this function. | |
1023 | */ | |
b20ac0d4 JR |
1024 | static int get_device_resources(struct device *dev, |
1025 | struct amd_iommu **iommu, | |
1026 | struct protection_domain **domain, | |
1027 | u16 *bdf) | |
1028 | { | |
1029 | struct dma_ops_domain *dma_dom; | |
1030 | struct pci_dev *pcidev; | |
1031 | u16 _bdf; | |
1032 | ||
dbcc112e JR |
1033 | *iommu = NULL; |
1034 | *domain = NULL; | |
1035 | *bdf = 0xffff; | |
1036 | ||
1037 | if (dev->bus != &pci_bus_type) | |
1038 | return 0; | |
b20ac0d4 JR |
1039 | |
1040 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1041 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1042 | |
431b2a20 | 1043 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1044 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1045 | return 0; |
b20ac0d4 JR |
1046 | |
1047 | *bdf = amd_iommu_alias_table[_bdf]; | |
1048 | ||
1049 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1050 | if (*iommu == NULL) | |
1051 | return 0; | |
b20ac0d4 JR |
1052 | *domain = domain_for_device(*bdf); |
1053 | if (*domain == NULL) { | |
bd60b735 JR |
1054 | dma_dom = find_protection_domain(*bdf); |
1055 | if (!dma_dom) | |
1056 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1057 | *domain = &dma_dom->domain; |
f1179dc0 | 1058 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 JR |
1059 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
1060 | "device ", (*domain)->id); | |
1061 | print_devid(_bdf, 1); | |
1062 | } | |
1063 | ||
f91ba190 | 1064 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1065 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1066 | |
b20ac0d4 JR |
1067 | return 1; |
1068 | } | |
1069 | ||
431b2a20 JR |
1070 | /* |
1071 | * This is the generic map function. It maps one 4kb page at paddr to | |
1072 | * the given address in the DMA address space for the domain. | |
1073 | */ | |
cb76c322 JR |
1074 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1075 | struct dma_ops_domain *dom, | |
1076 | unsigned long address, | |
1077 | phys_addr_t paddr, | |
1078 | int direction) | |
1079 | { | |
1080 | u64 *pte, __pte; | |
1081 | ||
1082 | WARN_ON(address > dom->aperture_size); | |
1083 | ||
1084 | paddr &= PAGE_MASK; | |
1085 | ||
1086 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1087 | pte += IOMMU_PTE_L0_INDEX(address); | |
1088 | ||
1089 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1090 | ||
1091 | if (direction == DMA_TO_DEVICE) | |
1092 | __pte |= IOMMU_PTE_IR; | |
1093 | else if (direction == DMA_FROM_DEVICE) | |
1094 | __pte |= IOMMU_PTE_IW; | |
1095 | else if (direction == DMA_BIDIRECTIONAL) | |
1096 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1097 | ||
1098 | WARN_ON(*pte); | |
1099 | ||
1100 | *pte = __pte; | |
1101 | ||
1102 | return (dma_addr_t)address; | |
1103 | } | |
1104 | ||
431b2a20 JR |
1105 | /* |
1106 | * The generic unmapping function for on page in the DMA address space. | |
1107 | */ | |
cb76c322 JR |
1108 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1109 | struct dma_ops_domain *dom, | |
1110 | unsigned long address) | |
1111 | { | |
1112 | u64 *pte; | |
1113 | ||
1114 | if (address >= dom->aperture_size) | |
1115 | return; | |
1116 | ||
8ad909c4 | 1117 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1118 | |
1119 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1120 | pte += IOMMU_PTE_L0_INDEX(address); | |
1121 | ||
1122 | WARN_ON(!*pte); | |
1123 | ||
1124 | *pte = 0ULL; | |
1125 | } | |
1126 | ||
431b2a20 JR |
1127 | /* |
1128 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1129 | * contiguous memory region into DMA address space. It is used by all |
1130 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1131 | * Must be called with the domain lock held. |
1132 | */ | |
cb76c322 JR |
1133 | static dma_addr_t __map_single(struct device *dev, |
1134 | struct amd_iommu *iommu, | |
1135 | struct dma_ops_domain *dma_dom, | |
1136 | phys_addr_t paddr, | |
1137 | size_t size, | |
6d4f343f | 1138 | int dir, |
832a90c3 JR |
1139 | bool align, |
1140 | u64 dma_mask) | |
cb76c322 JR |
1141 | { |
1142 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1143 | dma_addr_t address, start; | |
1144 | unsigned int pages; | |
6d4f343f | 1145 | unsigned long align_mask = 0; |
cb76c322 JR |
1146 | int i; |
1147 | ||
e3c449f5 | 1148 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1149 | paddr &= PAGE_MASK; |
1150 | ||
6d4f343f JR |
1151 | if (align) |
1152 | align_mask = (1UL << get_order(size)) - 1; | |
1153 | ||
832a90c3 JR |
1154 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1155 | dma_mask); | |
cb76c322 JR |
1156 | if (unlikely(address == bad_dma_address)) |
1157 | goto out; | |
1158 | ||
1159 | start = address; | |
1160 | for (i = 0; i < pages; ++i) { | |
1161 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1162 | paddr += PAGE_SIZE; | |
1163 | start += PAGE_SIZE; | |
1164 | } | |
1165 | address += offset; | |
1166 | ||
afa9fdc2 | 1167 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1168 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1169 | dma_dom->need_flush = false; | |
1170 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1171 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1172 | ||
cb76c322 JR |
1173 | out: |
1174 | return address; | |
1175 | } | |
1176 | ||
431b2a20 JR |
1177 | /* |
1178 | * Does the reverse of the __map_single function. Must be called with | |
1179 | * the domain lock held too | |
1180 | */ | |
cb76c322 JR |
1181 | static void __unmap_single(struct amd_iommu *iommu, |
1182 | struct dma_ops_domain *dma_dom, | |
1183 | dma_addr_t dma_addr, | |
1184 | size_t size, | |
1185 | int dir) | |
1186 | { | |
1187 | dma_addr_t i, start; | |
1188 | unsigned int pages; | |
1189 | ||
b8d9905d JR |
1190 | if ((dma_addr == bad_dma_address) || |
1191 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1192 | return; |
1193 | ||
e3c449f5 | 1194 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1195 | dma_addr &= PAGE_MASK; |
1196 | start = dma_addr; | |
1197 | ||
1198 | for (i = 0; i < pages; ++i) { | |
1199 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1200 | start += PAGE_SIZE; | |
1201 | } | |
1202 | ||
1203 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
270cab24 | 1204 | |
80be308d | 1205 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1206 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1207 | dma_dom->need_flush = false; |
1208 | } | |
cb76c322 JR |
1209 | } |
1210 | ||
431b2a20 JR |
1211 | /* |
1212 | * The exported map_single function for dma_ops. | |
1213 | */ | |
4da70b9e JR |
1214 | static dma_addr_t map_single(struct device *dev, phys_addr_t paddr, |
1215 | size_t size, int dir) | |
1216 | { | |
1217 | unsigned long flags; | |
1218 | struct amd_iommu *iommu; | |
1219 | struct protection_domain *domain; | |
1220 | u16 devid; | |
1221 | dma_addr_t addr; | |
832a90c3 | 1222 | u64 dma_mask; |
4da70b9e | 1223 | |
dbcc112e JR |
1224 | if (!check_device(dev)) |
1225 | return bad_dma_address; | |
1226 | ||
832a90c3 | 1227 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1228 | |
1229 | get_device_resources(dev, &iommu, &domain, &devid); | |
1230 | ||
1231 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1232 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1233 | return (dma_addr_t)paddr; |
1234 | ||
5b28df6f JR |
1235 | if (!dma_ops_domain(domain)) |
1236 | return bad_dma_address; | |
1237 | ||
4da70b9e | 1238 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1239 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1240 | dma_mask); | |
4da70b9e JR |
1241 | if (addr == bad_dma_address) |
1242 | goto out; | |
1243 | ||
09ee17eb | 1244 | iommu_completion_wait(iommu); |
4da70b9e JR |
1245 | |
1246 | out: | |
1247 | spin_unlock_irqrestore(&domain->lock, flags); | |
1248 | ||
1249 | return addr; | |
1250 | } | |
1251 | ||
431b2a20 JR |
1252 | /* |
1253 | * The exported unmap_single function for dma_ops. | |
1254 | */ | |
4da70b9e JR |
1255 | static void unmap_single(struct device *dev, dma_addr_t dma_addr, |
1256 | size_t size, int dir) | |
1257 | { | |
1258 | unsigned long flags; | |
1259 | struct amd_iommu *iommu; | |
1260 | struct protection_domain *domain; | |
1261 | u16 devid; | |
1262 | ||
dbcc112e JR |
1263 | if (!check_device(dev) || |
1264 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1265 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1266 | return; |
1267 | ||
5b28df6f JR |
1268 | if (!dma_ops_domain(domain)) |
1269 | return; | |
1270 | ||
4da70b9e JR |
1271 | spin_lock_irqsave(&domain->lock, flags); |
1272 | ||
1273 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1274 | ||
09ee17eb | 1275 | iommu_completion_wait(iommu); |
4da70b9e JR |
1276 | |
1277 | spin_unlock_irqrestore(&domain->lock, flags); | |
1278 | } | |
1279 | ||
431b2a20 JR |
1280 | /* |
1281 | * This is a special map_sg function which is used if we should map a | |
1282 | * device which is not handled by an AMD IOMMU in the system. | |
1283 | */ | |
65b050ad JR |
1284 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1285 | int nelems, int dir) | |
1286 | { | |
1287 | struct scatterlist *s; | |
1288 | int i; | |
1289 | ||
1290 | for_each_sg(sglist, s, nelems, i) { | |
1291 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1292 | s->dma_length = s->length; | |
1293 | } | |
1294 | ||
1295 | return nelems; | |
1296 | } | |
1297 | ||
431b2a20 JR |
1298 | /* |
1299 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1300 | * lists). | |
1301 | */ | |
65b050ad JR |
1302 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
1303 | int nelems, int dir) | |
1304 | { | |
1305 | unsigned long flags; | |
1306 | struct amd_iommu *iommu; | |
1307 | struct protection_domain *domain; | |
1308 | u16 devid; | |
1309 | int i; | |
1310 | struct scatterlist *s; | |
1311 | phys_addr_t paddr; | |
1312 | int mapped_elems = 0; | |
832a90c3 | 1313 | u64 dma_mask; |
65b050ad | 1314 | |
dbcc112e JR |
1315 | if (!check_device(dev)) |
1316 | return 0; | |
1317 | ||
832a90c3 | 1318 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1319 | |
1320 | get_device_resources(dev, &iommu, &domain, &devid); | |
1321 | ||
1322 | if (!iommu || !domain) | |
1323 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1324 | ||
5b28df6f JR |
1325 | if (!dma_ops_domain(domain)) |
1326 | return 0; | |
1327 | ||
65b050ad JR |
1328 | spin_lock_irqsave(&domain->lock, flags); |
1329 | ||
1330 | for_each_sg(sglist, s, nelems, i) { | |
1331 | paddr = sg_phys(s); | |
1332 | ||
1333 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1334 | paddr, s->length, dir, false, |
1335 | dma_mask); | |
65b050ad JR |
1336 | |
1337 | if (s->dma_address) { | |
1338 | s->dma_length = s->length; | |
1339 | mapped_elems++; | |
1340 | } else | |
1341 | goto unmap; | |
65b050ad JR |
1342 | } |
1343 | ||
09ee17eb | 1344 | iommu_completion_wait(iommu); |
65b050ad JR |
1345 | |
1346 | out: | |
1347 | spin_unlock_irqrestore(&domain->lock, flags); | |
1348 | ||
1349 | return mapped_elems; | |
1350 | unmap: | |
1351 | for_each_sg(sglist, s, mapped_elems, i) { | |
1352 | if (s->dma_address) | |
1353 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1354 | s->dma_length, dir); | |
1355 | s->dma_address = s->dma_length = 0; | |
1356 | } | |
1357 | ||
1358 | mapped_elems = 0; | |
1359 | ||
1360 | goto out; | |
1361 | } | |
1362 | ||
431b2a20 JR |
1363 | /* |
1364 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1365 | * lists). | |
1366 | */ | |
65b050ad JR |
1367 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
1368 | int nelems, int dir) | |
1369 | { | |
1370 | unsigned long flags; | |
1371 | struct amd_iommu *iommu; | |
1372 | struct protection_domain *domain; | |
1373 | struct scatterlist *s; | |
1374 | u16 devid; | |
1375 | int i; | |
1376 | ||
dbcc112e JR |
1377 | if (!check_device(dev) || |
1378 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1379 | return; |
1380 | ||
5b28df6f JR |
1381 | if (!dma_ops_domain(domain)) |
1382 | return; | |
1383 | ||
65b050ad JR |
1384 | spin_lock_irqsave(&domain->lock, flags); |
1385 | ||
1386 | for_each_sg(sglist, s, nelems, i) { | |
1387 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1388 | s->dma_length, dir); | |
65b050ad JR |
1389 | s->dma_address = s->dma_length = 0; |
1390 | } | |
1391 | ||
09ee17eb | 1392 | iommu_completion_wait(iommu); |
65b050ad JR |
1393 | |
1394 | spin_unlock_irqrestore(&domain->lock, flags); | |
1395 | } | |
1396 | ||
431b2a20 JR |
1397 | /* |
1398 | * The exported alloc_coherent function for dma_ops. | |
1399 | */ | |
5d8b53cf JR |
1400 | static void *alloc_coherent(struct device *dev, size_t size, |
1401 | dma_addr_t *dma_addr, gfp_t flag) | |
1402 | { | |
1403 | unsigned long flags; | |
1404 | void *virt_addr; | |
1405 | struct amd_iommu *iommu; | |
1406 | struct protection_domain *domain; | |
1407 | u16 devid; | |
1408 | phys_addr_t paddr; | |
832a90c3 | 1409 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1410 | |
dbcc112e JR |
1411 | if (!check_device(dev)) |
1412 | return NULL; | |
5d8b53cf | 1413 | |
13d9fead FT |
1414 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1415 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1416 | |
c97ac535 | 1417 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1418 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1419 | if (!virt_addr) | |
1420 | return 0; | |
1421 | ||
5d8b53cf JR |
1422 | paddr = virt_to_phys(virt_addr); |
1423 | ||
5d8b53cf JR |
1424 | if (!iommu || !domain) { |
1425 | *dma_addr = (dma_addr_t)paddr; | |
1426 | return virt_addr; | |
1427 | } | |
1428 | ||
5b28df6f JR |
1429 | if (!dma_ops_domain(domain)) |
1430 | goto out_free; | |
1431 | ||
832a90c3 JR |
1432 | if (!dma_mask) |
1433 | dma_mask = *dev->dma_mask; | |
1434 | ||
5d8b53cf JR |
1435 | spin_lock_irqsave(&domain->lock, flags); |
1436 | ||
1437 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1438 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1439 | |
5b28df6f JR |
1440 | if (*dma_addr == bad_dma_address) |
1441 | goto out_free; | |
5d8b53cf | 1442 | |
09ee17eb | 1443 | iommu_completion_wait(iommu); |
5d8b53cf | 1444 | |
5d8b53cf JR |
1445 | spin_unlock_irqrestore(&domain->lock, flags); |
1446 | ||
1447 | return virt_addr; | |
5b28df6f JR |
1448 | |
1449 | out_free: | |
1450 | ||
1451 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1452 | ||
1453 | return NULL; | |
5d8b53cf JR |
1454 | } |
1455 | ||
431b2a20 JR |
1456 | /* |
1457 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1458 | */ |
5d8b53cf JR |
1459 | static void free_coherent(struct device *dev, size_t size, |
1460 | void *virt_addr, dma_addr_t dma_addr) | |
1461 | { | |
1462 | unsigned long flags; | |
1463 | struct amd_iommu *iommu; | |
1464 | struct protection_domain *domain; | |
1465 | u16 devid; | |
1466 | ||
dbcc112e JR |
1467 | if (!check_device(dev)) |
1468 | return; | |
1469 | ||
5d8b53cf JR |
1470 | get_device_resources(dev, &iommu, &domain, &devid); |
1471 | ||
1472 | if (!iommu || !domain) | |
1473 | goto free_mem; | |
1474 | ||
5b28df6f JR |
1475 | if (!dma_ops_domain(domain)) |
1476 | goto free_mem; | |
1477 | ||
5d8b53cf JR |
1478 | spin_lock_irqsave(&domain->lock, flags); |
1479 | ||
1480 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1481 | |
09ee17eb | 1482 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1483 | |
1484 | spin_unlock_irqrestore(&domain->lock, flags); | |
1485 | ||
1486 | free_mem: | |
1487 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1488 | } | |
1489 | ||
b39ba6ad JR |
1490 | /* |
1491 | * This function is called by the DMA layer to find out if we can handle a | |
1492 | * particular device. It is part of the dma_ops. | |
1493 | */ | |
1494 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1495 | { | |
1496 | u16 bdf; | |
1497 | struct pci_dev *pcidev; | |
1498 | ||
1499 | /* No device or no PCI device */ | |
1500 | if (!dev || dev->bus != &pci_bus_type) | |
1501 | return 0; | |
1502 | ||
1503 | pcidev = to_pci_dev(dev); | |
1504 | ||
1505 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1506 | ||
1507 | /* Out of our scope? */ | |
1508 | if (bdf > amd_iommu_last_bdf) | |
1509 | return 0; | |
1510 | ||
1511 | return 1; | |
1512 | } | |
1513 | ||
c432f3df | 1514 | /* |
431b2a20 JR |
1515 | * The function for pre-allocating protection domains. |
1516 | * | |
c432f3df JR |
1517 | * If the driver core informs the DMA layer if a driver grabs a device |
1518 | * we don't need to preallocate the protection domains anymore. | |
1519 | * For now we have to. | |
1520 | */ | |
1521 | void prealloc_protection_domains(void) | |
1522 | { | |
1523 | struct pci_dev *dev = NULL; | |
1524 | struct dma_ops_domain *dma_dom; | |
1525 | struct amd_iommu *iommu; | |
1526 | int order = amd_iommu_aperture_order; | |
1527 | u16 devid; | |
1528 | ||
1529 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1530 | devid = (dev->bus->number << 8) | dev->devfn; | |
3a61ec38 | 1531 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1532 | continue; |
1533 | devid = amd_iommu_alias_table[devid]; | |
1534 | if (domain_for_device(devid)) | |
1535 | continue; | |
1536 | iommu = amd_iommu_rlookup_table[devid]; | |
1537 | if (!iommu) | |
1538 | continue; | |
1539 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1540 | if (!dma_dom) | |
1541 | continue; | |
1542 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1543 | dma_dom->target_dev = devid; |
1544 | ||
1545 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1546 | } |
1547 | } | |
1548 | ||
6631ee9d JR |
1549 | static struct dma_mapping_ops amd_iommu_dma_ops = { |
1550 | .alloc_coherent = alloc_coherent, | |
1551 | .free_coherent = free_coherent, | |
1552 | .map_single = map_single, | |
1553 | .unmap_single = unmap_single, | |
1554 | .map_sg = map_sg, | |
1555 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1556 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1557 | }; |
1558 | ||
431b2a20 JR |
1559 | /* |
1560 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1561 | */ | |
6631ee9d JR |
1562 | int __init amd_iommu_init_dma_ops(void) |
1563 | { | |
1564 | struct amd_iommu *iommu; | |
1565 | int order = amd_iommu_aperture_order; | |
1566 | int ret; | |
1567 | ||
431b2a20 JR |
1568 | /* |
1569 | * first allocate a default protection domain for every IOMMU we | |
1570 | * found in the system. Devices not assigned to any other | |
1571 | * protection domain will be assigned to the default one. | |
1572 | */ | |
6631ee9d JR |
1573 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1574 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1575 | if (iommu->default_dom == NULL) | |
1576 | return -ENOMEM; | |
e2dc14a2 | 1577 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1578 | ret = iommu_init_unity_mappings(iommu); |
1579 | if (ret) | |
1580 | goto free_domains; | |
1581 | } | |
1582 | ||
431b2a20 JR |
1583 | /* |
1584 | * If device isolation is enabled, pre-allocate the protection | |
1585 | * domains for each device. | |
1586 | */ | |
6631ee9d JR |
1587 | if (amd_iommu_isolate) |
1588 | prealloc_protection_domains(); | |
1589 | ||
1590 | iommu_detected = 1; | |
1591 | force_iommu = 1; | |
1592 | bad_dma_address = 0; | |
92af4e29 | 1593 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1594 | gart_iommu_aperture_disabled = 1; |
1595 | gart_iommu_aperture = 0; | |
92af4e29 | 1596 | #endif |
6631ee9d | 1597 | |
431b2a20 | 1598 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1599 | dma_ops = &amd_iommu_dma_ops; |
1600 | ||
26961efe JR |
1601 | #ifdef CONFIG_IOMMU_API |
1602 | register_iommu(&amd_iommu_ops); | |
1603 | #endif | |
1604 | ||
e275a2a0 JR |
1605 | bus_register_notifier(&pci_bus_type, &device_nb); |
1606 | ||
6631ee9d JR |
1607 | return 0; |
1608 | ||
1609 | free_domains: | |
1610 | ||
1611 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1612 | if (iommu->default_dom) | |
1613 | dma_ops_domain_free(iommu->default_dom); | |
1614 | } | |
1615 | ||
1616 | return ret; | |
1617 | } | |
6d98cd80 JR |
1618 | |
1619 | /***************************************************************************** | |
1620 | * | |
1621 | * The following functions belong to the exported interface of AMD IOMMU | |
1622 | * | |
1623 | * This interface allows access to lower level functions of the IOMMU | |
1624 | * like protection domain handling and assignement of devices to domains | |
1625 | * which is not possible with the dma_ops interface. | |
1626 | * | |
1627 | *****************************************************************************/ | |
1628 | ||
1629 | #ifdef CONFIG_IOMMU_API | |
1630 | ||
1631 | static void cleanup_domain(struct protection_domain *domain) | |
1632 | { | |
1633 | unsigned long flags; | |
1634 | u16 devid; | |
1635 | ||
1636 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1637 | ||
1638 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1639 | if (amd_iommu_pd_table[devid] == domain) | |
1640 | __detach_device(domain, devid); | |
1641 | ||
1642 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1643 | } | |
1644 | ||
c156e347 JR |
1645 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1646 | { | |
1647 | struct protection_domain *domain; | |
1648 | ||
1649 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1650 | if (!domain) | |
1651 | return -ENOMEM; | |
1652 | ||
1653 | spin_lock_init(&domain->lock); | |
1654 | domain->mode = PAGE_MODE_3_LEVEL; | |
1655 | domain->id = domain_id_alloc(); | |
1656 | if (!domain->id) | |
1657 | goto out_free; | |
1658 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1659 | if (!domain->pt_root) | |
1660 | goto out_free; | |
1661 | ||
1662 | dom->priv = domain; | |
1663 | ||
1664 | return 0; | |
1665 | ||
1666 | out_free: | |
1667 | kfree(domain); | |
1668 | ||
1669 | return -ENOMEM; | |
1670 | } | |
1671 | ||
98383fc3 JR |
1672 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1673 | { | |
1674 | struct protection_domain *domain = dom->priv; | |
1675 | ||
1676 | if (!domain) | |
1677 | return; | |
1678 | ||
1679 | if (domain->dev_cnt > 0) | |
1680 | cleanup_domain(domain); | |
1681 | ||
1682 | BUG_ON(domain->dev_cnt != 0); | |
1683 | ||
1684 | free_pagetable(domain); | |
1685 | ||
1686 | domain_id_free(domain->id); | |
1687 | ||
1688 | kfree(domain); | |
1689 | ||
1690 | dom->priv = NULL; | |
1691 | } | |
1692 | ||
684f2888 JR |
1693 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1694 | struct device *dev) | |
1695 | { | |
1696 | struct protection_domain *domain = dom->priv; | |
1697 | struct amd_iommu *iommu; | |
1698 | struct pci_dev *pdev; | |
1699 | u16 devid; | |
1700 | ||
1701 | if (dev->bus != &pci_bus_type) | |
1702 | return; | |
1703 | ||
1704 | pdev = to_pci_dev(dev); | |
1705 | ||
1706 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1707 | ||
1708 | if (devid > 0) | |
1709 | detach_device(domain, devid); | |
1710 | ||
1711 | iommu = amd_iommu_rlookup_table[devid]; | |
1712 | if (!iommu) | |
1713 | return; | |
1714 | ||
1715 | iommu_queue_inv_dev_entry(iommu, devid); | |
1716 | iommu_completion_wait(iommu); | |
1717 | } | |
1718 | ||
01106066 JR |
1719 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1720 | struct device *dev) | |
1721 | { | |
1722 | struct protection_domain *domain = dom->priv; | |
1723 | struct protection_domain *old_domain; | |
1724 | struct amd_iommu *iommu; | |
1725 | struct pci_dev *pdev; | |
1726 | u16 devid; | |
1727 | ||
1728 | if (dev->bus != &pci_bus_type) | |
1729 | return -EINVAL; | |
1730 | ||
1731 | pdev = to_pci_dev(dev); | |
1732 | ||
1733 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1734 | ||
1735 | if (devid >= amd_iommu_last_bdf || | |
1736 | devid != amd_iommu_alias_table[devid]) | |
1737 | return -EINVAL; | |
1738 | ||
1739 | iommu = amd_iommu_rlookup_table[devid]; | |
1740 | if (!iommu) | |
1741 | return -EINVAL; | |
1742 | ||
1743 | old_domain = domain_for_device(devid); | |
1744 | if (old_domain) | |
1745 | return -EBUSY; | |
1746 | ||
1747 | attach_device(iommu, domain, devid); | |
1748 | ||
1749 | iommu_completion_wait(iommu); | |
1750 | ||
1751 | return 0; | |
1752 | } | |
1753 | ||
c6229ca6 JR |
1754 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1755 | unsigned long iova, phys_addr_t paddr, | |
1756 | size_t size, int iommu_prot) | |
1757 | { | |
1758 | struct protection_domain *domain = dom->priv; | |
1759 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1760 | int prot = 0; | |
1761 | int ret; | |
1762 | ||
1763 | if (iommu_prot & IOMMU_READ) | |
1764 | prot |= IOMMU_PROT_IR; | |
1765 | if (iommu_prot & IOMMU_WRITE) | |
1766 | prot |= IOMMU_PROT_IW; | |
1767 | ||
1768 | iova &= PAGE_MASK; | |
1769 | paddr &= PAGE_MASK; | |
1770 | ||
1771 | for (i = 0; i < npages; ++i) { | |
1772 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1773 | if (ret) | |
1774 | return ret; | |
1775 | ||
1776 | iova += PAGE_SIZE; | |
1777 | paddr += PAGE_SIZE; | |
1778 | } | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
eb74ff6c JR |
1783 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1784 | unsigned long iova, size_t size) | |
1785 | { | |
1786 | ||
1787 | struct protection_domain *domain = dom->priv; | |
1788 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1789 | ||
1790 | iova &= PAGE_MASK; | |
1791 | ||
1792 | for (i = 0; i < npages; ++i) { | |
1793 | iommu_unmap_page(domain, iova); | |
1794 | iova += PAGE_SIZE; | |
1795 | } | |
1796 | ||
1797 | iommu_flush_domain(domain->id); | |
1798 | } | |
1799 | ||
645c4c8d JR |
1800 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1801 | unsigned long iova) | |
1802 | { | |
1803 | struct protection_domain *domain = dom->priv; | |
1804 | unsigned long offset = iova & ~PAGE_MASK; | |
1805 | phys_addr_t paddr; | |
1806 | u64 *pte; | |
1807 | ||
1808 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1809 | ||
1810 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1811 | return 0; | |
1812 | ||
1813 | pte = IOMMU_PTE_PAGE(*pte); | |
1814 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1815 | ||
1816 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1817 | return 0; | |
1818 | ||
1819 | pte = IOMMU_PTE_PAGE(*pte); | |
1820 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1821 | ||
1822 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1823 | return 0; | |
1824 | ||
1825 | paddr = *pte & IOMMU_PAGE_MASK; | |
1826 | paddr |= offset; | |
1827 | ||
1828 | return paddr; | |
1829 | } | |
1830 | ||
26961efe JR |
1831 | static struct iommu_ops amd_iommu_ops = { |
1832 | .domain_init = amd_iommu_domain_init, | |
1833 | .domain_destroy = amd_iommu_domain_destroy, | |
1834 | .attach_dev = amd_iommu_attach_device, | |
1835 | .detach_dev = amd_iommu_detach_device, | |
1836 | .map = amd_iommu_map_range, | |
1837 | .unmap = amd_iommu_unmap_range, | |
1838 | .iova_to_phys = amd_iommu_iova_to_phys, | |
1839 | }; | |
1840 | ||
6d98cd80 | 1841 | #endif |