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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
b6c02715 | 30 | #include <asm/proto.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
27c2127a | 33 | #include <asm/dma.h> |
6a9401a7 | 34 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 35 | #include <asm/amd_iommu_types.h> |
c6da992e | 36 | #include <asm/amd_iommu.h> |
b6c02715 JR |
37 | |
38 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
39 | ||
815b33fd | 40 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 41 | |
b6c02715 JR |
42 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
43 | ||
bd60b735 JR |
44 | /* A list of preallocated protection domains */ |
45 | static LIST_HEAD(iommu_pd_list); | |
46 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
47 | ||
8fa5f802 JR |
48 | /* List of all available dev_data structures */ |
49 | static LIST_HEAD(dev_data_list); | |
50 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
51 | ||
0feae533 JR |
52 | /* |
53 | * Domain for untranslated devices - only allocated | |
54 | * if iommu=pt passed on kernel cmd line. | |
55 | */ | |
56 | static struct protection_domain *pt_domain; | |
57 | ||
26961efe | 58 | static struct iommu_ops amd_iommu_ops; |
26961efe | 59 | |
431b2a20 JR |
60 | /* |
61 | * general struct to manage commands send to an IOMMU | |
62 | */ | |
d6449536 | 63 | struct iommu_cmd { |
b6c02715 JR |
64 | u32 data[4]; |
65 | }; | |
66 | ||
04bfdd84 | 67 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 68 | |
15898bbc JR |
69 | /**************************************************************************** |
70 | * | |
71 | * Helper functions | |
72 | * | |
73 | ****************************************************************************/ | |
74 | ||
f62dda66 | 75 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
76 | { |
77 | struct iommu_dev_data *dev_data; | |
78 | unsigned long flags; | |
79 | ||
80 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
81 | if (!dev_data) | |
82 | return NULL; | |
83 | ||
f62dda66 | 84 | dev_data->devid = devid; |
8fa5f802 JR |
85 | atomic_set(&dev_data->bind, 0); |
86 | ||
87 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
88 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
89 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
90 | ||
91 | return dev_data; | |
92 | } | |
93 | ||
94 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
95 | { | |
96 | unsigned long flags; | |
97 | ||
98 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
99 | list_del(&dev_data->dev_data_list); | |
100 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
101 | ||
102 | kfree(dev_data); | |
103 | } | |
104 | ||
15898bbc JR |
105 | static inline u16 get_device_id(struct device *dev) |
106 | { | |
107 | struct pci_dev *pdev = to_pci_dev(dev); | |
108 | ||
109 | return calc_devid(pdev->bus->number, pdev->devfn); | |
110 | } | |
111 | ||
657cbb6b JR |
112 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
113 | { | |
114 | return dev->archdata.iommu; | |
115 | } | |
116 | ||
71c70984 JR |
117 | /* |
118 | * In this function the list of preallocated protection domains is traversed to | |
119 | * find the domain for a specific device | |
120 | */ | |
121 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
122 | { | |
123 | struct dma_ops_domain *entry, *ret = NULL; | |
124 | unsigned long flags; | |
125 | u16 alias = amd_iommu_alias_table[devid]; | |
126 | ||
127 | if (list_empty(&iommu_pd_list)) | |
128 | return NULL; | |
129 | ||
130 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
131 | ||
132 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
133 | if (entry->target_dev == devid || | |
134 | entry->target_dev == alias) { | |
135 | ret = entry; | |
136 | break; | |
137 | } | |
138 | } | |
139 | ||
140 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
141 | ||
142 | return ret; | |
143 | } | |
144 | ||
98fc5a69 JR |
145 | /* |
146 | * This function checks if the driver got a valid device from the caller to | |
147 | * avoid dereferencing invalid pointers. | |
148 | */ | |
149 | static bool check_device(struct device *dev) | |
150 | { | |
151 | u16 devid; | |
152 | ||
153 | if (!dev || !dev->dma_mask) | |
154 | return false; | |
155 | ||
156 | /* No device or no PCI device */ | |
339d3261 | 157 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
158 | return false; |
159 | ||
160 | devid = get_device_id(dev); | |
161 | ||
162 | /* Out of our scope? */ | |
163 | if (devid > amd_iommu_last_bdf) | |
164 | return false; | |
165 | ||
166 | if (amd_iommu_rlookup_table[devid] == NULL) | |
167 | return false; | |
168 | ||
169 | return true; | |
170 | } | |
171 | ||
657cbb6b JR |
172 | static int iommu_init_device(struct device *dev) |
173 | { | |
174 | struct iommu_dev_data *dev_data; | |
175 | struct pci_dev *pdev; | |
8fa5f802 | 176 | u16 alias; |
657cbb6b JR |
177 | |
178 | if (dev->archdata.iommu) | |
179 | return 0; | |
180 | ||
f62dda66 | 181 | dev_data = alloc_dev_data(get_device_id(dev)); |
657cbb6b JR |
182 | if (!dev_data) |
183 | return -ENOMEM; | |
184 | ||
f62dda66 | 185 | alias = amd_iommu_alias_table[dev_data->devid]; |
657cbb6b JR |
186 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); |
187 | if (pdev) | |
188 | dev_data->alias = &pdev->dev; | |
26018874 | 189 | else { |
8fa5f802 | 190 | free_dev_data(dev_data); |
26018874 JR |
191 | return -ENOTSUPP; |
192 | } | |
657cbb6b JR |
193 | |
194 | dev->archdata.iommu = dev_data; | |
195 | ||
657cbb6b JR |
196 | return 0; |
197 | } | |
198 | ||
26018874 JR |
199 | static void iommu_ignore_device(struct device *dev) |
200 | { | |
201 | u16 devid, alias; | |
202 | ||
203 | devid = get_device_id(dev); | |
204 | alias = amd_iommu_alias_table[devid]; | |
205 | ||
206 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
207 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
208 | ||
209 | amd_iommu_rlookup_table[devid] = NULL; | |
210 | amd_iommu_rlookup_table[alias] = NULL; | |
211 | } | |
212 | ||
657cbb6b JR |
213 | static void iommu_uninit_device(struct device *dev) |
214 | { | |
8fa5f802 JR |
215 | /* |
216 | * Nothing to do here - we keep dev_data around for unplugged devices | |
217 | * and reuse it when the device is re-plugged - not doing so would | |
218 | * introduce a ton of races. | |
219 | */ | |
657cbb6b | 220 | } |
b7cc9554 JR |
221 | |
222 | void __init amd_iommu_uninit_devices(void) | |
223 | { | |
8fa5f802 | 224 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
225 | struct pci_dev *pdev = NULL; |
226 | ||
227 | for_each_pci_dev(pdev) { | |
228 | ||
229 | if (!check_device(&pdev->dev)) | |
230 | continue; | |
231 | ||
232 | iommu_uninit_device(&pdev->dev); | |
233 | } | |
8fa5f802 JR |
234 | |
235 | /* Free all of our dev_data structures */ | |
236 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
237 | free_dev_data(dev_data); | |
b7cc9554 JR |
238 | } |
239 | ||
240 | int __init amd_iommu_init_devices(void) | |
241 | { | |
242 | struct pci_dev *pdev = NULL; | |
243 | int ret = 0; | |
244 | ||
245 | for_each_pci_dev(pdev) { | |
246 | ||
247 | if (!check_device(&pdev->dev)) | |
248 | continue; | |
249 | ||
250 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
251 | if (ret == -ENOTSUPP) |
252 | iommu_ignore_device(&pdev->dev); | |
253 | else if (ret) | |
b7cc9554 JR |
254 | goto out_free; |
255 | } | |
256 | ||
257 | return 0; | |
258 | ||
259 | out_free: | |
260 | ||
261 | amd_iommu_uninit_devices(); | |
262 | ||
263 | return ret; | |
264 | } | |
7f26508b JR |
265 | #ifdef CONFIG_AMD_IOMMU_STATS |
266 | ||
267 | /* | |
268 | * Initialization code for statistics collection | |
269 | */ | |
270 | ||
da49f6df | 271 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 272 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 273 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 274 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 275 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 276 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 277 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 278 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 279 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 280 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 281 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 282 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 283 | |
7f26508b | 284 | static struct dentry *stats_dir; |
7f26508b JR |
285 | static struct dentry *de_fflush; |
286 | ||
287 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
288 | { | |
289 | if (stats_dir == NULL) | |
290 | return; | |
291 | ||
292 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
293 | &cnt->value); | |
294 | } | |
295 | ||
296 | static void amd_iommu_stats_init(void) | |
297 | { | |
298 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
299 | if (stats_dir == NULL) | |
300 | return; | |
301 | ||
7f26508b JR |
302 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
303 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
304 | |
305 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 306 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 307 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 308 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 309 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 310 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 311 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 312 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 313 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 314 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 315 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 316 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
317 | } |
318 | ||
319 | #endif | |
320 | ||
a80dc3e0 JR |
321 | /**************************************************************************** |
322 | * | |
323 | * Interrupt handling functions | |
324 | * | |
325 | ****************************************************************************/ | |
326 | ||
e3e59876 JR |
327 | static void dump_dte_entry(u16 devid) |
328 | { | |
329 | int i; | |
330 | ||
331 | for (i = 0; i < 8; ++i) | |
332 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
333 | amd_iommu_dev_table[devid].data[i]); | |
334 | } | |
335 | ||
945b4ac4 JR |
336 | static void dump_command(unsigned long phys_addr) |
337 | { | |
338 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
339 | int i; | |
340 | ||
341 | for (i = 0; i < 4; ++i) | |
342 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
343 | } | |
344 | ||
a345b23b | 345 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
346 | { |
347 | u32 *event = __evt; | |
348 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
349 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
350 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
351 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
352 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
353 | ||
4c6f40d4 | 354 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
355 | |
356 | switch (type) { | |
357 | case EVENT_TYPE_ILL_DEV: | |
358 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
359 | "address=0x%016llx flags=0x%04x]\n", | |
360 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
361 | address, flags); | |
e3e59876 | 362 | dump_dte_entry(devid); |
90008ee4 JR |
363 | break; |
364 | case EVENT_TYPE_IO_FAULT: | |
365 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
366 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
367 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
368 | domid, address, flags); | |
369 | break; | |
370 | case EVENT_TYPE_DEV_TAB_ERR: | |
371 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
372 | "address=0x%016llx flags=0x%04x]\n", | |
373 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
374 | address, flags); | |
375 | break; | |
376 | case EVENT_TYPE_PAGE_TAB_ERR: | |
377 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
378 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
379 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
380 | domid, address, flags); | |
381 | break; | |
382 | case EVENT_TYPE_ILL_CMD: | |
383 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 384 | dump_command(address); |
90008ee4 JR |
385 | break; |
386 | case EVENT_TYPE_CMD_HARD_ERR: | |
387 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
388 | "flags=0x%04x]\n", address, flags); | |
389 | break; | |
390 | case EVENT_TYPE_IOTLB_INV_TO: | |
391 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
392 | "address=0x%016llx]\n", | |
393 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
394 | address); | |
395 | break; | |
396 | case EVENT_TYPE_INV_DEV_REQ: | |
397 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
398 | "address=0x%016llx flags=0x%04x]\n", | |
399 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
400 | address, flags); | |
401 | break; | |
402 | default: | |
403 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
404 | } | |
405 | } | |
406 | ||
407 | static void iommu_poll_events(struct amd_iommu *iommu) | |
408 | { | |
409 | u32 head, tail; | |
410 | unsigned long flags; | |
411 | ||
412 | spin_lock_irqsave(&iommu->lock, flags); | |
413 | ||
414 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
415 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
416 | ||
417 | while (head != tail) { | |
a345b23b | 418 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
419 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
420 | } | |
421 | ||
422 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
423 | ||
424 | spin_unlock_irqrestore(&iommu->lock, flags); | |
425 | } | |
426 | ||
72fe00f0 | 427 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 428 | { |
90008ee4 JR |
429 | struct amd_iommu *iommu; |
430 | ||
3bd22172 | 431 | for_each_iommu(iommu) |
90008ee4 JR |
432 | iommu_poll_events(iommu); |
433 | ||
434 | return IRQ_HANDLED; | |
a80dc3e0 JR |
435 | } |
436 | ||
72fe00f0 JR |
437 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
438 | { | |
439 | return IRQ_WAKE_THREAD; | |
440 | } | |
441 | ||
431b2a20 JR |
442 | /**************************************************************************** |
443 | * | |
444 | * IOMMU command queuing functions | |
445 | * | |
446 | ****************************************************************************/ | |
447 | ||
ac0ea6e9 JR |
448 | static int wait_on_sem(volatile u64 *sem) |
449 | { | |
450 | int i = 0; | |
451 | ||
452 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
453 | udelay(1); | |
454 | i += 1; | |
455 | } | |
456 | ||
457 | if (i == LOOP_TIMEOUT) { | |
458 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
459 | return -EIO; | |
460 | } | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
466 | struct iommu_cmd *cmd, | |
467 | u32 tail) | |
a19ae1ec | 468 | { |
a19ae1ec JR |
469 | u8 *target; |
470 | ||
8a7c5ef3 | 471 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
472 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
473 | ||
474 | /* Copy command to buffer */ | |
475 | memcpy(target, cmd, sizeof(*cmd)); | |
476 | ||
477 | /* Tell the IOMMU about it */ | |
a19ae1ec | 478 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 479 | } |
a19ae1ec | 480 | |
815b33fd | 481 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 482 | { |
815b33fd JR |
483 | WARN_ON(address & 0x7ULL); |
484 | ||
ded46737 | 485 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
486 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
487 | cmd->data[1] = upper_32_bits(__pa(address)); | |
488 | cmd->data[2] = 1; | |
ded46737 JR |
489 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
490 | } | |
491 | ||
94fe79e2 JR |
492 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
493 | { | |
494 | memset(cmd, 0, sizeof(*cmd)); | |
495 | cmd->data[0] = devid; | |
496 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
497 | } | |
498 | ||
11b6402c JR |
499 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
500 | size_t size, u16 domid, int pde) | |
501 | { | |
502 | u64 pages; | |
503 | int s; | |
504 | ||
505 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
506 | s = 0; | |
507 | ||
508 | if (pages > 1) { | |
509 | /* | |
510 | * If we have to flush more than one page, flush all | |
511 | * TLB entries for this domain | |
512 | */ | |
513 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
514 | s = 1; | |
515 | } | |
516 | ||
517 | address &= PAGE_MASK; | |
518 | ||
519 | memset(cmd, 0, sizeof(*cmd)); | |
520 | cmd->data[1] |= domid; | |
521 | cmd->data[2] = lower_32_bits(address); | |
522 | cmd->data[3] = upper_32_bits(address); | |
523 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
524 | if (s) /* size bit - we flush more than one 4kb page */ | |
525 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
526 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
527 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
528 | } | |
529 | ||
cb41ed85 JR |
530 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
531 | u64 address, size_t size) | |
532 | { | |
533 | u64 pages; | |
534 | int s; | |
535 | ||
536 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
537 | s = 0; | |
538 | ||
539 | if (pages > 1) { | |
540 | /* | |
541 | * If we have to flush more than one page, flush all | |
542 | * TLB entries for this domain | |
543 | */ | |
544 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
545 | s = 1; | |
546 | } | |
547 | ||
548 | address &= PAGE_MASK; | |
549 | ||
550 | memset(cmd, 0, sizeof(*cmd)); | |
551 | cmd->data[0] = devid; | |
552 | cmd->data[0] |= (qdep & 0xff) << 24; | |
553 | cmd->data[1] = devid; | |
554 | cmd->data[2] = lower_32_bits(address); | |
555 | cmd->data[3] = upper_32_bits(address); | |
556 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
557 | if (s) | |
558 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
559 | } | |
560 | ||
58fc7f14 JR |
561 | static void build_inv_all(struct iommu_cmd *cmd) |
562 | { | |
563 | memset(cmd, 0, sizeof(*cmd)); | |
564 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
565 | } |
566 | ||
431b2a20 | 567 | /* |
431b2a20 | 568 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 569 | * hardware about the new command. |
431b2a20 | 570 | */ |
d6449536 | 571 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 572 | { |
ac0ea6e9 | 573 | u32 left, tail, head, next_tail; |
a19ae1ec | 574 | unsigned long flags; |
a19ae1ec | 575 | |
549c90dc | 576 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
577 | |
578 | again: | |
a19ae1ec | 579 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 580 | |
ac0ea6e9 JR |
581 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
582 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
583 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
584 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 585 | |
ac0ea6e9 JR |
586 | if (left <= 2) { |
587 | struct iommu_cmd sync_cmd; | |
588 | volatile u64 sem = 0; | |
589 | int ret; | |
8d201968 | 590 | |
ac0ea6e9 JR |
591 | build_completion_wait(&sync_cmd, (u64)&sem); |
592 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 593 | |
ac0ea6e9 JR |
594 | spin_unlock_irqrestore(&iommu->lock, flags); |
595 | ||
596 | if ((ret = wait_on_sem(&sem)) != 0) | |
597 | return ret; | |
598 | ||
599 | goto again; | |
8d201968 JR |
600 | } |
601 | ||
ac0ea6e9 JR |
602 | copy_cmd_to_buffer(iommu, cmd, tail); |
603 | ||
604 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 605 | iommu->need_sync = true; |
ac0ea6e9 | 606 | |
a19ae1ec | 607 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 608 | |
815b33fd | 609 | return 0; |
8d201968 JR |
610 | } |
611 | ||
612 | /* | |
613 | * This function queues a completion wait command into the command | |
614 | * buffer of an IOMMU | |
615 | */ | |
a19ae1ec | 616 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
617 | { |
618 | struct iommu_cmd cmd; | |
815b33fd | 619 | volatile u64 sem = 0; |
ac0ea6e9 | 620 | int ret; |
8d201968 | 621 | |
09ee17eb | 622 | if (!iommu->need_sync) |
815b33fd | 623 | return 0; |
09ee17eb | 624 | |
815b33fd | 625 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 626 | |
815b33fd | 627 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 628 | if (ret) |
815b33fd | 629 | return ret; |
8d201968 | 630 | |
ac0ea6e9 | 631 | return wait_on_sem(&sem); |
8d201968 JR |
632 | } |
633 | ||
d8c13085 | 634 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 635 | { |
d8c13085 | 636 | struct iommu_cmd cmd; |
a19ae1ec | 637 | |
d8c13085 | 638 | build_inv_dte(&cmd, devid); |
7e4f88da | 639 | |
d8c13085 JR |
640 | return iommu_queue_command(iommu, &cmd); |
641 | } | |
09ee17eb | 642 | |
7d0c5cc5 JR |
643 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
644 | { | |
645 | u32 devid; | |
09ee17eb | 646 | |
7d0c5cc5 JR |
647 | for (devid = 0; devid <= 0xffff; ++devid) |
648 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 649 | |
7d0c5cc5 JR |
650 | iommu_completion_wait(iommu); |
651 | } | |
84df8175 | 652 | |
7d0c5cc5 JR |
653 | /* |
654 | * This function uses heavy locking and may disable irqs for some time. But | |
655 | * this is no issue because it is only called during resume. | |
656 | */ | |
657 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
658 | { | |
659 | u32 dom_id; | |
a19ae1ec | 660 | |
7d0c5cc5 JR |
661 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
662 | struct iommu_cmd cmd; | |
663 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
664 | dom_id, 1); | |
665 | iommu_queue_command(iommu, &cmd); | |
666 | } | |
8eed9833 | 667 | |
7d0c5cc5 | 668 | iommu_completion_wait(iommu); |
a19ae1ec JR |
669 | } |
670 | ||
58fc7f14 | 671 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 672 | { |
58fc7f14 | 673 | struct iommu_cmd cmd; |
0518a3a4 | 674 | |
58fc7f14 | 675 | build_inv_all(&cmd); |
0518a3a4 | 676 | |
58fc7f14 JR |
677 | iommu_queue_command(iommu, &cmd); |
678 | iommu_completion_wait(iommu); | |
679 | } | |
680 | ||
7d0c5cc5 JR |
681 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
682 | { | |
58fc7f14 JR |
683 | if (iommu_feature(iommu, FEATURE_IA)) { |
684 | iommu_flush_all(iommu); | |
685 | } else { | |
686 | iommu_flush_dte_all(iommu); | |
687 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
688 | } |
689 | } | |
690 | ||
431b2a20 | 691 | /* |
cb41ed85 | 692 | * Command send function for flushing on-device TLB |
431b2a20 | 693 | */ |
6c542047 JR |
694 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
695 | u64 address, size_t size) | |
3fa43655 JR |
696 | { |
697 | struct amd_iommu *iommu; | |
b00d3bcf | 698 | struct iommu_cmd cmd; |
cb41ed85 | 699 | int qdep; |
3fa43655 | 700 | |
ea61cddb JR |
701 | qdep = dev_data->ats.qdep; |
702 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 703 | |
ea61cddb | 704 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
705 | |
706 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
707 | } |
708 | ||
431b2a20 | 709 | /* |
431b2a20 | 710 | * Command send function for invalidating a device table entry |
431b2a20 | 711 | */ |
6c542047 | 712 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 713 | { |
3fa43655 | 714 | struct amd_iommu *iommu; |
ee2fa743 | 715 | int ret; |
a19ae1ec | 716 | |
6c542047 | 717 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 718 | |
f62dda66 | 719 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
720 | if (ret) |
721 | return ret; | |
722 | ||
ea61cddb | 723 | if (dev_data->ats.enabled) |
6c542047 | 724 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 725 | |
ee2fa743 | 726 | return ret; |
a19ae1ec JR |
727 | } |
728 | ||
431b2a20 JR |
729 | /* |
730 | * TLB invalidation function which is called from the mapping functions. | |
731 | * It invalidates a single PTE if the range to flush is within a single | |
732 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
733 | */ | |
17b124bf JR |
734 | static void __domain_flush_pages(struct protection_domain *domain, |
735 | u64 address, size_t size, int pde) | |
a19ae1ec | 736 | { |
cb41ed85 | 737 | struct iommu_dev_data *dev_data; |
11b6402c JR |
738 | struct iommu_cmd cmd; |
739 | int ret = 0, i; | |
a19ae1ec | 740 | |
11b6402c | 741 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 742 | |
6de8ad9b JR |
743 | for (i = 0; i < amd_iommus_present; ++i) { |
744 | if (!domain->dev_iommu[i]) | |
745 | continue; | |
746 | ||
747 | /* | |
748 | * Devices of this domain are behind this IOMMU | |
749 | * We need a TLB flush | |
750 | */ | |
11b6402c | 751 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
752 | } |
753 | ||
cb41ed85 | 754 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 755 | |
ea61cddb | 756 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
757 | continue; |
758 | ||
6c542047 | 759 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
760 | } |
761 | ||
11b6402c | 762 | WARN_ON(ret); |
6de8ad9b JR |
763 | } |
764 | ||
17b124bf JR |
765 | static void domain_flush_pages(struct protection_domain *domain, |
766 | u64 address, size_t size) | |
6de8ad9b | 767 | { |
17b124bf | 768 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 769 | } |
b6c02715 | 770 | |
1c655773 | 771 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 772 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 773 | { |
17b124bf | 774 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
775 | } |
776 | ||
42a49f96 | 777 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 778 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 779 | { |
17b124bf | 780 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
781 | } |
782 | ||
17b124bf | 783 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 784 | { |
17b124bf | 785 | int i; |
18811f55 | 786 | |
17b124bf JR |
787 | for (i = 0; i < amd_iommus_present; ++i) { |
788 | if (!domain->dev_iommu[i]) | |
789 | continue; | |
bfd1be18 | 790 | |
17b124bf JR |
791 | /* |
792 | * Devices of this domain are behind this IOMMU | |
793 | * We need to wait for completion of all commands. | |
794 | */ | |
795 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 796 | } |
e394d72a JR |
797 | } |
798 | ||
b00d3bcf | 799 | |
09b42804 | 800 | /* |
b00d3bcf | 801 | * This function flushes the DTEs for all devices in domain |
09b42804 | 802 | */ |
17b124bf | 803 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 804 | { |
b00d3bcf | 805 | struct iommu_dev_data *dev_data; |
09b42804 JR |
806 | unsigned long flags; |
807 | ||
b00d3bcf | 808 | spin_lock_irqsave(&domain->lock, flags); |
b26e81b8 | 809 | |
b00d3bcf | 810 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 811 | device_flush_dte(dev_data); |
b26e81b8 | 812 | |
b00d3bcf | 813 | spin_unlock_irqrestore(&domain->lock, flags); |
a345b23b JR |
814 | } |
815 | ||
431b2a20 JR |
816 | /**************************************************************************** |
817 | * | |
818 | * The functions below are used the create the page table mappings for | |
819 | * unity mapped regions. | |
820 | * | |
821 | ****************************************************************************/ | |
822 | ||
308973d3 JR |
823 | /* |
824 | * This function is used to add another level to an IO page table. Adding | |
825 | * another level increases the size of the address space by 9 bits to a size up | |
826 | * to 64 bits. | |
827 | */ | |
828 | static bool increase_address_space(struct protection_domain *domain, | |
829 | gfp_t gfp) | |
830 | { | |
831 | u64 *pte; | |
832 | ||
833 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
834 | /* address space already 64 bit large */ | |
835 | return false; | |
836 | ||
837 | pte = (void *)get_zeroed_page(gfp); | |
838 | if (!pte) | |
839 | return false; | |
840 | ||
841 | *pte = PM_LEVEL_PDE(domain->mode, | |
842 | virt_to_phys(domain->pt_root)); | |
843 | domain->pt_root = pte; | |
844 | domain->mode += 1; | |
845 | domain->updated = true; | |
846 | ||
847 | return true; | |
848 | } | |
849 | ||
850 | static u64 *alloc_pte(struct protection_domain *domain, | |
851 | unsigned long address, | |
cbb9d729 | 852 | unsigned long page_size, |
308973d3 JR |
853 | u64 **pte_page, |
854 | gfp_t gfp) | |
855 | { | |
cbb9d729 | 856 | int level, end_lvl; |
308973d3 | 857 | u64 *pte, *page; |
cbb9d729 JR |
858 | |
859 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
860 | |
861 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
862 | increase_address_space(domain, gfp); | |
863 | ||
cbb9d729 JR |
864 | level = domain->mode - 1; |
865 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
866 | address = PAGE_SIZE_ALIGN(address, page_size); | |
867 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
868 | |
869 | while (level > end_lvl) { | |
870 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
871 | page = (u64 *)get_zeroed_page(gfp); | |
872 | if (!page) | |
873 | return NULL; | |
874 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
875 | } | |
876 | ||
cbb9d729 JR |
877 | /* No level skipping support yet */ |
878 | if (PM_PTE_LEVEL(*pte) != level) | |
879 | return NULL; | |
880 | ||
308973d3 JR |
881 | level -= 1; |
882 | ||
883 | pte = IOMMU_PTE_PAGE(*pte); | |
884 | ||
885 | if (pte_page && level == end_lvl) | |
886 | *pte_page = pte; | |
887 | ||
888 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
889 | } | |
890 | ||
891 | return pte; | |
892 | } | |
893 | ||
894 | /* | |
895 | * This function checks if there is a PTE for a given dma address. If | |
896 | * there is one, it returns the pointer to it. | |
897 | */ | |
24cd7723 | 898 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
899 | { |
900 | int level; | |
901 | u64 *pte; | |
902 | ||
24cd7723 JR |
903 | if (address > PM_LEVEL_SIZE(domain->mode)) |
904 | return NULL; | |
905 | ||
906 | level = domain->mode - 1; | |
907 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 908 | |
24cd7723 JR |
909 | while (level > 0) { |
910 | ||
911 | /* Not Present */ | |
308973d3 JR |
912 | if (!IOMMU_PTE_PRESENT(*pte)) |
913 | return NULL; | |
914 | ||
24cd7723 JR |
915 | /* Large PTE */ |
916 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
917 | unsigned long pte_mask, __pte; | |
918 | ||
919 | /* | |
920 | * If we have a series of large PTEs, make | |
921 | * sure to return a pointer to the first one. | |
922 | */ | |
923 | pte_mask = PTE_PAGE_SIZE(*pte); | |
924 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
925 | __pte = ((unsigned long)pte) & pte_mask; | |
926 | ||
927 | return (u64 *)__pte; | |
928 | } | |
929 | ||
930 | /* No level skipping support yet */ | |
931 | if (PM_PTE_LEVEL(*pte) != level) | |
932 | return NULL; | |
933 | ||
308973d3 JR |
934 | level -= 1; |
935 | ||
24cd7723 | 936 | /* Walk to the next level */ |
308973d3 JR |
937 | pte = IOMMU_PTE_PAGE(*pte); |
938 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
939 | } |
940 | ||
941 | return pte; | |
942 | } | |
943 | ||
431b2a20 JR |
944 | /* |
945 | * Generic mapping functions. It maps a physical address into a DMA | |
946 | * address space. It allocates the page table pages if necessary. | |
947 | * In the future it can be extended to a generic mapping function | |
948 | * supporting all features of AMD IOMMU page tables like level skipping | |
949 | * and full 64 bit address spaces. | |
950 | */ | |
38e817fe JR |
951 | static int iommu_map_page(struct protection_domain *dom, |
952 | unsigned long bus_addr, | |
953 | unsigned long phys_addr, | |
abdc5eb3 | 954 | int prot, |
cbb9d729 | 955 | unsigned long page_size) |
bd0e5211 | 956 | { |
8bda3092 | 957 | u64 __pte, *pte; |
cbb9d729 | 958 | int i, count; |
abdc5eb3 | 959 | |
bad1cac2 | 960 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
961 | return -EINVAL; |
962 | ||
cbb9d729 JR |
963 | bus_addr = PAGE_ALIGN(bus_addr); |
964 | phys_addr = PAGE_ALIGN(phys_addr); | |
965 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
966 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
967 | ||
968 | for (i = 0; i < count; ++i) | |
969 | if (IOMMU_PTE_PRESENT(pte[i])) | |
970 | return -EBUSY; | |
bd0e5211 | 971 | |
cbb9d729 JR |
972 | if (page_size > PAGE_SIZE) { |
973 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
974 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
975 | } else | |
976 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 977 | |
bd0e5211 JR |
978 | if (prot & IOMMU_PROT_IR) |
979 | __pte |= IOMMU_PTE_IR; | |
980 | if (prot & IOMMU_PROT_IW) | |
981 | __pte |= IOMMU_PTE_IW; | |
982 | ||
cbb9d729 JR |
983 | for (i = 0; i < count; ++i) |
984 | pte[i] = __pte; | |
bd0e5211 | 985 | |
04bfdd84 JR |
986 | update_domain(dom); |
987 | ||
bd0e5211 JR |
988 | return 0; |
989 | } | |
990 | ||
24cd7723 JR |
991 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
992 | unsigned long bus_addr, | |
993 | unsigned long page_size) | |
eb74ff6c | 994 | { |
24cd7723 JR |
995 | unsigned long long unmap_size, unmapped; |
996 | u64 *pte; | |
997 | ||
998 | BUG_ON(!is_power_of_2(page_size)); | |
999 | ||
1000 | unmapped = 0; | |
eb74ff6c | 1001 | |
24cd7723 JR |
1002 | while (unmapped < page_size) { |
1003 | ||
1004 | pte = fetch_pte(dom, bus_addr); | |
1005 | ||
1006 | if (!pte) { | |
1007 | /* | |
1008 | * No PTE for this address | |
1009 | * move forward in 4kb steps | |
1010 | */ | |
1011 | unmap_size = PAGE_SIZE; | |
1012 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1013 | /* 4kb PTE found for this address */ | |
1014 | unmap_size = PAGE_SIZE; | |
1015 | *pte = 0ULL; | |
1016 | } else { | |
1017 | int count, i; | |
1018 | ||
1019 | /* Large PTE found which maps this address */ | |
1020 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1021 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1022 | for (i = 0; i < count; i++) | |
1023 | pte[i] = 0ULL; | |
1024 | } | |
1025 | ||
1026 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1027 | unmapped += unmap_size; | |
1028 | } | |
1029 | ||
1030 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1031 | |
24cd7723 | 1032 | return unmapped; |
eb74ff6c | 1033 | } |
eb74ff6c | 1034 | |
431b2a20 JR |
1035 | /* |
1036 | * This function checks if a specific unity mapping entry is needed for | |
1037 | * this specific IOMMU. | |
1038 | */ | |
bd0e5211 JR |
1039 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1040 | struct unity_map_entry *entry) | |
1041 | { | |
1042 | u16 bdf, i; | |
1043 | ||
1044 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1045 | bdf = amd_iommu_alias_table[i]; | |
1046 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1047 | return 1; | |
1048 | } | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
431b2a20 JR |
1053 | /* |
1054 | * This function actually applies the mapping to the page table of the | |
1055 | * dma_ops domain. | |
1056 | */ | |
bd0e5211 JR |
1057 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1058 | struct unity_map_entry *e) | |
1059 | { | |
1060 | u64 addr; | |
1061 | int ret; | |
1062 | ||
1063 | for (addr = e->address_start; addr < e->address_end; | |
1064 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1065 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1066 | PAGE_SIZE); |
bd0e5211 JR |
1067 | if (ret) |
1068 | return ret; | |
1069 | /* | |
1070 | * if unity mapping is in aperture range mark the page | |
1071 | * as allocated in the aperture | |
1072 | */ | |
1073 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1074 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1075 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1076 | } |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
171e7b37 JR |
1081 | /* |
1082 | * Init the unity mappings for a specific IOMMU in the system | |
1083 | * | |
1084 | * Basically iterates over all unity mapping entries and applies them to | |
1085 | * the default domain DMA of that IOMMU if necessary. | |
1086 | */ | |
1087 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1088 | { | |
1089 | struct unity_map_entry *entry; | |
1090 | int ret; | |
1091 | ||
1092 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1093 | if (!iommu_for_unity_map(iommu, entry)) | |
1094 | continue; | |
1095 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1096 | if (ret) | |
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
431b2a20 JR |
1103 | /* |
1104 | * Inits the unity mappings required for a specific device | |
1105 | */ | |
bd0e5211 JR |
1106 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1107 | u16 devid) | |
1108 | { | |
1109 | struct unity_map_entry *e; | |
1110 | int ret; | |
1111 | ||
1112 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1113 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1114 | continue; | |
1115 | ret = dma_ops_unity_map(dma_dom, e); | |
1116 | if (ret) | |
1117 | return ret; | |
1118 | } | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
431b2a20 JR |
1123 | /**************************************************************************** |
1124 | * | |
1125 | * The next functions belong to the address allocator for the dma_ops | |
1126 | * interface functions. They work like the allocators in the other IOMMU | |
1127 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1128 | * the aperture. Maybe it could be enhanced in the future to a more | |
1129 | * efficient allocator. | |
1130 | * | |
1131 | ****************************************************************************/ | |
d3086444 | 1132 | |
431b2a20 | 1133 | /* |
384de729 | 1134 | * The address allocator core functions. |
431b2a20 JR |
1135 | * |
1136 | * called with domain->lock held | |
1137 | */ | |
384de729 | 1138 | |
171e7b37 JR |
1139 | /* |
1140 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1141 | * ranges. | |
1142 | */ | |
1143 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1144 | unsigned long start_page, | |
1145 | unsigned int pages) | |
1146 | { | |
1147 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1148 | ||
1149 | if (start_page + pages > last_page) | |
1150 | pages = last_page - start_page; | |
1151 | ||
1152 | for (i = start_page; i < start_page + pages; ++i) { | |
1153 | int index = i / APERTURE_RANGE_PAGES; | |
1154 | int page = i % APERTURE_RANGE_PAGES; | |
1155 | __set_bit(page, dom->aperture[index]->bitmap); | |
1156 | } | |
1157 | } | |
1158 | ||
9cabe89b JR |
1159 | /* |
1160 | * This function is used to add a new aperture range to an existing | |
1161 | * aperture in case of dma_ops domain allocation or address allocation | |
1162 | * failure. | |
1163 | */ | |
576175c2 | 1164 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1165 | bool populate, gfp_t gfp) |
1166 | { | |
1167 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1168 | struct amd_iommu *iommu; |
d91afd15 | 1169 | unsigned long i; |
9cabe89b | 1170 | |
f5e9705c JR |
1171 | #ifdef CONFIG_IOMMU_STRESS |
1172 | populate = false; | |
1173 | #endif | |
1174 | ||
9cabe89b JR |
1175 | if (index >= APERTURE_MAX_RANGES) |
1176 | return -ENOMEM; | |
1177 | ||
1178 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1179 | if (!dma_dom->aperture[index]) | |
1180 | return -ENOMEM; | |
1181 | ||
1182 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1183 | if (!dma_dom->aperture[index]->bitmap) | |
1184 | goto out_free; | |
1185 | ||
1186 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1187 | ||
1188 | if (populate) { | |
1189 | unsigned long address = dma_dom->aperture_size; | |
1190 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1191 | u64 *pte, *pte_page; | |
1192 | ||
1193 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1194 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1195 | &pte_page, gfp); |
1196 | if (!pte) | |
1197 | goto out_free; | |
1198 | ||
1199 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1200 | ||
1201 | address += APERTURE_RANGE_SIZE / 64; | |
1202 | } | |
1203 | } | |
1204 | ||
1205 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1206 | ||
b595076a | 1207 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1208 | for_each_iommu(iommu) { |
1209 | if (iommu->exclusion_start && | |
1210 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1211 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1212 | unsigned long startpage; | |
1213 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1214 | iommu->exclusion_length, | |
1215 | PAGE_SIZE); | |
1216 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1217 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1218 | } | |
00cd122a JR |
1219 | } |
1220 | ||
1221 | /* | |
1222 | * Check for areas already mapped as present in the new aperture | |
1223 | * range and mark those pages as reserved in the allocator. Such | |
1224 | * mappings may already exist as a result of requested unity | |
1225 | * mappings for devices. | |
1226 | */ | |
1227 | for (i = dma_dom->aperture[index]->offset; | |
1228 | i < dma_dom->aperture_size; | |
1229 | i += PAGE_SIZE) { | |
24cd7723 | 1230 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1231 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1232 | continue; | |
1233 | ||
1234 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1235 | } | |
1236 | ||
04bfdd84 JR |
1237 | update_domain(&dma_dom->domain); |
1238 | ||
9cabe89b JR |
1239 | return 0; |
1240 | ||
1241 | out_free: | |
04bfdd84 JR |
1242 | update_domain(&dma_dom->domain); |
1243 | ||
9cabe89b JR |
1244 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1245 | ||
1246 | kfree(dma_dom->aperture[index]); | |
1247 | dma_dom->aperture[index] = NULL; | |
1248 | ||
1249 | return -ENOMEM; | |
1250 | } | |
1251 | ||
384de729 JR |
1252 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1253 | struct dma_ops_domain *dom, | |
1254 | unsigned int pages, | |
1255 | unsigned long align_mask, | |
1256 | u64 dma_mask, | |
1257 | unsigned long start) | |
1258 | { | |
803b8cb4 | 1259 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1260 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1261 | int i = start >> APERTURE_RANGE_SHIFT; | |
1262 | unsigned long boundary_size; | |
1263 | unsigned long address = -1; | |
1264 | unsigned long limit; | |
1265 | ||
803b8cb4 JR |
1266 | next_bit >>= PAGE_SHIFT; |
1267 | ||
384de729 JR |
1268 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1269 | PAGE_SIZE) >> PAGE_SHIFT; | |
1270 | ||
1271 | for (;i < max_index; ++i) { | |
1272 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1273 | ||
1274 | if (dom->aperture[i]->offset >= dma_mask) | |
1275 | break; | |
1276 | ||
1277 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1278 | dma_mask >> PAGE_SHIFT); | |
1279 | ||
1280 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1281 | limit, next_bit, pages, 0, | |
1282 | boundary_size, align_mask); | |
1283 | if (address != -1) { | |
1284 | address = dom->aperture[i]->offset + | |
1285 | (address << PAGE_SHIFT); | |
803b8cb4 | 1286 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1287 | break; |
1288 | } | |
1289 | ||
1290 | next_bit = 0; | |
1291 | } | |
1292 | ||
1293 | return address; | |
1294 | } | |
1295 | ||
d3086444 JR |
1296 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1297 | struct dma_ops_domain *dom, | |
6d4f343f | 1298 | unsigned int pages, |
832a90c3 JR |
1299 | unsigned long align_mask, |
1300 | u64 dma_mask) | |
d3086444 | 1301 | { |
d3086444 | 1302 | unsigned long address; |
d3086444 | 1303 | |
fe16f088 JR |
1304 | #ifdef CONFIG_IOMMU_STRESS |
1305 | dom->next_address = 0; | |
1306 | dom->need_flush = true; | |
1307 | #endif | |
d3086444 | 1308 | |
384de729 | 1309 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1310 | dma_mask, dom->next_address); |
d3086444 | 1311 | |
1c655773 | 1312 | if (address == -1) { |
803b8cb4 | 1313 | dom->next_address = 0; |
384de729 JR |
1314 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1315 | dma_mask, 0); | |
1c655773 JR |
1316 | dom->need_flush = true; |
1317 | } | |
d3086444 | 1318 | |
384de729 | 1319 | if (unlikely(address == -1)) |
8fd524b3 | 1320 | address = DMA_ERROR_CODE; |
d3086444 JR |
1321 | |
1322 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1323 | ||
1324 | return address; | |
1325 | } | |
1326 | ||
431b2a20 JR |
1327 | /* |
1328 | * The address free function. | |
1329 | * | |
1330 | * called with domain->lock held | |
1331 | */ | |
d3086444 JR |
1332 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1333 | unsigned long address, | |
1334 | unsigned int pages) | |
1335 | { | |
384de729 JR |
1336 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1337 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1338 | |
384de729 JR |
1339 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1340 | ||
47bccd6b JR |
1341 | #ifdef CONFIG_IOMMU_STRESS |
1342 | if (i < 4) | |
1343 | return; | |
1344 | #endif | |
80be308d | 1345 | |
803b8cb4 | 1346 | if (address >= dom->next_address) |
80be308d | 1347 | dom->need_flush = true; |
384de729 JR |
1348 | |
1349 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1350 | |
a66022c4 | 1351 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1352 | |
d3086444 JR |
1353 | } |
1354 | ||
431b2a20 JR |
1355 | /**************************************************************************** |
1356 | * | |
1357 | * The next functions belong to the domain allocation. A domain is | |
1358 | * allocated for every IOMMU as the default domain. If device isolation | |
1359 | * is enabled, every device get its own domain. The most important thing | |
1360 | * about domains is the page table mapping the DMA address space they | |
1361 | * contain. | |
1362 | * | |
1363 | ****************************************************************************/ | |
1364 | ||
aeb26f55 JR |
1365 | /* |
1366 | * This function adds a protection domain to the global protection domain list | |
1367 | */ | |
1368 | static void add_domain_to_list(struct protection_domain *domain) | |
1369 | { | |
1370 | unsigned long flags; | |
1371 | ||
1372 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1373 | list_add(&domain->list, &amd_iommu_pd_list); | |
1374 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1375 | } | |
1376 | ||
1377 | /* | |
1378 | * This function removes a protection domain to the global | |
1379 | * protection domain list | |
1380 | */ | |
1381 | static void del_domain_from_list(struct protection_domain *domain) | |
1382 | { | |
1383 | unsigned long flags; | |
1384 | ||
1385 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1386 | list_del(&domain->list); | |
1387 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1388 | } | |
1389 | ||
ec487d1a JR |
1390 | static u16 domain_id_alloc(void) |
1391 | { | |
1392 | unsigned long flags; | |
1393 | int id; | |
1394 | ||
1395 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1396 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1397 | BUG_ON(id == 0); | |
1398 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1399 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1400 | else | |
1401 | id = 0; | |
1402 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1403 | ||
1404 | return id; | |
1405 | } | |
1406 | ||
a2acfb75 JR |
1407 | static void domain_id_free(int id) |
1408 | { | |
1409 | unsigned long flags; | |
1410 | ||
1411 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1412 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1413 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1414 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1415 | } | |
a2acfb75 | 1416 | |
86db2e5d | 1417 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1418 | { |
1419 | int i, j; | |
1420 | u64 *p1, *p2, *p3; | |
1421 | ||
86db2e5d | 1422 | p1 = domain->pt_root; |
ec487d1a JR |
1423 | |
1424 | if (!p1) | |
1425 | return; | |
1426 | ||
1427 | for (i = 0; i < 512; ++i) { | |
1428 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1429 | continue; | |
1430 | ||
1431 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1432 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1433 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1434 | continue; | |
1435 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1436 | free_page((unsigned long)p3); | |
1437 | } | |
1438 | ||
1439 | free_page((unsigned long)p2); | |
1440 | } | |
1441 | ||
1442 | free_page((unsigned long)p1); | |
86db2e5d JR |
1443 | |
1444 | domain->pt_root = NULL; | |
ec487d1a JR |
1445 | } |
1446 | ||
431b2a20 JR |
1447 | /* |
1448 | * Free a domain, only used if something went wrong in the | |
1449 | * allocation path and we need to free an already allocated page table | |
1450 | */ | |
ec487d1a JR |
1451 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1452 | { | |
384de729 JR |
1453 | int i; |
1454 | ||
ec487d1a JR |
1455 | if (!dom) |
1456 | return; | |
1457 | ||
aeb26f55 JR |
1458 | del_domain_from_list(&dom->domain); |
1459 | ||
86db2e5d | 1460 | free_pagetable(&dom->domain); |
ec487d1a | 1461 | |
384de729 JR |
1462 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1463 | if (!dom->aperture[i]) | |
1464 | continue; | |
1465 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1466 | kfree(dom->aperture[i]); | |
1467 | } | |
ec487d1a JR |
1468 | |
1469 | kfree(dom); | |
1470 | } | |
1471 | ||
431b2a20 JR |
1472 | /* |
1473 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1474 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1475 | * structures required for the dma_ops interface |
1476 | */ | |
87a64d52 | 1477 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1478 | { |
1479 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1480 | |
1481 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1482 | if (!dma_dom) | |
1483 | return NULL; | |
1484 | ||
1485 | spin_lock_init(&dma_dom->domain.lock); | |
1486 | ||
1487 | dma_dom->domain.id = domain_id_alloc(); | |
1488 | if (dma_dom->domain.id == 0) | |
1489 | goto free_dma_dom; | |
7c392cbe | 1490 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1491 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1492 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1493 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1494 | dma_dom->domain.priv = dma_dom; |
1495 | if (!dma_dom->domain.pt_root) | |
1496 | goto free_dma_dom; | |
ec487d1a | 1497 | |
1c655773 | 1498 | dma_dom->need_flush = false; |
bd60b735 | 1499 | dma_dom->target_dev = 0xffff; |
1c655773 | 1500 | |
aeb26f55 JR |
1501 | add_domain_to_list(&dma_dom->domain); |
1502 | ||
576175c2 | 1503 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1504 | goto free_dma_dom; |
ec487d1a | 1505 | |
431b2a20 | 1506 | /* |
ec487d1a JR |
1507 | * mark the first page as allocated so we never return 0 as |
1508 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1509 | */ |
384de729 | 1510 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1511 | dma_dom->next_address = 0; |
ec487d1a | 1512 | |
ec487d1a JR |
1513 | |
1514 | return dma_dom; | |
1515 | ||
1516 | free_dma_dom: | |
1517 | dma_ops_domain_free(dma_dom); | |
1518 | ||
1519 | return NULL; | |
1520 | } | |
1521 | ||
5b28df6f JR |
1522 | /* |
1523 | * little helper function to check whether a given protection domain is a | |
1524 | * dma_ops domain | |
1525 | */ | |
1526 | static bool dma_ops_domain(struct protection_domain *domain) | |
1527 | { | |
1528 | return domain->flags & PD_DMA_OPS_MASK; | |
1529 | } | |
1530 | ||
fd7b5535 | 1531 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1532 | { |
b20ac0d4 | 1533 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1534 | u32 flags = 0; |
863c74eb | 1535 | |
38ddf41b JR |
1536 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1537 | << DEV_ENTRY_MODE_SHIFT; | |
1538 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1539 | |
fd7b5535 JR |
1540 | if (ats) |
1541 | flags |= DTE_FLAG_IOTLB; | |
1542 | ||
1543 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1544 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1545 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1546 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1547 | } |
1548 | ||
1549 | static void clear_dte_entry(u16 devid) | |
1550 | { | |
15898bbc JR |
1551 | /* remove entry from the device table seen by the hardware */ |
1552 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1553 | amd_iommu_dev_table[devid].data[1] = 0; | |
1554 | amd_iommu_dev_table[devid].data[2] = 0; | |
1555 | ||
1556 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1557 | } |
1558 | ||
ec9e79ef JR |
1559 | static void do_attach(struct iommu_dev_data *dev_data, |
1560 | struct protection_domain *domain) | |
7f760ddd | 1561 | { |
7f760ddd | 1562 | struct amd_iommu *iommu; |
ec9e79ef | 1563 | bool ats; |
fd7b5535 | 1564 | |
ec9e79ef JR |
1565 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1566 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1567 | |
1568 | /* Update data structures */ | |
1569 | dev_data->domain = domain; | |
1570 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1571 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1572 | |
1573 | /* Do reference counting */ | |
1574 | domain->dev_iommu[iommu->index] += 1; | |
1575 | domain->dev_cnt += 1; | |
1576 | ||
1577 | /* Flush the DTE entry */ | |
6c542047 | 1578 | device_flush_dte(dev_data); |
7f760ddd JR |
1579 | } |
1580 | ||
ec9e79ef | 1581 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1582 | { |
7f760ddd | 1583 | struct amd_iommu *iommu; |
7f760ddd | 1584 | |
ec9e79ef | 1585 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1586 | |
1587 | /* decrease reference counters */ | |
7f760ddd JR |
1588 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1589 | dev_data->domain->dev_cnt -= 1; | |
1590 | ||
1591 | /* Update data structures */ | |
1592 | dev_data->domain = NULL; | |
1593 | list_del(&dev_data->list); | |
f62dda66 | 1594 | clear_dte_entry(dev_data->devid); |
15898bbc | 1595 | |
7f760ddd | 1596 | /* Flush the DTE entry */ |
6c542047 | 1597 | device_flush_dte(dev_data); |
2b681faf JR |
1598 | } |
1599 | ||
1600 | /* | |
1601 | * If a device is not yet associated with a domain, this function does | |
1602 | * assigns it visible for the hardware | |
1603 | */ | |
ec9e79ef | 1604 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1605 | struct protection_domain *domain) |
2b681faf | 1606 | { |
ec9e79ef | 1607 | struct iommu_dev_data *alias_data; |
84fe6c19 | 1608 | int ret; |
657cbb6b | 1609 | |
657cbb6b | 1610 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd | 1611 | |
657cbb6b JR |
1612 | if (!alias_data) |
1613 | return -EINVAL; | |
15898bbc | 1614 | |
2b681faf JR |
1615 | /* lock domain */ |
1616 | spin_lock(&domain->lock); | |
1617 | ||
15898bbc | 1618 | /* Some sanity checks */ |
84fe6c19 | 1619 | ret = -EBUSY; |
657cbb6b JR |
1620 | if (alias_data->domain != NULL && |
1621 | alias_data->domain != domain) | |
84fe6c19 | 1622 | goto out_unlock; |
eba6ac60 | 1623 | |
657cbb6b JR |
1624 | if (dev_data->domain != NULL && |
1625 | dev_data->domain != domain) | |
84fe6c19 | 1626 | goto out_unlock; |
15898bbc JR |
1627 | |
1628 | /* Do real assignment */ | |
ec9e79ef | 1629 | if (dev_data->devid != alias_data->devid) { |
7f760ddd | 1630 | if (alias_data->domain == NULL) |
ec9e79ef | 1631 | do_attach(alias_data, domain); |
24100055 JR |
1632 | |
1633 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1634 | } |
15898bbc | 1635 | |
7f760ddd | 1636 | if (dev_data->domain == NULL) |
ec9e79ef | 1637 | do_attach(dev_data, domain); |
eba6ac60 | 1638 | |
24100055 JR |
1639 | atomic_inc(&dev_data->bind); |
1640 | ||
84fe6c19 JL |
1641 | ret = 0; |
1642 | ||
1643 | out_unlock: | |
1644 | ||
eba6ac60 JR |
1645 | /* ready */ |
1646 | spin_unlock(&domain->lock); | |
15898bbc | 1647 | |
84fe6c19 | 1648 | return ret; |
0feae533 | 1649 | } |
b20ac0d4 | 1650 | |
407d733e JR |
1651 | /* |
1652 | * If a device is not yet associated with a domain, this function does | |
1653 | * assigns it visible for the hardware | |
1654 | */ | |
15898bbc JR |
1655 | static int attach_device(struct device *dev, |
1656 | struct protection_domain *domain) | |
0feae533 | 1657 | { |
fd7b5535 | 1658 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 1659 | struct iommu_dev_data *dev_data; |
eba6ac60 | 1660 | unsigned long flags; |
15898bbc | 1661 | int ret; |
eba6ac60 | 1662 | |
ea61cddb JR |
1663 | dev_data = get_dev_data(dev); |
1664 | ||
1665 | if (amd_iommu_iotlb_sup && pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
1666 | dev_data->ats.enabled = true; | |
1667 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1668 | } | |
fd7b5535 | 1669 | |
eba6ac60 | 1670 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 1671 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
1672 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1673 | ||
0feae533 JR |
1674 | /* |
1675 | * We might boot into a crash-kernel here. The crashed kernel | |
1676 | * left the caches in the IOMMU dirty. So we have to flush | |
1677 | * here to evict all dirty stuff. | |
1678 | */ | |
17b124bf | 1679 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1680 | |
1681 | return ret; | |
b20ac0d4 JR |
1682 | } |
1683 | ||
355bf553 JR |
1684 | /* |
1685 | * Removes a device from a protection domain (unlocked) | |
1686 | */ | |
ec9e79ef | 1687 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 1688 | { |
24100055 | 1689 | struct iommu_dev_data *alias_data; |
2ca76279 | 1690 | struct protection_domain *domain; |
7c392cbe | 1691 | unsigned long flags; |
c4596114 | 1692 | |
7f760ddd | 1693 | BUG_ON(!dev_data->domain); |
355bf553 | 1694 | |
2ca76279 JR |
1695 | domain = dev_data->domain; |
1696 | ||
1697 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1698 | |
ec9e79ef JR |
1699 | alias_data = get_dev_data(dev_data->alias); |
1700 | if (dev_data->devid != alias_data->devid) { | |
7f760ddd | 1701 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 1702 | do_detach(alias_data); |
24100055 JR |
1703 | } |
1704 | ||
7f760ddd | 1705 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 1706 | do_detach(dev_data); |
7f760ddd | 1707 | |
2ca76279 | 1708 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1709 | |
1710 | /* | |
1711 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1712 | * passthrough domain if it is detached from any other domain. |
1713 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1714 | */ |
d3ad9373 JR |
1715 | if (iommu_pass_through && |
1716 | (dev_data->domain == NULL && domain != pt_domain)) | |
ec9e79ef | 1717 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
1718 | } |
1719 | ||
1720 | /* | |
1721 | * Removes a device from a protection domain (with devtable_lock held) | |
1722 | */ | |
15898bbc | 1723 | static void detach_device(struct device *dev) |
355bf553 | 1724 | { |
ea61cddb | 1725 | struct iommu_dev_data *dev_data; |
355bf553 JR |
1726 | unsigned long flags; |
1727 | ||
ec9e79ef JR |
1728 | dev_data = get_dev_data(dev); |
1729 | ||
355bf553 JR |
1730 | /* lock device table */ |
1731 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 1732 | __detach_device(dev_data); |
355bf553 | 1733 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 1734 | |
ea61cddb JR |
1735 | if (dev_data->ats.enabled) { |
1736 | pci_disable_ats(to_pci_dev(dev)); | |
1737 | dev_data->ats.enabled = false; | |
1738 | } | |
355bf553 | 1739 | } |
e275a2a0 | 1740 | |
15898bbc JR |
1741 | /* |
1742 | * Find out the protection domain structure for a given PCI device. This | |
1743 | * will give us the pointer to the page table root for example. | |
1744 | */ | |
1745 | static struct protection_domain *domain_for_device(struct device *dev) | |
1746 | { | |
1747 | struct protection_domain *dom; | |
657cbb6b | 1748 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc | 1749 | unsigned long flags; |
15898bbc | 1750 | |
657cbb6b JR |
1751 | dev_data = get_dev_data(dev); |
1752 | alias_data = get_dev_data(dev_data->alias); | |
1753 | if (!alias_data) | |
1754 | return NULL; | |
15898bbc JR |
1755 | |
1756 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1757 | dom = dev_data->domain; |
15898bbc | 1758 | if (dom == NULL && |
657cbb6b | 1759 | alias_data->domain != NULL) { |
ec9e79ef | 1760 | __attach_device(dev_data, alias_data->domain); |
657cbb6b | 1761 | dom = alias_data->domain; |
15898bbc JR |
1762 | } |
1763 | ||
1764 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1765 | ||
1766 | return dom; | |
1767 | } | |
1768 | ||
e275a2a0 JR |
1769 | static int device_change_notifier(struct notifier_block *nb, |
1770 | unsigned long action, void *data) | |
1771 | { | |
1772 | struct device *dev = data; | |
98fc5a69 | 1773 | u16 devid; |
e275a2a0 JR |
1774 | struct protection_domain *domain; |
1775 | struct dma_ops_domain *dma_domain; | |
1776 | struct amd_iommu *iommu; | |
1ac4cbbc | 1777 | unsigned long flags; |
e275a2a0 | 1778 | |
98fc5a69 JR |
1779 | if (!check_device(dev)) |
1780 | return 0; | |
e275a2a0 | 1781 | |
98fc5a69 JR |
1782 | devid = get_device_id(dev); |
1783 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1784 | |
1785 | switch (action) { | |
c1eee67b | 1786 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1787 | |
1788 | domain = domain_for_device(dev); | |
1789 | ||
e275a2a0 JR |
1790 | if (!domain) |
1791 | goto out; | |
a1ca331c JR |
1792 | if (iommu_pass_through) |
1793 | break; | |
15898bbc | 1794 | detach_device(dev); |
1ac4cbbc JR |
1795 | break; |
1796 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1797 | |
1798 | iommu_init_device(dev); | |
1799 | ||
1800 | domain = domain_for_device(dev); | |
1801 | ||
1ac4cbbc JR |
1802 | /* allocate a protection domain if a device is added */ |
1803 | dma_domain = find_protection_domain(devid); | |
1804 | if (dma_domain) | |
1805 | goto out; | |
87a64d52 | 1806 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1807 | if (!dma_domain) |
1808 | goto out; | |
1809 | dma_domain->target_dev = devid; | |
1810 | ||
1811 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1812 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1813 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1814 | ||
e275a2a0 | 1815 | break; |
657cbb6b JR |
1816 | case BUS_NOTIFY_DEL_DEVICE: |
1817 | ||
1818 | iommu_uninit_device(dev); | |
1819 | ||
e275a2a0 JR |
1820 | default: |
1821 | goto out; | |
1822 | } | |
1823 | ||
e275a2a0 JR |
1824 | iommu_completion_wait(iommu); |
1825 | ||
1826 | out: | |
1827 | return 0; | |
1828 | } | |
1829 | ||
b25ae679 | 1830 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1831 | .notifier_call = device_change_notifier, |
1832 | }; | |
355bf553 | 1833 | |
8638c491 JR |
1834 | void amd_iommu_init_notifier(void) |
1835 | { | |
1836 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1837 | } | |
1838 | ||
431b2a20 JR |
1839 | /***************************************************************************** |
1840 | * | |
1841 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1842 | * | |
1843 | *****************************************************************************/ | |
1844 | ||
1845 | /* | |
1846 | * In the dma_ops path we only have the struct device. This function | |
1847 | * finds the corresponding IOMMU, the protection domain and the | |
1848 | * requestor id for a given device. | |
1849 | * If the device is not yet associated with a domain this is also done | |
1850 | * in this function. | |
1851 | */ | |
94f6d190 | 1852 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1853 | { |
94f6d190 | 1854 | struct protection_domain *domain; |
b20ac0d4 | 1855 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1856 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1857 | |
f99c0f1c | 1858 | if (!check_device(dev)) |
94f6d190 | 1859 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1860 | |
94f6d190 JR |
1861 | domain = domain_for_device(dev); |
1862 | if (domain != NULL && !dma_ops_domain(domain)) | |
1863 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1864 | |
94f6d190 JR |
1865 | if (domain != NULL) |
1866 | return domain; | |
b20ac0d4 | 1867 | |
15898bbc | 1868 | /* Device not bount yet - bind it */ |
94f6d190 | 1869 | dma_dom = find_protection_domain(devid); |
15898bbc | 1870 | if (!dma_dom) |
94f6d190 JR |
1871 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1872 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1873 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1874 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1875 | |
94f6d190 | 1876 | return &dma_dom->domain; |
b20ac0d4 JR |
1877 | } |
1878 | ||
04bfdd84 JR |
1879 | static void update_device_table(struct protection_domain *domain) |
1880 | { | |
492667da | 1881 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1882 | |
ea61cddb JR |
1883 | list_for_each_entry(dev_data, &domain->dev_list, list) |
1884 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
1885 | } |
1886 | ||
1887 | static void update_domain(struct protection_domain *domain) | |
1888 | { | |
1889 | if (!domain->updated) | |
1890 | return; | |
1891 | ||
1892 | update_device_table(domain); | |
17b124bf JR |
1893 | |
1894 | domain_flush_devices(domain); | |
1895 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1896 | |
1897 | domain->updated = false; | |
1898 | } | |
1899 | ||
8bda3092 JR |
1900 | /* |
1901 | * This function fetches the PTE for a given address in the aperture | |
1902 | */ | |
1903 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1904 | unsigned long address) | |
1905 | { | |
384de729 | 1906 | struct aperture_range *aperture; |
8bda3092 JR |
1907 | u64 *pte, *pte_page; |
1908 | ||
384de729 JR |
1909 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1910 | if (!aperture) | |
1911 | return NULL; | |
1912 | ||
1913 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1914 | if (!pte) { |
cbb9d729 | 1915 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1916 | GFP_ATOMIC); |
384de729 JR |
1917 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1918 | } else | |
8c8c143c | 1919 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1920 | |
04bfdd84 | 1921 | update_domain(&dom->domain); |
8bda3092 JR |
1922 | |
1923 | return pte; | |
1924 | } | |
1925 | ||
431b2a20 JR |
1926 | /* |
1927 | * This is the generic map function. It maps one 4kb page at paddr to | |
1928 | * the given address in the DMA address space for the domain. | |
1929 | */ | |
680525e0 | 1930 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1931 | unsigned long address, |
1932 | phys_addr_t paddr, | |
1933 | int direction) | |
1934 | { | |
1935 | u64 *pte, __pte; | |
1936 | ||
1937 | WARN_ON(address > dom->aperture_size); | |
1938 | ||
1939 | paddr &= PAGE_MASK; | |
1940 | ||
8bda3092 | 1941 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1942 | if (!pte) |
8fd524b3 | 1943 | return DMA_ERROR_CODE; |
cb76c322 JR |
1944 | |
1945 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1946 | ||
1947 | if (direction == DMA_TO_DEVICE) | |
1948 | __pte |= IOMMU_PTE_IR; | |
1949 | else if (direction == DMA_FROM_DEVICE) | |
1950 | __pte |= IOMMU_PTE_IW; | |
1951 | else if (direction == DMA_BIDIRECTIONAL) | |
1952 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1953 | ||
1954 | WARN_ON(*pte); | |
1955 | ||
1956 | *pte = __pte; | |
1957 | ||
1958 | return (dma_addr_t)address; | |
1959 | } | |
1960 | ||
431b2a20 JR |
1961 | /* |
1962 | * The generic unmapping function for on page in the DMA address space. | |
1963 | */ | |
680525e0 | 1964 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1965 | unsigned long address) |
1966 | { | |
384de729 | 1967 | struct aperture_range *aperture; |
cb76c322 JR |
1968 | u64 *pte; |
1969 | ||
1970 | if (address >= dom->aperture_size) | |
1971 | return; | |
1972 | ||
384de729 JR |
1973 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1974 | if (!aperture) | |
1975 | return; | |
1976 | ||
1977 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1978 | if (!pte) | |
1979 | return; | |
cb76c322 | 1980 | |
8c8c143c | 1981 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1982 | |
1983 | WARN_ON(!*pte); | |
1984 | ||
1985 | *pte = 0ULL; | |
1986 | } | |
1987 | ||
431b2a20 JR |
1988 | /* |
1989 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1990 | * contiguous memory region into DMA address space. It is used by all |
1991 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1992 | * Must be called with the domain lock held. |
1993 | */ | |
cb76c322 | 1994 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1995 | struct dma_ops_domain *dma_dom, |
1996 | phys_addr_t paddr, | |
1997 | size_t size, | |
6d4f343f | 1998 | int dir, |
832a90c3 JR |
1999 | bool align, |
2000 | u64 dma_mask) | |
cb76c322 JR |
2001 | { |
2002 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2003 | dma_addr_t address, start, ret; |
cb76c322 | 2004 | unsigned int pages; |
6d4f343f | 2005 | unsigned long align_mask = 0; |
cb76c322 JR |
2006 | int i; |
2007 | ||
e3c449f5 | 2008 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2009 | paddr &= PAGE_MASK; |
2010 | ||
8ecaf8f1 JR |
2011 | INC_STATS_COUNTER(total_map_requests); |
2012 | ||
c1858976 JR |
2013 | if (pages > 1) |
2014 | INC_STATS_COUNTER(cross_page); | |
2015 | ||
6d4f343f JR |
2016 | if (align) |
2017 | align_mask = (1UL << get_order(size)) - 1; | |
2018 | ||
11b83888 | 2019 | retry: |
832a90c3 JR |
2020 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2021 | dma_mask); | |
8fd524b3 | 2022 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2023 | /* |
2024 | * setting next_address here will let the address | |
2025 | * allocator only scan the new allocated range in the | |
2026 | * first run. This is a small optimization. | |
2027 | */ | |
2028 | dma_dom->next_address = dma_dom->aperture_size; | |
2029 | ||
576175c2 | 2030 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2031 | goto out; |
2032 | ||
2033 | /* | |
af901ca1 | 2034 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2035 | * allocation again |
2036 | */ | |
2037 | goto retry; | |
2038 | } | |
cb76c322 JR |
2039 | |
2040 | start = address; | |
2041 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2042 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2043 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2044 | goto out_unmap; |
2045 | ||
cb76c322 JR |
2046 | paddr += PAGE_SIZE; |
2047 | start += PAGE_SIZE; | |
2048 | } | |
2049 | address += offset; | |
2050 | ||
5774f7c5 JR |
2051 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2052 | ||
afa9fdc2 | 2053 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2054 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2055 | dma_dom->need_flush = false; |
318afd41 | 2056 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2057 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2058 | |
cb76c322 JR |
2059 | out: |
2060 | return address; | |
53812c11 JR |
2061 | |
2062 | out_unmap: | |
2063 | ||
2064 | for (--i; i >= 0; --i) { | |
2065 | start -= PAGE_SIZE; | |
680525e0 | 2066 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2067 | } |
2068 | ||
2069 | dma_ops_free_addresses(dma_dom, address, pages); | |
2070 | ||
8fd524b3 | 2071 | return DMA_ERROR_CODE; |
cb76c322 JR |
2072 | } |
2073 | ||
431b2a20 JR |
2074 | /* |
2075 | * Does the reverse of the __map_single function. Must be called with | |
2076 | * the domain lock held too | |
2077 | */ | |
cd8c82e8 | 2078 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2079 | dma_addr_t dma_addr, |
2080 | size_t size, | |
2081 | int dir) | |
2082 | { | |
04e0463e | 2083 | dma_addr_t flush_addr; |
cb76c322 JR |
2084 | dma_addr_t i, start; |
2085 | unsigned int pages; | |
2086 | ||
8fd524b3 | 2087 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2088 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2089 | return; |
2090 | ||
04e0463e | 2091 | flush_addr = dma_addr; |
e3c449f5 | 2092 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2093 | dma_addr &= PAGE_MASK; |
2094 | start = dma_addr; | |
2095 | ||
2096 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2097 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2098 | start += PAGE_SIZE; |
2099 | } | |
2100 | ||
5774f7c5 JR |
2101 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2102 | ||
cb76c322 | 2103 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2104 | |
80be308d | 2105 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2106 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2107 | dma_dom->need_flush = false; |
2108 | } | |
cb76c322 JR |
2109 | } |
2110 | ||
431b2a20 JR |
2111 | /* |
2112 | * The exported map_single function for dma_ops. | |
2113 | */ | |
51491367 FT |
2114 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2115 | unsigned long offset, size_t size, | |
2116 | enum dma_data_direction dir, | |
2117 | struct dma_attrs *attrs) | |
4da70b9e JR |
2118 | { |
2119 | unsigned long flags; | |
4da70b9e | 2120 | struct protection_domain *domain; |
4da70b9e | 2121 | dma_addr_t addr; |
832a90c3 | 2122 | u64 dma_mask; |
51491367 | 2123 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2124 | |
0f2a86f2 JR |
2125 | INC_STATS_COUNTER(cnt_map_single); |
2126 | ||
94f6d190 JR |
2127 | domain = get_domain(dev); |
2128 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2129 | return (dma_addr_t)paddr; |
94f6d190 JR |
2130 | else if (IS_ERR(domain)) |
2131 | return DMA_ERROR_CODE; | |
4da70b9e | 2132 | |
f99c0f1c JR |
2133 | dma_mask = *dev->dma_mask; |
2134 | ||
4da70b9e | 2135 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2136 | |
cd8c82e8 | 2137 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2138 | dma_mask); |
8fd524b3 | 2139 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2140 | goto out; |
2141 | ||
17b124bf | 2142 | domain_flush_complete(domain); |
4da70b9e JR |
2143 | |
2144 | out: | |
2145 | spin_unlock_irqrestore(&domain->lock, flags); | |
2146 | ||
2147 | return addr; | |
2148 | } | |
2149 | ||
431b2a20 JR |
2150 | /* |
2151 | * The exported unmap_single function for dma_ops. | |
2152 | */ | |
51491367 FT |
2153 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2154 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2155 | { |
2156 | unsigned long flags; | |
4da70b9e | 2157 | struct protection_domain *domain; |
4da70b9e | 2158 | |
146a6917 JR |
2159 | INC_STATS_COUNTER(cnt_unmap_single); |
2160 | ||
94f6d190 JR |
2161 | domain = get_domain(dev); |
2162 | if (IS_ERR(domain)) | |
5b28df6f JR |
2163 | return; |
2164 | ||
4da70b9e JR |
2165 | spin_lock_irqsave(&domain->lock, flags); |
2166 | ||
cd8c82e8 | 2167 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2168 | |
17b124bf | 2169 | domain_flush_complete(domain); |
4da70b9e JR |
2170 | |
2171 | spin_unlock_irqrestore(&domain->lock, flags); | |
2172 | } | |
2173 | ||
431b2a20 JR |
2174 | /* |
2175 | * This is a special map_sg function which is used if we should map a | |
2176 | * device which is not handled by an AMD IOMMU in the system. | |
2177 | */ | |
65b050ad JR |
2178 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2179 | int nelems, int dir) | |
2180 | { | |
2181 | struct scatterlist *s; | |
2182 | int i; | |
2183 | ||
2184 | for_each_sg(sglist, s, nelems, i) { | |
2185 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2186 | s->dma_length = s->length; | |
2187 | } | |
2188 | ||
2189 | return nelems; | |
2190 | } | |
2191 | ||
431b2a20 JR |
2192 | /* |
2193 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2194 | * lists). | |
2195 | */ | |
65b050ad | 2196 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2197 | int nelems, enum dma_data_direction dir, |
2198 | struct dma_attrs *attrs) | |
65b050ad JR |
2199 | { |
2200 | unsigned long flags; | |
65b050ad | 2201 | struct protection_domain *domain; |
65b050ad JR |
2202 | int i; |
2203 | struct scatterlist *s; | |
2204 | phys_addr_t paddr; | |
2205 | int mapped_elems = 0; | |
832a90c3 | 2206 | u64 dma_mask; |
65b050ad | 2207 | |
d03f067a JR |
2208 | INC_STATS_COUNTER(cnt_map_sg); |
2209 | ||
94f6d190 JR |
2210 | domain = get_domain(dev); |
2211 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2212 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2213 | else if (IS_ERR(domain)) |
2214 | return 0; | |
dbcc112e | 2215 | |
832a90c3 | 2216 | dma_mask = *dev->dma_mask; |
65b050ad | 2217 | |
65b050ad JR |
2218 | spin_lock_irqsave(&domain->lock, flags); |
2219 | ||
2220 | for_each_sg(sglist, s, nelems, i) { | |
2221 | paddr = sg_phys(s); | |
2222 | ||
cd8c82e8 | 2223 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2224 | paddr, s->length, dir, false, |
2225 | dma_mask); | |
65b050ad JR |
2226 | |
2227 | if (s->dma_address) { | |
2228 | s->dma_length = s->length; | |
2229 | mapped_elems++; | |
2230 | } else | |
2231 | goto unmap; | |
65b050ad JR |
2232 | } |
2233 | ||
17b124bf | 2234 | domain_flush_complete(domain); |
65b050ad JR |
2235 | |
2236 | out: | |
2237 | spin_unlock_irqrestore(&domain->lock, flags); | |
2238 | ||
2239 | return mapped_elems; | |
2240 | unmap: | |
2241 | for_each_sg(sglist, s, mapped_elems, i) { | |
2242 | if (s->dma_address) | |
cd8c82e8 | 2243 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2244 | s->dma_length, dir); |
2245 | s->dma_address = s->dma_length = 0; | |
2246 | } | |
2247 | ||
2248 | mapped_elems = 0; | |
2249 | ||
2250 | goto out; | |
2251 | } | |
2252 | ||
431b2a20 JR |
2253 | /* |
2254 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2255 | * lists). | |
2256 | */ | |
65b050ad | 2257 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2258 | int nelems, enum dma_data_direction dir, |
2259 | struct dma_attrs *attrs) | |
65b050ad JR |
2260 | { |
2261 | unsigned long flags; | |
65b050ad JR |
2262 | struct protection_domain *domain; |
2263 | struct scatterlist *s; | |
65b050ad JR |
2264 | int i; |
2265 | ||
55877a6b JR |
2266 | INC_STATS_COUNTER(cnt_unmap_sg); |
2267 | ||
94f6d190 JR |
2268 | domain = get_domain(dev); |
2269 | if (IS_ERR(domain)) | |
5b28df6f JR |
2270 | return; |
2271 | ||
65b050ad JR |
2272 | spin_lock_irqsave(&domain->lock, flags); |
2273 | ||
2274 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2275 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2276 | s->dma_length, dir); |
65b050ad JR |
2277 | s->dma_address = s->dma_length = 0; |
2278 | } | |
2279 | ||
17b124bf | 2280 | domain_flush_complete(domain); |
65b050ad JR |
2281 | |
2282 | spin_unlock_irqrestore(&domain->lock, flags); | |
2283 | } | |
2284 | ||
431b2a20 JR |
2285 | /* |
2286 | * The exported alloc_coherent function for dma_ops. | |
2287 | */ | |
5d8b53cf JR |
2288 | static void *alloc_coherent(struct device *dev, size_t size, |
2289 | dma_addr_t *dma_addr, gfp_t flag) | |
2290 | { | |
2291 | unsigned long flags; | |
2292 | void *virt_addr; | |
5d8b53cf | 2293 | struct protection_domain *domain; |
5d8b53cf | 2294 | phys_addr_t paddr; |
832a90c3 | 2295 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2296 | |
c8f0fb36 JR |
2297 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2298 | ||
94f6d190 JR |
2299 | domain = get_domain(dev); |
2300 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2301 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2302 | *dma_addr = __pa(virt_addr); | |
2303 | return virt_addr; | |
94f6d190 JR |
2304 | } else if (IS_ERR(domain)) |
2305 | return NULL; | |
5d8b53cf | 2306 | |
f99c0f1c JR |
2307 | dma_mask = dev->coherent_dma_mask; |
2308 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2309 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2310 | |
2311 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2312 | if (!virt_addr) | |
b25ae679 | 2313 | return NULL; |
5d8b53cf | 2314 | |
5d8b53cf JR |
2315 | paddr = virt_to_phys(virt_addr); |
2316 | ||
832a90c3 JR |
2317 | if (!dma_mask) |
2318 | dma_mask = *dev->dma_mask; | |
2319 | ||
5d8b53cf JR |
2320 | spin_lock_irqsave(&domain->lock, flags); |
2321 | ||
cd8c82e8 | 2322 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2323 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2324 | |
8fd524b3 | 2325 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2326 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2327 | goto out_free; |
367d04c4 | 2328 | } |
5d8b53cf | 2329 | |
17b124bf | 2330 | domain_flush_complete(domain); |
5d8b53cf | 2331 | |
5d8b53cf JR |
2332 | spin_unlock_irqrestore(&domain->lock, flags); |
2333 | ||
2334 | return virt_addr; | |
5b28df6f JR |
2335 | |
2336 | out_free: | |
2337 | ||
2338 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2339 | ||
2340 | return NULL; | |
5d8b53cf JR |
2341 | } |
2342 | ||
431b2a20 JR |
2343 | /* |
2344 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2345 | */ |
5d8b53cf JR |
2346 | static void free_coherent(struct device *dev, size_t size, |
2347 | void *virt_addr, dma_addr_t dma_addr) | |
2348 | { | |
2349 | unsigned long flags; | |
5d8b53cf | 2350 | struct protection_domain *domain; |
5d8b53cf | 2351 | |
5d31ee7e JR |
2352 | INC_STATS_COUNTER(cnt_free_coherent); |
2353 | ||
94f6d190 JR |
2354 | domain = get_domain(dev); |
2355 | if (IS_ERR(domain)) | |
5b28df6f JR |
2356 | goto free_mem; |
2357 | ||
5d8b53cf JR |
2358 | spin_lock_irqsave(&domain->lock, flags); |
2359 | ||
cd8c82e8 | 2360 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2361 | |
17b124bf | 2362 | domain_flush_complete(domain); |
5d8b53cf JR |
2363 | |
2364 | spin_unlock_irqrestore(&domain->lock, flags); | |
2365 | ||
2366 | free_mem: | |
2367 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2368 | } | |
2369 | ||
b39ba6ad JR |
2370 | /* |
2371 | * This function is called by the DMA layer to find out if we can handle a | |
2372 | * particular device. It is part of the dma_ops. | |
2373 | */ | |
2374 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2375 | { | |
420aef8a | 2376 | return check_device(dev); |
b39ba6ad JR |
2377 | } |
2378 | ||
c432f3df | 2379 | /* |
431b2a20 JR |
2380 | * The function for pre-allocating protection domains. |
2381 | * | |
c432f3df JR |
2382 | * If the driver core informs the DMA layer if a driver grabs a device |
2383 | * we don't need to preallocate the protection domains anymore. | |
2384 | * For now we have to. | |
2385 | */ | |
0e93dd88 | 2386 | static void prealloc_protection_domains(void) |
c432f3df JR |
2387 | { |
2388 | struct pci_dev *dev = NULL; | |
2389 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2390 | u16 devid; |
c432f3df | 2391 | |
d18c69d3 | 2392 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2393 | |
2394 | /* Do we handle this device? */ | |
2395 | if (!check_device(&dev->dev)) | |
c432f3df | 2396 | continue; |
98fc5a69 JR |
2397 | |
2398 | /* Is there already any domain for it? */ | |
15898bbc | 2399 | if (domain_for_device(&dev->dev)) |
c432f3df | 2400 | continue; |
98fc5a69 JR |
2401 | |
2402 | devid = get_device_id(&dev->dev); | |
2403 | ||
87a64d52 | 2404 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2405 | if (!dma_dom) |
2406 | continue; | |
2407 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2408 | dma_dom->target_dev = devid; |
2409 | ||
15898bbc | 2410 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2411 | |
bd60b735 | 2412 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2413 | } |
2414 | } | |
2415 | ||
160c1d8e | 2416 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2417 | .alloc_coherent = alloc_coherent, |
2418 | .free_coherent = free_coherent, | |
51491367 FT |
2419 | .map_page = map_page, |
2420 | .unmap_page = unmap_page, | |
6631ee9d JR |
2421 | .map_sg = map_sg, |
2422 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2423 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2424 | }; |
2425 | ||
27c2127a JR |
2426 | static unsigned device_dma_ops_init(void) |
2427 | { | |
2428 | struct pci_dev *pdev = NULL; | |
2429 | unsigned unhandled = 0; | |
2430 | ||
2431 | for_each_pci_dev(pdev) { | |
2432 | if (!check_device(&pdev->dev)) { | |
2433 | unhandled += 1; | |
2434 | continue; | |
2435 | } | |
2436 | ||
2437 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2438 | } | |
2439 | ||
2440 | return unhandled; | |
2441 | } | |
2442 | ||
431b2a20 JR |
2443 | /* |
2444 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2445 | */ | |
f5325094 JR |
2446 | |
2447 | void __init amd_iommu_init_api(void) | |
2448 | { | |
2449 | register_iommu(&amd_iommu_ops); | |
2450 | } | |
2451 | ||
6631ee9d JR |
2452 | int __init amd_iommu_init_dma_ops(void) |
2453 | { | |
2454 | struct amd_iommu *iommu; | |
27c2127a | 2455 | int ret, unhandled; |
6631ee9d | 2456 | |
431b2a20 JR |
2457 | /* |
2458 | * first allocate a default protection domain for every IOMMU we | |
2459 | * found in the system. Devices not assigned to any other | |
2460 | * protection domain will be assigned to the default one. | |
2461 | */ | |
3bd22172 | 2462 | for_each_iommu(iommu) { |
87a64d52 | 2463 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2464 | if (iommu->default_dom == NULL) |
2465 | return -ENOMEM; | |
e2dc14a2 | 2466 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2467 | ret = iommu_init_unity_mappings(iommu); |
2468 | if (ret) | |
2469 | goto free_domains; | |
2470 | } | |
2471 | ||
431b2a20 | 2472 | /* |
8793abeb | 2473 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2474 | */ |
8793abeb | 2475 | prealloc_protection_domains(); |
6631ee9d JR |
2476 | |
2477 | iommu_detected = 1; | |
75f1cdf1 | 2478 | swiotlb = 0; |
6631ee9d | 2479 | |
431b2a20 | 2480 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2481 | unhandled = device_dma_ops_init(); |
2482 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2483 | /* There are unhandled devices - initialize swiotlb for them */ | |
2484 | swiotlb = 1; | |
2485 | } | |
6631ee9d | 2486 | |
7f26508b JR |
2487 | amd_iommu_stats_init(); |
2488 | ||
6631ee9d JR |
2489 | return 0; |
2490 | ||
2491 | free_domains: | |
2492 | ||
3bd22172 | 2493 | for_each_iommu(iommu) { |
6631ee9d JR |
2494 | if (iommu->default_dom) |
2495 | dma_ops_domain_free(iommu->default_dom); | |
2496 | } | |
2497 | ||
2498 | return ret; | |
2499 | } | |
6d98cd80 JR |
2500 | |
2501 | /***************************************************************************** | |
2502 | * | |
2503 | * The following functions belong to the exported interface of AMD IOMMU | |
2504 | * | |
2505 | * This interface allows access to lower level functions of the IOMMU | |
2506 | * like protection domain handling and assignement of devices to domains | |
2507 | * which is not possible with the dma_ops interface. | |
2508 | * | |
2509 | *****************************************************************************/ | |
2510 | ||
6d98cd80 JR |
2511 | static void cleanup_domain(struct protection_domain *domain) |
2512 | { | |
492667da | 2513 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2514 | unsigned long flags; |
6d98cd80 JR |
2515 | |
2516 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2517 | ||
492667da | 2518 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 2519 | __detach_device(dev_data); |
492667da JR |
2520 | atomic_set(&dev_data->bind, 0); |
2521 | } | |
6d98cd80 JR |
2522 | |
2523 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2524 | } | |
2525 | ||
2650815f JR |
2526 | static void protection_domain_free(struct protection_domain *domain) |
2527 | { | |
2528 | if (!domain) | |
2529 | return; | |
2530 | ||
aeb26f55 JR |
2531 | del_domain_from_list(domain); |
2532 | ||
2650815f JR |
2533 | if (domain->id) |
2534 | domain_id_free(domain->id); | |
2535 | ||
2536 | kfree(domain); | |
2537 | } | |
2538 | ||
2539 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2540 | { |
2541 | struct protection_domain *domain; | |
2542 | ||
2543 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2544 | if (!domain) | |
2650815f | 2545 | return NULL; |
c156e347 JR |
2546 | |
2547 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2548 | mutex_init(&domain->api_lock); |
c156e347 JR |
2549 | domain->id = domain_id_alloc(); |
2550 | if (!domain->id) | |
2650815f | 2551 | goto out_err; |
7c392cbe | 2552 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2553 | |
aeb26f55 JR |
2554 | add_domain_to_list(domain); |
2555 | ||
2650815f JR |
2556 | return domain; |
2557 | ||
2558 | out_err: | |
2559 | kfree(domain); | |
2560 | ||
2561 | return NULL; | |
2562 | } | |
2563 | ||
2564 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2565 | { | |
2566 | struct protection_domain *domain; | |
2567 | ||
2568 | domain = protection_domain_alloc(); | |
2569 | if (!domain) | |
c156e347 | 2570 | goto out_free; |
2650815f JR |
2571 | |
2572 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2573 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2574 | if (!domain->pt_root) | |
2575 | goto out_free; | |
2576 | ||
2577 | dom->priv = domain; | |
2578 | ||
2579 | return 0; | |
2580 | ||
2581 | out_free: | |
2650815f | 2582 | protection_domain_free(domain); |
c156e347 JR |
2583 | |
2584 | return -ENOMEM; | |
2585 | } | |
2586 | ||
98383fc3 JR |
2587 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2588 | { | |
2589 | struct protection_domain *domain = dom->priv; | |
2590 | ||
2591 | if (!domain) | |
2592 | return; | |
2593 | ||
2594 | if (domain->dev_cnt > 0) | |
2595 | cleanup_domain(domain); | |
2596 | ||
2597 | BUG_ON(domain->dev_cnt != 0); | |
2598 | ||
2599 | free_pagetable(domain); | |
2600 | ||
8b408fe4 | 2601 | protection_domain_free(domain); |
98383fc3 JR |
2602 | |
2603 | dom->priv = NULL; | |
2604 | } | |
2605 | ||
684f2888 JR |
2606 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2607 | struct device *dev) | |
2608 | { | |
657cbb6b | 2609 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2610 | struct amd_iommu *iommu; |
684f2888 JR |
2611 | u16 devid; |
2612 | ||
98fc5a69 | 2613 | if (!check_device(dev)) |
684f2888 JR |
2614 | return; |
2615 | ||
98fc5a69 | 2616 | devid = get_device_id(dev); |
684f2888 | 2617 | |
657cbb6b | 2618 | if (dev_data->domain != NULL) |
15898bbc | 2619 | detach_device(dev); |
684f2888 JR |
2620 | |
2621 | iommu = amd_iommu_rlookup_table[devid]; | |
2622 | if (!iommu) | |
2623 | return; | |
2624 | ||
684f2888 JR |
2625 | iommu_completion_wait(iommu); |
2626 | } | |
2627 | ||
01106066 JR |
2628 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2629 | struct device *dev) | |
2630 | { | |
2631 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2632 | struct iommu_dev_data *dev_data; |
01106066 | 2633 | struct amd_iommu *iommu; |
15898bbc | 2634 | int ret; |
01106066 | 2635 | |
98fc5a69 | 2636 | if (!check_device(dev)) |
01106066 JR |
2637 | return -EINVAL; |
2638 | ||
657cbb6b JR |
2639 | dev_data = dev->archdata.iommu; |
2640 | ||
f62dda66 | 2641 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2642 | if (!iommu) |
2643 | return -EINVAL; | |
2644 | ||
657cbb6b | 2645 | if (dev_data->domain) |
15898bbc | 2646 | detach_device(dev); |
01106066 | 2647 | |
15898bbc | 2648 | ret = attach_device(dev, domain); |
01106066 JR |
2649 | |
2650 | iommu_completion_wait(iommu); | |
2651 | ||
15898bbc | 2652 | return ret; |
01106066 JR |
2653 | } |
2654 | ||
468e2366 JR |
2655 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2656 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2657 | { |
468e2366 | 2658 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2659 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2660 | int prot = 0; |
2661 | int ret; | |
2662 | ||
2663 | if (iommu_prot & IOMMU_READ) | |
2664 | prot |= IOMMU_PROT_IR; | |
2665 | if (iommu_prot & IOMMU_WRITE) | |
2666 | prot |= IOMMU_PROT_IW; | |
2667 | ||
5d214fe6 | 2668 | mutex_lock(&domain->api_lock); |
795e74f7 | 2669 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2670 | mutex_unlock(&domain->api_lock); |
2671 | ||
795e74f7 | 2672 | return ret; |
c6229ca6 JR |
2673 | } |
2674 | ||
468e2366 JR |
2675 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2676 | int gfp_order) | |
eb74ff6c | 2677 | { |
eb74ff6c | 2678 | struct protection_domain *domain = dom->priv; |
468e2366 | 2679 | unsigned long page_size, unmap_size; |
eb74ff6c | 2680 | |
468e2366 | 2681 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2682 | |
5d214fe6 | 2683 | mutex_lock(&domain->api_lock); |
468e2366 | 2684 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2685 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2686 | |
17b124bf | 2687 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2688 | |
468e2366 | 2689 | return get_order(unmap_size); |
eb74ff6c JR |
2690 | } |
2691 | ||
645c4c8d JR |
2692 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2693 | unsigned long iova) | |
2694 | { | |
2695 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2696 | unsigned long offset_mask; |
645c4c8d | 2697 | phys_addr_t paddr; |
f03152bb | 2698 | u64 *pte, __pte; |
645c4c8d | 2699 | |
24cd7723 | 2700 | pte = fetch_pte(domain, iova); |
645c4c8d | 2701 | |
a6d41a40 | 2702 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2703 | return 0; |
2704 | ||
f03152bb JR |
2705 | if (PM_PTE_LEVEL(*pte) == 0) |
2706 | offset_mask = PAGE_SIZE - 1; | |
2707 | else | |
2708 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2709 | ||
2710 | __pte = *pte & PM_ADDR_MASK; | |
2711 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2712 | |
2713 | return paddr; | |
2714 | } | |
2715 | ||
dbb9fd86 SY |
2716 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2717 | unsigned long cap) | |
2718 | { | |
80a506b8 JR |
2719 | switch (cap) { |
2720 | case IOMMU_CAP_CACHE_COHERENCY: | |
2721 | return 1; | |
2722 | } | |
2723 | ||
dbb9fd86 SY |
2724 | return 0; |
2725 | } | |
2726 | ||
26961efe JR |
2727 | static struct iommu_ops amd_iommu_ops = { |
2728 | .domain_init = amd_iommu_domain_init, | |
2729 | .domain_destroy = amd_iommu_domain_destroy, | |
2730 | .attach_dev = amd_iommu_attach_device, | |
2731 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2732 | .map = amd_iommu_map, |
2733 | .unmap = amd_iommu_unmap, | |
26961efe | 2734 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2735 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2736 | }; |
2737 | ||
0feae533 JR |
2738 | /***************************************************************************** |
2739 | * | |
2740 | * The next functions do a basic initialization of IOMMU for pass through | |
2741 | * mode | |
2742 | * | |
2743 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2744 | * DMA-API translation. | |
2745 | * | |
2746 | *****************************************************************************/ | |
2747 | ||
2748 | int __init amd_iommu_init_passthrough(void) | |
2749 | { | |
15898bbc | 2750 | struct amd_iommu *iommu; |
0feae533 | 2751 | struct pci_dev *dev = NULL; |
15898bbc | 2752 | u16 devid; |
0feae533 | 2753 | |
af901ca1 | 2754 | /* allocate passthrough domain */ |
0feae533 JR |
2755 | pt_domain = protection_domain_alloc(); |
2756 | if (!pt_domain) | |
2757 | return -ENOMEM; | |
2758 | ||
2759 | pt_domain->mode |= PAGE_MODE_NONE; | |
2760 | ||
6c54aabd | 2761 | for_each_pci_dev(dev) { |
98fc5a69 | 2762 | if (!check_device(&dev->dev)) |
0feae533 JR |
2763 | continue; |
2764 | ||
98fc5a69 JR |
2765 | devid = get_device_id(&dev->dev); |
2766 | ||
15898bbc | 2767 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2768 | if (!iommu) |
2769 | continue; | |
2770 | ||
15898bbc | 2771 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2772 | } |
2773 | ||
2774 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2775 | ||
2776 | return 0; | |
2777 | } |