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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
b6c02715 | 30 | #include <asm/proto.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
27c2127a | 33 | #include <asm/dma.h> |
6a9401a7 | 34 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 35 | #include <asm/amd_iommu_types.h> |
c6da992e | 36 | #include <asm/amd_iommu.h> |
b6c02715 JR |
37 | |
38 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
39 | ||
815b33fd | 40 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 41 | |
b6c02715 JR |
42 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
43 | ||
bd60b735 JR |
44 | /* A list of preallocated protection domains */ |
45 | static LIST_HEAD(iommu_pd_list); | |
46 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
47 | ||
8fa5f802 JR |
48 | /* List of all available dev_data structures */ |
49 | static LIST_HEAD(dev_data_list); | |
50 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
51 | ||
0feae533 JR |
52 | /* |
53 | * Domain for untranslated devices - only allocated | |
54 | * if iommu=pt passed on kernel cmd line. | |
55 | */ | |
56 | static struct protection_domain *pt_domain; | |
57 | ||
26961efe | 58 | static struct iommu_ops amd_iommu_ops; |
26961efe | 59 | |
431b2a20 JR |
60 | /* |
61 | * general struct to manage commands send to an IOMMU | |
62 | */ | |
d6449536 | 63 | struct iommu_cmd { |
b6c02715 JR |
64 | u32 data[4]; |
65 | }; | |
66 | ||
04bfdd84 | 67 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 68 | |
15898bbc JR |
69 | /**************************************************************************** |
70 | * | |
71 | * Helper functions | |
72 | * | |
73 | ****************************************************************************/ | |
74 | ||
f62dda66 | 75 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
76 | { |
77 | struct iommu_dev_data *dev_data; | |
78 | unsigned long flags; | |
79 | ||
80 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
81 | if (!dev_data) | |
82 | return NULL; | |
83 | ||
f62dda66 | 84 | dev_data->devid = devid; |
8fa5f802 JR |
85 | atomic_set(&dev_data->bind, 0); |
86 | ||
87 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
88 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
89 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
90 | ||
91 | return dev_data; | |
92 | } | |
93 | ||
94 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
95 | { | |
96 | unsigned long flags; | |
97 | ||
98 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
99 | list_del(&dev_data->dev_data_list); | |
100 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
101 | ||
102 | kfree(dev_data); | |
103 | } | |
104 | ||
15898bbc JR |
105 | static inline u16 get_device_id(struct device *dev) |
106 | { | |
107 | struct pci_dev *pdev = to_pci_dev(dev); | |
108 | ||
109 | return calc_devid(pdev->bus->number, pdev->devfn); | |
110 | } | |
111 | ||
657cbb6b JR |
112 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
113 | { | |
114 | return dev->archdata.iommu; | |
115 | } | |
116 | ||
71c70984 JR |
117 | /* |
118 | * In this function the list of preallocated protection domains is traversed to | |
119 | * find the domain for a specific device | |
120 | */ | |
121 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
122 | { | |
123 | struct dma_ops_domain *entry, *ret = NULL; | |
124 | unsigned long flags; | |
125 | u16 alias = amd_iommu_alias_table[devid]; | |
126 | ||
127 | if (list_empty(&iommu_pd_list)) | |
128 | return NULL; | |
129 | ||
130 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
131 | ||
132 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
133 | if (entry->target_dev == devid || | |
134 | entry->target_dev == alias) { | |
135 | ret = entry; | |
136 | break; | |
137 | } | |
138 | } | |
139 | ||
140 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
141 | ||
142 | return ret; | |
143 | } | |
144 | ||
98fc5a69 JR |
145 | /* |
146 | * This function checks if the driver got a valid device from the caller to | |
147 | * avoid dereferencing invalid pointers. | |
148 | */ | |
149 | static bool check_device(struct device *dev) | |
150 | { | |
151 | u16 devid; | |
152 | ||
153 | if (!dev || !dev->dma_mask) | |
154 | return false; | |
155 | ||
156 | /* No device or no PCI device */ | |
339d3261 | 157 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
158 | return false; |
159 | ||
160 | devid = get_device_id(dev); | |
161 | ||
162 | /* Out of our scope? */ | |
163 | if (devid > amd_iommu_last_bdf) | |
164 | return false; | |
165 | ||
166 | if (amd_iommu_rlookup_table[devid] == NULL) | |
167 | return false; | |
168 | ||
169 | return true; | |
170 | } | |
171 | ||
657cbb6b JR |
172 | static int iommu_init_device(struct device *dev) |
173 | { | |
174 | struct iommu_dev_data *dev_data; | |
175 | struct pci_dev *pdev; | |
8fa5f802 | 176 | u16 alias; |
657cbb6b JR |
177 | |
178 | if (dev->archdata.iommu) | |
179 | return 0; | |
180 | ||
f62dda66 | 181 | dev_data = alloc_dev_data(get_device_id(dev)); |
657cbb6b JR |
182 | if (!dev_data) |
183 | return -ENOMEM; | |
184 | ||
b00d3bcf JR |
185 | dev_data->dev = dev; |
186 | ||
f62dda66 | 187 | alias = amd_iommu_alias_table[dev_data->devid]; |
657cbb6b JR |
188 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); |
189 | if (pdev) | |
190 | dev_data->alias = &pdev->dev; | |
26018874 | 191 | else { |
8fa5f802 | 192 | free_dev_data(dev_data); |
26018874 JR |
193 | return -ENOTSUPP; |
194 | } | |
657cbb6b JR |
195 | |
196 | dev->archdata.iommu = dev_data; | |
197 | ||
657cbb6b JR |
198 | return 0; |
199 | } | |
200 | ||
26018874 JR |
201 | static void iommu_ignore_device(struct device *dev) |
202 | { | |
203 | u16 devid, alias; | |
204 | ||
205 | devid = get_device_id(dev); | |
206 | alias = amd_iommu_alias_table[devid]; | |
207 | ||
208 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
209 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
210 | ||
211 | amd_iommu_rlookup_table[devid] = NULL; | |
212 | amd_iommu_rlookup_table[alias] = NULL; | |
213 | } | |
214 | ||
657cbb6b JR |
215 | static void iommu_uninit_device(struct device *dev) |
216 | { | |
8fa5f802 JR |
217 | /* |
218 | * Nothing to do here - we keep dev_data around for unplugged devices | |
219 | * and reuse it when the device is re-plugged - not doing so would | |
220 | * introduce a ton of races. | |
221 | */ | |
657cbb6b | 222 | } |
b7cc9554 JR |
223 | |
224 | void __init amd_iommu_uninit_devices(void) | |
225 | { | |
8fa5f802 | 226 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
227 | struct pci_dev *pdev = NULL; |
228 | ||
229 | for_each_pci_dev(pdev) { | |
230 | ||
231 | if (!check_device(&pdev->dev)) | |
232 | continue; | |
233 | ||
234 | iommu_uninit_device(&pdev->dev); | |
235 | } | |
8fa5f802 JR |
236 | |
237 | /* Free all of our dev_data structures */ | |
238 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
239 | free_dev_data(dev_data); | |
b7cc9554 JR |
240 | } |
241 | ||
242 | int __init amd_iommu_init_devices(void) | |
243 | { | |
244 | struct pci_dev *pdev = NULL; | |
245 | int ret = 0; | |
246 | ||
247 | for_each_pci_dev(pdev) { | |
248 | ||
249 | if (!check_device(&pdev->dev)) | |
250 | continue; | |
251 | ||
252 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
253 | if (ret == -ENOTSUPP) |
254 | iommu_ignore_device(&pdev->dev); | |
255 | else if (ret) | |
b7cc9554 JR |
256 | goto out_free; |
257 | } | |
258 | ||
259 | return 0; | |
260 | ||
261 | out_free: | |
262 | ||
263 | amd_iommu_uninit_devices(); | |
264 | ||
265 | return ret; | |
266 | } | |
7f26508b JR |
267 | #ifdef CONFIG_AMD_IOMMU_STATS |
268 | ||
269 | /* | |
270 | * Initialization code for statistics collection | |
271 | */ | |
272 | ||
da49f6df | 273 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 274 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 275 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 276 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 277 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 278 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 279 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 280 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 281 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 282 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 283 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 284 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 285 | |
7f26508b | 286 | static struct dentry *stats_dir; |
7f26508b JR |
287 | static struct dentry *de_fflush; |
288 | ||
289 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
290 | { | |
291 | if (stats_dir == NULL) | |
292 | return; | |
293 | ||
294 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
295 | &cnt->value); | |
296 | } | |
297 | ||
298 | static void amd_iommu_stats_init(void) | |
299 | { | |
300 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
301 | if (stats_dir == NULL) | |
302 | return; | |
303 | ||
7f26508b JR |
304 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
305 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
306 | |
307 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 308 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 309 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 310 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 311 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 312 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 313 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 314 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 315 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 316 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 317 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 318 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
319 | } |
320 | ||
321 | #endif | |
322 | ||
a80dc3e0 JR |
323 | /**************************************************************************** |
324 | * | |
325 | * Interrupt handling functions | |
326 | * | |
327 | ****************************************************************************/ | |
328 | ||
e3e59876 JR |
329 | static void dump_dte_entry(u16 devid) |
330 | { | |
331 | int i; | |
332 | ||
333 | for (i = 0; i < 8; ++i) | |
334 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
335 | amd_iommu_dev_table[devid].data[i]); | |
336 | } | |
337 | ||
945b4ac4 JR |
338 | static void dump_command(unsigned long phys_addr) |
339 | { | |
340 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
341 | int i; | |
342 | ||
343 | for (i = 0; i < 4; ++i) | |
344 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
345 | } | |
346 | ||
a345b23b | 347 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
348 | { |
349 | u32 *event = __evt; | |
350 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
351 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
352 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
353 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
354 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
355 | ||
4c6f40d4 | 356 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
357 | |
358 | switch (type) { | |
359 | case EVENT_TYPE_ILL_DEV: | |
360 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
361 | "address=0x%016llx flags=0x%04x]\n", | |
362 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
363 | address, flags); | |
e3e59876 | 364 | dump_dte_entry(devid); |
90008ee4 JR |
365 | break; |
366 | case EVENT_TYPE_IO_FAULT: | |
367 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
368 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
369 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
370 | domid, address, flags); | |
371 | break; | |
372 | case EVENT_TYPE_DEV_TAB_ERR: | |
373 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
374 | "address=0x%016llx flags=0x%04x]\n", | |
375 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
376 | address, flags); | |
377 | break; | |
378 | case EVENT_TYPE_PAGE_TAB_ERR: | |
379 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
380 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
381 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
382 | domid, address, flags); | |
383 | break; | |
384 | case EVENT_TYPE_ILL_CMD: | |
385 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 386 | dump_command(address); |
90008ee4 JR |
387 | break; |
388 | case EVENT_TYPE_CMD_HARD_ERR: | |
389 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
390 | "flags=0x%04x]\n", address, flags); | |
391 | break; | |
392 | case EVENT_TYPE_IOTLB_INV_TO: | |
393 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
394 | "address=0x%016llx]\n", | |
395 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
396 | address); | |
397 | break; | |
398 | case EVENT_TYPE_INV_DEV_REQ: | |
399 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
400 | "address=0x%016llx flags=0x%04x]\n", | |
401 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
402 | address, flags); | |
403 | break; | |
404 | default: | |
405 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
406 | } | |
407 | } | |
408 | ||
409 | static void iommu_poll_events(struct amd_iommu *iommu) | |
410 | { | |
411 | u32 head, tail; | |
412 | unsigned long flags; | |
413 | ||
414 | spin_lock_irqsave(&iommu->lock, flags); | |
415 | ||
416 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
417 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
418 | ||
419 | while (head != tail) { | |
a345b23b | 420 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
421 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
422 | } | |
423 | ||
424 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
425 | ||
426 | spin_unlock_irqrestore(&iommu->lock, flags); | |
427 | } | |
428 | ||
72fe00f0 | 429 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 430 | { |
90008ee4 JR |
431 | struct amd_iommu *iommu; |
432 | ||
3bd22172 | 433 | for_each_iommu(iommu) |
90008ee4 JR |
434 | iommu_poll_events(iommu); |
435 | ||
436 | return IRQ_HANDLED; | |
a80dc3e0 JR |
437 | } |
438 | ||
72fe00f0 JR |
439 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
440 | { | |
441 | return IRQ_WAKE_THREAD; | |
442 | } | |
443 | ||
431b2a20 JR |
444 | /**************************************************************************** |
445 | * | |
446 | * IOMMU command queuing functions | |
447 | * | |
448 | ****************************************************************************/ | |
449 | ||
ac0ea6e9 JR |
450 | static int wait_on_sem(volatile u64 *sem) |
451 | { | |
452 | int i = 0; | |
453 | ||
454 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
455 | udelay(1); | |
456 | i += 1; | |
457 | } | |
458 | ||
459 | if (i == LOOP_TIMEOUT) { | |
460 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
461 | return -EIO; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
468 | struct iommu_cmd *cmd, | |
469 | u32 tail) | |
a19ae1ec | 470 | { |
a19ae1ec JR |
471 | u8 *target; |
472 | ||
8a7c5ef3 | 473 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
474 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
475 | ||
476 | /* Copy command to buffer */ | |
477 | memcpy(target, cmd, sizeof(*cmd)); | |
478 | ||
479 | /* Tell the IOMMU about it */ | |
a19ae1ec | 480 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 481 | } |
a19ae1ec | 482 | |
815b33fd | 483 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 484 | { |
815b33fd JR |
485 | WARN_ON(address & 0x7ULL); |
486 | ||
ded46737 | 487 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
488 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
489 | cmd->data[1] = upper_32_bits(__pa(address)); | |
490 | cmd->data[2] = 1; | |
ded46737 JR |
491 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
492 | } | |
493 | ||
94fe79e2 JR |
494 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
495 | { | |
496 | memset(cmd, 0, sizeof(*cmd)); | |
497 | cmd->data[0] = devid; | |
498 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
499 | } | |
500 | ||
11b6402c JR |
501 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
502 | size_t size, u16 domid, int pde) | |
503 | { | |
504 | u64 pages; | |
505 | int s; | |
506 | ||
507 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
508 | s = 0; | |
509 | ||
510 | if (pages > 1) { | |
511 | /* | |
512 | * If we have to flush more than one page, flush all | |
513 | * TLB entries for this domain | |
514 | */ | |
515 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
516 | s = 1; | |
517 | } | |
518 | ||
519 | address &= PAGE_MASK; | |
520 | ||
521 | memset(cmd, 0, sizeof(*cmd)); | |
522 | cmd->data[1] |= domid; | |
523 | cmd->data[2] = lower_32_bits(address); | |
524 | cmd->data[3] = upper_32_bits(address); | |
525 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
526 | if (s) /* size bit - we flush more than one 4kb page */ | |
527 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
528 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
529 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
530 | } | |
531 | ||
cb41ed85 JR |
532 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
533 | u64 address, size_t size) | |
534 | { | |
535 | u64 pages; | |
536 | int s; | |
537 | ||
538 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
539 | s = 0; | |
540 | ||
541 | if (pages > 1) { | |
542 | /* | |
543 | * If we have to flush more than one page, flush all | |
544 | * TLB entries for this domain | |
545 | */ | |
546 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
547 | s = 1; | |
548 | } | |
549 | ||
550 | address &= PAGE_MASK; | |
551 | ||
552 | memset(cmd, 0, sizeof(*cmd)); | |
553 | cmd->data[0] = devid; | |
554 | cmd->data[0] |= (qdep & 0xff) << 24; | |
555 | cmd->data[1] = devid; | |
556 | cmd->data[2] = lower_32_bits(address); | |
557 | cmd->data[3] = upper_32_bits(address); | |
558 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
559 | if (s) | |
560 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
561 | } | |
562 | ||
58fc7f14 JR |
563 | static void build_inv_all(struct iommu_cmd *cmd) |
564 | { | |
565 | memset(cmd, 0, sizeof(*cmd)); | |
566 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
567 | } |
568 | ||
431b2a20 | 569 | /* |
431b2a20 | 570 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 571 | * hardware about the new command. |
431b2a20 | 572 | */ |
d6449536 | 573 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 574 | { |
ac0ea6e9 | 575 | u32 left, tail, head, next_tail; |
a19ae1ec | 576 | unsigned long flags; |
a19ae1ec | 577 | |
549c90dc | 578 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
579 | |
580 | again: | |
a19ae1ec | 581 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 582 | |
ac0ea6e9 JR |
583 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
584 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
585 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
586 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 587 | |
ac0ea6e9 JR |
588 | if (left <= 2) { |
589 | struct iommu_cmd sync_cmd; | |
590 | volatile u64 sem = 0; | |
591 | int ret; | |
8d201968 | 592 | |
ac0ea6e9 JR |
593 | build_completion_wait(&sync_cmd, (u64)&sem); |
594 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 595 | |
ac0ea6e9 JR |
596 | spin_unlock_irqrestore(&iommu->lock, flags); |
597 | ||
598 | if ((ret = wait_on_sem(&sem)) != 0) | |
599 | return ret; | |
600 | ||
601 | goto again; | |
8d201968 JR |
602 | } |
603 | ||
ac0ea6e9 JR |
604 | copy_cmd_to_buffer(iommu, cmd, tail); |
605 | ||
606 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 607 | iommu->need_sync = true; |
ac0ea6e9 | 608 | |
a19ae1ec | 609 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 610 | |
815b33fd | 611 | return 0; |
8d201968 JR |
612 | } |
613 | ||
614 | /* | |
615 | * This function queues a completion wait command into the command | |
616 | * buffer of an IOMMU | |
617 | */ | |
a19ae1ec | 618 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
619 | { |
620 | struct iommu_cmd cmd; | |
815b33fd | 621 | volatile u64 sem = 0; |
ac0ea6e9 | 622 | int ret; |
8d201968 | 623 | |
09ee17eb | 624 | if (!iommu->need_sync) |
815b33fd | 625 | return 0; |
09ee17eb | 626 | |
815b33fd | 627 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 628 | |
815b33fd | 629 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 630 | if (ret) |
815b33fd | 631 | return ret; |
8d201968 | 632 | |
ac0ea6e9 | 633 | return wait_on_sem(&sem); |
8d201968 JR |
634 | } |
635 | ||
d8c13085 | 636 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 637 | { |
d8c13085 | 638 | struct iommu_cmd cmd; |
a19ae1ec | 639 | |
d8c13085 | 640 | build_inv_dte(&cmd, devid); |
7e4f88da | 641 | |
d8c13085 JR |
642 | return iommu_queue_command(iommu, &cmd); |
643 | } | |
09ee17eb | 644 | |
7d0c5cc5 JR |
645 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
646 | { | |
647 | u32 devid; | |
09ee17eb | 648 | |
7d0c5cc5 JR |
649 | for (devid = 0; devid <= 0xffff; ++devid) |
650 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 651 | |
7d0c5cc5 JR |
652 | iommu_completion_wait(iommu); |
653 | } | |
84df8175 | 654 | |
7d0c5cc5 JR |
655 | /* |
656 | * This function uses heavy locking and may disable irqs for some time. But | |
657 | * this is no issue because it is only called during resume. | |
658 | */ | |
659 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
660 | { | |
661 | u32 dom_id; | |
a19ae1ec | 662 | |
7d0c5cc5 JR |
663 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
664 | struct iommu_cmd cmd; | |
665 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
666 | dom_id, 1); | |
667 | iommu_queue_command(iommu, &cmd); | |
668 | } | |
8eed9833 | 669 | |
7d0c5cc5 | 670 | iommu_completion_wait(iommu); |
a19ae1ec JR |
671 | } |
672 | ||
58fc7f14 | 673 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 674 | { |
58fc7f14 | 675 | struct iommu_cmd cmd; |
0518a3a4 | 676 | |
58fc7f14 | 677 | build_inv_all(&cmd); |
0518a3a4 | 678 | |
58fc7f14 JR |
679 | iommu_queue_command(iommu, &cmd); |
680 | iommu_completion_wait(iommu); | |
681 | } | |
682 | ||
7d0c5cc5 JR |
683 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
684 | { | |
58fc7f14 JR |
685 | if (iommu_feature(iommu, FEATURE_IA)) { |
686 | iommu_flush_all(iommu); | |
687 | } else { | |
688 | iommu_flush_dte_all(iommu); | |
689 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
690 | } |
691 | } | |
692 | ||
431b2a20 | 693 | /* |
cb41ed85 | 694 | * Command send function for flushing on-device TLB |
431b2a20 | 695 | */ |
cb41ed85 | 696 | static int device_flush_iotlb(struct device *dev, u64 address, size_t size) |
3fa43655 | 697 | { |
cb41ed85 | 698 | struct pci_dev *pdev = to_pci_dev(dev); |
3fa43655 | 699 | struct amd_iommu *iommu; |
b00d3bcf | 700 | struct iommu_cmd cmd; |
3fa43655 | 701 | u16 devid; |
cb41ed85 | 702 | int qdep; |
3fa43655 | 703 | |
cb41ed85 | 704 | qdep = pci_ats_queue_depth(pdev); |
3fa43655 JR |
705 | devid = get_device_id(dev); |
706 | iommu = amd_iommu_rlookup_table[devid]; | |
707 | ||
cb41ed85 | 708 | build_inv_iotlb_pages(&cmd, devid, qdep, address, size); |
b00d3bcf JR |
709 | |
710 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
711 | } |
712 | ||
431b2a20 | 713 | /* |
431b2a20 | 714 | * Command send function for invalidating a device table entry |
431b2a20 | 715 | */ |
d8c13085 | 716 | static int device_flush_dte(struct device *dev) |
a19ae1ec | 717 | { |
f62dda66 | 718 | struct iommu_dev_data *dev_data; |
3fa43655 | 719 | struct amd_iommu *iommu; |
cb41ed85 | 720 | struct pci_dev *pdev; |
ee2fa743 | 721 | int ret; |
a19ae1ec | 722 | |
f62dda66 JR |
723 | pdev = to_pci_dev(dev); |
724 | dev_data = get_dev_data(dev); | |
725 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
a19ae1ec | 726 | |
f62dda66 | 727 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
728 | if (ret) |
729 | return ret; | |
730 | ||
731 | if (pci_ats_enabled(pdev)) | |
732 | ret = device_flush_iotlb(dev, 0, ~0UL); | |
ee2fa743 | 733 | |
ee2fa743 | 734 | return ret; |
a19ae1ec JR |
735 | } |
736 | ||
431b2a20 JR |
737 | /* |
738 | * TLB invalidation function which is called from the mapping functions. | |
739 | * It invalidates a single PTE if the range to flush is within a single | |
740 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
741 | */ | |
17b124bf JR |
742 | static void __domain_flush_pages(struct protection_domain *domain, |
743 | u64 address, size_t size, int pde) | |
a19ae1ec | 744 | { |
cb41ed85 | 745 | struct iommu_dev_data *dev_data; |
11b6402c JR |
746 | struct iommu_cmd cmd; |
747 | int ret = 0, i; | |
a19ae1ec | 748 | |
11b6402c | 749 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 750 | |
6de8ad9b JR |
751 | for (i = 0; i < amd_iommus_present; ++i) { |
752 | if (!domain->dev_iommu[i]) | |
753 | continue; | |
754 | ||
755 | /* | |
756 | * Devices of this domain are behind this IOMMU | |
757 | * We need a TLB flush | |
758 | */ | |
11b6402c | 759 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
760 | } |
761 | ||
cb41ed85 JR |
762 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
763 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); | |
764 | ||
765 | if (!pci_ats_enabled(pdev)) | |
766 | continue; | |
767 | ||
768 | ret |= device_flush_iotlb(dev_data->dev, address, size); | |
769 | } | |
770 | ||
11b6402c | 771 | WARN_ON(ret); |
6de8ad9b JR |
772 | } |
773 | ||
17b124bf JR |
774 | static void domain_flush_pages(struct protection_domain *domain, |
775 | u64 address, size_t size) | |
6de8ad9b | 776 | { |
17b124bf | 777 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 778 | } |
b6c02715 | 779 | |
1c655773 | 780 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 781 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 782 | { |
17b124bf | 783 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
784 | } |
785 | ||
42a49f96 | 786 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 787 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 788 | { |
17b124bf | 789 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
790 | } |
791 | ||
17b124bf | 792 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 793 | { |
17b124bf | 794 | int i; |
18811f55 | 795 | |
17b124bf JR |
796 | for (i = 0; i < amd_iommus_present; ++i) { |
797 | if (!domain->dev_iommu[i]) | |
798 | continue; | |
bfd1be18 | 799 | |
17b124bf JR |
800 | /* |
801 | * Devices of this domain are behind this IOMMU | |
802 | * We need to wait for completion of all commands. | |
803 | */ | |
804 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 805 | } |
e394d72a JR |
806 | } |
807 | ||
b00d3bcf | 808 | |
09b42804 | 809 | /* |
b00d3bcf | 810 | * This function flushes the DTEs for all devices in domain |
09b42804 | 811 | */ |
17b124bf | 812 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 813 | { |
b00d3bcf | 814 | struct iommu_dev_data *dev_data; |
09b42804 JR |
815 | unsigned long flags; |
816 | ||
b00d3bcf | 817 | spin_lock_irqsave(&domain->lock, flags); |
b26e81b8 | 818 | |
b00d3bcf | 819 | list_for_each_entry(dev_data, &domain->dev_list, list) |
d8c13085 | 820 | device_flush_dte(dev_data->dev); |
b26e81b8 | 821 | |
b00d3bcf | 822 | spin_unlock_irqrestore(&domain->lock, flags); |
a345b23b JR |
823 | } |
824 | ||
431b2a20 JR |
825 | /**************************************************************************** |
826 | * | |
827 | * The functions below are used the create the page table mappings for | |
828 | * unity mapped regions. | |
829 | * | |
830 | ****************************************************************************/ | |
831 | ||
308973d3 JR |
832 | /* |
833 | * This function is used to add another level to an IO page table. Adding | |
834 | * another level increases the size of the address space by 9 bits to a size up | |
835 | * to 64 bits. | |
836 | */ | |
837 | static bool increase_address_space(struct protection_domain *domain, | |
838 | gfp_t gfp) | |
839 | { | |
840 | u64 *pte; | |
841 | ||
842 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
843 | /* address space already 64 bit large */ | |
844 | return false; | |
845 | ||
846 | pte = (void *)get_zeroed_page(gfp); | |
847 | if (!pte) | |
848 | return false; | |
849 | ||
850 | *pte = PM_LEVEL_PDE(domain->mode, | |
851 | virt_to_phys(domain->pt_root)); | |
852 | domain->pt_root = pte; | |
853 | domain->mode += 1; | |
854 | domain->updated = true; | |
855 | ||
856 | return true; | |
857 | } | |
858 | ||
859 | static u64 *alloc_pte(struct protection_domain *domain, | |
860 | unsigned long address, | |
cbb9d729 | 861 | unsigned long page_size, |
308973d3 JR |
862 | u64 **pte_page, |
863 | gfp_t gfp) | |
864 | { | |
cbb9d729 | 865 | int level, end_lvl; |
308973d3 | 866 | u64 *pte, *page; |
cbb9d729 JR |
867 | |
868 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
869 | |
870 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
871 | increase_address_space(domain, gfp); | |
872 | ||
cbb9d729 JR |
873 | level = domain->mode - 1; |
874 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
875 | address = PAGE_SIZE_ALIGN(address, page_size); | |
876 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
877 | |
878 | while (level > end_lvl) { | |
879 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
880 | page = (u64 *)get_zeroed_page(gfp); | |
881 | if (!page) | |
882 | return NULL; | |
883 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
884 | } | |
885 | ||
cbb9d729 JR |
886 | /* No level skipping support yet */ |
887 | if (PM_PTE_LEVEL(*pte) != level) | |
888 | return NULL; | |
889 | ||
308973d3 JR |
890 | level -= 1; |
891 | ||
892 | pte = IOMMU_PTE_PAGE(*pte); | |
893 | ||
894 | if (pte_page && level == end_lvl) | |
895 | *pte_page = pte; | |
896 | ||
897 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
898 | } | |
899 | ||
900 | return pte; | |
901 | } | |
902 | ||
903 | /* | |
904 | * This function checks if there is a PTE for a given dma address. If | |
905 | * there is one, it returns the pointer to it. | |
906 | */ | |
24cd7723 | 907 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
908 | { |
909 | int level; | |
910 | u64 *pte; | |
911 | ||
24cd7723 JR |
912 | if (address > PM_LEVEL_SIZE(domain->mode)) |
913 | return NULL; | |
914 | ||
915 | level = domain->mode - 1; | |
916 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 917 | |
24cd7723 JR |
918 | while (level > 0) { |
919 | ||
920 | /* Not Present */ | |
308973d3 JR |
921 | if (!IOMMU_PTE_PRESENT(*pte)) |
922 | return NULL; | |
923 | ||
24cd7723 JR |
924 | /* Large PTE */ |
925 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
926 | unsigned long pte_mask, __pte; | |
927 | ||
928 | /* | |
929 | * If we have a series of large PTEs, make | |
930 | * sure to return a pointer to the first one. | |
931 | */ | |
932 | pte_mask = PTE_PAGE_SIZE(*pte); | |
933 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
934 | __pte = ((unsigned long)pte) & pte_mask; | |
935 | ||
936 | return (u64 *)__pte; | |
937 | } | |
938 | ||
939 | /* No level skipping support yet */ | |
940 | if (PM_PTE_LEVEL(*pte) != level) | |
941 | return NULL; | |
942 | ||
308973d3 JR |
943 | level -= 1; |
944 | ||
24cd7723 | 945 | /* Walk to the next level */ |
308973d3 JR |
946 | pte = IOMMU_PTE_PAGE(*pte); |
947 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
948 | } |
949 | ||
950 | return pte; | |
951 | } | |
952 | ||
431b2a20 JR |
953 | /* |
954 | * Generic mapping functions. It maps a physical address into a DMA | |
955 | * address space. It allocates the page table pages if necessary. | |
956 | * In the future it can be extended to a generic mapping function | |
957 | * supporting all features of AMD IOMMU page tables like level skipping | |
958 | * and full 64 bit address spaces. | |
959 | */ | |
38e817fe JR |
960 | static int iommu_map_page(struct protection_domain *dom, |
961 | unsigned long bus_addr, | |
962 | unsigned long phys_addr, | |
abdc5eb3 | 963 | int prot, |
cbb9d729 | 964 | unsigned long page_size) |
bd0e5211 | 965 | { |
8bda3092 | 966 | u64 __pte, *pte; |
cbb9d729 | 967 | int i, count; |
abdc5eb3 | 968 | |
bad1cac2 | 969 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
970 | return -EINVAL; |
971 | ||
cbb9d729 JR |
972 | bus_addr = PAGE_ALIGN(bus_addr); |
973 | phys_addr = PAGE_ALIGN(phys_addr); | |
974 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
975 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
976 | ||
977 | for (i = 0; i < count; ++i) | |
978 | if (IOMMU_PTE_PRESENT(pte[i])) | |
979 | return -EBUSY; | |
bd0e5211 | 980 | |
cbb9d729 JR |
981 | if (page_size > PAGE_SIZE) { |
982 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
983 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
984 | } else | |
985 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 986 | |
bd0e5211 JR |
987 | if (prot & IOMMU_PROT_IR) |
988 | __pte |= IOMMU_PTE_IR; | |
989 | if (prot & IOMMU_PROT_IW) | |
990 | __pte |= IOMMU_PTE_IW; | |
991 | ||
cbb9d729 JR |
992 | for (i = 0; i < count; ++i) |
993 | pte[i] = __pte; | |
bd0e5211 | 994 | |
04bfdd84 JR |
995 | update_domain(dom); |
996 | ||
bd0e5211 JR |
997 | return 0; |
998 | } | |
999 | ||
24cd7723 JR |
1000 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1001 | unsigned long bus_addr, | |
1002 | unsigned long page_size) | |
eb74ff6c | 1003 | { |
24cd7723 JR |
1004 | unsigned long long unmap_size, unmapped; |
1005 | u64 *pte; | |
1006 | ||
1007 | BUG_ON(!is_power_of_2(page_size)); | |
1008 | ||
1009 | unmapped = 0; | |
eb74ff6c | 1010 | |
24cd7723 JR |
1011 | while (unmapped < page_size) { |
1012 | ||
1013 | pte = fetch_pte(dom, bus_addr); | |
1014 | ||
1015 | if (!pte) { | |
1016 | /* | |
1017 | * No PTE for this address | |
1018 | * move forward in 4kb steps | |
1019 | */ | |
1020 | unmap_size = PAGE_SIZE; | |
1021 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1022 | /* 4kb PTE found for this address */ | |
1023 | unmap_size = PAGE_SIZE; | |
1024 | *pte = 0ULL; | |
1025 | } else { | |
1026 | int count, i; | |
1027 | ||
1028 | /* Large PTE found which maps this address */ | |
1029 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1030 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1031 | for (i = 0; i < count; i++) | |
1032 | pte[i] = 0ULL; | |
1033 | } | |
1034 | ||
1035 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1036 | unmapped += unmap_size; | |
1037 | } | |
1038 | ||
1039 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1040 | |
24cd7723 | 1041 | return unmapped; |
eb74ff6c | 1042 | } |
eb74ff6c | 1043 | |
431b2a20 JR |
1044 | /* |
1045 | * This function checks if a specific unity mapping entry is needed for | |
1046 | * this specific IOMMU. | |
1047 | */ | |
bd0e5211 JR |
1048 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1049 | struct unity_map_entry *entry) | |
1050 | { | |
1051 | u16 bdf, i; | |
1052 | ||
1053 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1054 | bdf = amd_iommu_alias_table[i]; | |
1055 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1056 | return 1; | |
1057 | } | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
431b2a20 JR |
1062 | /* |
1063 | * This function actually applies the mapping to the page table of the | |
1064 | * dma_ops domain. | |
1065 | */ | |
bd0e5211 JR |
1066 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1067 | struct unity_map_entry *e) | |
1068 | { | |
1069 | u64 addr; | |
1070 | int ret; | |
1071 | ||
1072 | for (addr = e->address_start; addr < e->address_end; | |
1073 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1074 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1075 | PAGE_SIZE); |
bd0e5211 JR |
1076 | if (ret) |
1077 | return ret; | |
1078 | /* | |
1079 | * if unity mapping is in aperture range mark the page | |
1080 | * as allocated in the aperture | |
1081 | */ | |
1082 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1083 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1084 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1085 | } |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
171e7b37 JR |
1090 | /* |
1091 | * Init the unity mappings for a specific IOMMU in the system | |
1092 | * | |
1093 | * Basically iterates over all unity mapping entries and applies them to | |
1094 | * the default domain DMA of that IOMMU if necessary. | |
1095 | */ | |
1096 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1097 | { | |
1098 | struct unity_map_entry *entry; | |
1099 | int ret; | |
1100 | ||
1101 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1102 | if (!iommu_for_unity_map(iommu, entry)) | |
1103 | continue; | |
1104 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1105 | if (ret) | |
1106 | return ret; | |
1107 | } | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | ||
431b2a20 JR |
1112 | /* |
1113 | * Inits the unity mappings required for a specific device | |
1114 | */ | |
bd0e5211 JR |
1115 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1116 | u16 devid) | |
1117 | { | |
1118 | struct unity_map_entry *e; | |
1119 | int ret; | |
1120 | ||
1121 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1122 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1123 | continue; | |
1124 | ret = dma_ops_unity_map(dma_dom, e); | |
1125 | if (ret) | |
1126 | return ret; | |
1127 | } | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
431b2a20 JR |
1132 | /**************************************************************************** |
1133 | * | |
1134 | * The next functions belong to the address allocator for the dma_ops | |
1135 | * interface functions. They work like the allocators in the other IOMMU | |
1136 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1137 | * the aperture. Maybe it could be enhanced in the future to a more | |
1138 | * efficient allocator. | |
1139 | * | |
1140 | ****************************************************************************/ | |
d3086444 | 1141 | |
431b2a20 | 1142 | /* |
384de729 | 1143 | * The address allocator core functions. |
431b2a20 JR |
1144 | * |
1145 | * called with domain->lock held | |
1146 | */ | |
384de729 | 1147 | |
171e7b37 JR |
1148 | /* |
1149 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1150 | * ranges. | |
1151 | */ | |
1152 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1153 | unsigned long start_page, | |
1154 | unsigned int pages) | |
1155 | { | |
1156 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1157 | ||
1158 | if (start_page + pages > last_page) | |
1159 | pages = last_page - start_page; | |
1160 | ||
1161 | for (i = start_page; i < start_page + pages; ++i) { | |
1162 | int index = i / APERTURE_RANGE_PAGES; | |
1163 | int page = i % APERTURE_RANGE_PAGES; | |
1164 | __set_bit(page, dom->aperture[index]->bitmap); | |
1165 | } | |
1166 | } | |
1167 | ||
9cabe89b JR |
1168 | /* |
1169 | * This function is used to add a new aperture range to an existing | |
1170 | * aperture in case of dma_ops domain allocation or address allocation | |
1171 | * failure. | |
1172 | */ | |
576175c2 | 1173 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1174 | bool populate, gfp_t gfp) |
1175 | { | |
1176 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1177 | struct amd_iommu *iommu; |
d91afd15 | 1178 | unsigned long i; |
9cabe89b | 1179 | |
f5e9705c JR |
1180 | #ifdef CONFIG_IOMMU_STRESS |
1181 | populate = false; | |
1182 | #endif | |
1183 | ||
9cabe89b JR |
1184 | if (index >= APERTURE_MAX_RANGES) |
1185 | return -ENOMEM; | |
1186 | ||
1187 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1188 | if (!dma_dom->aperture[index]) | |
1189 | return -ENOMEM; | |
1190 | ||
1191 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1192 | if (!dma_dom->aperture[index]->bitmap) | |
1193 | goto out_free; | |
1194 | ||
1195 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1196 | ||
1197 | if (populate) { | |
1198 | unsigned long address = dma_dom->aperture_size; | |
1199 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1200 | u64 *pte, *pte_page; | |
1201 | ||
1202 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1203 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1204 | &pte_page, gfp); |
1205 | if (!pte) | |
1206 | goto out_free; | |
1207 | ||
1208 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1209 | ||
1210 | address += APERTURE_RANGE_SIZE / 64; | |
1211 | } | |
1212 | } | |
1213 | ||
1214 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1215 | ||
b595076a | 1216 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1217 | for_each_iommu(iommu) { |
1218 | if (iommu->exclusion_start && | |
1219 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1220 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1221 | unsigned long startpage; | |
1222 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1223 | iommu->exclusion_length, | |
1224 | PAGE_SIZE); | |
1225 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1226 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1227 | } | |
00cd122a JR |
1228 | } |
1229 | ||
1230 | /* | |
1231 | * Check for areas already mapped as present in the new aperture | |
1232 | * range and mark those pages as reserved in the allocator. Such | |
1233 | * mappings may already exist as a result of requested unity | |
1234 | * mappings for devices. | |
1235 | */ | |
1236 | for (i = dma_dom->aperture[index]->offset; | |
1237 | i < dma_dom->aperture_size; | |
1238 | i += PAGE_SIZE) { | |
24cd7723 | 1239 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1240 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1241 | continue; | |
1242 | ||
1243 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1244 | } | |
1245 | ||
04bfdd84 JR |
1246 | update_domain(&dma_dom->domain); |
1247 | ||
9cabe89b JR |
1248 | return 0; |
1249 | ||
1250 | out_free: | |
04bfdd84 JR |
1251 | update_domain(&dma_dom->domain); |
1252 | ||
9cabe89b JR |
1253 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1254 | ||
1255 | kfree(dma_dom->aperture[index]); | |
1256 | dma_dom->aperture[index] = NULL; | |
1257 | ||
1258 | return -ENOMEM; | |
1259 | } | |
1260 | ||
384de729 JR |
1261 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1262 | struct dma_ops_domain *dom, | |
1263 | unsigned int pages, | |
1264 | unsigned long align_mask, | |
1265 | u64 dma_mask, | |
1266 | unsigned long start) | |
1267 | { | |
803b8cb4 | 1268 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1269 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1270 | int i = start >> APERTURE_RANGE_SHIFT; | |
1271 | unsigned long boundary_size; | |
1272 | unsigned long address = -1; | |
1273 | unsigned long limit; | |
1274 | ||
803b8cb4 JR |
1275 | next_bit >>= PAGE_SHIFT; |
1276 | ||
384de729 JR |
1277 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1278 | PAGE_SIZE) >> PAGE_SHIFT; | |
1279 | ||
1280 | for (;i < max_index; ++i) { | |
1281 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1282 | ||
1283 | if (dom->aperture[i]->offset >= dma_mask) | |
1284 | break; | |
1285 | ||
1286 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1287 | dma_mask >> PAGE_SHIFT); | |
1288 | ||
1289 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1290 | limit, next_bit, pages, 0, | |
1291 | boundary_size, align_mask); | |
1292 | if (address != -1) { | |
1293 | address = dom->aperture[i]->offset + | |
1294 | (address << PAGE_SHIFT); | |
803b8cb4 | 1295 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1296 | break; |
1297 | } | |
1298 | ||
1299 | next_bit = 0; | |
1300 | } | |
1301 | ||
1302 | return address; | |
1303 | } | |
1304 | ||
d3086444 JR |
1305 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1306 | struct dma_ops_domain *dom, | |
6d4f343f | 1307 | unsigned int pages, |
832a90c3 JR |
1308 | unsigned long align_mask, |
1309 | u64 dma_mask) | |
d3086444 | 1310 | { |
d3086444 | 1311 | unsigned long address; |
d3086444 | 1312 | |
fe16f088 JR |
1313 | #ifdef CONFIG_IOMMU_STRESS |
1314 | dom->next_address = 0; | |
1315 | dom->need_flush = true; | |
1316 | #endif | |
d3086444 | 1317 | |
384de729 | 1318 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1319 | dma_mask, dom->next_address); |
d3086444 | 1320 | |
1c655773 | 1321 | if (address == -1) { |
803b8cb4 | 1322 | dom->next_address = 0; |
384de729 JR |
1323 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1324 | dma_mask, 0); | |
1c655773 JR |
1325 | dom->need_flush = true; |
1326 | } | |
d3086444 | 1327 | |
384de729 | 1328 | if (unlikely(address == -1)) |
8fd524b3 | 1329 | address = DMA_ERROR_CODE; |
d3086444 JR |
1330 | |
1331 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1332 | ||
1333 | return address; | |
1334 | } | |
1335 | ||
431b2a20 JR |
1336 | /* |
1337 | * The address free function. | |
1338 | * | |
1339 | * called with domain->lock held | |
1340 | */ | |
d3086444 JR |
1341 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1342 | unsigned long address, | |
1343 | unsigned int pages) | |
1344 | { | |
384de729 JR |
1345 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1346 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1347 | |
384de729 JR |
1348 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1349 | ||
47bccd6b JR |
1350 | #ifdef CONFIG_IOMMU_STRESS |
1351 | if (i < 4) | |
1352 | return; | |
1353 | #endif | |
80be308d | 1354 | |
803b8cb4 | 1355 | if (address >= dom->next_address) |
80be308d | 1356 | dom->need_flush = true; |
384de729 JR |
1357 | |
1358 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1359 | |
a66022c4 | 1360 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1361 | |
d3086444 JR |
1362 | } |
1363 | ||
431b2a20 JR |
1364 | /**************************************************************************** |
1365 | * | |
1366 | * The next functions belong to the domain allocation. A domain is | |
1367 | * allocated for every IOMMU as the default domain. If device isolation | |
1368 | * is enabled, every device get its own domain. The most important thing | |
1369 | * about domains is the page table mapping the DMA address space they | |
1370 | * contain. | |
1371 | * | |
1372 | ****************************************************************************/ | |
1373 | ||
aeb26f55 JR |
1374 | /* |
1375 | * This function adds a protection domain to the global protection domain list | |
1376 | */ | |
1377 | static void add_domain_to_list(struct protection_domain *domain) | |
1378 | { | |
1379 | unsigned long flags; | |
1380 | ||
1381 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1382 | list_add(&domain->list, &amd_iommu_pd_list); | |
1383 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1384 | } | |
1385 | ||
1386 | /* | |
1387 | * This function removes a protection domain to the global | |
1388 | * protection domain list | |
1389 | */ | |
1390 | static void del_domain_from_list(struct protection_domain *domain) | |
1391 | { | |
1392 | unsigned long flags; | |
1393 | ||
1394 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1395 | list_del(&domain->list); | |
1396 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1397 | } | |
1398 | ||
ec487d1a JR |
1399 | static u16 domain_id_alloc(void) |
1400 | { | |
1401 | unsigned long flags; | |
1402 | int id; | |
1403 | ||
1404 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1405 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1406 | BUG_ON(id == 0); | |
1407 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1408 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1409 | else | |
1410 | id = 0; | |
1411 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1412 | ||
1413 | return id; | |
1414 | } | |
1415 | ||
a2acfb75 JR |
1416 | static void domain_id_free(int id) |
1417 | { | |
1418 | unsigned long flags; | |
1419 | ||
1420 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1421 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1422 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1423 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1424 | } | |
a2acfb75 | 1425 | |
86db2e5d | 1426 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1427 | { |
1428 | int i, j; | |
1429 | u64 *p1, *p2, *p3; | |
1430 | ||
86db2e5d | 1431 | p1 = domain->pt_root; |
ec487d1a JR |
1432 | |
1433 | if (!p1) | |
1434 | return; | |
1435 | ||
1436 | for (i = 0; i < 512; ++i) { | |
1437 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1438 | continue; | |
1439 | ||
1440 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1441 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1442 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1443 | continue; | |
1444 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1445 | free_page((unsigned long)p3); | |
1446 | } | |
1447 | ||
1448 | free_page((unsigned long)p2); | |
1449 | } | |
1450 | ||
1451 | free_page((unsigned long)p1); | |
86db2e5d JR |
1452 | |
1453 | domain->pt_root = NULL; | |
ec487d1a JR |
1454 | } |
1455 | ||
431b2a20 JR |
1456 | /* |
1457 | * Free a domain, only used if something went wrong in the | |
1458 | * allocation path and we need to free an already allocated page table | |
1459 | */ | |
ec487d1a JR |
1460 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1461 | { | |
384de729 JR |
1462 | int i; |
1463 | ||
ec487d1a JR |
1464 | if (!dom) |
1465 | return; | |
1466 | ||
aeb26f55 JR |
1467 | del_domain_from_list(&dom->domain); |
1468 | ||
86db2e5d | 1469 | free_pagetable(&dom->domain); |
ec487d1a | 1470 | |
384de729 JR |
1471 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1472 | if (!dom->aperture[i]) | |
1473 | continue; | |
1474 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1475 | kfree(dom->aperture[i]); | |
1476 | } | |
ec487d1a JR |
1477 | |
1478 | kfree(dom); | |
1479 | } | |
1480 | ||
431b2a20 JR |
1481 | /* |
1482 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1483 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1484 | * structures required for the dma_ops interface |
1485 | */ | |
87a64d52 | 1486 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1487 | { |
1488 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1489 | |
1490 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1491 | if (!dma_dom) | |
1492 | return NULL; | |
1493 | ||
1494 | spin_lock_init(&dma_dom->domain.lock); | |
1495 | ||
1496 | dma_dom->domain.id = domain_id_alloc(); | |
1497 | if (dma_dom->domain.id == 0) | |
1498 | goto free_dma_dom; | |
7c392cbe | 1499 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1500 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1501 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1502 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1503 | dma_dom->domain.priv = dma_dom; |
1504 | if (!dma_dom->domain.pt_root) | |
1505 | goto free_dma_dom; | |
ec487d1a | 1506 | |
1c655773 | 1507 | dma_dom->need_flush = false; |
bd60b735 | 1508 | dma_dom->target_dev = 0xffff; |
1c655773 | 1509 | |
aeb26f55 JR |
1510 | add_domain_to_list(&dma_dom->domain); |
1511 | ||
576175c2 | 1512 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1513 | goto free_dma_dom; |
ec487d1a | 1514 | |
431b2a20 | 1515 | /* |
ec487d1a JR |
1516 | * mark the first page as allocated so we never return 0 as |
1517 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1518 | */ |
384de729 | 1519 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1520 | dma_dom->next_address = 0; |
ec487d1a | 1521 | |
ec487d1a JR |
1522 | |
1523 | return dma_dom; | |
1524 | ||
1525 | free_dma_dom: | |
1526 | dma_ops_domain_free(dma_dom); | |
1527 | ||
1528 | return NULL; | |
1529 | } | |
1530 | ||
5b28df6f JR |
1531 | /* |
1532 | * little helper function to check whether a given protection domain is a | |
1533 | * dma_ops domain | |
1534 | */ | |
1535 | static bool dma_ops_domain(struct protection_domain *domain) | |
1536 | { | |
1537 | return domain->flags & PD_DMA_OPS_MASK; | |
1538 | } | |
1539 | ||
fd7b5535 | 1540 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1541 | { |
b20ac0d4 | 1542 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1543 | u32 flags = 0; |
863c74eb | 1544 | |
38ddf41b JR |
1545 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1546 | << DEV_ENTRY_MODE_SHIFT; | |
1547 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1548 | |
fd7b5535 JR |
1549 | if (ats) |
1550 | flags |= DTE_FLAG_IOTLB; | |
1551 | ||
1552 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1553 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1554 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1555 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1556 | } |
1557 | ||
1558 | static void clear_dte_entry(u16 devid) | |
1559 | { | |
15898bbc JR |
1560 | /* remove entry from the device table seen by the hardware */ |
1561 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1562 | amd_iommu_dev_table[devid].data[1] = 0; | |
1563 | amd_iommu_dev_table[devid].data[2] = 0; | |
1564 | ||
1565 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1566 | } |
1567 | ||
1568 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1569 | { | |
1570 | struct iommu_dev_data *dev_data; | |
1571 | struct amd_iommu *iommu; | |
fd7b5535 JR |
1572 | struct pci_dev *pdev; |
1573 | bool ats = false; | |
7f760ddd | 1574 | |
7f760ddd | 1575 | dev_data = get_dev_data(dev); |
f62dda66 | 1576 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
fd7b5535 JR |
1577 | pdev = to_pci_dev(dev); |
1578 | ||
1579 | if (amd_iommu_iotlb_sup) | |
1580 | ats = pci_ats_enabled(pdev); | |
7f760ddd JR |
1581 | |
1582 | /* Update data structures */ | |
1583 | dev_data->domain = domain; | |
1584 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1585 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1586 | |
1587 | /* Do reference counting */ | |
1588 | domain->dev_iommu[iommu->index] += 1; | |
1589 | domain->dev_cnt += 1; | |
1590 | ||
1591 | /* Flush the DTE entry */ | |
d8c13085 | 1592 | device_flush_dte(dev); |
7f760ddd JR |
1593 | } |
1594 | ||
1595 | static void do_detach(struct device *dev) | |
1596 | { | |
1597 | struct iommu_dev_data *dev_data; | |
1598 | struct amd_iommu *iommu; | |
7f760ddd | 1599 | |
7f760ddd | 1600 | dev_data = get_dev_data(dev); |
f62dda66 | 1601 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1602 | |
1603 | /* decrease reference counters */ | |
7f760ddd JR |
1604 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1605 | dev_data->domain->dev_cnt -= 1; | |
1606 | ||
1607 | /* Update data structures */ | |
1608 | dev_data->domain = NULL; | |
1609 | list_del(&dev_data->list); | |
f62dda66 | 1610 | clear_dte_entry(dev_data->devid); |
15898bbc | 1611 | |
7f760ddd | 1612 | /* Flush the DTE entry */ |
d8c13085 | 1613 | device_flush_dte(dev); |
2b681faf JR |
1614 | } |
1615 | ||
1616 | /* | |
1617 | * If a device is not yet associated with a domain, this function does | |
1618 | * assigns it visible for the hardware | |
1619 | */ | |
15898bbc JR |
1620 | static int __attach_device(struct device *dev, |
1621 | struct protection_domain *domain) | |
2b681faf | 1622 | { |
657cbb6b | 1623 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1624 | int ret; |
657cbb6b | 1625 | |
657cbb6b JR |
1626 | dev_data = get_dev_data(dev); |
1627 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1628 | |
657cbb6b JR |
1629 | if (!alias_data) |
1630 | return -EINVAL; | |
15898bbc | 1631 | |
2b681faf JR |
1632 | /* lock domain */ |
1633 | spin_lock(&domain->lock); | |
1634 | ||
15898bbc | 1635 | /* Some sanity checks */ |
84fe6c19 | 1636 | ret = -EBUSY; |
657cbb6b JR |
1637 | if (alias_data->domain != NULL && |
1638 | alias_data->domain != domain) | |
84fe6c19 | 1639 | goto out_unlock; |
eba6ac60 | 1640 | |
657cbb6b JR |
1641 | if (dev_data->domain != NULL && |
1642 | dev_data->domain != domain) | |
84fe6c19 | 1643 | goto out_unlock; |
15898bbc JR |
1644 | |
1645 | /* Do real assignment */ | |
7f760ddd JR |
1646 | if (dev_data->alias != dev) { |
1647 | alias_data = get_dev_data(dev_data->alias); | |
1648 | if (alias_data->domain == NULL) | |
1649 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1650 | |
1651 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1652 | } |
15898bbc | 1653 | |
7f760ddd JR |
1654 | if (dev_data->domain == NULL) |
1655 | do_attach(dev, domain); | |
eba6ac60 | 1656 | |
24100055 JR |
1657 | atomic_inc(&dev_data->bind); |
1658 | ||
84fe6c19 JL |
1659 | ret = 0; |
1660 | ||
1661 | out_unlock: | |
1662 | ||
eba6ac60 JR |
1663 | /* ready */ |
1664 | spin_unlock(&domain->lock); | |
15898bbc | 1665 | |
84fe6c19 | 1666 | return ret; |
0feae533 | 1667 | } |
b20ac0d4 | 1668 | |
407d733e JR |
1669 | /* |
1670 | * If a device is not yet associated with a domain, this function does | |
1671 | * assigns it visible for the hardware | |
1672 | */ | |
15898bbc JR |
1673 | static int attach_device(struct device *dev, |
1674 | struct protection_domain *domain) | |
0feae533 | 1675 | { |
fd7b5535 | 1676 | struct pci_dev *pdev = to_pci_dev(dev); |
eba6ac60 | 1677 | unsigned long flags; |
15898bbc | 1678 | int ret; |
eba6ac60 | 1679 | |
fd7b5535 JR |
1680 | if (amd_iommu_iotlb_sup) |
1681 | pci_enable_ats(pdev, PAGE_SHIFT); | |
1682 | ||
eba6ac60 | 1683 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
15898bbc | 1684 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1685 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1686 | ||
0feae533 JR |
1687 | /* |
1688 | * We might boot into a crash-kernel here. The crashed kernel | |
1689 | * left the caches in the IOMMU dirty. So we have to flush | |
1690 | * here to evict all dirty stuff. | |
1691 | */ | |
17b124bf | 1692 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1693 | |
1694 | return ret; | |
b20ac0d4 JR |
1695 | } |
1696 | ||
355bf553 JR |
1697 | /* |
1698 | * Removes a device from a protection domain (unlocked) | |
1699 | */ | |
15898bbc | 1700 | static void __detach_device(struct device *dev) |
355bf553 | 1701 | { |
657cbb6b | 1702 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1703 | struct iommu_dev_data *alias_data; |
2ca76279 | 1704 | struct protection_domain *domain; |
7c392cbe | 1705 | unsigned long flags; |
c4596114 | 1706 | |
7f760ddd | 1707 | BUG_ON(!dev_data->domain); |
355bf553 | 1708 | |
2ca76279 JR |
1709 | domain = dev_data->domain; |
1710 | ||
1711 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1712 | |
7f760ddd | 1713 | if (dev_data->alias != dev) { |
24100055 | 1714 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1715 | if (atomic_dec_and_test(&alias_data->bind)) |
1716 | do_detach(dev_data->alias); | |
24100055 JR |
1717 | } |
1718 | ||
7f760ddd JR |
1719 | if (atomic_dec_and_test(&dev_data->bind)) |
1720 | do_detach(dev); | |
1721 | ||
2ca76279 | 1722 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1723 | |
1724 | /* | |
1725 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1726 | * passthrough domain if it is detached from any other domain. |
1727 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1728 | */ |
d3ad9373 JR |
1729 | if (iommu_pass_through && |
1730 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1731 | __attach_device(dev, pt_domain); |
355bf553 JR |
1732 | } |
1733 | ||
1734 | /* | |
1735 | * Removes a device from a protection domain (with devtable_lock held) | |
1736 | */ | |
15898bbc | 1737 | static void detach_device(struct device *dev) |
355bf553 | 1738 | { |
fd7b5535 | 1739 | struct pci_dev *pdev = to_pci_dev(dev); |
355bf553 JR |
1740 | unsigned long flags; |
1741 | ||
1742 | /* lock device table */ | |
1743 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1744 | __detach_device(dev); |
355bf553 | 1745 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 JR |
1746 | |
1747 | if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev)) | |
1748 | pci_disable_ats(pdev); | |
355bf553 | 1749 | } |
e275a2a0 | 1750 | |
15898bbc JR |
1751 | /* |
1752 | * Find out the protection domain structure for a given PCI device. This | |
1753 | * will give us the pointer to the page table root for example. | |
1754 | */ | |
1755 | static struct protection_domain *domain_for_device(struct device *dev) | |
1756 | { | |
1757 | struct protection_domain *dom; | |
657cbb6b | 1758 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc | 1759 | unsigned long flags; |
15898bbc | 1760 | |
657cbb6b JR |
1761 | dev_data = get_dev_data(dev); |
1762 | alias_data = get_dev_data(dev_data->alias); | |
1763 | if (!alias_data) | |
1764 | return NULL; | |
15898bbc JR |
1765 | |
1766 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1767 | dom = dev_data->domain; |
15898bbc | 1768 | if (dom == NULL && |
657cbb6b JR |
1769 | alias_data->domain != NULL) { |
1770 | __attach_device(dev, alias_data->domain); | |
1771 | dom = alias_data->domain; | |
15898bbc JR |
1772 | } |
1773 | ||
1774 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1775 | ||
1776 | return dom; | |
1777 | } | |
1778 | ||
e275a2a0 JR |
1779 | static int device_change_notifier(struct notifier_block *nb, |
1780 | unsigned long action, void *data) | |
1781 | { | |
1782 | struct device *dev = data; | |
98fc5a69 | 1783 | u16 devid; |
e275a2a0 JR |
1784 | struct protection_domain *domain; |
1785 | struct dma_ops_domain *dma_domain; | |
1786 | struct amd_iommu *iommu; | |
1ac4cbbc | 1787 | unsigned long flags; |
e275a2a0 | 1788 | |
98fc5a69 JR |
1789 | if (!check_device(dev)) |
1790 | return 0; | |
e275a2a0 | 1791 | |
98fc5a69 JR |
1792 | devid = get_device_id(dev); |
1793 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1794 | |
1795 | switch (action) { | |
c1eee67b | 1796 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1797 | |
1798 | domain = domain_for_device(dev); | |
1799 | ||
e275a2a0 JR |
1800 | if (!domain) |
1801 | goto out; | |
a1ca331c JR |
1802 | if (iommu_pass_through) |
1803 | break; | |
15898bbc | 1804 | detach_device(dev); |
1ac4cbbc JR |
1805 | break; |
1806 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1807 | |
1808 | iommu_init_device(dev); | |
1809 | ||
1810 | domain = domain_for_device(dev); | |
1811 | ||
1ac4cbbc JR |
1812 | /* allocate a protection domain if a device is added */ |
1813 | dma_domain = find_protection_domain(devid); | |
1814 | if (dma_domain) | |
1815 | goto out; | |
87a64d52 | 1816 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1817 | if (!dma_domain) |
1818 | goto out; | |
1819 | dma_domain->target_dev = devid; | |
1820 | ||
1821 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1822 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1823 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1824 | ||
e275a2a0 | 1825 | break; |
657cbb6b JR |
1826 | case BUS_NOTIFY_DEL_DEVICE: |
1827 | ||
1828 | iommu_uninit_device(dev); | |
1829 | ||
e275a2a0 JR |
1830 | default: |
1831 | goto out; | |
1832 | } | |
1833 | ||
e275a2a0 JR |
1834 | iommu_completion_wait(iommu); |
1835 | ||
1836 | out: | |
1837 | return 0; | |
1838 | } | |
1839 | ||
b25ae679 | 1840 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1841 | .notifier_call = device_change_notifier, |
1842 | }; | |
355bf553 | 1843 | |
8638c491 JR |
1844 | void amd_iommu_init_notifier(void) |
1845 | { | |
1846 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1847 | } | |
1848 | ||
431b2a20 JR |
1849 | /***************************************************************************** |
1850 | * | |
1851 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1852 | * | |
1853 | *****************************************************************************/ | |
1854 | ||
1855 | /* | |
1856 | * In the dma_ops path we only have the struct device. This function | |
1857 | * finds the corresponding IOMMU, the protection domain and the | |
1858 | * requestor id for a given device. | |
1859 | * If the device is not yet associated with a domain this is also done | |
1860 | * in this function. | |
1861 | */ | |
94f6d190 | 1862 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1863 | { |
94f6d190 | 1864 | struct protection_domain *domain; |
b20ac0d4 | 1865 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1866 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1867 | |
f99c0f1c | 1868 | if (!check_device(dev)) |
94f6d190 | 1869 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1870 | |
94f6d190 JR |
1871 | domain = domain_for_device(dev); |
1872 | if (domain != NULL && !dma_ops_domain(domain)) | |
1873 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1874 | |
94f6d190 JR |
1875 | if (domain != NULL) |
1876 | return domain; | |
b20ac0d4 | 1877 | |
15898bbc | 1878 | /* Device not bount yet - bind it */ |
94f6d190 | 1879 | dma_dom = find_protection_domain(devid); |
15898bbc | 1880 | if (!dma_dom) |
94f6d190 JR |
1881 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1882 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1883 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1884 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1885 | |
94f6d190 | 1886 | return &dma_dom->domain; |
b20ac0d4 JR |
1887 | } |
1888 | ||
04bfdd84 JR |
1889 | static void update_device_table(struct protection_domain *domain) |
1890 | { | |
492667da | 1891 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1892 | |
492667da | 1893 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
fd7b5535 | 1894 | struct pci_dev *pdev = to_pci_dev(dev_data->dev); |
f62dda66 | 1895 | set_dte_entry(dev_data->devid, domain, pci_ats_enabled(pdev)); |
04bfdd84 JR |
1896 | } |
1897 | } | |
1898 | ||
1899 | static void update_domain(struct protection_domain *domain) | |
1900 | { | |
1901 | if (!domain->updated) | |
1902 | return; | |
1903 | ||
1904 | update_device_table(domain); | |
17b124bf JR |
1905 | |
1906 | domain_flush_devices(domain); | |
1907 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1908 | |
1909 | domain->updated = false; | |
1910 | } | |
1911 | ||
8bda3092 JR |
1912 | /* |
1913 | * This function fetches the PTE for a given address in the aperture | |
1914 | */ | |
1915 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1916 | unsigned long address) | |
1917 | { | |
384de729 | 1918 | struct aperture_range *aperture; |
8bda3092 JR |
1919 | u64 *pte, *pte_page; |
1920 | ||
384de729 JR |
1921 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1922 | if (!aperture) | |
1923 | return NULL; | |
1924 | ||
1925 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1926 | if (!pte) { |
cbb9d729 | 1927 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1928 | GFP_ATOMIC); |
384de729 JR |
1929 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1930 | } else | |
8c8c143c | 1931 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1932 | |
04bfdd84 | 1933 | update_domain(&dom->domain); |
8bda3092 JR |
1934 | |
1935 | return pte; | |
1936 | } | |
1937 | ||
431b2a20 JR |
1938 | /* |
1939 | * This is the generic map function. It maps one 4kb page at paddr to | |
1940 | * the given address in the DMA address space for the domain. | |
1941 | */ | |
680525e0 | 1942 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1943 | unsigned long address, |
1944 | phys_addr_t paddr, | |
1945 | int direction) | |
1946 | { | |
1947 | u64 *pte, __pte; | |
1948 | ||
1949 | WARN_ON(address > dom->aperture_size); | |
1950 | ||
1951 | paddr &= PAGE_MASK; | |
1952 | ||
8bda3092 | 1953 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1954 | if (!pte) |
8fd524b3 | 1955 | return DMA_ERROR_CODE; |
cb76c322 JR |
1956 | |
1957 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1958 | ||
1959 | if (direction == DMA_TO_DEVICE) | |
1960 | __pte |= IOMMU_PTE_IR; | |
1961 | else if (direction == DMA_FROM_DEVICE) | |
1962 | __pte |= IOMMU_PTE_IW; | |
1963 | else if (direction == DMA_BIDIRECTIONAL) | |
1964 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1965 | ||
1966 | WARN_ON(*pte); | |
1967 | ||
1968 | *pte = __pte; | |
1969 | ||
1970 | return (dma_addr_t)address; | |
1971 | } | |
1972 | ||
431b2a20 JR |
1973 | /* |
1974 | * The generic unmapping function for on page in the DMA address space. | |
1975 | */ | |
680525e0 | 1976 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1977 | unsigned long address) |
1978 | { | |
384de729 | 1979 | struct aperture_range *aperture; |
cb76c322 JR |
1980 | u64 *pte; |
1981 | ||
1982 | if (address >= dom->aperture_size) | |
1983 | return; | |
1984 | ||
384de729 JR |
1985 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1986 | if (!aperture) | |
1987 | return; | |
1988 | ||
1989 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1990 | if (!pte) | |
1991 | return; | |
cb76c322 | 1992 | |
8c8c143c | 1993 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1994 | |
1995 | WARN_ON(!*pte); | |
1996 | ||
1997 | *pte = 0ULL; | |
1998 | } | |
1999 | ||
431b2a20 JR |
2000 | /* |
2001 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2002 | * contiguous memory region into DMA address space. It is used by all |
2003 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2004 | * Must be called with the domain lock held. |
2005 | */ | |
cb76c322 | 2006 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2007 | struct dma_ops_domain *dma_dom, |
2008 | phys_addr_t paddr, | |
2009 | size_t size, | |
6d4f343f | 2010 | int dir, |
832a90c3 JR |
2011 | bool align, |
2012 | u64 dma_mask) | |
cb76c322 JR |
2013 | { |
2014 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2015 | dma_addr_t address, start, ret; |
cb76c322 | 2016 | unsigned int pages; |
6d4f343f | 2017 | unsigned long align_mask = 0; |
cb76c322 JR |
2018 | int i; |
2019 | ||
e3c449f5 | 2020 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2021 | paddr &= PAGE_MASK; |
2022 | ||
8ecaf8f1 JR |
2023 | INC_STATS_COUNTER(total_map_requests); |
2024 | ||
c1858976 JR |
2025 | if (pages > 1) |
2026 | INC_STATS_COUNTER(cross_page); | |
2027 | ||
6d4f343f JR |
2028 | if (align) |
2029 | align_mask = (1UL << get_order(size)) - 1; | |
2030 | ||
11b83888 | 2031 | retry: |
832a90c3 JR |
2032 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2033 | dma_mask); | |
8fd524b3 | 2034 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2035 | /* |
2036 | * setting next_address here will let the address | |
2037 | * allocator only scan the new allocated range in the | |
2038 | * first run. This is a small optimization. | |
2039 | */ | |
2040 | dma_dom->next_address = dma_dom->aperture_size; | |
2041 | ||
576175c2 | 2042 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2043 | goto out; |
2044 | ||
2045 | /* | |
af901ca1 | 2046 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2047 | * allocation again |
2048 | */ | |
2049 | goto retry; | |
2050 | } | |
cb76c322 JR |
2051 | |
2052 | start = address; | |
2053 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2054 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2055 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2056 | goto out_unmap; |
2057 | ||
cb76c322 JR |
2058 | paddr += PAGE_SIZE; |
2059 | start += PAGE_SIZE; | |
2060 | } | |
2061 | address += offset; | |
2062 | ||
5774f7c5 JR |
2063 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2064 | ||
afa9fdc2 | 2065 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2066 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2067 | dma_dom->need_flush = false; |
318afd41 | 2068 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2069 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2070 | |
cb76c322 JR |
2071 | out: |
2072 | return address; | |
53812c11 JR |
2073 | |
2074 | out_unmap: | |
2075 | ||
2076 | for (--i; i >= 0; --i) { | |
2077 | start -= PAGE_SIZE; | |
680525e0 | 2078 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2079 | } |
2080 | ||
2081 | dma_ops_free_addresses(dma_dom, address, pages); | |
2082 | ||
8fd524b3 | 2083 | return DMA_ERROR_CODE; |
cb76c322 JR |
2084 | } |
2085 | ||
431b2a20 JR |
2086 | /* |
2087 | * Does the reverse of the __map_single function. Must be called with | |
2088 | * the domain lock held too | |
2089 | */ | |
cd8c82e8 | 2090 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2091 | dma_addr_t dma_addr, |
2092 | size_t size, | |
2093 | int dir) | |
2094 | { | |
04e0463e | 2095 | dma_addr_t flush_addr; |
cb76c322 JR |
2096 | dma_addr_t i, start; |
2097 | unsigned int pages; | |
2098 | ||
8fd524b3 | 2099 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2100 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2101 | return; |
2102 | ||
04e0463e | 2103 | flush_addr = dma_addr; |
e3c449f5 | 2104 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2105 | dma_addr &= PAGE_MASK; |
2106 | start = dma_addr; | |
2107 | ||
2108 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2109 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2110 | start += PAGE_SIZE; |
2111 | } | |
2112 | ||
5774f7c5 JR |
2113 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2114 | ||
cb76c322 | 2115 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2116 | |
80be308d | 2117 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2118 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2119 | dma_dom->need_flush = false; |
2120 | } | |
cb76c322 JR |
2121 | } |
2122 | ||
431b2a20 JR |
2123 | /* |
2124 | * The exported map_single function for dma_ops. | |
2125 | */ | |
51491367 FT |
2126 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2127 | unsigned long offset, size_t size, | |
2128 | enum dma_data_direction dir, | |
2129 | struct dma_attrs *attrs) | |
4da70b9e JR |
2130 | { |
2131 | unsigned long flags; | |
4da70b9e | 2132 | struct protection_domain *domain; |
4da70b9e | 2133 | dma_addr_t addr; |
832a90c3 | 2134 | u64 dma_mask; |
51491367 | 2135 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2136 | |
0f2a86f2 JR |
2137 | INC_STATS_COUNTER(cnt_map_single); |
2138 | ||
94f6d190 JR |
2139 | domain = get_domain(dev); |
2140 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2141 | return (dma_addr_t)paddr; |
94f6d190 JR |
2142 | else if (IS_ERR(domain)) |
2143 | return DMA_ERROR_CODE; | |
4da70b9e | 2144 | |
f99c0f1c JR |
2145 | dma_mask = *dev->dma_mask; |
2146 | ||
4da70b9e | 2147 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2148 | |
cd8c82e8 | 2149 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2150 | dma_mask); |
8fd524b3 | 2151 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2152 | goto out; |
2153 | ||
17b124bf | 2154 | domain_flush_complete(domain); |
4da70b9e JR |
2155 | |
2156 | out: | |
2157 | spin_unlock_irqrestore(&domain->lock, flags); | |
2158 | ||
2159 | return addr; | |
2160 | } | |
2161 | ||
431b2a20 JR |
2162 | /* |
2163 | * The exported unmap_single function for dma_ops. | |
2164 | */ | |
51491367 FT |
2165 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2166 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2167 | { |
2168 | unsigned long flags; | |
4da70b9e | 2169 | struct protection_domain *domain; |
4da70b9e | 2170 | |
146a6917 JR |
2171 | INC_STATS_COUNTER(cnt_unmap_single); |
2172 | ||
94f6d190 JR |
2173 | domain = get_domain(dev); |
2174 | if (IS_ERR(domain)) | |
5b28df6f JR |
2175 | return; |
2176 | ||
4da70b9e JR |
2177 | spin_lock_irqsave(&domain->lock, flags); |
2178 | ||
cd8c82e8 | 2179 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2180 | |
17b124bf | 2181 | domain_flush_complete(domain); |
4da70b9e JR |
2182 | |
2183 | spin_unlock_irqrestore(&domain->lock, flags); | |
2184 | } | |
2185 | ||
431b2a20 JR |
2186 | /* |
2187 | * This is a special map_sg function which is used if we should map a | |
2188 | * device which is not handled by an AMD IOMMU in the system. | |
2189 | */ | |
65b050ad JR |
2190 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2191 | int nelems, int dir) | |
2192 | { | |
2193 | struct scatterlist *s; | |
2194 | int i; | |
2195 | ||
2196 | for_each_sg(sglist, s, nelems, i) { | |
2197 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2198 | s->dma_length = s->length; | |
2199 | } | |
2200 | ||
2201 | return nelems; | |
2202 | } | |
2203 | ||
431b2a20 JR |
2204 | /* |
2205 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2206 | * lists). | |
2207 | */ | |
65b050ad | 2208 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2209 | int nelems, enum dma_data_direction dir, |
2210 | struct dma_attrs *attrs) | |
65b050ad JR |
2211 | { |
2212 | unsigned long flags; | |
65b050ad | 2213 | struct protection_domain *domain; |
65b050ad JR |
2214 | int i; |
2215 | struct scatterlist *s; | |
2216 | phys_addr_t paddr; | |
2217 | int mapped_elems = 0; | |
832a90c3 | 2218 | u64 dma_mask; |
65b050ad | 2219 | |
d03f067a JR |
2220 | INC_STATS_COUNTER(cnt_map_sg); |
2221 | ||
94f6d190 JR |
2222 | domain = get_domain(dev); |
2223 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2224 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2225 | else if (IS_ERR(domain)) |
2226 | return 0; | |
dbcc112e | 2227 | |
832a90c3 | 2228 | dma_mask = *dev->dma_mask; |
65b050ad | 2229 | |
65b050ad JR |
2230 | spin_lock_irqsave(&domain->lock, flags); |
2231 | ||
2232 | for_each_sg(sglist, s, nelems, i) { | |
2233 | paddr = sg_phys(s); | |
2234 | ||
cd8c82e8 | 2235 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2236 | paddr, s->length, dir, false, |
2237 | dma_mask); | |
65b050ad JR |
2238 | |
2239 | if (s->dma_address) { | |
2240 | s->dma_length = s->length; | |
2241 | mapped_elems++; | |
2242 | } else | |
2243 | goto unmap; | |
65b050ad JR |
2244 | } |
2245 | ||
17b124bf | 2246 | domain_flush_complete(domain); |
65b050ad JR |
2247 | |
2248 | out: | |
2249 | spin_unlock_irqrestore(&domain->lock, flags); | |
2250 | ||
2251 | return mapped_elems; | |
2252 | unmap: | |
2253 | for_each_sg(sglist, s, mapped_elems, i) { | |
2254 | if (s->dma_address) | |
cd8c82e8 | 2255 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2256 | s->dma_length, dir); |
2257 | s->dma_address = s->dma_length = 0; | |
2258 | } | |
2259 | ||
2260 | mapped_elems = 0; | |
2261 | ||
2262 | goto out; | |
2263 | } | |
2264 | ||
431b2a20 JR |
2265 | /* |
2266 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2267 | * lists). | |
2268 | */ | |
65b050ad | 2269 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2270 | int nelems, enum dma_data_direction dir, |
2271 | struct dma_attrs *attrs) | |
65b050ad JR |
2272 | { |
2273 | unsigned long flags; | |
65b050ad JR |
2274 | struct protection_domain *domain; |
2275 | struct scatterlist *s; | |
65b050ad JR |
2276 | int i; |
2277 | ||
55877a6b JR |
2278 | INC_STATS_COUNTER(cnt_unmap_sg); |
2279 | ||
94f6d190 JR |
2280 | domain = get_domain(dev); |
2281 | if (IS_ERR(domain)) | |
5b28df6f JR |
2282 | return; |
2283 | ||
65b050ad JR |
2284 | spin_lock_irqsave(&domain->lock, flags); |
2285 | ||
2286 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2287 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2288 | s->dma_length, dir); |
65b050ad JR |
2289 | s->dma_address = s->dma_length = 0; |
2290 | } | |
2291 | ||
17b124bf | 2292 | domain_flush_complete(domain); |
65b050ad JR |
2293 | |
2294 | spin_unlock_irqrestore(&domain->lock, flags); | |
2295 | } | |
2296 | ||
431b2a20 JR |
2297 | /* |
2298 | * The exported alloc_coherent function for dma_ops. | |
2299 | */ | |
5d8b53cf JR |
2300 | static void *alloc_coherent(struct device *dev, size_t size, |
2301 | dma_addr_t *dma_addr, gfp_t flag) | |
2302 | { | |
2303 | unsigned long flags; | |
2304 | void *virt_addr; | |
5d8b53cf | 2305 | struct protection_domain *domain; |
5d8b53cf | 2306 | phys_addr_t paddr; |
832a90c3 | 2307 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2308 | |
c8f0fb36 JR |
2309 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2310 | ||
94f6d190 JR |
2311 | domain = get_domain(dev); |
2312 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2313 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2314 | *dma_addr = __pa(virt_addr); | |
2315 | return virt_addr; | |
94f6d190 JR |
2316 | } else if (IS_ERR(domain)) |
2317 | return NULL; | |
5d8b53cf | 2318 | |
f99c0f1c JR |
2319 | dma_mask = dev->coherent_dma_mask; |
2320 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2321 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2322 | |
2323 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2324 | if (!virt_addr) | |
b25ae679 | 2325 | return NULL; |
5d8b53cf | 2326 | |
5d8b53cf JR |
2327 | paddr = virt_to_phys(virt_addr); |
2328 | ||
832a90c3 JR |
2329 | if (!dma_mask) |
2330 | dma_mask = *dev->dma_mask; | |
2331 | ||
5d8b53cf JR |
2332 | spin_lock_irqsave(&domain->lock, flags); |
2333 | ||
cd8c82e8 | 2334 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2335 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2336 | |
8fd524b3 | 2337 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2338 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2339 | goto out_free; |
367d04c4 | 2340 | } |
5d8b53cf | 2341 | |
17b124bf | 2342 | domain_flush_complete(domain); |
5d8b53cf | 2343 | |
5d8b53cf JR |
2344 | spin_unlock_irqrestore(&domain->lock, flags); |
2345 | ||
2346 | return virt_addr; | |
5b28df6f JR |
2347 | |
2348 | out_free: | |
2349 | ||
2350 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2351 | ||
2352 | return NULL; | |
5d8b53cf JR |
2353 | } |
2354 | ||
431b2a20 JR |
2355 | /* |
2356 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2357 | */ |
5d8b53cf JR |
2358 | static void free_coherent(struct device *dev, size_t size, |
2359 | void *virt_addr, dma_addr_t dma_addr) | |
2360 | { | |
2361 | unsigned long flags; | |
5d8b53cf | 2362 | struct protection_domain *domain; |
5d8b53cf | 2363 | |
5d31ee7e JR |
2364 | INC_STATS_COUNTER(cnt_free_coherent); |
2365 | ||
94f6d190 JR |
2366 | domain = get_domain(dev); |
2367 | if (IS_ERR(domain)) | |
5b28df6f JR |
2368 | goto free_mem; |
2369 | ||
5d8b53cf JR |
2370 | spin_lock_irqsave(&domain->lock, flags); |
2371 | ||
cd8c82e8 | 2372 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2373 | |
17b124bf | 2374 | domain_flush_complete(domain); |
5d8b53cf JR |
2375 | |
2376 | spin_unlock_irqrestore(&domain->lock, flags); | |
2377 | ||
2378 | free_mem: | |
2379 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2380 | } | |
2381 | ||
b39ba6ad JR |
2382 | /* |
2383 | * This function is called by the DMA layer to find out if we can handle a | |
2384 | * particular device. It is part of the dma_ops. | |
2385 | */ | |
2386 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2387 | { | |
420aef8a | 2388 | return check_device(dev); |
b39ba6ad JR |
2389 | } |
2390 | ||
c432f3df | 2391 | /* |
431b2a20 JR |
2392 | * The function for pre-allocating protection domains. |
2393 | * | |
c432f3df JR |
2394 | * If the driver core informs the DMA layer if a driver grabs a device |
2395 | * we don't need to preallocate the protection domains anymore. | |
2396 | * For now we have to. | |
2397 | */ | |
0e93dd88 | 2398 | static void prealloc_protection_domains(void) |
c432f3df JR |
2399 | { |
2400 | struct pci_dev *dev = NULL; | |
2401 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2402 | u16 devid; |
c432f3df | 2403 | |
d18c69d3 | 2404 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2405 | |
2406 | /* Do we handle this device? */ | |
2407 | if (!check_device(&dev->dev)) | |
c432f3df | 2408 | continue; |
98fc5a69 JR |
2409 | |
2410 | /* Is there already any domain for it? */ | |
15898bbc | 2411 | if (domain_for_device(&dev->dev)) |
c432f3df | 2412 | continue; |
98fc5a69 JR |
2413 | |
2414 | devid = get_device_id(&dev->dev); | |
2415 | ||
87a64d52 | 2416 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2417 | if (!dma_dom) |
2418 | continue; | |
2419 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2420 | dma_dom->target_dev = devid; |
2421 | ||
15898bbc | 2422 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2423 | |
bd60b735 | 2424 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2425 | } |
2426 | } | |
2427 | ||
160c1d8e | 2428 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2429 | .alloc_coherent = alloc_coherent, |
2430 | .free_coherent = free_coherent, | |
51491367 FT |
2431 | .map_page = map_page, |
2432 | .unmap_page = unmap_page, | |
6631ee9d JR |
2433 | .map_sg = map_sg, |
2434 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2435 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2436 | }; |
2437 | ||
27c2127a JR |
2438 | static unsigned device_dma_ops_init(void) |
2439 | { | |
2440 | struct pci_dev *pdev = NULL; | |
2441 | unsigned unhandled = 0; | |
2442 | ||
2443 | for_each_pci_dev(pdev) { | |
2444 | if (!check_device(&pdev->dev)) { | |
2445 | unhandled += 1; | |
2446 | continue; | |
2447 | } | |
2448 | ||
2449 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2450 | } | |
2451 | ||
2452 | return unhandled; | |
2453 | } | |
2454 | ||
431b2a20 JR |
2455 | /* |
2456 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2457 | */ | |
f5325094 JR |
2458 | |
2459 | void __init amd_iommu_init_api(void) | |
2460 | { | |
2461 | register_iommu(&amd_iommu_ops); | |
2462 | } | |
2463 | ||
6631ee9d JR |
2464 | int __init amd_iommu_init_dma_ops(void) |
2465 | { | |
2466 | struct amd_iommu *iommu; | |
27c2127a | 2467 | int ret, unhandled; |
6631ee9d | 2468 | |
431b2a20 JR |
2469 | /* |
2470 | * first allocate a default protection domain for every IOMMU we | |
2471 | * found in the system. Devices not assigned to any other | |
2472 | * protection domain will be assigned to the default one. | |
2473 | */ | |
3bd22172 | 2474 | for_each_iommu(iommu) { |
87a64d52 | 2475 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2476 | if (iommu->default_dom == NULL) |
2477 | return -ENOMEM; | |
e2dc14a2 | 2478 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2479 | ret = iommu_init_unity_mappings(iommu); |
2480 | if (ret) | |
2481 | goto free_domains; | |
2482 | } | |
2483 | ||
431b2a20 | 2484 | /* |
8793abeb | 2485 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2486 | */ |
8793abeb | 2487 | prealloc_protection_domains(); |
6631ee9d JR |
2488 | |
2489 | iommu_detected = 1; | |
75f1cdf1 | 2490 | swiotlb = 0; |
6631ee9d | 2491 | |
431b2a20 | 2492 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2493 | unhandled = device_dma_ops_init(); |
2494 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2495 | /* There are unhandled devices - initialize swiotlb for them */ | |
2496 | swiotlb = 1; | |
2497 | } | |
6631ee9d | 2498 | |
7f26508b JR |
2499 | amd_iommu_stats_init(); |
2500 | ||
6631ee9d JR |
2501 | return 0; |
2502 | ||
2503 | free_domains: | |
2504 | ||
3bd22172 | 2505 | for_each_iommu(iommu) { |
6631ee9d JR |
2506 | if (iommu->default_dom) |
2507 | dma_ops_domain_free(iommu->default_dom); | |
2508 | } | |
2509 | ||
2510 | return ret; | |
2511 | } | |
6d98cd80 JR |
2512 | |
2513 | /***************************************************************************** | |
2514 | * | |
2515 | * The following functions belong to the exported interface of AMD IOMMU | |
2516 | * | |
2517 | * This interface allows access to lower level functions of the IOMMU | |
2518 | * like protection domain handling and assignement of devices to domains | |
2519 | * which is not possible with the dma_ops interface. | |
2520 | * | |
2521 | *****************************************************************************/ | |
2522 | ||
6d98cd80 JR |
2523 | static void cleanup_domain(struct protection_domain *domain) |
2524 | { | |
492667da | 2525 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2526 | unsigned long flags; |
6d98cd80 JR |
2527 | |
2528 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2529 | ||
492667da JR |
2530 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2531 | struct device *dev = dev_data->dev; | |
2532 | ||
04e856c0 | 2533 | __detach_device(dev); |
492667da JR |
2534 | atomic_set(&dev_data->bind, 0); |
2535 | } | |
6d98cd80 JR |
2536 | |
2537 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2538 | } | |
2539 | ||
2650815f JR |
2540 | static void protection_domain_free(struct protection_domain *domain) |
2541 | { | |
2542 | if (!domain) | |
2543 | return; | |
2544 | ||
aeb26f55 JR |
2545 | del_domain_from_list(domain); |
2546 | ||
2650815f JR |
2547 | if (domain->id) |
2548 | domain_id_free(domain->id); | |
2549 | ||
2550 | kfree(domain); | |
2551 | } | |
2552 | ||
2553 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2554 | { |
2555 | struct protection_domain *domain; | |
2556 | ||
2557 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2558 | if (!domain) | |
2650815f | 2559 | return NULL; |
c156e347 JR |
2560 | |
2561 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2562 | mutex_init(&domain->api_lock); |
c156e347 JR |
2563 | domain->id = domain_id_alloc(); |
2564 | if (!domain->id) | |
2650815f | 2565 | goto out_err; |
7c392cbe | 2566 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2567 | |
aeb26f55 JR |
2568 | add_domain_to_list(domain); |
2569 | ||
2650815f JR |
2570 | return domain; |
2571 | ||
2572 | out_err: | |
2573 | kfree(domain); | |
2574 | ||
2575 | return NULL; | |
2576 | } | |
2577 | ||
2578 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2579 | { | |
2580 | struct protection_domain *domain; | |
2581 | ||
2582 | domain = protection_domain_alloc(); | |
2583 | if (!domain) | |
c156e347 | 2584 | goto out_free; |
2650815f JR |
2585 | |
2586 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2587 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2588 | if (!domain->pt_root) | |
2589 | goto out_free; | |
2590 | ||
2591 | dom->priv = domain; | |
2592 | ||
2593 | return 0; | |
2594 | ||
2595 | out_free: | |
2650815f | 2596 | protection_domain_free(domain); |
c156e347 JR |
2597 | |
2598 | return -ENOMEM; | |
2599 | } | |
2600 | ||
98383fc3 JR |
2601 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2602 | { | |
2603 | struct protection_domain *domain = dom->priv; | |
2604 | ||
2605 | if (!domain) | |
2606 | return; | |
2607 | ||
2608 | if (domain->dev_cnt > 0) | |
2609 | cleanup_domain(domain); | |
2610 | ||
2611 | BUG_ON(domain->dev_cnt != 0); | |
2612 | ||
2613 | free_pagetable(domain); | |
2614 | ||
8b408fe4 | 2615 | protection_domain_free(domain); |
98383fc3 JR |
2616 | |
2617 | dom->priv = NULL; | |
2618 | } | |
2619 | ||
684f2888 JR |
2620 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2621 | struct device *dev) | |
2622 | { | |
657cbb6b | 2623 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2624 | struct amd_iommu *iommu; |
684f2888 JR |
2625 | u16 devid; |
2626 | ||
98fc5a69 | 2627 | if (!check_device(dev)) |
684f2888 JR |
2628 | return; |
2629 | ||
98fc5a69 | 2630 | devid = get_device_id(dev); |
684f2888 | 2631 | |
657cbb6b | 2632 | if (dev_data->domain != NULL) |
15898bbc | 2633 | detach_device(dev); |
684f2888 JR |
2634 | |
2635 | iommu = amd_iommu_rlookup_table[devid]; | |
2636 | if (!iommu) | |
2637 | return; | |
2638 | ||
684f2888 JR |
2639 | iommu_completion_wait(iommu); |
2640 | } | |
2641 | ||
01106066 JR |
2642 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2643 | struct device *dev) | |
2644 | { | |
2645 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2646 | struct iommu_dev_data *dev_data; |
01106066 | 2647 | struct amd_iommu *iommu; |
15898bbc | 2648 | int ret; |
01106066 | 2649 | |
98fc5a69 | 2650 | if (!check_device(dev)) |
01106066 JR |
2651 | return -EINVAL; |
2652 | ||
657cbb6b JR |
2653 | dev_data = dev->archdata.iommu; |
2654 | ||
f62dda66 | 2655 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2656 | if (!iommu) |
2657 | return -EINVAL; | |
2658 | ||
657cbb6b | 2659 | if (dev_data->domain) |
15898bbc | 2660 | detach_device(dev); |
01106066 | 2661 | |
15898bbc | 2662 | ret = attach_device(dev, domain); |
01106066 JR |
2663 | |
2664 | iommu_completion_wait(iommu); | |
2665 | ||
15898bbc | 2666 | return ret; |
01106066 JR |
2667 | } |
2668 | ||
468e2366 JR |
2669 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2670 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2671 | { |
468e2366 | 2672 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2673 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2674 | int prot = 0; |
2675 | int ret; | |
2676 | ||
2677 | if (iommu_prot & IOMMU_READ) | |
2678 | prot |= IOMMU_PROT_IR; | |
2679 | if (iommu_prot & IOMMU_WRITE) | |
2680 | prot |= IOMMU_PROT_IW; | |
2681 | ||
5d214fe6 | 2682 | mutex_lock(&domain->api_lock); |
795e74f7 | 2683 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2684 | mutex_unlock(&domain->api_lock); |
2685 | ||
795e74f7 | 2686 | return ret; |
c6229ca6 JR |
2687 | } |
2688 | ||
468e2366 JR |
2689 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2690 | int gfp_order) | |
eb74ff6c | 2691 | { |
eb74ff6c | 2692 | struct protection_domain *domain = dom->priv; |
468e2366 | 2693 | unsigned long page_size, unmap_size; |
eb74ff6c | 2694 | |
468e2366 | 2695 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2696 | |
5d214fe6 | 2697 | mutex_lock(&domain->api_lock); |
468e2366 | 2698 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2699 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2700 | |
17b124bf | 2701 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2702 | |
468e2366 | 2703 | return get_order(unmap_size); |
eb74ff6c JR |
2704 | } |
2705 | ||
645c4c8d JR |
2706 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2707 | unsigned long iova) | |
2708 | { | |
2709 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2710 | unsigned long offset_mask; |
645c4c8d | 2711 | phys_addr_t paddr; |
f03152bb | 2712 | u64 *pte, __pte; |
645c4c8d | 2713 | |
24cd7723 | 2714 | pte = fetch_pte(domain, iova); |
645c4c8d | 2715 | |
a6d41a40 | 2716 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2717 | return 0; |
2718 | ||
f03152bb JR |
2719 | if (PM_PTE_LEVEL(*pte) == 0) |
2720 | offset_mask = PAGE_SIZE - 1; | |
2721 | else | |
2722 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2723 | ||
2724 | __pte = *pte & PM_ADDR_MASK; | |
2725 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2726 | |
2727 | return paddr; | |
2728 | } | |
2729 | ||
dbb9fd86 SY |
2730 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2731 | unsigned long cap) | |
2732 | { | |
80a506b8 JR |
2733 | switch (cap) { |
2734 | case IOMMU_CAP_CACHE_COHERENCY: | |
2735 | return 1; | |
2736 | } | |
2737 | ||
dbb9fd86 SY |
2738 | return 0; |
2739 | } | |
2740 | ||
26961efe JR |
2741 | static struct iommu_ops amd_iommu_ops = { |
2742 | .domain_init = amd_iommu_domain_init, | |
2743 | .domain_destroy = amd_iommu_domain_destroy, | |
2744 | .attach_dev = amd_iommu_attach_device, | |
2745 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2746 | .map = amd_iommu_map, |
2747 | .unmap = amd_iommu_unmap, | |
26961efe | 2748 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2749 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2750 | }; |
2751 | ||
0feae533 JR |
2752 | /***************************************************************************** |
2753 | * | |
2754 | * The next functions do a basic initialization of IOMMU for pass through | |
2755 | * mode | |
2756 | * | |
2757 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2758 | * DMA-API translation. | |
2759 | * | |
2760 | *****************************************************************************/ | |
2761 | ||
2762 | int __init amd_iommu_init_passthrough(void) | |
2763 | { | |
15898bbc | 2764 | struct amd_iommu *iommu; |
0feae533 | 2765 | struct pci_dev *dev = NULL; |
15898bbc | 2766 | u16 devid; |
0feae533 | 2767 | |
af901ca1 | 2768 | /* allocate passthrough domain */ |
0feae533 JR |
2769 | pt_domain = protection_domain_alloc(); |
2770 | if (!pt_domain) | |
2771 | return -ENOMEM; | |
2772 | ||
2773 | pt_domain->mode |= PAGE_MODE_NONE; | |
2774 | ||
6c54aabd | 2775 | for_each_pci_dev(dev) { |
98fc5a69 | 2776 | if (!check_device(&dev->dev)) |
0feae533 JR |
2777 | continue; |
2778 | ||
98fc5a69 JR |
2779 | devid = get_device_id(&dev->dev); |
2780 | ||
15898bbc | 2781 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2782 | if (!iommu) |
2783 | continue; | |
2784 | ||
15898bbc | 2785 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2786 | } |
2787 | ||
2788 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2789 | ||
2790 | return 0; | |
2791 | } |