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f6e2e6b6 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 | 27 | #include <asm/pci-direct.h> |
6a9401a7 | 28 | #include <asm/amd_iommu_proto.h> |
f6e2e6b6 | 29 | #include <asm/amd_iommu_types.h> |
c6da992e | 30 | #include <asm/amd_iommu.h> |
46a7fa27 | 31 | #include <asm/iommu.h> |
1d9b16d1 | 32 | #include <asm/gart.h> |
ea1b0d39 | 33 | #include <asm/x86_init.h> |
f6e2e6b6 JR |
34 | |
35 | /* | |
36 | * definitions for the ACPI scanning code | |
37 | */ | |
f6e2e6b6 | 38 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
39 | |
40 | #define ACPI_IVHD_TYPE 0x10 | |
41 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
42 | #define ACPI_IVMD_TYPE 0x21 | |
43 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
44 | ||
45 | #define IVHD_DEV_ALL 0x01 | |
46 | #define IVHD_DEV_SELECT 0x02 | |
47 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
48 | #define IVHD_DEV_RANGE_END 0x04 | |
49 | #define IVHD_DEV_ALIAS 0x42 | |
50 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
51 | #define IVHD_DEV_EXT_SELECT 0x46 | |
52 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
53 | ||
6da7342f JR |
54 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
55 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
56 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
57 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
58 | |
59 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
60 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
61 | ||
62 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
63 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
64 | #define ACPI_DEVFLAG_NMI 0x04 | |
65 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
66 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
67 | #define ACPI_DEVFLAG_LINT0 0x40 | |
68 | #define ACPI_DEVFLAG_LINT1 0x80 | |
69 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
70 | ||
b65233a9 JR |
71 | /* |
72 | * ACPI table definitions | |
73 | * | |
74 | * These data structures are laid over the table to parse the important values | |
75 | * out of it. | |
76 | */ | |
77 | ||
78 | /* | |
79 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
80 | * or more ivhd_entrys. | |
81 | */ | |
f6e2e6b6 JR |
82 | struct ivhd_header { |
83 | u8 type; | |
84 | u8 flags; | |
85 | u16 length; | |
86 | u16 devid; | |
87 | u16 cap_ptr; | |
88 | u64 mmio_phys; | |
89 | u16 pci_seg; | |
90 | u16 info; | |
91 | u32 reserved; | |
92 | } __attribute__((packed)); | |
93 | ||
b65233a9 JR |
94 | /* |
95 | * A device entry describing which devices a specific IOMMU translates and | |
96 | * which requestor ids they use. | |
97 | */ | |
f6e2e6b6 JR |
98 | struct ivhd_entry { |
99 | u8 type; | |
100 | u16 devid; | |
101 | u8 flags; | |
102 | u32 ext; | |
103 | } __attribute__((packed)); | |
104 | ||
b65233a9 JR |
105 | /* |
106 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
107 | * ranges for devices and regions that should be unity mapped. | |
108 | */ | |
f6e2e6b6 JR |
109 | struct ivmd_header { |
110 | u8 type; | |
111 | u8 flags; | |
112 | u16 length; | |
113 | u16 devid; | |
114 | u16 aux; | |
115 | u64 resv; | |
116 | u64 range_start; | |
117 | u64 range_length; | |
118 | } __attribute__((packed)); | |
119 | ||
fefda117 JR |
120 | bool amd_iommu_dump; |
121 | ||
c1cbebee | 122 | static int __initdata amd_iommu_detected; |
a5235725 | 123 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 124 | |
b65233a9 JR |
125 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
126 | to handle */ | |
2e22847f | 127 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 128 | we find in ACPI */ |
afa9fdc2 | 129 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 130 | |
2e22847f | 131 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 132 | system */ |
928abd25 | 133 | |
bb52777e JR |
134 | /* Array to assign indices to IOMMUs*/ |
135 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
136 | int amd_iommus_present; | |
137 | ||
318afd41 JR |
138 | /* IOMMUs have a non-present cache? */ |
139 | bool amd_iommu_np_cache __read_mostly; | |
140 | ||
0f764806 | 141 | /* |
3551a708 | 142 | * The ACPI table parsing functions set this variable on an error |
0f764806 | 143 | */ |
3551a708 | 144 | static int __initdata amd_iommu_init_err; |
0f764806 | 145 | |
aeb26f55 JR |
146 | /* |
147 | * List of protection domains - used during resume | |
148 | */ | |
149 | LIST_HEAD(amd_iommu_pd_list); | |
150 | spinlock_t amd_iommu_pd_lock; | |
151 | ||
b65233a9 JR |
152 | /* |
153 | * Pointer to the device table which is shared by all AMD IOMMUs | |
154 | * it is indexed by the PCI device id or the HT unit id and contains | |
155 | * information about the domain the device belongs to as well as the | |
156 | * page table root pointer. | |
157 | */ | |
928abd25 | 158 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
159 | |
160 | /* | |
161 | * The alias table is a driver specific data structure which contains the | |
162 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
163 | * More than one device can share the same requestor id. | |
164 | */ | |
928abd25 | 165 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
166 | |
167 | /* | |
168 | * The rlookup table is used to find the IOMMU which is responsible | |
169 | * for a specific device. It is also indexed by the PCI device id. | |
170 | */ | |
928abd25 | 171 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 172 | |
b65233a9 JR |
173 | /* |
174 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
175 | * to know which ones are already in use. | |
176 | */ | |
928abd25 JR |
177 | unsigned long *amd_iommu_pd_alloc_bitmap; |
178 | ||
b65233a9 JR |
179 | static u32 dev_table_size; /* size of the device table */ |
180 | static u32 alias_table_size; /* size of the alias table */ | |
181 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 182 | |
208ec8c9 JR |
183 | static inline void update_last_devid(u16 devid) |
184 | { | |
185 | if (devid > amd_iommu_last_bdf) | |
186 | amd_iommu_last_bdf = devid; | |
187 | } | |
188 | ||
c571484e JR |
189 | static inline unsigned long tbl_size(int entry_size) |
190 | { | |
191 | unsigned shift = PAGE_SHIFT + | |
421f909c | 192 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
193 | |
194 | return 1UL << shift; | |
195 | } | |
196 | ||
b65233a9 JR |
197 | /**************************************************************************** |
198 | * | |
199 | * AMD IOMMU MMIO register space handling functions | |
200 | * | |
201 | * These functions are used to program the IOMMU device registers in | |
202 | * MMIO space required for that driver. | |
203 | * | |
204 | ****************************************************************************/ | |
3e8064ba | 205 | |
b65233a9 JR |
206 | /* |
207 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
208 | * exclusion range are passed through untranslated | |
209 | */ | |
05f92db9 | 210 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
211 | { |
212 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
213 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
214 | u64 entry; | |
215 | ||
216 | if (!iommu->exclusion_start) | |
217 | return; | |
218 | ||
219 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
220 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
221 | &entry, sizeof(entry)); | |
222 | ||
223 | entry = limit; | |
224 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
225 | &entry, sizeof(entry)); | |
226 | } | |
227 | ||
b65233a9 | 228 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
229 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
230 | { | |
f609891f | 231 | u64 entry; |
b2026aa2 JR |
232 | |
233 | BUG_ON(iommu->mmio_base == NULL); | |
234 | ||
235 | entry = virt_to_phys(amd_iommu_dev_table); | |
236 | entry |= (dev_table_size >> 12) - 1; | |
237 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
238 | &entry, sizeof(entry)); | |
239 | } | |
240 | ||
b65233a9 | 241 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 242 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
243 | { |
244 | u32 ctrl; | |
245 | ||
246 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
247 | ctrl |= (1 << bit); | |
248 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
249 | } | |
250 | ||
ca020711 | 251 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
252 | { |
253 | u32 ctrl; | |
254 | ||
199d0d50 | 255 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
256 | ctrl &= ~(1 << bit); |
257 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
258 | } | |
259 | ||
b65233a9 | 260 | /* Function to enable the hardware */ |
05f92db9 | 261 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 262 | { |
4c6f40d4 | 263 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n", |
a4e267c8 | 264 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 JR |
265 | |
266 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
267 | } |
268 | ||
92ac4320 | 269 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 270 | { |
a8c485bb CW |
271 | /* Disable command buffer */ |
272 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
273 | ||
274 | /* Disable event logging and event interrupts */ | |
275 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
276 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
277 | ||
278 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 279 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
280 | } |
281 | ||
b65233a9 JR |
282 | /* |
283 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
284 | * the system has one. | |
285 | */ | |
6c56747b JR |
286 | static u8 * __init iommu_map_mmio_space(u64 address) |
287 | { | |
288 | u8 *ret; | |
289 | ||
290 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
291 | return NULL; | |
292 | ||
293 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
294 | if (ret != NULL) | |
295 | return ret; | |
296 | ||
297 | release_mem_region(address, MMIO_REGION_LENGTH); | |
298 | ||
299 | return NULL; | |
300 | } | |
301 | ||
302 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
303 | { | |
304 | if (iommu->mmio_base) | |
305 | iounmap(iommu->mmio_base); | |
306 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
307 | } | |
308 | ||
b65233a9 JR |
309 | /**************************************************************************** |
310 | * | |
311 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
312 | * parsing. In this pass we try to find out the highest device id this | |
313 | * code has to handle. Upon this information the size of the shared data | |
314 | * structures is determined later. | |
315 | * | |
316 | ****************************************************************************/ | |
317 | ||
b514e555 JR |
318 | /* |
319 | * This function calculates the length of a given IVHD entry | |
320 | */ | |
321 | static inline int ivhd_entry_length(u8 *ivhd) | |
322 | { | |
323 | return 0x04 << (*ivhd >> 6); | |
324 | } | |
325 | ||
b65233a9 JR |
326 | /* |
327 | * This function reads the last device id the IOMMU has to handle from the PCI | |
328 | * capability header for this IOMMU | |
329 | */ | |
3e8064ba JR |
330 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
331 | { | |
332 | u32 cap; | |
333 | ||
334 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 335 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
336 | |
337 | return 0; | |
338 | } | |
339 | ||
b65233a9 JR |
340 | /* |
341 | * After reading the highest device id from the IOMMU PCI capability header | |
342 | * this function looks if there is a higher device id defined in the ACPI table | |
343 | */ | |
3e8064ba JR |
344 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
345 | { | |
346 | u8 *p = (void *)h, *end = (void *)h; | |
347 | struct ivhd_entry *dev; | |
348 | ||
349 | p += sizeof(*h); | |
350 | end += h->length; | |
351 | ||
352 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
353 | PCI_SLOT(h->devid), | |
354 | PCI_FUNC(h->devid), | |
355 | h->cap_ptr); | |
356 | ||
357 | while (p < end) { | |
358 | dev = (struct ivhd_entry *)p; | |
359 | switch (dev->type) { | |
360 | case IVHD_DEV_SELECT: | |
361 | case IVHD_DEV_RANGE_END: | |
362 | case IVHD_DEV_ALIAS: | |
363 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 364 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 365 | update_last_devid(dev->devid); |
3e8064ba JR |
366 | break; |
367 | default: | |
368 | break; | |
369 | } | |
b514e555 | 370 | p += ivhd_entry_length(p); |
3e8064ba JR |
371 | } |
372 | ||
373 | WARN_ON(p != end); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
b65233a9 JR |
378 | /* |
379 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
380 | * id which we need to handle. This is the first of three functions which parse | |
381 | * the ACPI table. So we check the checksum here. | |
382 | */ | |
3e8064ba JR |
383 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
384 | { | |
385 | int i; | |
386 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
387 | struct ivhd_header *h; | |
388 | ||
389 | /* | |
390 | * Validate checksum here so we don't need to do it when | |
391 | * we actually parse the table | |
392 | */ | |
393 | for (i = 0; i < table->length; ++i) | |
394 | checksum += p[i]; | |
3551a708 | 395 | if (checksum != 0) { |
3e8064ba | 396 | /* ACPI table corrupt */ |
3551a708 JR |
397 | amd_iommu_init_err = -ENODEV; |
398 | return 0; | |
399 | } | |
3e8064ba JR |
400 | |
401 | p += IVRS_HEADER_LENGTH; | |
402 | ||
403 | end += table->length; | |
404 | while (p < end) { | |
405 | h = (struct ivhd_header *)p; | |
406 | switch (h->type) { | |
407 | case ACPI_IVHD_TYPE: | |
408 | find_last_devid_from_ivhd(h); | |
409 | break; | |
410 | default: | |
411 | break; | |
412 | } | |
413 | p += h->length; | |
414 | } | |
415 | WARN_ON(p != end); | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
b65233a9 JR |
420 | /**************************************************************************** |
421 | * | |
422 | * The following functions belong the the code path which parses the ACPI table | |
423 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
424 | * data structures, initialize the device/alias/rlookup table and also | |
425 | * basically initialize the hardware. | |
426 | * | |
427 | ****************************************************************************/ | |
428 | ||
429 | /* | |
430 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
431 | * write commands to that buffer later and the IOMMU will execute them | |
432 | * asynchronously | |
433 | */ | |
b36ca91e JR |
434 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
435 | { | |
d0312b21 | 436 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 437 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
438 | |
439 | if (cmd_buf == NULL) | |
440 | return NULL; | |
441 | ||
549c90dc | 442 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 443 | |
58492e12 JR |
444 | return cmd_buf; |
445 | } | |
446 | ||
93f1cc67 JR |
447 | /* |
448 | * This function resets the command buffer if the IOMMU stopped fetching | |
449 | * commands from it. | |
450 | */ | |
451 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
452 | { | |
453 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
454 | ||
455 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
456 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
457 | ||
458 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
459 | } | |
460 | ||
58492e12 JR |
461 | /* |
462 | * This function writes the command buffer address to the hardware and | |
463 | * enables it. | |
464 | */ | |
465 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
466 | { | |
467 | u64 entry; | |
468 | ||
469 | BUG_ON(iommu->cmd_buf == NULL); | |
470 | ||
471 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 472 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 473 | |
b36ca91e | 474 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 475 | &entry, sizeof(entry)); |
b36ca91e | 476 | |
93f1cc67 | 477 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 478 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
479 | } |
480 | ||
481 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
482 | { | |
23c1713f | 483 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 484 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
485 | } |
486 | ||
335503e5 JR |
487 | /* allocates the memory where the IOMMU will log its events to */ |
488 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
489 | { | |
335503e5 JR |
490 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
491 | get_order(EVT_BUFFER_SIZE)); | |
492 | ||
493 | if (iommu->evt_buf == NULL) | |
494 | return NULL; | |
495 | ||
1bc6f838 JR |
496 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
497 | ||
58492e12 JR |
498 | return iommu->evt_buf; |
499 | } | |
500 | ||
501 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
502 | { | |
503 | u64 entry; | |
504 | ||
505 | BUG_ON(iommu->evt_buf == NULL); | |
506 | ||
335503e5 | 507 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 508 | |
335503e5 JR |
509 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
510 | &entry, sizeof(entry)); | |
511 | ||
09067207 JR |
512 | /* set head and tail to zero manually */ |
513 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
514 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
515 | ||
58492e12 | 516 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
517 | } |
518 | ||
519 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
520 | { | |
521 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
522 | } | |
523 | ||
b65233a9 | 524 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
525 | static void set_dev_entry_bit(u16 devid, u8 bit) |
526 | { | |
527 | int i = (bit >> 5) & 0x07; | |
528 | int _bit = bit & 0x1f; | |
529 | ||
530 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
531 | } | |
532 | ||
c5cca146 JR |
533 | static int get_dev_entry_bit(u16 devid, u8 bit) |
534 | { | |
535 | int i = (bit >> 5) & 0x07; | |
536 | int _bit = bit & 0x1f; | |
537 | ||
538 | return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit; | |
539 | } | |
540 | ||
541 | ||
542 | void amd_iommu_apply_erratum_63(u16 devid) | |
543 | { | |
544 | int sysmgt; | |
545 | ||
546 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
547 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
548 | ||
549 | if (sysmgt == 0x01) | |
550 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
551 | } | |
552 | ||
5ff4789d JR |
553 | /* Writes the specific IOMMU for a device into the rlookup table */ |
554 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
555 | { | |
556 | amd_iommu_rlookup_table[devid] = iommu; | |
557 | } | |
558 | ||
b65233a9 JR |
559 | /* |
560 | * This function takes the device specific flags read from the ACPI | |
561 | * table and sets up the device table entry with that information | |
562 | */ | |
5ff4789d JR |
563 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
564 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
565 | { |
566 | if (flags & ACPI_DEVFLAG_INITPASS) | |
567 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
568 | if (flags & ACPI_DEVFLAG_EXTINT) | |
569 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
570 | if (flags & ACPI_DEVFLAG_NMI) | |
571 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
572 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
573 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
574 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
575 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
576 | if (flags & ACPI_DEVFLAG_LINT0) | |
577 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
578 | if (flags & ACPI_DEVFLAG_LINT1) | |
579 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 580 | |
c5cca146 JR |
581 | amd_iommu_apply_erratum_63(devid); |
582 | ||
5ff4789d | 583 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
584 | } |
585 | ||
b65233a9 JR |
586 | /* |
587 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
588 | * it | |
589 | */ | |
3566b778 JR |
590 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
591 | { | |
592 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
593 | ||
594 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
595 | return; | |
596 | ||
597 | if (iommu) { | |
b65233a9 JR |
598 | /* |
599 | * We only can configure exclusion ranges per IOMMU, not | |
600 | * per device. But we can enable the exclusion range per | |
601 | * device. This is done here | |
602 | */ | |
3566b778 JR |
603 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
604 | iommu->exclusion_start = m->range_start; | |
605 | iommu->exclusion_length = m->range_length; | |
606 | } | |
607 | } | |
608 | ||
b65233a9 JR |
609 | /* |
610 | * This function reads some important data from the IOMMU PCI space and | |
611 | * initializes the driver data structure with it. It reads the hardware | |
612 | * capabilities and the first/last device entries | |
613 | */ | |
5d0c8e49 JR |
614 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
615 | { | |
5d0c8e49 | 616 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 617 | u32 range, misc; |
5d0c8e49 | 618 | |
3eaf28a1 JR |
619 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
620 | &iommu->cap); | |
621 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
622 | &range); | |
a80dc3e0 JR |
623 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
624 | &misc); | |
5d0c8e49 | 625 | |
d591b0a3 JR |
626 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
627 | MMIO_GET_FD(range)); | |
628 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
629 | MMIO_GET_LD(range)); | |
a80dc3e0 | 630 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
631 | } |
632 | ||
b65233a9 JR |
633 | /* |
634 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
635 | * initializes the hardware and our data structures with it. | |
636 | */ | |
5d0c8e49 JR |
637 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
638 | struct ivhd_header *h) | |
639 | { | |
640 | u8 *p = (u8 *)h; | |
641 | u8 *end = p, flags = 0; | |
642 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
643 | u32 ext_flags = 0; | |
58a3bee5 | 644 | bool alias = false; |
5d0c8e49 JR |
645 | struct ivhd_entry *e; |
646 | ||
647 | /* | |
648 | * First set the recommended feature enable bits from ACPI | |
649 | * into the IOMMU control registers | |
650 | */ | |
6da7342f | 651 | h->flags & IVHD_FLAG_HT_TUN_EN_MASK ? |
5d0c8e49 JR |
652 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : |
653 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
654 | ||
6da7342f | 655 | h->flags & IVHD_FLAG_PASSPW_EN_MASK ? |
5d0c8e49 JR |
656 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : |
657 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
658 | ||
6da7342f | 659 | h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ? |
5d0c8e49 JR |
660 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : |
661 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
662 | ||
6da7342f | 663 | h->flags & IVHD_FLAG_ISOC_EN_MASK ? |
5d0c8e49 JR |
664 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : |
665 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
666 | ||
667 | /* | |
668 | * make IOMMU memory accesses cache coherent | |
669 | */ | |
670 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
671 | ||
672 | /* | |
673 | * Done. Now parse the device entries | |
674 | */ | |
675 | p += sizeof(struct ivhd_header); | |
676 | end += h->length; | |
677 | ||
42a698f4 | 678 | |
5d0c8e49 JR |
679 | while (p < end) { |
680 | e = (struct ivhd_entry *)p; | |
681 | switch (e->type) { | |
682 | case IVHD_DEV_ALL: | |
42a698f4 JR |
683 | |
684 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
685 | " last device %02x:%02x.%x flags: %02x\n", | |
686 | PCI_BUS(iommu->first_device), | |
687 | PCI_SLOT(iommu->first_device), | |
688 | PCI_FUNC(iommu->first_device), | |
689 | PCI_BUS(iommu->last_device), | |
690 | PCI_SLOT(iommu->last_device), | |
691 | PCI_FUNC(iommu->last_device), | |
692 | e->flags); | |
693 | ||
5d0c8e49 JR |
694 | for (dev_i = iommu->first_device; |
695 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
696 | set_dev_entry_from_acpi(iommu, dev_i, |
697 | e->flags, 0); | |
5d0c8e49 JR |
698 | break; |
699 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
700 | |
701 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
702 | "flags: %02x\n", | |
703 | PCI_BUS(e->devid), | |
704 | PCI_SLOT(e->devid), | |
705 | PCI_FUNC(e->devid), | |
706 | e->flags); | |
707 | ||
5d0c8e49 | 708 | devid = e->devid; |
5ff4789d | 709 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
710 | break; |
711 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
712 | |
713 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
714 | "devid: %02x:%02x.%x flags: %02x\n", | |
715 | PCI_BUS(e->devid), | |
716 | PCI_SLOT(e->devid), | |
717 | PCI_FUNC(e->devid), | |
718 | e->flags); | |
719 | ||
5d0c8e49 JR |
720 | devid_start = e->devid; |
721 | flags = e->flags; | |
722 | ext_flags = 0; | |
58a3bee5 | 723 | alias = false; |
5d0c8e49 JR |
724 | break; |
725 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
726 | |
727 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
728 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
729 | PCI_BUS(e->devid), | |
730 | PCI_SLOT(e->devid), | |
731 | PCI_FUNC(e->devid), | |
732 | e->flags, | |
733 | PCI_BUS(e->ext >> 8), | |
734 | PCI_SLOT(e->ext >> 8), | |
735 | PCI_FUNC(e->ext >> 8)); | |
736 | ||
5d0c8e49 JR |
737 | devid = e->devid; |
738 | devid_to = e->ext >> 8; | |
7a6a3a08 | 739 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 740 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
741 | amd_iommu_alias_table[devid] = devid_to; |
742 | break; | |
743 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
744 | |
745 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
746 | "devid: %02x:%02x.%x flags: %02x " | |
747 | "devid_to: %02x:%02x.%x\n", | |
748 | PCI_BUS(e->devid), | |
749 | PCI_SLOT(e->devid), | |
750 | PCI_FUNC(e->devid), | |
751 | e->flags, | |
752 | PCI_BUS(e->ext >> 8), | |
753 | PCI_SLOT(e->ext >> 8), | |
754 | PCI_FUNC(e->ext >> 8)); | |
755 | ||
5d0c8e49 JR |
756 | devid_start = e->devid; |
757 | flags = e->flags; | |
758 | devid_to = e->ext >> 8; | |
759 | ext_flags = 0; | |
58a3bee5 | 760 | alias = true; |
5d0c8e49 JR |
761 | break; |
762 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
763 | |
764 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
765 | "flags: %02x ext: %08x\n", | |
766 | PCI_BUS(e->devid), | |
767 | PCI_SLOT(e->devid), | |
768 | PCI_FUNC(e->devid), | |
769 | e->flags, e->ext); | |
770 | ||
5d0c8e49 | 771 | devid = e->devid; |
5ff4789d JR |
772 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
773 | e->ext); | |
5d0c8e49 JR |
774 | break; |
775 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
776 | |
777 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
778 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
779 | PCI_BUS(e->devid), | |
780 | PCI_SLOT(e->devid), | |
781 | PCI_FUNC(e->devid), | |
782 | e->flags, e->ext); | |
783 | ||
5d0c8e49 JR |
784 | devid_start = e->devid; |
785 | flags = e->flags; | |
786 | ext_flags = e->ext; | |
58a3bee5 | 787 | alias = false; |
5d0c8e49 JR |
788 | break; |
789 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
790 | |
791 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
792 | PCI_BUS(e->devid), | |
793 | PCI_SLOT(e->devid), | |
794 | PCI_FUNC(e->devid)); | |
795 | ||
5d0c8e49 JR |
796 | devid = e->devid; |
797 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 798 | if (alias) { |
5d0c8e49 | 799 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
800 | set_dev_entry_from_acpi(iommu, |
801 | devid_to, flags, ext_flags); | |
802 | } | |
803 | set_dev_entry_from_acpi(iommu, dev_i, | |
804 | flags, ext_flags); | |
5d0c8e49 JR |
805 | } |
806 | break; | |
807 | default: | |
808 | break; | |
809 | } | |
810 | ||
b514e555 | 811 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
812 | } |
813 | } | |
814 | ||
b65233a9 | 815 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
816 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
817 | { | |
818 | u16 i; | |
819 | ||
820 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
821 | set_iommu_for_device(iommu, i); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
e47d402d JR |
826 | static void __init free_iommu_one(struct amd_iommu *iommu) |
827 | { | |
828 | free_command_buffer(iommu); | |
335503e5 | 829 | free_event_buffer(iommu); |
e47d402d JR |
830 | iommu_unmap_mmio_space(iommu); |
831 | } | |
832 | ||
833 | static void __init free_iommu_all(void) | |
834 | { | |
835 | struct amd_iommu *iommu, *next; | |
836 | ||
3bd22172 | 837 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
838 | list_del(&iommu->list); |
839 | free_iommu_one(iommu); | |
840 | kfree(iommu); | |
841 | } | |
842 | } | |
843 | ||
b65233a9 JR |
844 | /* |
845 | * This function clues the initialization function for one IOMMU | |
846 | * together and also allocates the command buffer and programs the | |
847 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
848 | */ | |
e47d402d JR |
849 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
850 | { | |
851 | spin_lock_init(&iommu->lock); | |
bb52777e JR |
852 | |
853 | /* Add IOMMU to internal data structures */ | |
e47d402d | 854 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
855 | iommu->index = amd_iommus_present++; |
856 | ||
857 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
858 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
859 | return -ENOSYS; | |
860 | } | |
861 | ||
862 | /* Index is fine - add IOMMU to the array */ | |
863 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
864 | |
865 | /* | |
866 | * Copy data from ACPI table entry to the iommu struct | |
867 | */ | |
3eaf28a1 JR |
868 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
869 | if (!iommu->dev) | |
870 | return 1; | |
871 | ||
e47d402d | 872 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 873 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
874 | iommu->mmio_phys = h->mmio_phys; |
875 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
876 | if (!iommu->mmio_base) | |
877 | return -ENOMEM; | |
878 | ||
e47d402d JR |
879 | iommu->cmd_buf = alloc_command_buffer(iommu); |
880 | if (!iommu->cmd_buf) | |
881 | return -ENOMEM; | |
882 | ||
335503e5 JR |
883 | iommu->evt_buf = alloc_event_buffer(iommu); |
884 | if (!iommu->evt_buf) | |
885 | return -ENOMEM; | |
886 | ||
a80dc3e0 JR |
887 | iommu->int_enabled = false; |
888 | ||
e47d402d JR |
889 | init_iommu_from_pci(iommu); |
890 | init_iommu_from_acpi(iommu, h); | |
891 | init_iommu_devices(iommu); | |
892 | ||
318afd41 JR |
893 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) |
894 | amd_iommu_np_cache = true; | |
895 | ||
8a66712b | 896 | return pci_enable_device(iommu->dev); |
e47d402d JR |
897 | } |
898 | ||
b65233a9 JR |
899 | /* |
900 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
901 | * IOMMU structure and initializes it with init_iommu_one() | |
902 | */ | |
e47d402d JR |
903 | static int __init init_iommu_all(struct acpi_table_header *table) |
904 | { | |
905 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
906 | struct ivhd_header *h; | |
907 | struct amd_iommu *iommu; | |
908 | int ret; | |
909 | ||
e47d402d JR |
910 | end += table->length; |
911 | p += IVRS_HEADER_LENGTH; | |
912 | ||
913 | while (p < end) { | |
914 | h = (struct ivhd_header *)p; | |
915 | switch (*p) { | |
916 | case ACPI_IVHD_TYPE: | |
9c72041f | 917 | |
ae908c22 | 918 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
919 | "seg: %d flags: %01x info %04x\n", |
920 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
921 | PCI_FUNC(h->devid), h->cap_ptr, | |
922 | h->pci_seg, h->flags, h->info); | |
923 | DUMP_printk(" mmio-addr: %016llx\n", | |
924 | h->mmio_phys); | |
925 | ||
e47d402d | 926 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
3551a708 JR |
927 | if (iommu == NULL) { |
928 | amd_iommu_init_err = -ENOMEM; | |
929 | return 0; | |
930 | } | |
931 | ||
e47d402d | 932 | ret = init_iommu_one(iommu, h); |
3551a708 JR |
933 | if (ret) { |
934 | amd_iommu_init_err = ret; | |
935 | return 0; | |
936 | } | |
e47d402d JR |
937 | break; |
938 | default: | |
939 | break; | |
940 | } | |
941 | p += h->length; | |
942 | ||
943 | } | |
944 | WARN_ON(p != end); | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
a80dc3e0 JR |
949 | /**************************************************************************** |
950 | * | |
951 | * The following functions initialize the MSI interrupts for all IOMMUs | |
952 | * in the system. Its a bit challenging because there could be multiple | |
953 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
954 | * pci_dev. | |
955 | * | |
956 | ****************************************************************************/ | |
957 | ||
9f800de3 | 958 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
959 | { |
960 | int r; | |
a80dc3e0 JR |
961 | |
962 | if (pci_enable_msi(iommu->dev)) | |
963 | return 1; | |
964 | ||
965 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
966 | IRQF_SAMPLE_RANDOM, | |
4c6f40d4 | 967 | "AMD-Vi", |
a80dc3e0 JR |
968 | NULL); |
969 | ||
970 | if (r) { | |
971 | pci_disable_msi(iommu->dev); | |
972 | return 1; | |
973 | } | |
974 | ||
fab6afa3 | 975 | iommu->int_enabled = true; |
58492e12 JR |
976 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
977 | ||
a80dc3e0 JR |
978 | return 0; |
979 | } | |
980 | ||
05f92db9 | 981 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
982 | { |
983 | if (iommu->int_enabled) | |
984 | return 0; | |
985 | ||
d91cecdd | 986 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
987 | return iommu_setup_msi(iommu); |
988 | ||
989 | return 1; | |
990 | } | |
991 | ||
b65233a9 JR |
992 | /**************************************************************************** |
993 | * | |
994 | * The next functions belong to the third pass of parsing the ACPI | |
995 | * table. In this last pass the memory mapping requirements are | |
996 | * gathered (like exclusion and unity mapping reanges). | |
997 | * | |
998 | ****************************************************************************/ | |
999 | ||
be2a022c JR |
1000 | static void __init free_unity_maps(void) |
1001 | { | |
1002 | struct unity_map_entry *entry, *next; | |
1003 | ||
1004 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1005 | list_del(&entry->list); | |
1006 | kfree(entry); | |
1007 | } | |
1008 | } | |
1009 | ||
b65233a9 | 1010 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1011 | static int __init init_exclusion_range(struct ivmd_header *m) |
1012 | { | |
1013 | int i; | |
1014 | ||
1015 | switch (m->type) { | |
1016 | case ACPI_IVMD_TYPE: | |
1017 | set_device_exclusion_range(m->devid, m); | |
1018 | break; | |
1019 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1020 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1021 | set_device_exclusion_range(i, m); |
1022 | break; | |
1023 | case ACPI_IVMD_TYPE_RANGE: | |
1024 | for (i = m->devid; i <= m->aux; ++i) | |
1025 | set_device_exclusion_range(i, m); | |
1026 | break; | |
1027 | default: | |
1028 | break; | |
1029 | } | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
b65233a9 | 1034 | /* called for unity map ACPI definition */ |
be2a022c JR |
1035 | static int __init init_unity_map_range(struct ivmd_header *m) |
1036 | { | |
1037 | struct unity_map_entry *e = 0; | |
02acc43a | 1038 | char *s; |
be2a022c JR |
1039 | |
1040 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1041 | if (e == NULL) | |
1042 | return -ENOMEM; | |
1043 | ||
1044 | switch (m->type) { | |
1045 | default: | |
0bc252f4 JR |
1046 | kfree(e); |
1047 | return 0; | |
be2a022c | 1048 | case ACPI_IVMD_TYPE: |
02acc43a | 1049 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1050 | e->devid_start = e->devid_end = m->devid; |
1051 | break; | |
1052 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1053 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1054 | e->devid_start = 0; |
1055 | e->devid_end = amd_iommu_last_bdf; | |
1056 | break; | |
1057 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1058 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1059 | e->devid_start = m->devid; |
1060 | e->devid_end = m->aux; | |
1061 | break; | |
1062 | } | |
1063 | e->address_start = PAGE_ALIGN(m->range_start); | |
1064 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1065 | e->prot = m->flags >> 1; | |
1066 | ||
02acc43a JR |
1067 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1068 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1069 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1070 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1071 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1072 | e->address_start, e->address_end, m->flags); | |
1073 | ||
be2a022c JR |
1074 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
b65233a9 | 1079 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1080 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1081 | { | |
1082 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1083 | struct ivmd_header *m; | |
1084 | ||
be2a022c JR |
1085 | end += table->length; |
1086 | p += IVRS_HEADER_LENGTH; | |
1087 | ||
1088 | while (p < end) { | |
1089 | m = (struct ivmd_header *)p; | |
1090 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1091 | init_exclusion_range(m); | |
1092 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1093 | init_unity_map_range(m); | |
1094 | ||
1095 | p += m->length; | |
1096 | } | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
9f5f5fb3 JR |
1101 | /* |
1102 | * Init the device table to not allow DMA access for devices and | |
1103 | * suppress all page faults | |
1104 | */ | |
1105 | static void init_device_table(void) | |
1106 | { | |
1107 | u16 devid; | |
1108 | ||
1109 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1110 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1111 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1112 | } |
1113 | } | |
1114 | ||
b65233a9 JR |
1115 | /* |
1116 | * This function finally enables all IOMMUs found in the system after | |
1117 | * they have been initialized | |
1118 | */ | |
05f92db9 | 1119 | static void enable_iommus(void) |
8736197b JR |
1120 | { |
1121 | struct amd_iommu *iommu; | |
1122 | ||
3bd22172 | 1123 | for_each_iommu(iommu) { |
a8c485bb | 1124 | iommu_disable(iommu); |
58492e12 JR |
1125 | iommu_set_device_table(iommu); |
1126 | iommu_enable_command_buffer(iommu); | |
1127 | iommu_enable_event_buffer(iommu); | |
8736197b | 1128 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1129 | iommu_init_msi(iommu); |
8736197b JR |
1130 | iommu_enable(iommu); |
1131 | } | |
1132 | } | |
1133 | ||
92ac4320 JR |
1134 | static void disable_iommus(void) |
1135 | { | |
1136 | struct amd_iommu *iommu; | |
1137 | ||
1138 | for_each_iommu(iommu) | |
1139 | iommu_disable(iommu); | |
1140 | } | |
1141 | ||
7441e9cb JR |
1142 | /* |
1143 | * Suspend/Resume support | |
1144 | * disable suspend until real resume implemented | |
1145 | */ | |
1146 | ||
1147 | static int amd_iommu_resume(struct sys_device *dev) | |
1148 | { | |
736501ee JR |
1149 | /* re-load the hardware */ |
1150 | enable_iommus(); | |
1151 | ||
1152 | /* | |
1153 | * we have to flush after the IOMMUs are enabled because a | |
1154 | * disabled IOMMU will never execute the commands we send | |
1155 | */ | |
736501ee | 1156 | amd_iommu_flush_all_devices(); |
6a047d8b | 1157 | amd_iommu_flush_all_domains(); |
736501ee | 1158 | |
7441e9cb JR |
1159 | return 0; |
1160 | } | |
1161 | ||
1162 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
1163 | { | |
736501ee JR |
1164 | /* disable IOMMUs to go out of the way for BIOS */ |
1165 | disable_iommus(); | |
1166 | ||
1167 | return 0; | |
7441e9cb JR |
1168 | } |
1169 | ||
1170 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1171 | .name = "amd_iommu", | |
1172 | .suspend = amd_iommu_suspend, | |
1173 | .resume = amd_iommu_resume, | |
1174 | }; | |
1175 | ||
1176 | static struct sys_device device_amd_iommu = { | |
1177 | .id = 0, | |
1178 | .cls = &amd_iommu_sysdev_class, | |
1179 | }; | |
1180 | ||
b65233a9 JR |
1181 | /* |
1182 | * This is the core init function for AMD IOMMU hardware in the system. | |
1183 | * This function is called from the generic x86 DMA layer initialization | |
1184 | * code. | |
1185 | * | |
1186 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1187 | * three times: | |
1188 | * | |
1189 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1190 | * Upon this information the size of the data structures is | |
1191 | * determined that needs to be allocated. | |
1192 | * | |
1193 | * 2 pass) Initialize the data structures just allocated with the | |
1194 | * information in the ACPI table about available AMD IOMMUs | |
1195 | * in the system. It also maps the PCI devices in the | |
1196 | * system to specific IOMMUs | |
1197 | * | |
1198 | * 3 pass) After the basic data structures are allocated and | |
1199 | * initialized we update them with information about memory | |
1200 | * remapping requirements parsed out of the ACPI table in | |
1201 | * this last pass. | |
1202 | * | |
1203 | * After that the hardware is initialized and ready to go. In the last | |
1204 | * step we do some Linux specific things like registering the driver in | |
1205 | * the dma_ops interface and initializing the suspend/resume support | |
1206 | * functions. Finally it prints some information about AMD IOMMUs and | |
1207 | * the driver state and enables the hardware. | |
1208 | */ | |
ea1b0d39 | 1209 | static int __init amd_iommu_init(void) |
fe74c9cf JR |
1210 | { |
1211 | int i, ret = 0; | |
1212 | ||
fe74c9cf JR |
1213 | /* |
1214 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1215 | * we need to handle. Upon this information the shared data | |
1216 | * structures for the IOMMUs in the system will be allocated | |
1217 | */ | |
1218 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1219 | return -ENODEV; | |
1220 | ||
3551a708 JR |
1221 | ret = amd_iommu_init_err; |
1222 | if (ret) | |
1223 | goto out; | |
1224 | ||
c571484e JR |
1225 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1226 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1227 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1228 | |
1229 | ret = -ENOMEM; | |
1230 | ||
1231 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1232 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1233 | get_order(dev_table_size)); |
1234 | if (amd_iommu_dev_table == NULL) | |
1235 | goto out; | |
1236 | ||
1237 | /* | |
1238 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1239 | * IOMMU see for that device | |
1240 | */ | |
1241 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1242 | get_order(alias_table_size)); | |
1243 | if (amd_iommu_alias_table == NULL) | |
1244 | goto free; | |
1245 | ||
1246 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1247 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1248 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1249 | get_order(rlookup_table_size)); |
1250 | if (amd_iommu_rlookup_table == NULL) | |
1251 | goto free; | |
1252 | ||
5dc8bff0 JR |
1253 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1254 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1255 | get_order(MAX_DOMAIN_ID/8)); |
1256 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1257 | goto free; | |
1258 | ||
9f5f5fb3 JR |
1259 | /* init the device table */ |
1260 | init_device_table(); | |
1261 | ||
fe74c9cf | 1262 | /* |
5dc8bff0 | 1263 | * let all alias entries point to itself |
fe74c9cf | 1264 | */ |
3a61ec38 | 1265 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1266 | amd_iommu_alias_table[i] = i; |
1267 | ||
fe74c9cf JR |
1268 | /* |
1269 | * never allocate domain 0 because its used as the non-allocated and | |
1270 | * error value placeholder | |
1271 | */ | |
1272 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1273 | ||
aeb26f55 JR |
1274 | spin_lock_init(&amd_iommu_pd_lock); |
1275 | ||
fe74c9cf JR |
1276 | /* |
1277 | * now the data structures are allocated and basically initialized | |
1278 | * start the real acpi table scan | |
1279 | */ | |
1280 | ret = -ENODEV; | |
1281 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1282 | goto free; | |
1283 | ||
3551a708 JR |
1284 | if (amd_iommu_init_err) { |
1285 | ret = amd_iommu_init_err; | |
0f764806 | 1286 | goto free; |
3551a708 | 1287 | } |
0f764806 | 1288 | |
fe74c9cf JR |
1289 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) |
1290 | goto free; | |
1291 | ||
3551a708 JR |
1292 | if (amd_iommu_init_err) { |
1293 | ret = amd_iommu_init_err; | |
1294 | goto free; | |
1295 | } | |
1296 | ||
129d6aba | 1297 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1298 | if (ret) |
1299 | goto free; | |
1300 | ||
129d6aba | 1301 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1302 | if (ret) |
1303 | goto free; | |
1304 | ||
b7cc9554 JR |
1305 | ret = amd_iommu_init_devices(); |
1306 | if (ret) | |
1307 | goto free; | |
1308 | ||
75f66533 CW |
1309 | enable_iommus(); |
1310 | ||
4751a951 JR |
1311 | if (iommu_pass_through) |
1312 | ret = amd_iommu_init_passthrough(); | |
1313 | else | |
1314 | ret = amd_iommu_init_dma_ops(); | |
f5325094 | 1315 | |
7441e9cb JR |
1316 | if (ret) |
1317 | goto free; | |
1318 | ||
f5325094 JR |
1319 | amd_iommu_init_api(); |
1320 | ||
8638c491 JR |
1321 | amd_iommu_init_notifier(); |
1322 | ||
4751a951 JR |
1323 | if (iommu_pass_through) |
1324 | goto out; | |
1325 | ||
afa9fdc2 | 1326 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1327 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1328 | else |
4c6f40d4 | 1329 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1330 | |
338bac52 | 1331 | x86_platform.iommu_shutdown = disable_iommus; |
fe74c9cf JR |
1332 | out: |
1333 | return ret; | |
1334 | ||
1335 | free: | |
75f66533 | 1336 | disable_iommus(); |
b7cc9554 JR |
1337 | |
1338 | amd_iommu_uninit_devices(); | |
1339 | ||
d58befd3 JR |
1340 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1341 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1342 | |
9a836de0 JR |
1343 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1344 | get_order(rlookup_table_size)); | |
fe74c9cf | 1345 | |
9a836de0 JR |
1346 | free_pages((unsigned long)amd_iommu_alias_table, |
1347 | get_order(alias_table_size)); | |
fe74c9cf | 1348 | |
9a836de0 JR |
1349 | free_pages((unsigned long)amd_iommu_dev_table, |
1350 | get_order(dev_table_size)); | |
fe74c9cf JR |
1351 | |
1352 | free_iommu_all(); | |
1353 | ||
1354 | free_unity_maps(); | |
1355 | ||
1356 | goto out; | |
1357 | } | |
1358 | ||
b65233a9 JR |
1359 | /**************************************************************************** |
1360 | * | |
1361 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1362 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1363 | * IOMMUs | |
1364 | * | |
1365 | ****************************************************************************/ | |
ae7877de JR |
1366 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1367 | { | |
1368 | return 0; | |
1369 | } | |
1370 | ||
1371 | void __init amd_iommu_detect(void) | |
1372 | { | |
75f1cdf1 | 1373 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1374 | return; |
1375 | ||
a5235725 JR |
1376 | if (amd_iommu_disabled) |
1377 | return; | |
1378 | ||
ae7877de JR |
1379 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1380 | iommu_detected = 1; | |
c1cbebee | 1381 | amd_iommu_detected = 1; |
ea1b0d39 | 1382 | x86_init.iommu.iommu_init = amd_iommu_init; |
11bd04f6 | 1383 | |
5d990b62 CW |
1384 | /* Make sure ACS will be enabled */ |
1385 | pci_request_acs(); | |
ae7877de JR |
1386 | } |
1387 | } | |
1388 | ||
b65233a9 JR |
1389 | /**************************************************************************** |
1390 | * | |
1391 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1392 | * options. | |
1393 | * | |
1394 | ****************************************************************************/ | |
1395 | ||
fefda117 JR |
1396 | static int __init parse_amd_iommu_dump(char *str) |
1397 | { | |
1398 | amd_iommu_dump = true; | |
1399 | ||
1400 | return 1; | |
1401 | } | |
1402 | ||
918ad6c5 JR |
1403 | static int __init parse_amd_iommu_options(char *str) |
1404 | { | |
1405 | for (; *str; ++str) { | |
695b5676 | 1406 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1407 | amd_iommu_unmap_flush = true; |
a5235725 JR |
1408 | if (strncmp(str, "off", 3) == 0) |
1409 | amd_iommu_disabled = true; | |
918ad6c5 JR |
1410 | } |
1411 | ||
1412 | return 1; | |
1413 | } | |
1414 | ||
fefda117 | 1415 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1416 | __setup("amd_iommu=", parse_amd_iommu_options); |