]>
Commit | Line | Data |
---|---|---|
f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
f6e2e6b6 JR |
31 | |
32 | /* | |
33 | * definitions for the ACPI scanning code | |
34 | */ | |
f6e2e6b6 | 35 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
36 | |
37 | #define ACPI_IVHD_TYPE 0x10 | |
38 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
39 | #define ACPI_IVMD_TYPE 0x21 | |
40 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
41 | ||
42 | #define IVHD_DEV_ALL 0x01 | |
43 | #define IVHD_DEV_SELECT 0x02 | |
44 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
45 | #define IVHD_DEV_RANGE_END 0x04 | |
46 | #define IVHD_DEV_ALIAS 0x42 | |
47 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
48 | #define IVHD_DEV_EXT_SELECT 0x46 | |
49 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
50 | ||
51 | #define IVHD_FLAG_HT_TUN_EN 0x00 | |
52 | #define IVHD_FLAG_PASSPW_EN 0x01 | |
53 | #define IVHD_FLAG_RESPASSPW_EN 0x02 | |
54 | #define IVHD_FLAG_ISOC_EN 0x03 | |
55 | ||
56 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
57 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
58 | ||
59 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
60 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
61 | #define ACPI_DEVFLAG_NMI 0x04 | |
62 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
63 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
64 | #define ACPI_DEVFLAG_LINT0 0x40 | |
65 | #define ACPI_DEVFLAG_LINT1 0x80 | |
66 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
67 | ||
b65233a9 JR |
68 | /* |
69 | * ACPI table definitions | |
70 | * | |
71 | * These data structures are laid over the table to parse the important values | |
72 | * out of it. | |
73 | */ | |
74 | ||
75 | /* | |
76 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
77 | * or more ivhd_entrys. | |
78 | */ | |
f6e2e6b6 JR |
79 | struct ivhd_header { |
80 | u8 type; | |
81 | u8 flags; | |
82 | u16 length; | |
83 | u16 devid; | |
84 | u16 cap_ptr; | |
85 | u64 mmio_phys; | |
86 | u16 pci_seg; | |
87 | u16 info; | |
88 | u32 reserved; | |
89 | } __attribute__((packed)); | |
90 | ||
b65233a9 JR |
91 | /* |
92 | * A device entry describing which devices a specific IOMMU translates and | |
93 | * which requestor ids they use. | |
94 | */ | |
f6e2e6b6 JR |
95 | struct ivhd_entry { |
96 | u8 type; | |
97 | u16 devid; | |
98 | u8 flags; | |
99 | u32 ext; | |
100 | } __attribute__((packed)); | |
101 | ||
b65233a9 JR |
102 | /* |
103 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
104 | * ranges for devices and regions that should be unity mapped. | |
105 | */ | |
f6e2e6b6 JR |
106 | struct ivmd_header { |
107 | u8 type; | |
108 | u8 flags; | |
109 | u16 length; | |
110 | u16 devid; | |
111 | u16 aux; | |
112 | u64 resv; | |
113 | u64 range_start; | |
114 | u64 range_length; | |
115 | } __attribute__((packed)); | |
116 | ||
c1cbebee JR |
117 | static int __initdata amd_iommu_detected; |
118 | ||
b65233a9 JR |
119 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
120 | to handle */ | |
2e22847f | 121 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 JR |
122 | we find in ACPI */ |
123 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
124 | int amd_iommu_isolate; /* if 1, device isolation is enabled */ | |
928abd25 | 125 | |
2e22847f | 126 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 127 | system */ |
928abd25 | 128 | |
b65233a9 JR |
129 | /* |
130 | * Pointer to the device table which is shared by all AMD IOMMUs | |
131 | * it is indexed by the PCI device id or the HT unit id and contains | |
132 | * information about the domain the device belongs to as well as the | |
133 | * page table root pointer. | |
134 | */ | |
928abd25 | 135 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
136 | |
137 | /* | |
138 | * The alias table is a driver specific data structure which contains the | |
139 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
140 | * More than one device can share the same requestor id. | |
141 | */ | |
928abd25 | 142 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
143 | |
144 | /* | |
145 | * The rlookup table is used to find the IOMMU which is responsible | |
146 | * for a specific device. It is also indexed by the PCI device id. | |
147 | */ | |
928abd25 | 148 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
149 | |
150 | /* | |
151 | * The pd table (protection domain table) is used to find the protection domain | |
152 | * data structure a device belongs to. Indexed with the PCI device id too. | |
153 | */ | |
928abd25 | 154 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
155 | |
156 | /* | |
157 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
158 | * to know which ones are already in use. | |
159 | */ | |
928abd25 JR |
160 | unsigned long *amd_iommu_pd_alloc_bitmap; |
161 | ||
b65233a9 JR |
162 | static u32 dev_table_size; /* size of the device table */ |
163 | static u32 alias_table_size; /* size of the alias table */ | |
164 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 165 | |
208ec8c9 JR |
166 | static inline void update_last_devid(u16 devid) |
167 | { | |
168 | if (devid > amd_iommu_last_bdf) | |
169 | amd_iommu_last_bdf = devid; | |
170 | } | |
171 | ||
c571484e JR |
172 | static inline unsigned long tbl_size(int entry_size) |
173 | { | |
174 | unsigned shift = PAGE_SHIFT + | |
175 | get_order(amd_iommu_last_bdf * entry_size); | |
176 | ||
177 | return 1UL << shift; | |
178 | } | |
179 | ||
b65233a9 JR |
180 | /**************************************************************************** |
181 | * | |
182 | * AMD IOMMU MMIO register space handling functions | |
183 | * | |
184 | * These functions are used to program the IOMMU device registers in | |
185 | * MMIO space required for that driver. | |
186 | * | |
187 | ****************************************************************************/ | |
3e8064ba | 188 | |
b65233a9 JR |
189 | /* |
190 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
191 | * exclusion range are passed through untranslated | |
192 | */ | |
b2026aa2 JR |
193 | static void __init iommu_set_exclusion_range(struct amd_iommu *iommu) |
194 | { | |
195 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
196 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
197 | u64 entry; | |
198 | ||
199 | if (!iommu->exclusion_start) | |
200 | return; | |
201 | ||
202 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
203 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
204 | &entry, sizeof(entry)); | |
205 | ||
206 | entry = limit; | |
207 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
208 | &entry, sizeof(entry)); | |
209 | } | |
210 | ||
b65233a9 | 211 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
212 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
213 | { | |
214 | u32 entry; | |
215 | ||
216 | BUG_ON(iommu->mmio_base == NULL); | |
217 | ||
218 | entry = virt_to_phys(amd_iommu_dev_table); | |
219 | entry |= (dev_table_size >> 12) - 1; | |
220 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
221 | &entry, sizeof(entry)); | |
222 | } | |
223 | ||
b65233a9 | 224 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
b2026aa2 JR |
225 | static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
226 | { | |
227 | u32 ctrl; | |
228 | ||
229 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
230 | ctrl |= (1 << bit); | |
231 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
232 | } | |
233 | ||
234 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
235 | { | |
236 | u32 ctrl; | |
237 | ||
238 | ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
239 | ctrl &= ~(1 << bit); | |
240 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
241 | } | |
242 | ||
b65233a9 | 243 | /* Function to enable the hardware */ |
b2026aa2 JR |
244 | void __init iommu_enable(struct amd_iommu *iommu) |
245 | { | |
3eaf28a1 JR |
246 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU " |
247 | "at %02x:%02x.%x cap 0x%hx\n", | |
248 | iommu->dev->bus->number, | |
249 | PCI_SLOT(iommu->dev->devfn), | |
250 | PCI_FUNC(iommu->dev->devfn), | |
251 | iommu->cap_ptr); | |
b2026aa2 JR |
252 | |
253 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
254 | } |
255 | ||
b65233a9 JR |
256 | /* |
257 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
258 | * the system has one. | |
259 | */ | |
6c56747b JR |
260 | static u8 * __init iommu_map_mmio_space(u64 address) |
261 | { | |
262 | u8 *ret; | |
263 | ||
264 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
265 | return NULL; | |
266 | ||
267 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
268 | if (ret != NULL) | |
269 | return ret; | |
270 | ||
271 | release_mem_region(address, MMIO_REGION_LENGTH); | |
272 | ||
273 | return NULL; | |
274 | } | |
275 | ||
276 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
277 | { | |
278 | if (iommu->mmio_base) | |
279 | iounmap(iommu->mmio_base); | |
280 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
281 | } | |
282 | ||
b65233a9 JR |
283 | /**************************************************************************** |
284 | * | |
285 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
286 | * parsing. In this pass we try to find out the highest device id this | |
287 | * code has to handle. Upon this information the size of the shared data | |
288 | * structures is determined later. | |
289 | * | |
290 | ****************************************************************************/ | |
291 | ||
292 | /* | |
293 | * This function reads the last device id the IOMMU has to handle from the PCI | |
294 | * capability header for this IOMMU | |
295 | */ | |
3e8064ba JR |
296 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
297 | { | |
298 | u32 cap; | |
299 | ||
300 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 301 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
302 | |
303 | return 0; | |
304 | } | |
305 | ||
b65233a9 JR |
306 | /* |
307 | * After reading the highest device id from the IOMMU PCI capability header | |
308 | * this function looks if there is a higher device id defined in the ACPI table | |
309 | */ | |
3e8064ba JR |
310 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
311 | { | |
312 | u8 *p = (void *)h, *end = (void *)h; | |
313 | struct ivhd_entry *dev; | |
314 | ||
315 | p += sizeof(*h); | |
316 | end += h->length; | |
317 | ||
318 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
319 | PCI_SLOT(h->devid), | |
320 | PCI_FUNC(h->devid), | |
321 | h->cap_ptr); | |
322 | ||
323 | while (p < end) { | |
324 | dev = (struct ivhd_entry *)p; | |
325 | switch (dev->type) { | |
326 | case IVHD_DEV_SELECT: | |
327 | case IVHD_DEV_RANGE_END: | |
328 | case IVHD_DEV_ALIAS: | |
329 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 330 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 331 | update_last_devid(dev->devid); |
3e8064ba JR |
332 | break; |
333 | default: | |
334 | break; | |
335 | } | |
336 | p += 0x04 << (*p >> 6); | |
337 | } | |
338 | ||
339 | WARN_ON(p != end); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
b65233a9 JR |
344 | /* |
345 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
346 | * id which we need to handle. This is the first of three functions which parse | |
347 | * the ACPI table. So we check the checksum here. | |
348 | */ | |
3e8064ba JR |
349 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
350 | { | |
351 | int i; | |
352 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
353 | struct ivhd_header *h; | |
354 | ||
355 | /* | |
356 | * Validate checksum here so we don't need to do it when | |
357 | * we actually parse the table | |
358 | */ | |
359 | for (i = 0; i < table->length; ++i) | |
360 | checksum += p[i]; | |
361 | if (checksum != 0) | |
362 | /* ACPI table corrupt */ | |
363 | return -ENODEV; | |
364 | ||
365 | p += IVRS_HEADER_LENGTH; | |
366 | ||
367 | end += table->length; | |
368 | while (p < end) { | |
369 | h = (struct ivhd_header *)p; | |
370 | switch (h->type) { | |
371 | case ACPI_IVHD_TYPE: | |
372 | find_last_devid_from_ivhd(h); | |
373 | break; | |
374 | default: | |
375 | break; | |
376 | } | |
377 | p += h->length; | |
378 | } | |
379 | WARN_ON(p != end); | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
b65233a9 JR |
384 | /**************************************************************************** |
385 | * | |
386 | * The following functions belong the the code path which parses the ACPI table | |
387 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
388 | * data structures, initialize the device/alias/rlookup table and also | |
389 | * basically initialize the hardware. | |
390 | * | |
391 | ****************************************************************************/ | |
392 | ||
393 | /* | |
394 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
395 | * write commands to that buffer later and the IOMMU will execute them | |
396 | * asynchronously | |
397 | */ | |
b36ca91e JR |
398 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
399 | { | |
d0312b21 | 400 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 401 | get_order(CMD_BUFFER_SIZE)); |
d0312b21 | 402 | u64 entry; |
b36ca91e JR |
403 | |
404 | if (cmd_buf == NULL) | |
405 | return NULL; | |
406 | ||
407 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
408 | ||
b36ca91e JR |
409 | entry = (u64)virt_to_phys(cmd_buf); |
410 | entry |= MMIO_CMD_SIZE_512; | |
411 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, | |
412 | &entry, sizeof(entry)); | |
413 | ||
414 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
415 | ||
416 | return cmd_buf; | |
417 | } | |
418 | ||
419 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
420 | { | |
9a836de0 | 421 | free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
422 | } |
423 | ||
335503e5 JR |
424 | /* allocates the memory where the IOMMU will log its events to */ |
425 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
426 | { | |
427 | u64 entry; | |
428 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
429 | get_order(EVT_BUFFER_SIZE)); | |
430 | ||
431 | if (iommu->evt_buf == NULL) | |
432 | return NULL; | |
433 | ||
434 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; | |
435 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, | |
436 | &entry, sizeof(entry)); | |
437 | ||
438 | iommu->evt_buf_size = EVT_BUFFER_SIZE; | |
439 | ||
440 | return iommu->evt_buf; | |
441 | } | |
442 | ||
443 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
444 | { | |
445 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
446 | } | |
447 | ||
b65233a9 | 448 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
449 | static void set_dev_entry_bit(u16 devid, u8 bit) |
450 | { | |
451 | int i = (bit >> 5) & 0x07; | |
452 | int _bit = bit & 0x1f; | |
453 | ||
454 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
455 | } | |
456 | ||
5ff4789d JR |
457 | /* Writes the specific IOMMU for a device into the rlookup table */ |
458 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
459 | { | |
460 | amd_iommu_rlookup_table[devid] = iommu; | |
461 | } | |
462 | ||
b65233a9 JR |
463 | /* |
464 | * This function takes the device specific flags read from the ACPI | |
465 | * table and sets up the device table entry with that information | |
466 | */ | |
5ff4789d JR |
467 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
468 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
469 | { |
470 | if (flags & ACPI_DEVFLAG_INITPASS) | |
471 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
472 | if (flags & ACPI_DEVFLAG_EXTINT) | |
473 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
474 | if (flags & ACPI_DEVFLAG_NMI) | |
475 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
476 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
477 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
478 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
479 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
480 | if (flags & ACPI_DEVFLAG_LINT0) | |
481 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
482 | if (flags & ACPI_DEVFLAG_LINT1) | |
483 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 484 | |
5ff4789d | 485 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
486 | } |
487 | ||
b65233a9 JR |
488 | /* |
489 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
490 | * it | |
491 | */ | |
3566b778 JR |
492 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
493 | { | |
494 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
495 | ||
496 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
497 | return; | |
498 | ||
499 | if (iommu) { | |
b65233a9 JR |
500 | /* |
501 | * We only can configure exclusion ranges per IOMMU, not | |
502 | * per device. But we can enable the exclusion range per | |
503 | * device. This is done here | |
504 | */ | |
3566b778 JR |
505 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
506 | iommu->exclusion_start = m->range_start; | |
507 | iommu->exclusion_length = m->range_length; | |
508 | } | |
509 | } | |
510 | ||
b65233a9 JR |
511 | /* |
512 | * This function reads some important data from the IOMMU PCI space and | |
513 | * initializes the driver data structure with it. It reads the hardware | |
514 | * capabilities and the first/last device entries | |
515 | */ | |
5d0c8e49 JR |
516 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
517 | { | |
5d0c8e49 | 518 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 519 | u32 range, misc; |
5d0c8e49 | 520 | |
3eaf28a1 JR |
521 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
522 | &iommu->cap); | |
523 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
524 | &range); | |
a80dc3e0 JR |
525 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
526 | &misc); | |
5d0c8e49 | 527 | |
d591b0a3 JR |
528 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
529 | MMIO_GET_FD(range)); | |
530 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
531 | MMIO_GET_LD(range)); | |
a80dc3e0 | 532 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
533 | } |
534 | ||
b65233a9 JR |
535 | /* |
536 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
537 | * initializes the hardware and our data structures with it. | |
538 | */ | |
5d0c8e49 JR |
539 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
540 | struct ivhd_header *h) | |
541 | { | |
542 | u8 *p = (u8 *)h; | |
543 | u8 *end = p, flags = 0; | |
544 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
545 | u32 ext_flags = 0; | |
58a3bee5 | 546 | bool alias = false; |
5d0c8e49 JR |
547 | struct ivhd_entry *e; |
548 | ||
549 | /* | |
550 | * First set the recommended feature enable bits from ACPI | |
551 | * into the IOMMU control registers | |
552 | */ | |
553 | h->flags & IVHD_FLAG_HT_TUN_EN ? | |
554 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
555 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
556 | ||
557 | h->flags & IVHD_FLAG_PASSPW_EN ? | |
558 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
559 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
560 | ||
561 | h->flags & IVHD_FLAG_RESPASSPW_EN ? | |
562 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
563 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
564 | ||
565 | h->flags & IVHD_FLAG_ISOC_EN ? | |
566 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
567 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
568 | ||
569 | /* | |
570 | * make IOMMU memory accesses cache coherent | |
571 | */ | |
572 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
573 | ||
574 | /* | |
575 | * Done. Now parse the device entries | |
576 | */ | |
577 | p += sizeof(struct ivhd_header); | |
578 | end += h->length; | |
579 | ||
580 | while (p < end) { | |
581 | e = (struct ivhd_entry *)p; | |
582 | switch (e->type) { | |
583 | case IVHD_DEV_ALL: | |
584 | for (dev_i = iommu->first_device; | |
585 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
586 | set_dev_entry_from_acpi(iommu, dev_i, |
587 | e->flags, 0); | |
5d0c8e49 JR |
588 | break; |
589 | case IVHD_DEV_SELECT: | |
590 | devid = e->devid; | |
5ff4789d | 591 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
592 | break; |
593 | case IVHD_DEV_SELECT_RANGE_START: | |
594 | devid_start = e->devid; | |
595 | flags = e->flags; | |
596 | ext_flags = 0; | |
58a3bee5 | 597 | alias = false; |
5d0c8e49 JR |
598 | break; |
599 | case IVHD_DEV_ALIAS: | |
600 | devid = e->devid; | |
601 | devid_to = e->ext >> 8; | |
5ff4789d | 602 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
603 | amd_iommu_alias_table[devid] = devid_to; |
604 | break; | |
605 | case IVHD_DEV_ALIAS_RANGE: | |
606 | devid_start = e->devid; | |
607 | flags = e->flags; | |
608 | devid_to = e->ext >> 8; | |
609 | ext_flags = 0; | |
58a3bee5 | 610 | alias = true; |
5d0c8e49 JR |
611 | break; |
612 | case IVHD_DEV_EXT_SELECT: | |
613 | devid = e->devid; | |
5ff4789d JR |
614 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
615 | e->ext); | |
5d0c8e49 JR |
616 | break; |
617 | case IVHD_DEV_EXT_SELECT_RANGE: | |
618 | devid_start = e->devid; | |
619 | flags = e->flags; | |
620 | ext_flags = e->ext; | |
58a3bee5 | 621 | alias = false; |
5d0c8e49 JR |
622 | break; |
623 | case IVHD_DEV_RANGE_END: | |
624 | devid = e->devid; | |
625 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
626 | if (alias) | |
627 | amd_iommu_alias_table[dev_i] = devid_to; | |
5ff4789d | 628 | set_dev_entry_from_acpi(iommu, |
5d0c8e49 JR |
629 | amd_iommu_alias_table[dev_i], |
630 | flags, ext_flags); | |
631 | } | |
632 | break; | |
633 | default: | |
634 | break; | |
635 | } | |
636 | ||
637 | p += 0x04 << (e->type >> 6); | |
638 | } | |
639 | } | |
640 | ||
b65233a9 | 641 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
642 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
643 | { | |
644 | u16 i; | |
645 | ||
646 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
647 | set_iommu_for_device(iommu, i); | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
e47d402d JR |
652 | static void __init free_iommu_one(struct amd_iommu *iommu) |
653 | { | |
654 | free_command_buffer(iommu); | |
335503e5 | 655 | free_event_buffer(iommu); |
e47d402d JR |
656 | iommu_unmap_mmio_space(iommu); |
657 | } | |
658 | ||
659 | static void __init free_iommu_all(void) | |
660 | { | |
661 | struct amd_iommu *iommu, *next; | |
662 | ||
663 | list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) { | |
664 | list_del(&iommu->list); | |
665 | free_iommu_one(iommu); | |
666 | kfree(iommu); | |
667 | } | |
668 | } | |
669 | ||
b65233a9 JR |
670 | /* |
671 | * This function clues the initialization function for one IOMMU | |
672 | * together and also allocates the command buffer and programs the | |
673 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
674 | */ | |
e47d402d JR |
675 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
676 | { | |
677 | spin_lock_init(&iommu->lock); | |
678 | list_add_tail(&iommu->list, &amd_iommu_list); | |
679 | ||
680 | /* | |
681 | * Copy data from ACPI table entry to the iommu struct | |
682 | */ | |
3eaf28a1 JR |
683 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
684 | if (!iommu->dev) | |
685 | return 1; | |
686 | ||
e47d402d | 687 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 688 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
689 | iommu->mmio_phys = h->mmio_phys; |
690 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
691 | if (!iommu->mmio_base) | |
692 | return -ENOMEM; | |
693 | ||
694 | iommu_set_device_table(iommu); | |
695 | iommu->cmd_buf = alloc_command_buffer(iommu); | |
696 | if (!iommu->cmd_buf) | |
697 | return -ENOMEM; | |
698 | ||
335503e5 JR |
699 | iommu->evt_buf = alloc_event_buffer(iommu); |
700 | if (!iommu->evt_buf) | |
701 | return -ENOMEM; | |
702 | ||
a80dc3e0 JR |
703 | iommu->int_enabled = false; |
704 | ||
e47d402d JR |
705 | init_iommu_from_pci(iommu); |
706 | init_iommu_from_acpi(iommu, h); | |
707 | init_iommu_devices(iommu); | |
708 | ||
3eaf28a1 JR |
709 | pci_enable_device(iommu->dev); |
710 | ||
e47d402d JR |
711 | return 0; |
712 | } | |
713 | ||
b65233a9 JR |
714 | /* |
715 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
716 | * IOMMU structure and initializes it with init_iommu_one() | |
717 | */ | |
e47d402d JR |
718 | static int __init init_iommu_all(struct acpi_table_header *table) |
719 | { | |
720 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
721 | struct ivhd_header *h; | |
722 | struct amd_iommu *iommu; | |
723 | int ret; | |
724 | ||
e47d402d JR |
725 | end += table->length; |
726 | p += IVRS_HEADER_LENGTH; | |
727 | ||
728 | while (p < end) { | |
729 | h = (struct ivhd_header *)p; | |
730 | switch (*p) { | |
731 | case ACPI_IVHD_TYPE: | |
732 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
733 | if (iommu == NULL) | |
734 | return -ENOMEM; | |
735 | ret = init_iommu_one(iommu, h); | |
736 | if (ret) | |
737 | return ret; | |
738 | break; | |
739 | default: | |
740 | break; | |
741 | } | |
742 | p += h->length; | |
743 | ||
744 | } | |
745 | WARN_ON(p != end); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
a80dc3e0 JR |
750 | /**************************************************************************** |
751 | * | |
752 | * The following functions initialize the MSI interrupts for all IOMMUs | |
753 | * in the system. Its a bit challenging because there could be multiple | |
754 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
755 | * pci_dev. | |
756 | * | |
757 | ****************************************************************************/ | |
758 | ||
759 | static int __init iommu_setup_msix(struct amd_iommu *iommu) | |
760 | { | |
761 | struct amd_iommu *curr; | |
762 | struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */ | |
763 | int nvec = 0, i; | |
764 | ||
765 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
766 | if (curr->dev == iommu->dev) { | |
767 | entries[nvec].entry = curr->evt_msi_num; | |
768 | entries[nvec].vector = 0; | |
769 | curr->int_enabled = true; | |
770 | nvec++; | |
771 | } | |
772 | } | |
773 | ||
774 | if (pci_enable_msix(iommu->dev, entries, nvec)) { | |
775 | pci_disable_msix(iommu->dev); | |
776 | return 1; | |
777 | } | |
778 | ||
779 | for (i = 0; i < nvec; ++i) { | |
780 | int r = request_irq(entries->vector, amd_iommu_int_handler, | |
781 | IRQF_SAMPLE_RANDOM, | |
782 | "AMD IOMMU", | |
783 | NULL); | |
784 | if (r) | |
785 | goto out_free; | |
786 | } | |
787 | ||
788 | return 0; | |
789 | ||
790 | out_free: | |
791 | for (i -= 1; i >= 0; --i) | |
792 | free_irq(entries->vector, NULL); | |
793 | ||
794 | pci_disable_msix(iommu->dev); | |
795 | ||
796 | return 1; | |
797 | } | |
798 | ||
799 | static int __init iommu_setup_msi(struct amd_iommu *iommu) | |
800 | { | |
801 | int r; | |
802 | struct amd_iommu *curr; | |
803 | ||
804 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
805 | if (curr->dev == iommu->dev) | |
806 | curr->int_enabled = true; | |
807 | } | |
808 | ||
809 | ||
810 | if (pci_enable_msi(iommu->dev)) | |
811 | return 1; | |
812 | ||
813 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
814 | IRQF_SAMPLE_RANDOM, | |
815 | "AMD IOMMU", | |
816 | NULL); | |
817 | ||
818 | if (r) { | |
819 | pci_disable_msi(iommu->dev); | |
820 | return 1; | |
821 | } | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
826 | static int __init iommu_init_msi(struct amd_iommu *iommu) | |
827 | { | |
828 | if (iommu->int_enabled) | |
829 | return 0; | |
830 | ||
831 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX)) | |
832 | return iommu_setup_msix(iommu); | |
833 | else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) | |
834 | return iommu_setup_msi(iommu); | |
835 | ||
836 | return 1; | |
837 | } | |
838 | ||
b65233a9 JR |
839 | /**************************************************************************** |
840 | * | |
841 | * The next functions belong to the third pass of parsing the ACPI | |
842 | * table. In this last pass the memory mapping requirements are | |
843 | * gathered (like exclusion and unity mapping reanges). | |
844 | * | |
845 | ****************************************************************************/ | |
846 | ||
be2a022c JR |
847 | static void __init free_unity_maps(void) |
848 | { | |
849 | struct unity_map_entry *entry, *next; | |
850 | ||
851 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
852 | list_del(&entry->list); | |
853 | kfree(entry); | |
854 | } | |
855 | } | |
856 | ||
b65233a9 | 857 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
858 | static int __init init_exclusion_range(struct ivmd_header *m) |
859 | { | |
860 | int i; | |
861 | ||
862 | switch (m->type) { | |
863 | case ACPI_IVMD_TYPE: | |
864 | set_device_exclusion_range(m->devid, m); | |
865 | break; | |
866 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 867 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
868 | set_device_exclusion_range(i, m); |
869 | break; | |
870 | case ACPI_IVMD_TYPE_RANGE: | |
871 | for (i = m->devid; i <= m->aux; ++i) | |
872 | set_device_exclusion_range(i, m); | |
873 | break; | |
874 | default: | |
875 | break; | |
876 | } | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
b65233a9 | 881 | /* called for unity map ACPI definition */ |
be2a022c JR |
882 | static int __init init_unity_map_range(struct ivmd_header *m) |
883 | { | |
884 | struct unity_map_entry *e = 0; | |
885 | ||
886 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
887 | if (e == NULL) | |
888 | return -ENOMEM; | |
889 | ||
890 | switch (m->type) { | |
891 | default: | |
892 | case ACPI_IVMD_TYPE: | |
893 | e->devid_start = e->devid_end = m->devid; | |
894 | break; | |
895 | case ACPI_IVMD_TYPE_ALL: | |
896 | e->devid_start = 0; | |
897 | e->devid_end = amd_iommu_last_bdf; | |
898 | break; | |
899 | case ACPI_IVMD_TYPE_RANGE: | |
900 | e->devid_start = m->devid; | |
901 | e->devid_end = m->aux; | |
902 | break; | |
903 | } | |
904 | e->address_start = PAGE_ALIGN(m->range_start); | |
905 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
906 | e->prot = m->flags >> 1; | |
907 | ||
908 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
b65233a9 | 913 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
914 | static int __init init_memory_definitions(struct acpi_table_header *table) |
915 | { | |
916 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
917 | struct ivmd_header *m; | |
918 | ||
be2a022c JR |
919 | end += table->length; |
920 | p += IVRS_HEADER_LENGTH; | |
921 | ||
922 | while (p < end) { | |
923 | m = (struct ivmd_header *)p; | |
924 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
925 | init_exclusion_range(m); | |
926 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
927 | init_unity_map_range(m); | |
928 | ||
929 | p += m->length; | |
930 | } | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
9f5f5fb3 JR |
935 | /* |
936 | * Init the device table to not allow DMA access for devices and | |
937 | * suppress all page faults | |
938 | */ | |
939 | static void init_device_table(void) | |
940 | { | |
941 | u16 devid; | |
942 | ||
943 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
944 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
945 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
946 | set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT); | |
947 | } | |
948 | } | |
949 | ||
b65233a9 JR |
950 | /* |
951 | * This function finally enables all IOMMUs found in the system after | |
952 | * they have been initialized | |
953 | */ | |
8736197b JR |
954 | static void __init enable_iommus(void) |
955 | { | |
956 | struct amd_iommu *iommu; | |
957 | ||
958 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
959 | iommu_set_exclusion_range(iommu); | |
a80dc3e0 | 960 | iommu_init_msi(iommu); |
8736197b JR |
961 | iommu_enable(iommu); |
962 | } | |
963 | } | |
964 | ||
7441e9cb JR |
965 | /* |
966 | * Suspend/Resume support | |
967 | * disable suspend until real resume implemented | |
968 | */ | |
969 | ||
970 | static int amd_iommu_resume(struct sys_device *dev) | |
971 | { | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
976 | { | |
977 | return -EINVAL; | |
978 | } | |
979 | ||
980 | static struct sysdev_class amd_iommu_sysdev_class = { | |
981 | .name = "amd_iommu", | |
982 | .suspend = amd_iommu_suspend, | |
983 | .resume = amd_iommu_resume, | |
984 | }; | |
985 | ||
986 | static struct sys_device device_amd_iommu = { | |
987 | .id = 0, | |
988 | .cls = &amd_iommu_sysdev_class, | |
989 | }; | |
990 | ||
b65233a9 JR |
991 | /* |
992 | * This is the core init function for AMD IOMMU hardware in the system. | |
993 | * This function is called from the generic x86 DMA layer initialization | |
994 | * code. | |
995 | * | |
996 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
997 | * three times: | |
998 | * | |
999 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1000 | * Upon this information the size of the data structures is | |
1001 | * determined that needs to be allocated. | |
1002 | * | |
1003 | * 2 pass) Initialize the data structures just allocated with the | |
1004 | * information in the ACPI table about available AMD IOMMUs | |
1005 | * in the system. It also maps the PCI devices in the | |
1006 | * system to specific IOMMUs | |
1007 | * | |
1008 | * 3 pass) After the basic data structures are allocated and | |
1009 | * initialized we update them with information about memory | |
1010 | * remapping requirements parsed out of the ACPI table in | |
1011 | * this last pass. | |
1012 | * | |
1013 | * After that the hardware is initialized and ready to go. In the last | |
1014 | * step we do some Linux specific things like registering the driver in | |
1015 | * the dma_ops interface and initializing the suspend/resume support | |
1016 | * functions. Finally it prints some information about AMD IOMMUs and | |
1017 | * the driver state and enables the hardware. | |
1018 | */ | |
fe74c9cf JR |
1019 | int __init amd_iommu_init(void) |
1020 | { | |
1021 | int i, ret = 0; | |
1022 | ||
1023 | ||
8b14518f | 1024 | if (no_iommu) { |
fe74c9cf JR |
1025 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
1026 | return 0; | |
1027 | } | |
1028 | ||
c1cbebee JR |
1029 | if (!amd_iommu_detected) |
1030 | return -ENODEV; | |
1031 | ||
fe74c9cf JR |
1032 | /* |
1033 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1034 | * we need to handle. Upon this information the shared data | |
1035 | * structures for the IOMMUs in the system will be allocated | |
1036 | */ | |
1037 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1038 | return -ENODEV; | |
1039 | ||
c571484e JR |
1040 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1041 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1042 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1043 | |
1044 | ret = -ENOMEM; | |
1045 | ||
1046 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1047 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1048 | get_order(dev_table_size)); |
1049 | if (amd_iommu_dev_table == NULL) | |
1050 | goto out; | |
1051 | ||
1052 | /* | |
1053 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1054 | * IOMMU see for that device | |
1055 | */ | |
1056 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1057 | get_order(alias_table_size)); | |
1058 | if (amd_iommu_alias_table == NULL) | |
1059 | goto free; | |
1060 | ||
1061 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
1062 | amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL, | |
1063 | get_order(rlookup_table_size)); | |
1064 | if (amd_iommu_rlookup_table == NULL) | |
1065 | goto free; | |
1066 | ||
1067 | /* | |
1068 | * Protection Domain table - maps devices to protection domains | |
1069 | * This table has the same size as the rlookup_table | |
1070 | */ | |
5dc8bff0 | 1071 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1072 | get_order(rlookup_table_size)); |
1073 | if (amd_iommu_pd_table == NULL) | |
1074 | goto free; | |
1075 | ||
5dc8bff0 JR |
1076 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1077 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1078 | get_order(MAX_DOMAIN_ID/8)); |
1079 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1080 | goto free; | |
1081 | ||
9f5f5fb3 JR |
1082 | /* init the device table */ |
1083 | init_device_table(); | |
1084 | ||
fe74c9cf | 1085 | /* |
5dc8bff0 | 1086 | * let all alias entries point to itself |
fe74c9cf | 1087 | */ |
3a61ec38 | 1088 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1089 | amd_iommu_alias_table[i] = i; |
1090 | ||
fe74c9cf JR |
1091 | /* |
1092 | * never allocate domain 0 because its used as the non-allocated and | |
1093 | * error value placeholder | |
1094 | */ | |
1095 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1096 | ||
1097 | /* | |
1098 | * now the data structures are allocated and basically initialized | |
1099 | * start the real acpi table scan | |
1100 | */ | |
1101 | ret = -ENODEV; | |
1102 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1103 | goto free; | |
1104 | ||
1105 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1106 | goto free; | |
1107 | ||
129d6aba | 1108 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1109 | if (ret) |
1110 | goto free; | |
1111 | ||
129d6aba | 1112 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1113 | if (ret) |
1114 | goto free; | |
1115 | ||
129d6aba | 1116 | ret = amd_iommu_init_dma_ops(); |
7441e9cb JR |
1117 | if (ret) |
1118 | goto free; | |
1119 | ||
8736197b JR |
1120 | enable_iommus(); |
1121 | ||
fe74c9cf JR |
1122 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
1123 | (1 << (amd_iommu_aperture_order-20))); | |
1124 | ||
1125 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
1126 | if (amd_iommu_isolate) | |
1127 | printk("enabled\n"); | |
1128 | else | |
1129 | printk("disabled\n"); | |
1130 | ||
1c655773 JR |
1131 | if (iommu_fullflush) |
1132 | printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n"); | |
1133 | else | |
1134 | printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n"); | |
1135 | ||
fe74c9cf JR |
1136 | out: |
1137 | return ret; | |
1138 | ||
1139 | free: | |
9a836de0 | 1140 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1); |
fe74c9cf | 1141 | |
9a836de0 JR |
1142 | free_pages((unsigned long)amd_iommu_pd_table, |
1143 | get_order(rlookup_table_size)); | |
fe74c9cf | 1144 | |
9a836de0 JR |
1145 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1146 | get_order(rlookup_table_size)); | |
fe74c9cf | 1147 | |
9a836de0 JR |
1148 | free_pages((unsigned long)amd_iommu_alias_table, |
1149 | get_order(alias_table_size)); | |
fe74c9cf | 1150 | |
9a836de0 JR |
1151 | free_pages((unsigned long)amd_iommu_dev_table, |
1152 | get_order(dev_table_size)); | |
fe74c9cf JR |
1153 | |
1154 | free_iommu_all(); | |
1155 | ||
1156 | free_unity_maps(); | |
1157 | ||
1158 | goto out; | |
1159 | } | |
1160 | ||
b65233a9 JR |
1161 | /**************************************************************************** |
1162 | * | |
1163 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1164 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1165 | * IOMMUs | |
1166 | * | |
1167 | ****************************************************************************/ | |
ae7877de JR |
1168 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1169 | { | |
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | void __init amd_iommu_detect(void) | |
1174 | { | |
299a140d | 1175 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1176 | return; |
1177 | ||
ae7877de JR |
1178 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1179 | iommu_detected = 1; | |
c1cbebee | 1180 | amd_iommu_detected = 1; |
92af4e29 | 1181 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1182 | gart_iommu_aperture_disabled = 1; |
1183 | gart_iommu_aperture = 0; | |
92af4e29 | 1184 | #endif |
ae7877de JR |
1185 | } |
1186 | } | |
1187 | ||
b65233a9 JR |
1188 | /**************************************************************************** |
1189 | * | |
1190 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1191 | * options. | |
1192 | * | |
1193 | ****************************************************************************/ | |
1194 | ||
918ad6c5 JR |
1195 | static int __init parse_amd_iommu_options(char *str) |
1196 | { | |
1197 | for (; *str; ++str) { | |
1c655773 | 1198 | if (strncmp(str, "isolate", 7) == 0) |
918ad6c5 JR |
1199 | amd_iommu_isolate = 1; |
1200 | } | |
1201 | ||
1202 | return 1; | |
1203 | } | |
1204 | ||
1205 | static int __init parse_amd_iommu_size_options(char *str) | |
1206 | { | |
0906372e JR |
1207 | unsigned order = PAGE_SHIFT + get_order(memparse(str, &str)); |
1208 | ||
1209 | if ((order > 24) && (order < 31)) | |
1210 | amd_iommu_aperture_order = order; | |
918ad6c5 JR |
1211 | |
1212 | return 1; | |
1213 | } | |
1214 | ||
1215 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1216 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |