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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
ea1b0d39 | 32 | #include <asm/x86_init.h> |
f6e2e6b6 JR |
33 | |
34 | /* | |
35 | * definitions for the ACPI scanning code | |
36 | */ | |
f6e2e6b6 | 37 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
38 | |
39 | #define ACPI_IVHD_TYPE 0x10 | |
40 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
41 | #define ACPI_IVMD_TYPE 0x21 | |
42 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
43 | ||
44 | #define IVHD_DEV_ALL 0x01 | |
45 | #define IVHD_DEV_SELECT 0x02 | |
46 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
47 | #define IVHD_DEV_RANGE_END 0x04 | |
48 | #define IVHD_DEV_ALIAS 0x42 | |
49 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
50 | #define IVHD_DEV_EXT_SELECT 0x46 | |
51 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
52 | ||
6da7342f JR |
53 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
54 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
55 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
56 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
57 | |
58 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
59 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
60 | ||
61 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
62 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
63 | #define ACPI_DEVFLAG_NMI 0x04 | |
64 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
65 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
66 | #define ACPI_DEVFLAG_LINT0 0x40 | |
67 | #define ACPI_DEVFLAG_LINT1 0x80 | |
68 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
69 | ||
b65233a9 JR |
70 | /* |
71 | * ACPI table definitions | |
72 | * | |
73 | * These data structures are laid over the table to parse the important values | |
74 | * out of it. | |
75 | */ | |
76 | ||
77 | /* | |
78 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
79 | * or more ivhd_entrys. | |
80 | */ | |
f6e2e6b6 JR |
81 | struct ivhd_header { |
82 | u8 type; | |
83 | u8 flags; | |
84 | u16 length; | |
85 | u16 devid; | |
86 | u16 cap_ptr; | |
87 | u64 mmio_phys; | |
88 | u16 pci_seg; | |
89 | u16 info; | |
90 | u32 reserved; | |
91 | } __attribute__((packed)); | |
92 | ||
b65233a9 JR |
93 | /* |
94 | * A device entry describing which devices a specific IOMMU translates and | |
95 | * which requestor ids they use. | |
96 | */ | |
f6e2e6b6 JR |
97 | struct ivhd_entry { |
98 | u8 type; | |
99 | u16 devid; | |
100 | u8 flags; | |
101 | u32 ext; | |
102 | } __attribute__((packed)); | |
103 | ||
b65233a9 JR |
104 | /* |
105 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
106 | * ranges for devices and regions that should be unity mapped. | |
107 | */ | |
f6e2e6b6 JR |
108 | struct ivmd_header { |
109 | u8 type; | |
110 | u8 flags; | |
111 | u16 length; | |
112 | u16 devid; | |
113 | u16 aux; | |
114 | u64 resv; | |
115 | u64 range_start; | |
116 | u64 range_length; | |
117 | } __attribute__((packed)); | |
118 | ||
fefda117 JR |
119 | bool amd_iommu_dump; |
120 | ||
c1cbebee JR |
121 | static int __initdata amd_iommu_detected; |
122 | ||
b65233a9 JR |
123 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
124 | to handle */ | |
2e22847f | 125 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 126 | we find in ACPI */ |
2e8b5696 JR |
127 | #ifdef CONFIG_IOMMU_STRESS |
128 | bool amd_iommu_isolate = false; | |
129 | #else | |
c226f853 JR |
130 | bool amd_iommu_isolate = true; /* if true, device isolation is |
131 | enabled */ | |
2e8b5696 JR |
132 | #endif |
133 | ||
afa9fdc2 | 134 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 135 | |
2e22847f | 136 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 137 | system */ |
928abd25 | 138 | |
b65233a9 JR |
139 | /* |
140 | * Pointer to the device table which is shared by all AMD IOMMUs | |
141 | * it is indexed by the PCI device id or the HT unit id and contains | |
142 | * information about the domain the device belongs to as well as the | |
143 | * page table root pointer. | |
144 | */ | |
928abd25 | 145 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
146 | |
147 | /* | |
148 | * The alias table is a driver specific data structure which contains the | |
149 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
150 | * More than one device can share the same requestor id. | |
151 | */ | |
928abd25 | 152 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
153 | |
154 | /* | |
155 | * The rlookup table is used to find the IOMMU which is responsible | |
156 | * for a specific device. It is also indexed by the PCI device id. | |
157 | */ | |
928abd25 | 158 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
159 | |
160 | /* | |
161 | * The pd table (protection domain table) is used to find the protection domain | |
162 | * data structure a device belongs to. Indexed with the PCI device id too. | |
163 | */ | |
928abd25 | 164 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
165 | |
166 | /* | |
167 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
168 | * to know which ones are already in use. | |
169 | */ | |
928abd25 JR |
170 | unsigned long *amd_iommu_pd_alloc_bitmap; |
171 | ||
b65233a9 JR |
172 | static u32 dev_table_size; /* size of the device table */ |
173 | static u32 alias_table_size; /* size of the alias table */ | |
174 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 175 | |
208ec8c9 JR |
176 | static inline void update_last_devid(u16 devid) |
177 | { | |
178 | if (devid > amd_iommu_last_bdf) | |
179 | amd_iommu_last_bdf = devid; | |
180 | } | |
181 | ||
c571484e JR |
182 | static inline unsigned long tbl_size(int entry_size) |
183 | { | |
184 | unsigned shift = PAGE_SHIFT + | |
421f909c | 185 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
186 | |
187 | return 1UL << shift; | |
188 | } | |
189 | ||
b65233a9 JR |
190 | /**************************************************************************** |
191 | * | |
192 | * AMD IOMMU MMIO register space handling functions | |
193 | * | |
194 | * These functions are used to program the IOMMU device registers in | |
195 | * MMIO space required for that driver. | |
196 | * | |
197 | ****************************************************************************/ | |
3e8064ba | 198 | |
b65233a9 JR |
199 | /* |
200 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
201 | * exclusion range are passed through untranslated | |
202 | */ | |
05f92db9 | 203 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
204 | { |
205 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
206 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
207 | u64 entry; | |
208 | ||
209 | if (!iommu->exclusion_start) | |
210 | return; | |
211 | ||
212 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
213 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
214 | &entry, sizeof(entry)); | |
215 | ||
216 | entry = limit; | |
217 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
218 | &entry, sizeof(entry)); | |
219 | } | |
220 | ||
b65233a9 | 221 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
222 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
223 | { | |
f609891f | 224 | u64 entry; |
b2026aa2 JR |
225 | |
226 | BUG_ON(iommu->mmio_base == NULL); | |
227 | ||
228 | entry = virt_to_phys(amd_iommu_dev_table); | |
229 | entry |= (dev_table_size >> 12) - 1; | |
230 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
231 | &entry, sizeof(entry)); | |
232 | } | |
233 | ||
b65233a9 | 234 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 235 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
236 | { |
237 | u32 ctrl; | |
238 | ||
239 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
240 | ctrl |= (1 << bit); | |
241 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
242 | } | |
243 | ||
ca020711 | 244 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
245 | { |
246 | u32 ctrl; | |
247 | ||
199d0d50 | 248 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
249 | ctrl &= ~(1 << bit); |
250 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
251 | } | |
252 | ||
b65233a9 | 253 | /* Function to enable the hardware */ |
05f92db9 | 254 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 255 | { |
4c6f40d4 | 256 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n", |
a4e267c8 | 257 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 JR |
258 | |
259 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
260 | } |
261 | ||
92ac4320 | 262 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 263 | { |
a8c485bb CW |
264 | /* Disable command buffer */ |
265 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
266 | ||
267 | /* Disable event logging and event interrupts */ | |
268 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
269 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
270 | ||
271 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 272 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
273 | } |
274 | ||
b65233a9 JR |
275 | /* |
276 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
277 | * the system has one. | |
278 | */ | |
6c56747b JR |
279 | static u8 * __init iommu_map_mmio_space(u64 address) |
280 | { | |
281 | u8 *ret; | |
282 | ||
283 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
284 | return NULL; | |
285 | ||
286 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
287 | if (ret != NULL) | |
288 | return ret; | |
289 | ||
290 | release_mem_region(address, MMIO_REGION_LENGTH); | |
291 | ||
292 | return NULL; | |
293 | } | |
294 | ||
295 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
296 | { | |
297 | if (iommu->mmio_base) | |
298 | iounmap(iommu->mmio_base); | |
299 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
300 | } | |
301 | ||
b65233a9 JR |
302 | /**************************************************************************** |
303 | * | |
304 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
305 | * parsing. In this pass we try to find out the highest device id this | |
306 | * code has to handle. Upon this information the size of the shared data | |
307 | * structures is determined later. | |
308 | * | |
309 | ****************************************************************************/ | |
310 | ||
b514e555 JR |
311 | /* |
312 | * This function calculates the length of a given IVHD entry | |
313 | */ | |
314 | static inline int ivhd_entry_length(u8 *ivhd) | |
315 | { | |
316 | return 0x04 << (*ivhd >> 6); | |
317 | } | |
318 | ||
b65233a9 JR |
319 | /* |
320 | * This function reads the last device id the IOMMU has to handle from the PCI | |
321 | * capability header for this IOMMU | |
322 | */ | |
3e8064ba JR |
323 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
324 | { | |
325 | u32 cap; | |
326 | ||
327 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 328 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
b65233a9 JR |
333 | /* |
334 | * After reading the highest device id from the IOMMU PCI capability header | |
335 | * this function looks if there is a higher device id defined in the ACPI table | |
336 | */ | |
3e8064ba JR |
337 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
338 | { | |
339 | u8 *p = (void *)h, *end = (void *)h; | |
340 | struct ivhd_entry *dev; | |
341 | ||
342 | p += sizeof(*h); | |
343 | end += h->length; | |
344 | ||
345 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
346 | PCI_SLOT(h->devid), | |
347 | PCI_FUNC(h->devid), | |
348 | h->cap_ptr); | |
349 | ||
350 | while (p < end) { | |
351 | dev = (struct ivhd_entry *)p; | |
352 | switch (dev->type) { | |
353 | case IVHD_DEV_SELECT: | |
354 | case IVHD_DEV_RANGE_END: | |
355 | case IVHD_DEV_ALIAS: | |
356 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 357 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 358 | update_last_devid(dev->devid); |
3e8064ba JR |
359 | break; |
360 | default: | |
361 | break; | |
362 | } | |
b514e555 | 363 | p += ivhd_entry_length(p); |
3e8064ba JR |
364 | } |
365 | ||
366 | WARN_ON(p != end); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
b65233a9 JR |
371 | /* |
372 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
373 | * id which we need to handle. This is the first of three functions which parse | |
374 | * the ACPI table. So we check the checksum here. | |
375 | */ | |
3e8064ba JR |
376 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
377 | { | |
378 | int i; | |
379 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
380 | struct ivhd_header *h; | |
381 | ||
382 | /* | |
383 | * Validate checksum here so we don't need to do it when | |
384 | * we actually parse the table | |
385 | */ | |
386 | for (i = 0; i < table->length; ++i) | |
387 | checksum += p[i]; | |
388 | if (checksum != 0) | |
389 | /* ACPI table corrupt */ | |
390 | return -ENODEV; | |
391 | ||
392 | p += IVRS_HEADER_LENGTH; | |
393 | ||
394 | end += table->length; | |
395 | while (p < end) { | |
396 | h = (struct ivhd_header *)p; | |
397 | switch (h->type) { | |
398 | case ACPI_IVHD_TYPE: | |
399 | find_last_devid_from_ivhd(h); | |
400 | break; | |
401 | default: | |
402 | break; | |
403 | } | |
404 | p += h->length; | |
405 | } | |
406 | WARN_ON(p != end); | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
b65233a9 JR |
411 | /**************************************************************************** |
412 | * | |
413 | * The following functions belong the the code path which parses the ACPI table | |
414 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
415 | * data structures, initialize the device/alias/rlookup table and also | |
416 | * basically initialize the hardware. | |
417 | * | |
418 | ****************************************************************************/ | |
419 | ||
420 | /* | |
421 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
422 | * write commands to that buffer later and the IOMMU will execute them | |
423 | * asynchronously | |
424 | */ | |
b36ca91e JR |
425 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
426 | { | |
d0312b21 | 427 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 428 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
429 | |
430 | if (cmd_buf == NULL) | |
431 | return NULL; | |
432 | ||
433 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
434 | ||
58492e12 JR |
435 | return cmd_buf; |
436 | } | |
437 | ||
93f1cc67 JR |
438 | /* |
439 | * This function resets the command buffer if the IOMMU stopped fetching | |
440 | * commands from it. | |
441 | */ | |
442 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
443 | { | |
444 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
445 | ||
446 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
447 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
448 | ||
449 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
450 | } | |
451 | ||
58492e12 JR |
452 | /* |
453 | * This function writes the command buffer address to the hardware and | |
454 | * enables it. | |
455 | */ | |
456 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
457 | { | |
458 | u64 entry; | |
459 | ||
460 | BUG_ON(iommu->cmd_buf == NULL); | |
461 | ||
462 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 463 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 464 | |
b36ca91e | 465 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 466 | &entry, sizeof(entry)); |
b36ca91e | 467 | |
93f1cc67 | 468 | amd_iommu_reset_cmd_buffer(iommu); |
b36ca91e JR |
469 | } |
470 | ||
471 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
472 | { | |
23c1713f JR |
473 | free_pages((unsigned long)iommu->cmd_buf, |
474 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
475 | } |
476 | ||
335503e5 JR |
477 | /* allocates the memory where the IOMMU will log its events to */ |
478 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
479 | { | |
335503e5 JR |
480 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
481 | get_order(EVT_BUFFER_SIZE)); | |
482 | ||
483 | if (iommu->evt_buf == NULL) | |
484 | return NULL; | |
485 | ||
1bc6f838 JR |
486 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
487 | ||
58492e12 JR |
488 | return iommu->evt_buf; |
489 | } | |
490 | ||
491 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
492 | { | |
493 | u64 entry; | |
494 | ||
495 | BUG_ON(iommu->evt_buf == NULL); | |
496 | ||
335503e5 | 497 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 498 | |
335503e5 JR |
499 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
500 | &entry, sizeof(entry)); | |
501 | ||
09067207 JR |
502 | /* set head and tail to zero manually */ |
503 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
504 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
505 | ||
58492e12 | 506 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
507 | } |
508 | ||
509 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
510 | { | |
511 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
512 | } | |
513 | ||
b65233a9 | 514 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
515 | static void set_dev_entry_bit(u16 devid, u8 bit) |
516 | { | |
517 | int i = (bit >> 5) & 0x07; | |
518 | int _bit = bit & 0x1f; | |
519 | ||
520 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
521 | } | |
522 | ||
c5cca146 JR |
523 | static int get_dev_entry_bit(u16 devid, u8 bit) |
524 | { | |
525 | int i = (bit >> 5) & 0x07; | |
526 | int _bit = bit & 0x1f; | |
527 | ||
528 | return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit; | |
529 | } | |
530 | ||
531 | ||
532 | void amd_iommu_apply_erratum_63(u16 devid) | |
533 | { | |
534 | int sysmgt; | |
535 | ||
536 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
537 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
538 | ||
539 | if (sysmgt == 0x01) | |
540 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
541 | } | |
542 | ||
5ff4789d JR |
543 | /* Writes the specific IOMMU for a device into the rlookup table */ |
544 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
545 | { | |
546 | amd_iommu_rlookup_table[devid] = iommu; | |
547 | } | |
548 | ||
b65233a9 JR |
549 | /* |
550 | * This function takes the device specific flags read from the ACPI | |
551 | * table and sets up the device table entry with that information | |
552 | */ | |
5ff4789d JR |
553 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
554 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
555 | { |
556 | if (flags & ACPI_DEVFLAG_INITPASS) | |
557 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
558 | if (flags & ACPI_DEVFLAG_EXTINT) | |
559 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
560 | if (flags & ACPI_DEVFLAG_NMI) | |
561 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
562 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
563 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
564 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
565 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
566 | if (flags & ACPI_DEVFLAG_LINT0) | |
567 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
568 | if (flags & ACPI_DEVFLAG_LINT1) | |
569 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 570 | |
c5cca146 JR |
571 | amd_iommu_apply_erratum_63(devid); |
572 | ||
5ff4789d | 573 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
574 | } |
575 | ||
b65233a9 JR |
576 | /* |
577 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
578 | * it | |
579 | */ | |
3566b778 JR |
580 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
581 | { | |
582 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
583 | ||
584 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
585 | return; | |
586 | ||
587 | if (iommu) { | |
b65233a9 JR |
588 | /* |
589 | * We only can configure exclusion ranges per IOMMU, not | |
590 | * per device. But we can enable the exclusion range per | |
591 | * device. This is done here | |
592 | */ | |
3566b778 JR |
593 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
594 | iommu->exclusion_start = m->range_start; | |
595 | iommu->exclusion_length = m->range_length; | |
596 | } | |
597 | } | |
598 | ||
b65233a9 JR |
599 | /* |
600 | * This function reads some important data from the IOMMU PCI space and | |
601 | * initializes the driver data structure with it. It reads the hardware | |
602 | * capabilities and the first/last device entries | |
603 | */ | |
5d0c8e49 JR |
604 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
605 | { | |
5d0c8e49 | 606 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 607 | u32 range, misc; |
5d0c8e49 | 608 | |
3eaf28a1 JR |
609 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
610 | &iommu->cap); | |
611 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
612 | &range); | |
a80dc3e0 JR |
613 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
614 | &misc); | |
5d0c8e49 | 615 | |
d591b0a3 JR |
616 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
617 | MMIO_GET_FD(range)); | |
618 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
619 | MMIO_GET_LD(range)); | |
a80dc3e0 | 620 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
621 | } |
622 | ||
b65233a9 JR |
623 | /* |
624 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
625 | * initializes the hardware and our data structures with it. | |
626 | */ | |
5d0c8e49 JR |
627 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
628 | struct ivhd_header *h) | |
629 | { | |
630 | u8 *p = (u8 *)h; | |
631 | u8 *end = p, flags = 0; | |
632 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
633 | u32 ext_flags = 0; | |
58a3bee5 | 634 | bool alias = false; |
5d0c8e49 JR |
635 | struct ivhd_entry *e; |
636 | ||
637 | /* | |
638 | * First set the recommended feature enable bits from ACPI | |
639 | * into the IOMMU control registers | |
640 | */ | |
6da7342f | 641 | h->flags & IVHD_FLAG_HT_TUN_EN_MASK ? |
5d0c8e49 JR |
642 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : |
643 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
644 | ||
6da7342f | 645 | h->flags & IVHD_FLAG_PASSPW_EN_MASK ? |
5d0c8e49 JR |
646 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : |
647 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
648 | ||
6da7342f | 649 | h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ? |
5d0c8e49 JR |
650 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : |
651 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
652 | ||
6da7342f | 653 | h->flags & IVHD_FLAG_ISOC_EN_MASK ? |
5d0c8e49 JR |
654 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : |
655 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
656 | ||
657 | /* | |
658 | * make IOMMU memory accesses cache coherent | |
659 | */ | |
660 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
661 | ||
662 | /* | |
663 | * Done. Now parse the device entries | |
664 | */ | |
665 | p += sizeof(struct ivhd_header); | |
666 | end += h->length; | |
667 | ||
42a698f4 | 668 | |
5d0c8e49 JR |
669 | while (p < end) { |
670 | e = (struct ivhd_entry *)p; | |
671 | switch (e->type) { | |
672 | case IVHD_DEV_ALL: | |
42a698f4 JR |
673 | |
674 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
675 | " last device %02x:%02x.%x flags: %02x\n", | |
676 | PCI_BUS(iommu->first_device), | |
677 | PCI_SLOT(iommu->first_device), | |
678 | PCI_FUNC(iommu->first_device), | |
679 | PCI_BUS(iommu->last_device), | |
680 | PCI_SLOT(iommu->last_device), | |
681 | PCI_FUNC(iommu->last_device), | |
682 | e->flags); | |
683 | ||
5d0c8e49 JR |
684 | for (dev_i = iommu->first_device; |
685 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
686 | set_dev_entry_from_acpi(iommu, dev_i, |
687 | e->flags, 0); | |
5d0c8e49 JR |
688 | break; |
689 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
690 | |
691 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
692 | "flags: %02x\n", | |
693 | PCI_BUS(e->devid), | |
694 | PCI_SLOT(e->devid), | |
695 | PCI_FUNC(e->devid), | |
696 | e->flags); | |
697 | ||
5d0c8e49 | 698 | devid = e->devid; |
5ff4789d | 699 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
700 | break; |
701 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
702 | |
703 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
704 | "devid: %02x:%02x.%x flags: %02x\n", | |
705 | PCI_BUS(e->devid), | |
706 | PCI_SLOT(e->devid), | |
707 | PCI_FUNC(e->devid), | |
708 | e->flags); | |
709 | ||
5d0c8e49 JR |
710 | devid_start = e->devid; |
711 | flags = e->flags; | |
712 | ext_flags = 0; | |
58a3bee5 | 713 | alias = false; |
5d0c8e49 JR |
714 | break; |
715 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
716 | |
717 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
718 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
719 | PCI_BUS(e->devid), | |
720 | PCI_SLOT(e->devid), | |
721 | PCI_FUNC(e->devid), | |
722 | e->flags, | |
723 | PCI_BUS(e->ext >> 8), | |
724 | PCI_SLOT(e->ext >> 8), | |
725 | PCI_FUNC(e->ext >> 8)); | |
726 | ||
5d0c8e49 JR |
727 | devid = e->devid; |
728 | devid_to = e->ext >> 8; | |
7a6a3a08 | 729 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 730 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
731 | amd_iommu_alias_table[devid] = devid_to; |
732 | break; | |
733 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
734 | |
735 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
736 | "devid: %02x:%02x.%x flags: %02x " | |
737 | "devid_to: %02x:%02x.%x\n", | |
738 | PCI_BUS(e->devid), | |
739 | PCI_SLOT(e->devid), | |
740 | PCI_FUNC(e->devid), | |
741 | e->flags, | |
742 | PCI_BUS(e->ext >> 8), | |
743 | PCI_SLOT(e->ext >> 8), | |
744 | PCI_FUNC(e->ext >> 8)); | |
745 | ||
5d0c8e49 JR |
746 | devid_start = e->devid; |
747 | flags = e->flags; | |
748 | devid_to = e->ext >> 8; | |
749 | ext_flags = 0; | |
58a3bee5 | 750 | alias = true; |
5d0c8e49 JR |
751 | break; |
752 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
753 | |
754 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
755 | "flags: %02x ext: %08x\n", | |
756 | PCI_BUS(e->devid), | |
757 | PCI_SLOT(e->devid), | |
758 | PCI_FUNC(e->devid), | |
759 | e->flags, e->ext); | |
760 | ||
5d0c8e49 | 761 | devid = e->devid; |
5ff4789d JR |
762 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
763 | e->ext); | |
5d0c8e49 JR |
764 | break; |
765 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
766 | |
767 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
768 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
769 | PCI_BUS(e->devid), | |
770 | PCI_SLOT(e->devid), | |
771 | PCI_FUNC(e->devid), | |
772 | e->flags, e->ext); | |
773 | ||
5d0c8e49 JR |
774 | devid_start = e->devid; |
775 | flags = e->flags; | |
776 | ext_flags = e->ext; | |
58a3bee5 | 777 | alias = false; |
5d0c8e49 JR |
778 | break; |
779 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
780 | |
781 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
782 | PCI_BUS(e->devid), | |
783 | PCI_SLOT(e->devid), | |
784 | PCI_FUNC(e->devid)); | |
785 | ||
5d0c8e49 JR |
786 | devid = e->devid; |
787 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 788 | if (alias) { |
5d0c8e49 | 789 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
790 | set_dev_entry_from_acpi(iommu, |
791 | devid_to, flags, ext_flags); | |
792 | } | |
793 | set_dev_entry_from_acpi(iommu, dev_i, | |
794 | flags, ext_flags); | |
5d0c8e49 JR |
795 | } |
796 | break; | |
797 | default: | |
798 | break; | |
799 | } | |
800 | ||
b514e555 | 801 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
802 | } |
803 | } | |
804 | ||
b65233a9 | 805 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
806 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
807 | { | |
808 | u16 i; | |
809 | ||
810 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
811 | set_iommu_for_device(iommu, i); | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
e47d402d JR |
816 | static void __init free_iommu_one(struct amd_iommu *iommu) |
817 | { | |
818 | free_command_buffer(iommu); | |
335503e5 | 819 | free_event_buffer(iommu); |
e47d402d JR |
820 | iommu_unmap_mmio_space(iommu); |
821 | } | |
822 | ||
823 | static void __init free_iommu_all(void) | |
824 | { | |
825 | struct amd_iommu *iommu, *next; | |
826 | ||
3bd22172 | 827 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
828 | list_del(&iommu->list); |
829 | free_iommu_one(iommu); | |
830 | kfree(iommu); | |
831 | } | |
832 | } | |
833 | ||
b65233a9 JR |
834 | /* |
835 | * This function clues the initialization function for one IOMMU | |
836 | * together and also allocates the command buffer and programs the | |
837 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
838 | */ | |
e47d402d JR |
839 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
840 | { | |
841 | spin_lock_init(&iommu->lock); | |
842 | list_add_tail(&iommu->list, &amd_iommu_list); | |
843 | ||
844 | /* | |
845 | * Copy data from ACPI table entry to the iommu struct | |
846 | */ | |
3eaf28a1 JR |
847 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
848 | if (!iommu->dev) | |
849 | return 1; | |
850 | ||
e47d402d | 851 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 852 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
853 | iommu->mmio_phys = h->mmio_phys; |
854 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
855 | if (!iommu->mmio_base) | |
856 | return -ENOMEM; | |
857 | ||
e47d402d JR |
858 | iommu->cmd_buf = alloc_command_buffer(iommu); |
859 | if (!iommu->cmd_buf) | |
860 | return -ENOMEM; | |
861 | ||
335503e5 JR |
862 | iommu->evt_buf = alloc_event_buffer(iommu); |
863 | if (!iommu->evt_buf) | |
864 | return -ENOMEM; | |
865 | ||
a80dc3e0 JR |
866 | iommu->int_enabled = false; |
867 | ||
e47d402d JR |
868 | init_iommu_from_pci(iommu); |
869 | init_iommu_from_acpi(iommu, h); | |
870 | init_iommu_devices(iommu); | |
871 | ||
8a66712b | 872 | return pci_enable_device(iommu->dev); |
e47d402d JR |
873 | } |
874 | ||
b65233a9 JR |
875 | /* |
876 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
877 | * IOMMU structure and initializes it with init_iommu_one() | |
878 | */ | |
e47d402d JR |
879 | static int __init init_iommu_all(struct acpi_table_header *table) |
880 | { | |
881 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
882 | struct ivhd_header *h; | |
883 | struct amd_iommu *iommu; | |
884 | int ret; | |
885 | ||
e47d402d JR |
886 | end += table->length; |
887 | p += IVRS_HEADER_LENGTH; | |
888 | ||
889 | while (p < end) { | |
890 | h = (struct ivhd_header *)p; | |
891 | switch (*p) { | |
892 | case ACPI_IVHD_TYPE: | |
9c72041f | 893 | |
ae908c22 | 894 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
895 | "seg: %d flags: %01x info %04x\n", |
896 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
897 | PCI_FUNC(h->devid), h->cap_ptr, | |
898 | h->pci_seg, h->flags, h->info); | |
899 | DUMP_printk(" mmio-addr: %016llx\n", | |
900 | h->mmio_phys); | |
901 | ||
e47d402d JR |
902 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
903 | if (iommu == NULL) | |
904 | return -ENOMEM; | |
905 | ret = init_iommu_one(iommu, h); | |
906 | if (ret) | |
907 | return ret; | |
908 | break; | |
909 | default: | |
910 | break; | |
911 | } | |
912 | p += h->length; | |
913 | ||
914 | } | |
915 | WARN_ON(p != end); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
a80dc3e0 JR |
920 | /**************************************************************************** |
921 | * | |
922 | * The following functions initialize the MSI interrupts for all IOMMUs | |
923 | * in the system. Its a bit challenging because there could be multiple | |
924 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
925 | * pci_dev. | |
926 | * | |
927 | ****************************************************************************/ | |
928 | ||
a80dc3e0 JR |
929 | static int __init iommu_setup_msi(struct amd_iommu *iommu) |
930 | { | |
931 | int r; | |
a80dc3e0 JR |
932 | |
933 | if (pci_enable_msi(iommu->dev)) | |
934 | return 1; | |
935 | ||
936 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
937 | IRQF_SAMPLE_RANDOM, | |
4c6f40d4 | 938 | "AMD-Vi", |
a80dc3e0 JR |
939 | NULL); |
940 | ||
941 | if (r) { | |
942 | pci_disable_msi(iommu->dev); | |
943 | return 1; | |
944 | } | |
945 | ||
fab6afa3 | 946 | iommu->int_enabled = true; |
58492e12 JR |
947 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
948 | ||
a80dc3e0 JR |
949 | return 0; |
950 | } | |
951 | ||
05f92db9 | 952 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
953 | { |
954 | if (iommu->int_enabled) | |
955 | return 0; | |
956 | ||
d91cecdd | 957 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
958 | return iommu_setup_msi(iommu); |
959 | ||
960 | return 1; | |
961 | } | |
962 | ||
b65233a9 JR |
963 | /**************************************************************************** |
964 | * | |
965 | * The next functions belong to the third pass of parsing the ACPI | |
966 | * table. In this last pass the memory mapping requirements are | |
967 | * gathered (like exclusion and unity mapping reanges). | |
968 | * | |
969 | ****************************************************************************/ | |
970 | ||
be2a022c JR |
971 | static void __init free_unity_maps(void) |
972 | { | |
973 | struct unity_map_entry *entry, *next; | |
974 | ||
975 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
976 | list_del(&entry->list); | |
977 | kfree(entry); | |
978 | } | |
979 | } | |
980 | ||
b65233a9 | 981 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
982 | static int __init init_exclusion_range(struct ivmd_header *m) |
983 | { | |
984 | int i; | |
985 | ||
986 | switch (m->type) { | |
987 | case ACPI_IVMD_TYPE: | |
988 | set_device_exclusion_range(m->devid, m); | |
989 | break; | |
990 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 991 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
992 | set_device_exclusion_range(i, m); |
993 | break; | |
994 | case ACPI_IVMD_TYPE_RANGE: | |
995 | for (i = m->devid; i <= m->aux; ++i) | |
996 | set_device_exclusion_range(i, m); | |
997 | break; | |
998 | default: | |
999 | break; | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
b65233a9 | 1005 | /* called for unity map ACPI definition */ |
be2a022c JR |
1006 | static int __init init_unity_map_range(struct ivmd_header *m) |
1007 | { | |
1008 | struct unity_map_entry *e = 0; | |
02acc43a | 1009 | char *s; |
be2a022c JR |
1010 | |
1011 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1012 | if (e == NULL) | |
1013 | return -ENOMEM; | |
1014 | ||
1015 | switch (m->type) { | |
1016 | default: | |
0bc252f4 JR |
1017 | kfree(e); |
1018 | return 0; | |
be2a022c | 1019 | case ACPI_IVMD_TYPE: |
02acc43a | 1020 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1021 | e->devid_start = e->devid_end = m->devid; |
1022 | break; | |
1023 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1024 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1025 | e->devid_start = 0; |
1026 | e->devid_end = amd_iommu_last_bdf; | |
1027 | break; | |
1028 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1029 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1030 | e->devid_start = m->devid; |
1031 | e->devid_end = m->aux; | |
1032 | break; | |
1033 | } | |
1034 | e->address_start = PAGE_ALIGN(m->range_start); | |
1035 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1036 | e->prot = m->flags >> 1; | |
1037 | ||
02acc43a JR |
1038 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1039 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1040 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1041 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1042 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1043 | e->address_start, e->address_end, m->flags); | |
1044 | ||
be2a022c JR |
1045 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
b65233a9 | 1050 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1051 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1052 | { | |
1053 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1054 | struct ivmd_header *m; | |
1055 | ||
be2a022c JR |
1056 | end += table->length; |
1057 | p += IVRS_HEADER_LENGTH; | |
1058 | ||
1059 | while (p < end) { | |
1060 | m = (struct ivmd_header *)p; | |
1061 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1062 | init_exclusion_range(m); | |
1063 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1064 | init_unity_map_range(m); | |
1065 | ||
1066 | p += m->length; | |
1067 | } | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
9f5f5fb3 JR |
1072 | /* |
1073 | * Init the device table to not allow DMA access for devices and | |
1074 | * suppress all page faults | |
1075 | */ | |
1076 | static void init_device_table(void) | |
1077 | { | |
1078 | u16 devid; | |
1079 | ||
1080 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1081 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1082 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1083 | } |
1084 | } | |
1085 | ||
b65233a9 JR |
1086 | /* |
1087 | * This function finally enables all IOMMUs found in the system after | |
1088 | * they have been initialized | |
1089 | */ | |
05f92db9 | 1090 | static void enable_iommus(void) |
8736197b JR |
1091 | { |
1092 | struct amd_iommu *iommu; | |
1093 | ||
3bd22172 | 1094 | for_each_iommu(iommu) { |
a8c485bb | 1095 | iommu_disable(iommu); |
58492e12 JR |
1096 | iommu_set_device_table(iommu); |
1097 | iommu_enable_command_buffer(iommu); | |
1098 | iommu_enable_event_buffer(iommu); | |
8736197b | 1099 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1100 | iommu_init_msi(iommu); |
8736197b JR |
1101 | iommu_enable(iommu); |
1102 | } | |
1103 | } | |
1104 | ||
92ac4320 JR |
1105 | static void disable_iommus(void) |
1106 | { | |
1107 | struct amd_iommu *iommu; | |
1108 | ||
1109 | for_each_iommu(iommu) | |
1110 | iommu_disable(iommu); | |
1111 | } | |
1112 | ||
7441e9cb JR |
1113 | /* |
1114 | * Suspend/Resume support | |
1115 | * disable suspend until real resume implemented | |
1116 | */ | |
1117 | ||
1118 | static int amd_iommu_resume(struct sys_device *dev) | |
1119 | { | |
736501ee JR |
1120 | /* re-load the hardware */ |
1121 | enable_iommus(); | |
1122 | ||
1123 | /* | |
1124 | * we have to flush after the IOMMUs are enabled because a | |
1125 | * disabled IOMMU will never execute the commands we send | |
1126 | */ | |
736501ee | 1127 | amd_iommu_flush_all_devices(); |
6a047d8b | 1128 | amd_iommu_flush_all_domains(); |
736501ee | 1129 | |
7441e9cb JR |
1130 | return 0; |
1131 | } | |
1132 | ||
1133 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
1134 | { | |
736501ee JR |
1135 | /* disable IOMMUs to go out of the way for BIOS */ |
1136 | disable_iommus(); | |
1137 | ||
1138 | return 0; | |
7441e9cb JR |
1139 | } |
1140 | ||
1141 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1142 | .name = "amd_iommu", | |
1143 | .suspend = amd_iommu_suspend, | |
1144 | .resume = amd_iommu_resume, | |
1145 | }; | |
1146 | ||
1147 | static struct sys_device device_amd_iommu = { | |
1148 | .id = 0, | |
1149 | .cls = &amd_iommu_sysdev_class, | |
1150 | }; | |
1151 | ||
b65233a9 JR |
1152 | /* |
1153 | * This is the core init function for AMD IOMMU hardware in the system. | |
1154 | * This function is called from the generic x86 DMA layer initialization | |
1155 | * code. | |
1156 | * | |
1157 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1158 | * three times: | |
1159 | * | |
1160 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1161 | * Upon this information the size of the data structures is | |
1162 | * determined that needs to be allocated. | |
1163 | * | |
1164 | * 2 pass) Initialize the data structures just allocated with the | |
1165 | * information in the ACPI table about available AMD IOMMUs | |
1166 | * in the system. It also maps the PCI devices in the | |
1167 | * system to specific IOMMUs | |
1168 | * | |
1169 | * 3 pass) After the basic data structures are allocated and | |
1170 | * initialized we update them with information about memory | |
1171 | * remapping requirements parsed out of the ACPI table in | |
1172 | * this last pass. | |
1173 | * | |
1174 | * After that the hardware is initialized and ready to go. In the last | |
1175 | * step we do some Linux specific things like registering the driver in | |
1176 | * the dma_ops interface and initializing the suspend/resume support | |
1177 | * functions. Finally it prints some information about AMD IOMMUs and | |
1178 | * the driver state and enables the hardware. | |
1179 | */ | |
ea1b0d39 | 1180 | static int __init amd_iommu_init(void) |
fe74c9cf JR |
1181 | { |
1182 | int i, ret = 0; | |
1183 | ||
fe74c9cf JR |
1184 | /* |
1185 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1186 | * we need to handle. Upon this information the shared data | |
1187 | * structures for the IOMMUs in the system will be allocated | |
1188 | */ | |
1189 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1190 | return -ENODEV; | |
1191 | ||
c571484e JR |
1192 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1193 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1194 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1195 | |
1196 | ret = -ENOMEM; | |
1197 | ||
1198 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1199 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1200 | get_order(dev_table_size)); |
1201 | if (amd_iommu_dev_table == NULL) | |
1202 | goto out; | |
1203 | ||
1204 | /* | |
1205 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1206 | * IOMMU see for that device | |
1207 | */ | |
1208 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1209 | get_order(alias_table_size)); | |
1210 | if (amd_iommu_alias_table == NULL) | |
1211 | goto free; | |
1212 | ||
1213 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1214 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1215 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1216 | get_order(rlookup_table_size)); |
1217 | if (amd_iommu_rlookup_table == NULL) | |
1218 | goto free; | |
1219 | ||
1220 | /* | |
1221 | * Protection Domain table - maps devices to protection domains | |
1222 | * This table has the same size as the rlookup_table | |
1223 | */ | |
5dc8bff0 | 1224 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1225 | get_order(rlookup_table_size)); |
1226 | if (amd_iommu_pd_table == NULL) | |
1227 | goto free; | |
1228 | ||
5dc8bff0 JR |
1229 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1230 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1231 | get_order(MAX_DOMAIN_ID/8)); |
1232 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1233 | goto free; | |
1234 | ||
9f5f5fb3 JR |
1235 | /* init the device table */ |
1236 | init_device_table(); | |
1237 | ||
fe74c9cf | 1238 | /* |
5dc8bff0 | 1239 | * let all alias entries point to itself |
fe74c9cf | 1240 | */ |
3a61ec38 | 1241 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1242 | amd_iommu_alias_table[i] = i; |
1243 | ||
fe74c9cf JR |
1244 | /* |
1245 | * never allocate domain 0 because its used as the non-allocated and | |
1246 | * error value placeholder | |
1247 | */ | |
1248 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1249 | ||
1250 | /* | |
1251 | * now the data structures are allocated and basically initialized | |
1252 | * start the real acpi table scan | |
1253 | */ | |
1254 | ret = -ENODEV; | |
1255 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1256 | goto free; | |
1257 | ||
1258 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1259 | goto free; | |
1260 | ||
129d6aba | 1261 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1262 | if (ret) |
1263 | goto free; | |
1264 | ||
129d6aba | 1265 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1266 | if (ret) |
1267 | goto free; | |
1268 | ||
4751a951 JR |
1269 | if (iommu_pass_through) |
1270 | ret = amd_iommu_init_passthrough(); | |
1271 | else | |
1272 | ret = amd_iommu_init_dma_ops(); | |
7441e9cb JR |
1273 | if (ret) |
1274 | goto free; | |
1275 | ||
8736197b JR |
1276 | enable_iommus(); |
1277 | ||
4751a951 JR |
1278 | if (iommu_pass_through) |
1279 | goto out; | |
1280 | ||
4c6f40d4 | 1281 | printk(KERN_INFO "AMD-Vi: device isolation "); |
fe74c9cf JR |
1282 | if (amd_iommu_isolate) |
1283 | printk("enabled\n"); | |
1284 | else | |
1285 | printk("disabled\n"); | |
1286 | ||
afa9fdc2 | 1287 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1288 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1289 | else |
4c6f40d4 | 1290 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1291 | |
338bac52 | 1292 | x86_platform.iommu_shutdown = disable_iommus; |
fe74c9cf JR |
1293 | out: |
1294 | return ret; | |
1295 | ||
1296 | free: | |
d58befd3 JR |
1297 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1298 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1299 | |
9a836de0 JR |
1300 | free_pages((unsigned long)amd_iommu_pd_table, |
1301 | get_order(rlookup_table_size)); | |
fe74c9cf | 1302 | |
9a836de0 JR |
1303 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1304 | get_order(rlookup_table_size)); | |
fe74c9cf | 1305 | |
9a836de0 JR |
1306 | free_pages((unsigned long)amd_iommu_alias_table, |
1307 | get_order(alias_table_size)); | |
fe74c9cf | 1308 | |
9a836de0 JR |
1309 | free_pages((unsigned long)amd_iommu_dev_table, |
1310 | get_order(dev_table_size)); | |
fe74c9cf JR |
1311 | |
1312 | free_iommu_all(); | |
1313 | ||
1314 | free_unity_maps(); | |
1315 | ||
1316 | goto out; | |
1317 | } | |
1318 | ||
b65233a9 JR |
1319 | /**************************************************************************** |
1320 | * | |
1321 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1322 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1323 | * IOMMUs | |
1324 | * | |
1325 | ****************************************************************************/ | |
ae7877de JR |
1326 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1327 | { | |
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | void __init amd_iommu_detect(void) | |
1332 | { | |
299a140d | 1333 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1334 | return; |
1335 | ||
ae7877de JR |
1336 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1337 | iommu_detected = 1; | |
c1cbebee | 1338 | amd_iommu_detected = 1; |
ea1b0d39 | 1339 | x86_init.iommu.iommu_init = amd_iommu_init; |
ae7877de JR |
1340 | } |
1341 | } | |
1342 | ||
b65233a9 JR |
1343 | /**************************************************************************** |
1344 | * | |
1345 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1346 | * options. | |
1347 | * | |
1348 | ****************************************************************************/ | |
1349 | ||
fefda117 JR |
1350 | static int __init parse_amd_iommu_dump(char *str) |
1351 | { | |
1352 | amd_iommu_dump = true; | |
1353 | ||
1354 | return 1; | |
1355 | } | |
1356 | ||
918ad6c5 JR |
1357 | static int __init parse_amd_iommu_options(char *str) |
1358 | { | |
1359 | for (; *str; ++str) { | |
1c655773 | 1360 | if (strncmp(str, "isolate", 7) == 0) |
c226f853 | 1361 | amd_iommu_isolate = true; |
e5e1f606 | 1362 | if (strncmp(str, "share", 5) == 0) |
c226f853 | 1363 | amd_iommu_isolate = false; |
695b5676 | 1364 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1365 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1366 | } |
1367 | ||
1368 | return 1; | |
1369 | } | |
1370 | ||
fefda117 | 1371 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1372 | __setup("amd_iommu=", parse_amd_iommu_options); |