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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
f6e2e6b6 JR |
25 | #include <asm/pci-direct.h> |
26 | #include <asm/amd_iommu_types.h> | |
c6da992e | 27 | #include <asm/amd_iommu.h> |
f6e2e6b6 JR |
28 | #include <asm/gart.h> |
29 | ||
30 | /* | |
31 | * definitions for the ACPI scanning code | |
32 | */ | |
f6e2e6b6 JR |
33 | #define DEVID(bus, devfn) (((bus) << 8) | (devfn)) |
34 | #define PCI_BUS(x) (((x) >> 8) & 0xff) | |
35 | #define IVRS_HEADER_LENGTH 48 | |
f6e2e6b6 JR |
36 | |
37 | #define ACPI_IVHD_TYPE 0x10 | |
38 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
39 | #define ACPI_IVMD_TYPE 0x21 | |
40 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
41 | ||
42 | #define IVHD_DEV_ALL 0x01 | |
43 | #define IVHD_DEV_SELECT 0x02 | |
44 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
45 | #define IVHD_DEV_RANGE_END 0x04 | |
46 | #define IVHD_DEV_ALIAS 0x42 | |
47 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
48 | #define IVHD_DEV_EXT_SELECT 0x46 | |
49 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
50 | ||
51 | #define IVHD_FLAG_HT_TUN_EN 0x00 | |
52 | #define IVHD_FLAG_PASSPW_EN 0x01 | |
53 | #define IVHD_FLAG_RESPASSPW_EN 0x02 | |
54 | #define IVHD_FLAG_ISOC_EN 0x03 | |
55 | ||
56 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
57 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
58 | ||
59 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
60 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
61 | #define ACPI_DEVFLAG_NMI 0x04 | |
62 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
63 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
64 | #define ACPI_DEVFLAG_LINT0 0x40 | |
65 | #define ACPI_DEVFLAG_LINT1 0x80 | |
66 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
67 | ||
b65233a9 JR |
68 | /* |
69 | * ACPI table definitions | |
70 | * | |
71 | * These data structures are laid over the table to parse the important values | |
72 | * out of it. | |
73 | */ | |
74 | ||
75 | /* | |
76 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
77 | * or more ivhd_entrys. | |
78 | */ | |
f6e2e6b6 JR |
79 | struct ivhd_header { |
80 | u8 type; | |
81 | u8 flags; | |
82 | u16 length; | |
83 | u16 devid; | |
84 | u16 cap_ptr; | |
85 | u64 mmio_phys; | |
86 | u16 pci_seg; | |
87 | u16 info; | |
88 | u32 reserved; | |
89 | } __attribute__((packed)); | |
90 | ||
b65233a9 JR |
91 | /* |
92 | * A device entry describing which devices a specific IOMMU translates and | |
93 | * which requestor ids they use. | |
94 | */ | |
f6e2e6b6 JR |
95 | struct ivhd_entry { |
96 | u8 type; | |
97 | u16 devid; | |
98 | u8 flags; | |
99 | u32 ext; | |
100 | } __attribute__((packed)); | |
101 | ||
b65233a9 JR |
102 | /* |
103 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
104 | * ranges for devices and regions that should be unity mapped. | |
105 | */ | |
f6e2e6b6 JR |
106 | struct ivmd_header { |
107 | u8 type; | |
108 | u8 flags; | |
109 | u16 length; | |
110 | u16 devid; | |
111 | u16 aux; | |
112 | u64 resv; | |
113 | u64 range_start; | |
114 | u64 range_length; | |
115 | } __attribute__((packed)); | |
116 | ||
c1cbebee JR |
117 | static int __initdata amd_iommu_detected; |
118 | ||
b65233a9 JR |
119 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
120 | to handle */ | |
121 | struct list_head amd_iommu_unity_map; /* a list of required unity mappings | |
122 | we find in ACPI */ | |
123 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
124 | int amd_iommu_isolate; /* if 1, device isolation is enabled */ | |
928abd25 | 125 | |
b65233a9 JR |
126 | struct list_head amd_iommu_list; /* list of all AMD IOMMUs in the |
127 | system */ | |
128 | ||
129 | /* | |
130 | * Pointer to the device table which is shared by all AMD IOMMUs | |
131 | * it is indexed by the PCI device id or the HT unit id and contains | |
132 | * information about the domain the device belongs to as well as the | |
133 | * page table root pointer. | |
134 | */ | |
928abd25 | 135 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
136 | |
137 | /* | |
138 | * The alias table is a driver specific data structure which contains the | |
139 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
140 | * More than one device can share the same requestor id. | |
141 | */ | |
928abd25 | 142 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
143 | |
144 | /* | |
145 | * The rlookup table is used to find the IOMMU which is responsible | |
146 | * for a specific device. It is also indexed by the PCI device id. | |
147 | */ | |
928abd25 | 148 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
149 | |
150 | /* | |
151 | * The pd table (protection domain table) is used to find the protection domain | |
152 | * data structure a device belongs to. Indexed with the PCI device id too. | |
153 | */ | |
928abd25 | 154 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
155 | |
156 | /* | |
157 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
158 | * to know which ones are already in use. | |
159 | */ | |
928abd25 JR |
160 | unsigned long *amd_iommu_pd_alloc_bitmap; |
161 | ||
b65233a9 JR |
162 | static u32 dev_table_size; /* size of the device table */ |
163 | static u32 alias_table_size; /* size of the alias table */ | |
164 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
165 | ||
208ec8c9 JR |
166 | static inline void update_last_devid(u16 devid) |
167 | { | |
168 | if (devid > amd_iommu_last_bdf) | |
169 | amd_iommu_last_bdf = devid; | |
170 | } | |
171 | ||
c571484e JR |
172 | static inline unsigned long tbl_size(int entry_size) |
173 | { | |
174 | unsigned shift = PAGE_SHIFT + | |
175 | get_order(amd_iommu_last_bdf * entry_size); | |
176 | ||
177 | return 1UL << shift; | |
178 | } | |
179 | ||
b65233a9 JR |
180 | /**************************************************************************** |
181 | * | |
182 | * AMD IOMMU MMIO register space handling functions | |
183 | * | |
184 | * These functions are used to program the IOMMU device registers in | |
185 | * MMIO space required for that driver. | |
186 | * | |
187 | ****************************************************************************/ | |
3e8064ba | 188 | |
b65233a9 JR |
189 | /* |
190 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
191 | * exclusion range are passed through untranslated | |
192 | */ | |
b2026aa2 JR |
193 | static void __init iommu_set_exclusion_range(struct amd_iommu *iommu) |
194 | { | |
195 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
196 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
197 | u64 entry; | |
198 | ||
199 | if (!iommu->exclusion_start) | |
200 | return; | |
201 | ||
202 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
203 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
204 | &entry, sizeof(entry)); | |
205 | ||
206 | entry = limit; | |
207 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
208 | &entry, sizeof(entry)); | |
209 | } | |
210 | ||
b65233a9 | 211 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
212 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
213 | { | |
214 | u32 entry; | |
215 | ||
216 | BUG_ON(iommu->mmio_base == NULL); | |
217 | ||
218 | entry = virt_to_phys(amd_iommu_dev_table); | |
219 | entry |= (dev_table_size >> 12) - 1; | |
220 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
221 | &entry, sizeof(entry)); | |
222 | } | |
223 | ||
b65233a9 | 224 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
b2026aa2 JR |
225 | static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
226 | { | |
227 | u32 ctrl; | |
228 | ||
229 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
230 | ctrl |= (1 << bit); | |
231 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
232 | } | |
233 | ||
234 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
235 | { | |
236 | u32 ctrl; | |
237 | ||
238 | ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
239 | ctrl &= ~(1 << bit); | |
240 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
241 | } | |
242 | ||
b65233a9 | 243 | /* Function to enable the hardware */ |
b2026aa2 JR |
244 | void __init iommu_enable(struct amd_iommu *iommu) |
245 | { | |
b2026aa2 JR |
246 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at "); |
247 | print_devid(iommu->devid, 0); | |
248 | printk(" cap 0x%hx\n", iommu->cap_ptr); | |
249 | ||
250 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
251 | } |
252 | ||
b65233a9 JR |
253 | /* |
254 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
255 | * the system has one. | |
256 | */ | |
6c56747b JR |
257 | static u8 * __init iommu_map_mmio_space(u64 address) |
258 | { | |
259 | u8 *ret; | |
260 | ||
261 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
262 | return NULL; | |
263 | ||
264 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
265 | if (ret != NULL) | |
266 | return ret; | |
267 | ||
268 | release_mem_region(address, MMIO_REGION_LENGTH); | |
269 | ||
270 | return NULL; | |
271 | } | |
272 | ||
273 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
274 | { | |
275 | if (iommu->mmio_base) | |
276 | iounmap(iommu->mmio_base); | |
277 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
278 | } | |
279 | ||
b65233a9 JR |
280 | /**************************************************************************** |
281 | * | |
282 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
283 | * parsing. In this pass we try to find out the highest device id this | |
284 | * code has to handle. Upon this information the size of the shared data | |
285 | * structures is determined later. | |
286 | * | |
287 | ****************************************************************************/ | |
288 | ||
289 | /* | |
290 | * This function reads the last device id the IOMMU has to handle from the PCI | |
291 | * capability header for this IOMMU | |
292 | */ | |
3e8064ba JR |
293 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
294 | { | |
295 | u32 cap; | |
296 | ||
297 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
208ec8c9 | 298 | update_last_devid(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
299 | |
300 | return 0; | |
301 | } | |
302 | ||
b65233a9 JR |
303 | /* |
304 | * After reading the highest device id from the IOMMU PCI capability header | |
305 | * this function looks if there is a higher device id defined in the ACPI table | |
306 | */ | |
3e8064ba JR |
307 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
308 | { | |
309 | u8 *p = (void *)h, *end = (void *)h; | |
310 | struct ivhd_entry *dev; | |
311 | ||
312 | p += sizeof(*h); | |
313 | end += h->length; | |
314 | ||
315 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
316 | PCI_SLOT(h->devid), | |
317 | PCI_FUNC(h->devid), | |
318 | h->cap_ptr); | |
319 | ||
320 | while (p < end) { | |
321 | dev = (struct ivhd_entry *)p; | |
322 | switch (dev->type) { | |
323 | case IVHD_DEV_SELECT: | |
324 | case IVHD_DEV_RANGE_END: | |
325 | case IVHD_DEV_ALIAS: | |
326 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 327 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 328 | update_last_devid(dev->devid); |
3e8064ba JR |
329 | break; |
330 | default: | |
331 | break; | |
332 | } | |
333 | p += 0x04 << (*p >> 6); | |
334 | } | |
335 | ||
336 | WARN_ON(p != end); | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
b65233a9 JR |
341 | /* |
342 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
343 | * id which we need to handle. This is the first of three functions which parse | |
344 | * the ACPI table. So we check the checksum here. | |
345 | */ | |
3e8064ba JR |
346 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
347 | { | |
348 | int i; | |
349 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
350 | struct ivhd_header *h; | |
351 | ||
352 | /* | |
353 | * Validate checksum here so we don't need to do it when | |
354 | * we actually parse the table | |
355 | */ | |
356 | for (i = 0; i < table->length; ++i) | |
357 | checksum += p[i]; | |
358 | if (checksum != 0) | |
359 | /* ACPI table corrupt */ | |
360 | return -ENODEV; | |
361 | ||
362 | p += IVRS_HEADER_LENGTH; | |
363 | ||
364 | end += table->length; | |
365 | while (p < end) { | |
366 | h = (struct ivhd_header *)p; | |
367 | switch (h->type) { | |
368 | case ACPI_IVHD_TYPE: | |
369 | find_last_devid_from_ivhd(h); | |
370 | break; | |
371 | default: | |
372 | break; | |
373 | } | |
374 | p += h->length; | |
375 | } | |
376 | WARN_ON(p != end); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
b65233a9 JR |
381 | /**************************************************************************** |
382 | * | |
383 | * The following functions belong the the code path which parses the ACPI table | |
384 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
385 | * data structures, initialize the device/alias/rlookup table and also | |
386 | * basically initialize the hardware. | |
387 | * | |
388 | ****************************************************************************/ | |
389 | ||
390 | /* | |
391 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
392 | * write commands to that buffer later and the IOMMU will execute them | |
393 | * asynchronously | |
394 | */ | |
b36ca91e JR |
395 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
396 | { | |
397 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL, | |
398 | get_order(CMD_BUFFER_SIZE)); | |
399 | u64 entry = 0; | |
400 | ||
401 | if (cmd_buf == NULL) | |
402 | return NULL; | |
403 | ||
404 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
405 | ||
406 | memset(cmd_buf, 0, CMD_BUFFER_SIZE); | |
407 | ||
408 | entry = (u64)virt_to_phys(cmd_buf); | |
409 | entry |= MMIO_CMD_SIZE_512; | |
410 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, | |
411 | &entry, sizeof(entry)); | |
412 | ||
413 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
414 | ||
415 | return cmd_buf; | |
416 | } | |
417 | ||
418 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
419 | { | |
9a836de0 | 420 | free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
421 | } |
422 | ||
b65233a9 | 423 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
424 | static void set_dev_entry_bit(u16 devid, u8 bit) |
425 | { | |
426 | int i = (bit >> 5) & 0x07; | |
427 | int _bit = bit & 0x1f; | |
428 | ||
429 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
430 | } | |
431 | ||
b65233a9 JR |
432 | /* |
433 | * This function takes the device specific flags read from the ACPI | |
434 | * table and sets up the device table entry with that information | |
435 | */ | |
3566b778 JR |
436 | static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags) |
437 | { | |
438 | if (flags & ACPI_DEVFLAG_INITPASS) | |
439 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
440 | if (flags & ACPI_DEVFLAG_EXTINT) | |
441 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
442 | if (flags & ACPI_DEVFLAG_NMI) | |
443 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
444 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
445 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
446 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
447 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
448 | if (flags & ACPI_DEVFLAG_LINT0) | |
449 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
450 | if (flags & ACPI_DEVFLAG_LINT1) | |
451 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
452 | } | |
453 | ||
b65233a9 | 454 | /* Writes the specific IOMMU for a device into the rlookup table */ |
3566b778 JR |
455 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) |
456 | { | |
457 | amd_iommu_rlookup_table[devid] = iommu; | |
458 | } | |
459 | ||
b65233a9 JR |
460 | /* |
461 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
462 | * it | |
463 | */ | |
3566b778 JR |
464 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
465 | { | |
466 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
467 | ||
468 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
469 | return; | |
470 | ||
471 | if (iommu) { | |
b65233a9 JR |
472 | /* |
473 | * We only can configure exclusion ranges per IOMMU, not | |
474 | * per device. But we can enable the exclusion range per | |
475 | * device. This is done here | |
476 | */ | |
3566b778 JR |
477 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
478 | iommu->exclusion_start = m->range_start; | |
479 | iommu->exclusion_length = m->range_length; | |
480 | } | |
481 | } | |
482 | ||
b65233a9 JR |
483 | /* |
484 | * This function reads some important data from the IOMMU PCI space and | |
485 | * initializes the driver data structure with it. It reads the hardware | |
486 | * capabilities and the first/last device entries | |
487 | */ | |
5d0c8e49 JR |
488 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
489 | { | |
490 | int bus = PCI_BUS(iommu->devid); | |
491 | int dev = PCI_SLOT(iommu->devid); | |
492 | int fn = PCI_FUNC(iommu->devid); | |
493 | int cap_ptr = iommu->cap_ptr; | |
494 | u32 range; | |
495 | ||
496 | iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET); | |
497 | ||
498 | range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
499 | iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range)); | |
500 | iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range)); | |
501 | } | |
502 | ||
b65233a9 JR |
503 | /* |
504 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
505 | * initializes the hardware and our data structures with it. | |
506 | */ | |
5d0c8e49 JR |
507 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
508 | struct ivhd_header *h) | |
509 | { | |
510 | u8 *p = (u8 *)h; | |
511 | u8 *end = p, flags = 0; | |
512 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
513 | u32 ext_flags = 0; | |
514 | bool alias = 0; | |
515 | struct ivhd_entry *e; | |
516 | ||
517 | /* | |
518 | * First set the recommended feature enable bits from ACPI | |
519 | * into the IOMMU control registers | |
520 | */ | |
521 | h->flags & IVHD_FLAG_HT_TUN_EN ? | |
522 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
523 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
524 | ||
525 | h->flags & IVHD_FLAG_PASSPW_EN ? | |
526 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
527 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
528 | ||
529 | h->flags & IVHD_FLAG_RESPASSPW_EN ? | |
530 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
531 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
532 | ||
533 | h->flags & IVHD_FLAG_ISOC_EN ? | |
534 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
535 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
536 | ||
537 | /* | |
538 | * make IOMMU memory accesses cache coherent | |
539 | */ | |
540 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
541 | ||
542 | /* | |
543 | * Done. Now parse the device entries | |
544 | */ | |
545 | p += sizeof(struct ivhd_header); | |
546 | end += h->length; | |
547 | ||
548 | while (p < end) { | |
549 | e = (struct ivhd_entry *)p; | |
550 | switch (e->type) { | |
551 | case IVHD_DEV_ALL: | |
552 | for (dev_i = iommu->first_device; | |
553 | dev_i <= iommu->last_device; ++dev_i) | |
554 | set_dev_entry_from_acpi(dev_i, e->flags, 0); | |
555 | break; | |
556 | case IVHD_DEV_SELECT: | |
557 | devid = e->devid; | |
558 | set_dev_entry_from_acpi(devid, e->flags, 0); | |
559 | break; | |
560 | case IVHD_DEV_SELECT_RANGE_START: | |
561 | devid_start = e->devid; | |
562 | flags = e->flags; | |
563 | ext_flags = 0; | |
564 | alias = 0; | |
565 | break; | |
566 | case IVHD_DEV_ALIAS: | |
567 | devid = e->devid; | |
568 | devid_to = e->ext >> 8; | |
569 | set_dev_entry_from_acpi(devid, e->flags, 0); | |
570 | amd_iommu_alias_table[devid] = devid_to; | |
571 | break; | |
572 | case IVHD_DEV_ALIAS_RANGE: | |
573 | devid_start = e->devid; | |
574 | flags = e->flags; | |
575 | devid_to = e->ext >> 8; | |
576 | ext_flags = 0; | |
577 | alias = 1; | |
578 | break; | |
579 | case IVHD_DEV_EXT_SELECT: | |
580 | devid = e->devid; | |
581 | set_dev_entry_from_acpi(devid, e->flags, e->ext); | |
582 | break; | |
583 | case IVHD_DEV_EXT_SELECT_RANGE: | |
584 | devid_start = e->devid; | |
585 | flags = e->flags; | |
586 | ext_flags = e->ext; | |
587 | alias = 0; | |
588 | break; | |
589 | case IVHD_DEV_RANGE_END: | |
590 | devid = e->devid; | |
591 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
592 | if (alias) | |
593 | amd_iommu_alias_table[dev_i] = devid_to; | |
594 | set_dev_entry_from_acpi( | |
595 | amd_iommu_alias_table[dev_i], | |
596 | flags, ext_flags); | |
597 | } | |
598 | break; | |
599 | default: | |
600 | break; | |
601 | } | |
602 | ||
603 | p += 0x04 << (e->type >> 6); | |
604 | } | |
605 | } | |
606 | ||
b65233a9 | 607 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
608 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
609 | { | |
610 | u16 i; | |
611 | ||
612 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
613 | set_iommu_for_device(iommu, i); | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
e47d402d JR |
618 | static void __init free_iommu_one(struct amd_iommu *iommu) |
619 | { | |
620 | free_command_buffer(iommu); | |
621 | iommu_unmap_mmio_space(iommu); | |
622 | } | |
623 | ||
624 | static void __init free_iommu_all(void) | |
625 | { | |
626 | struct amd_iommu *iommu, *next; | |
627 | ||
628 | list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) { | |
629 | list_del(&iommu->list); | |
630 | free_iommu_one(iommu); | |
631 | kfree(iommu); | |
632 | } | |
633 | } | |
634 | ||
b65233a9 JR |
635 | /* |
636 | * This function clues the initialization function for one IOMMU | |
637 | * together and also allocates the command buffer and programs the | |
638 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
639 | */ | |
e47d402d JR |
640 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
641 | { | |
642 | spin_lock_init(&iommu->lock); | |
643 | list_add_tail(&iommu->list, &amd_iommu_list); | |
644 | ||
645 | /* | |
646 | * Copy data from ACPI table entry to the iommu struct | |
647 | */ | |
648 | iommu->devid = h->devid; | |
649 | iommu->cap_ptr = h->cap_ptr; | |
650 | iommu->mmio_phys = h->mmio_phys; | |
651 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
652 | if (!iommu->mmio_base) | |
653 | return -ENOMEM; | |
654 | ||
655 | iommu_set_device_table(iommu); | |
656 | iommu->cmd_buf = alloc_command_buffer(iommu); | |
657 | if (!iommu->cmd_buf) | |
658 | return -ENOMEM; | |
659 | ||
660 | init_iommu_from_pci(iommu); | |
661 | init_iommu_from_acpi(iommu, h); | |
662 | init_iommu_devices(iommu); | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
b65233a9 JR |
667 | /* |
668 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
669 | * IOMMU structure and initializes it with init_iommu_one() | |
670 | */ | |
e47d402d JR |
671 | static int __init init_iommu_all(struct acpi_table_header *table) |
672 | { | |
673 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
674 | struct ivhd_header *h; | |
675 | struct amd_iommu *iommu; | |
676 | int ret; | |
677 | ||
678 | INIT_LIST_HEAD(&amd_iommu_list); | |
679 | ||
680 | end += table->length; | |
681 | p += IVRS_HEADER_LENGTH; | |
682 | ||
683 | while (p < end) { | |
684 | h = (struct ivhd_header *)p; | |
685 | switch (*p) { | |
686 | case ACPI_IVHD_TYPE: | |
687 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
688 | if (iommu == NULL) | |
689 | return -ENOMEM; | |
690 | ret = init_iommu_one(iommu, h); | |
691 | if (ret) | |
692 | return ret; | |
693 | break; | |
694 | default: | |
695 | break; | |
696 | } | |
697 | p += h->length; | |
698 | ||
699 | } | |
700 | WARN_ON(p != end); | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
b65233a9 JR |
705 | /**************************************************************************** |
706 | * | |
707 | * The next functions belong to the third pass of parsing the ACPI | |
708 | * table. In this last pass the memory mapping requirements are | |
709 | * gathered (like exclusion and unity mapping reanges). | |
710 | * | |
711 | ****************************************************************************/ | |
712 | ||
be2a022c JR |
713 | static void __init free_unity_maps(void) |
714 | { | |
715 | struct unity_map_entry *entry, *next; | |
716 | ||
717 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
718 | list_del(&entry->list); | |
719 | kfree(entry); | |
720 | } | |
721 | } | |
722 | ||
b65233a9 | 723 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
724 | static int __init init_exclusion_range(struct ivmd_header *m) |
725 | { | |
726 | int i; | |
727 | ||
728 | switch (m->type) { | |
729 | case ACPI_IVMD_TYPE: | |
730 | set_device_exclusion_range(m->devid, m); | |
731 | break; | |
732 | case ACPI_IVMD_TYPE_ALL: | |
733 | for (i = 0; i < amd_iommu_last_bdf; ++i) | |
734 | set_device_exclusion_range(i, m); | |
735 | break; | |
736 | case ACPI_IVMD_TYPE_RANGE: | |
737 | for (i = m->devid; i <= m->aux; ++i) | |
738 | set_device_exclusion_range(i, m); | |
739 | break; | |
740 | default: | |
741 | break; | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
b65233a9 | 747 | /* called for unity map ACPI definition */ |
be2a022c JR |
748 | static int __init init_unity_map_range(struct ivmd_header *m) |
749 | { | |
750 | struct unity_map_entry *e = 0; | |
751 | ||
752 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
753 | if (e == NULL) | |
754 | return -ENOMEM; | |
755 | ||
756 | switch (m->type) { | |
757 | default: | |
758 | case ACPI_IVMD_TYPE: | |
759 | e->devid_start = e->devid_end = m->devid; | |
760 | break; | |
761 | case ACPI_IVMD_TYPE_ALL: | |
762 | e->devid_start = 0; | |
763 | e->devid_end = amd_iommu_last_bdf; | |
764 | break; | |
765 | case ACPI_IVMD_TYPE_RANGE: | |
766 | e->devid_start = m->devid; | |
767 | e->devid_end = m->aux; | |
768 | break; | |
769 | } | |
770 | e->address_start = PAGE_ALIGN(m->range_start); | |
771 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
772 | e->prot = m->flags >> 1; | |
773 | ||
774 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
b65233a9 | 779 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
780 | static int __init init_memory_definitions(struct acpi_table_header *table) |
781 | { | |
782 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
783 | struct ivmd_header *m; | |
784 | ||
785 | INIT_LIST_HEAD(&amd_iommu_unity_map); | |
786 | ||
787 | end += table->length; | |
788 | p += IVRS_HEADER_LENGTH; | |
789 | ||
790 | while (p < end) { | |
791 | m = (struct ivmd_header *)p; | |
792 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
793 | init_exclusion_range(m); | |
794 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
795 | init_unity_map_range(m); | |
796 | ||
797 | p += m->length; | |
798 | } | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
b65233a9 JR |
803 | /* |
804 | * This function finally enables all IOMMUs found in the system after | |
805 | * they have been initialized | |
806 | */ | |
8736197b JR |
807 | static void __init enable_iommus(void) |
808 | { | |
809 | struct amd_iommu *iommu; | |
810 | ||
811 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
812 | iommu_set_exclusion_range(iommu); | |
813 | iommu_enable(iommu); | |
814 | } | |
815 | } | |
816 | ||
7441e9cb JR |
817 | /* |
818 | * Suspend/Resume support | |
819 | * disable suspend until real resume implemented | |
820 | */ | |
821 | ||
822 | static int amd_iommu_resume(struct sys_device *dev) | |
823 | { | |
824 | return 0; | |
825 | } | |
826 | ||
827 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
828 | { | |
829 | return -EINVAL; | |
830 | } | |
831 | ||
832 | static struct sysdev_class amd_iommu_sysdev_class = { | |
833 | .name = "amd_iommu", | |
834 | .suspend = amd_iommu_suspend, | |
835 | .resume = amd_iommu_resume, | |
836 | }; | |
837 | ||
838 | static struct sys_device device_amd_iommu = { | |
839 | .id = 0, | |
840 | .cls = &amd_iommu_sysdev_class, | |
841 | }; | |
842 | ||
b65233a9 JR |
843 | /* |
844 | * This is the core init function for AMD IOMMU hardware in the system. | |
845 | * This function is called from the generic x86 DMA layer initialization | |
846 | * code. | |
847 | * | |
848 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
849 | * three times: | |
850 | * | |
851 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
852 | * Upon this information the size of the data structures is | |
853 | * determined that needs to be allocated. | |
854 | * | |
855 | * 2 pass) Initialize the data structures just allocated with the | |
856 | * information in the ACPI table about available AMD IOMMUs | |
857 | * in the system. It also maps the PCI devices in the | |
858 | * system to specific IOMMUs | |
859 | * | |
860 | * 3 pass) After the basic data structures are allocated and | |
861 | * initialized we update them with information about memory | |
862 | * remapping requirements parsed out of the ACPI table in | |
863 | * this last pass. | |
864 | * | |
865 | * After that the hardware is initialized and ready to go. In the last | |
866 | * step we do some Linux specific things like registering the driver in | |
867 | * the dma_ops interface and initializing the suspend/resume support | |
868 | * functions. Finally it prints some information about AMD IOMMUs and | |
869 | * the driver state and enables the hardware. | |
870 | */ | |
fe74c9cf JR |
871 | int __init amd_iommu_init(void) |
872 | { | |
873 | int i, ret = 0; | |
874 | ||
875 | ||
8b14518f | 876 | if (no_iommu) { |
fe74c9cf JR |
877 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
878 | return 0; | |
879 | } | |
880 | ||
c1cbebee JR |
881 | if (!amd_iommu_detected) |
882 | return -ENODEV; | |
883 | ||
fe74c9cf JR |
884 | /* |
885 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
886 | * we need to handle. Upon this information the shared data | |
887 | * structures for the IOMMUs in the system will be allocated | |
888 | */ | |
889 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
890 | return -ENODEV; | |
891 | ||
c571484e JR |
892 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
893 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
894 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
895 | |
896 | ret = -ENOMEM; | |
897 | ||
898 | /* Device table - directly used by all IOMMUs */ | |
899 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL, | |
900 | get_order(dev_table_size)); | |
901 | if (amd_iommu_dev_table == NULL) | |
902 | goto out; | |
903 | ||
904 | /* | |
905 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
906 | * IOMMU see for that device | |
907 | */ | |
908 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
909 | get_order(alias_table_size)); | |
910 | if (amd_iommu_alias_table == NULL) | |
911 | goto free; | |
912 | ||
913 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
914 | amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL, | |
915 | get_order(rlookup_table_size)); | |
916 | if (amd_iommu_rlookup_table == NULL) | |
917 | goto free; | |
918 | ||
919 | /* | |
920 | * Protection Domain table - maps devices to protection domains | |
921 | * This table has the same size as the rlookup_table | |
922 | */ | |
923 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL, | |
924 | get_order(rlookup_table_size)); | |
925 | if (amd_iommu_pd_table == NULL) | |
926 | goto free; | |
927 | ||
928 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(GFP_KERNEL, | |
929 | get_order(MAX_DOMAIN_ID/8)); | |
930 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
931 | goto free; | |
932 | ||
933 | /* | |
934 | * memory is allocated now; initialize the device table with all zeroes | |
935 | * and let all alias entries point to itself | |
936 | */ | |
937 | memset(amd_iommu_dev_table, 0, dev_table_size); | |
938 | for (i = 0; i < amd_iommu_last_bdf; ++i) | |
939 | amd_iommu_alias_table[i] = i; | |
940 | ||
941 | memset(amd_iommu_pd_table, 0, rlookup_table_size); | |
942 | memset(amd_iommu_pd_alloc_bitmap, 0, MAX_DOMAIN_ID / 8); | |
943 | ||
944 | /* | |
945 | * never allocate domain 0 because its used as the non-allocated and | |
946 | * error value placeholder | |
947 | */ | |
948 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
949 | ||
950 | /* | |
951 | * now the data structures are allocated and basically initialized | |
952 | * start the real acpi table scan | |
953 | */ | |
954 | ret = -ENODEV; | |
955 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
956 | goto free; | |
957 | ||
958 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
959 | goto free; | |
960 | ||
8736197b JR |
961 | ret = amd_iommu_init_dma_ops(); |
962 | if (ret) | |
963 | goto free; | |
964 | ||
7441e9cb JR |
965 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
966 | if (ret) | |
967 | goto free; | |
968 | ||
969 | ret = sysdev_register(&device_amd_iommu); | |
970 | if (ret) | |
971 | goto free; | |
972 | ||
8736197b JR |
973 | enable_iommus(); |
974 | ||
fe74c9cf JR |
975 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
976 | (1 << (amd_iommu_aperture_order-20))); | |
977 | ||
978 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
979 | if (amd_iommu_isolate) | |
980 | printk("enabled\n"); | |
981 | else | |
982 | printk("disabled\n"); | |
983 | ||
984 | out: | |
985 | return ret; | |
986 | ||
987 | free: | |
9a836de0 | 988 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1); |
fe74c9cf | 989 | |
9a836de0 JR |
990 | free_pages((unsigned long)amd_iommu_pd_table, |
991 | get_order(rlookup_table_size)); | |
fe74c9cf | 992 | |
9a836de0 JR |
993 | free_pages((unsigned long)amd_iommu_rlookup_table, |
994 | get_order(rlookup_table_size)); | |
fe74c9cf | 995 | |
9a836de0 JR |
996 | free_pages((unsigned long)amd_iommu_alias_table, |
997 | get_order(alias_table_size)); | |
fe74c9cf | 998 | |
9a836de0 JR |
999 | free_pages((unsigned long)amd_iommu_dev_table, |
1000 | get_order(dev_table_size)); | |
fe74c9cf JR |
1001 | |
1002 | free_iommu_all(); | |
1003 | ||
1004 | free_unity_maps(); | |
1005 | ||
1006 | goto out; | |
1007 | } | |
1008 | ||
b65233a9 JR |
1009 | /**************************************************************************** |
1010 | * | |
1011 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1012 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1013 | * IOMMUs | |
1014 | * | |
1015 | ****************************************************************************/ | |
ae7877de JR |
1016 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1017 | { | |
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | void __init amd_iommu_detect(void) | |
1022 | { | |
299a140d | 1023 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1024 | return; |
1025 | ||
ae7877de JR |
1026 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1027 | iommu_detected = 1; | |
c1cbebee | 1028 | amd_iommu_detected = 1; |
92af4e29 | 1029 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1030 | gart_iommu_aperture_disabled = 1; |
1031 | gart_iommu_aperture = 0; | |
92af4e29 | 1032 | #endif |
ae7877de JR |
1033 | } |
1034 | } | |
1035 | ||
b65233a9 JR |
1036 | /**************************************************************************** |
1037 | * | |
1038 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1039 | * options. | |
1040 | * | |
1041 | ****************************************************************************/ | |
1042 | ||
918ad6c5 JR |
1043 | static int __init parse_amd_iommu_options(char *str) |
1044 | { | |
1045 | for (; *str; ++str) { | |
918ad6c5 JR |
1046 | if (strcmp(str, "isolate") == 0) |
1047 | amd_iommu_isolate = 1; | |
1048 | } | |
1049 | ||
1050 | return 1; | |
1051 | } | |
1052 | ||
1053 | static int __init parse_amd_iommu_size_options(char *str) | |
1054 | { | |
1055 | for (; *str; ++str) { | |
1056 | if (strcmp(str, "32M") == 0) | |
1057 | amd_iommu_aperture_order = 25; | |
1058 | if (strcmp(str, "64M") == 0) | |
1059 | amd_iommu_aperture_order = 26; | |
1060 | if (strcmp(str, "128M") == 0) | |
1061 | amd_iommu_aperture_order = 27; | |
1062 | if (strcmp(str, "256M") == 0) | |
1063 | amd_iommu_aperture_order = 28; | |
1064 | if (strcmp(str, "512M") == 0) | |
1065 | amd_iommu_aperture_order = 29; | |
1066 | if (strcmp(str, "1G") == 0) | |
1067 | amd_iommu_aperture_order = 30; | |
1068 | } | |
1069 | ||
1070 | return 1; | |
1071 | } | |
1072 | ||
1073 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1074 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |