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f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
f6e2e6b6 JR |
32 | |
33 | /* | |
34 | * definitions for the ACPI scanning code | |
35 | */ | |
f6e2e6b6 | 36 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
37 | |
38 | #define ACPI_IVHD_TYPE 0x10 | |
39 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
40 | #define ACPI_IVMD_TYPE 0x21 | |
41 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
42 | ||
43 | #define IVHD_DEV_ALL 0x01 | |
44 | #define IVHD_DEV_SELECT 0x02 | |
45 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
46 | #define IVHD_DEV_RANGE_END 0x04 | |
47 | #define IVHD_DEV_ALIAS 0x42 | |
48 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
49 | #define IVHD_DEV_EXT_SELECT 0x46 | |
50 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
51 | ||
6da7342f JR |
52 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
53 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
54 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
55 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
56 | |
57 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
58 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
59 | ||
60 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
61 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
62 | #define ACPI_DEVFLAG_NMI 0x04 | |
63 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
64 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
65 | #define ACPI_DEVFLAG_LINT0 0x40 | |
66 | #define ACPI_DEVFLAG_LINT1 0x80 | |
67 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
68 | ||
b65233a9 JR |
69 | /* |
70 | * ACPI table definitions | |
71 | * | |
72 | * These data structures are laid over the table to parse the important values | |
73 | * out of it. | |
74 | */ | |
75 | ||
76 | /* | |
77 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
78 | * or more ivhd_entrys. | |
79 | */ | |
f6e2e6b6 JR |
80 | struct ivhd_header { |
81 | u8 type; | |
82 | u8 flags; | |
83 | u16 length; | |
84 | u16 devid; | |
85 | u16 cap_ptr; | |
86 | u64 mmio_phys; | |
87 | u16 pci_seg; | |
88 | u16 info; | |
89 | u32 reserved; | |
90 | } __attribute__((packed)); | |
91 | ||
b65233a9 JR |
92 | /* |
93 | * A device entry describing which devices a specific IOMMU translates and | |
94 | * which requestor ids they use. | |
95 | */ | |
f6e2e6b6 JR |
96 | struct ivhd_entry { |
97 | u8 type; | |
98 | u16 devid; | |
99 | u8 flags; | |
100 | u32 ext; | |
101 | } __attribute__((packed)); | |
102 | ||
b65233a9 JR |
103 | /* |
104 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
105 | * ranges for devices and regions that should be unity mapped. | |
106 | */ | |
f6e2e6b6 JR |
107 | struct ivmd_header { |
108 | u8 type; | |
109 | u8 flags; | |
110 | u16 length; | |
111 | u16 devid; | |
112 | u16 aux; | |
113 | u64 resv; | |
114 | u64 range_start; | |
115 | u64 range_length; | |
116 | } __attribute__((packed)); | |
117 | ||
c1cbebee JR |
118 | static int __initdata amd_iommu_detected; |
119 | ||
b65233a9 JR |
120 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
121 | to handle */ | |
2e22847f | 122 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 JR |
123 | we find in ACPI */ |
124 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
c226f853 JR |
125 | bool amd_iommu_isolate = true; /* if true, device isolation is |
126 | enabled */ | |
afa9fdc2 | 127 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 128 | |
2e22847f | 129 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 130 | system */ |
928abd25 | 131 | |
b65233a9 JR |
132 | /* |
133 | * Pointer to the device table which is shared by all AMD IOMMUs | |
134 | * it is indexed by the PCI device id or the HT unit id and contains | |
135 | * information about the domain the device belongs to as well as the | |
136 | * page table root pointer. | |
137 | */ | |
928abd25 | 138 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
139 | |
140 | /* | |
141 | * The alias table is a driver specific data structure which contains the | |
142 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
143 | * More than one device can share the same requestor id. | |
144 | */ | |
928abd25 | 145 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
146 | |
147 | /* | |
148 | * The rlookup table is used to find the IOMMU which is responsible | |
149 | * for a specific device. It is also indexed by the PCI device id. | |
150 | */ | |
928abd25 | 151 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
152 | |
153 | /* | |
154 | * The pd table (protection domain table) is used to find the protection domain | |
155 | * data structure a device belongs to. Indexed with the PCI device id too. | |
156 | */ | |
928abd25 | 157 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
158 | |
159 | /* | |
160 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
161 | * to know which ones are already in use. | |
162 | */ | |
928abd25 JR |
163 | unsigned long *amd_iommu_pd_alloc_bitmap; |
164 | ||
b65233a9 JR |
165 | static u32 dev_table_size; /* size of the device table */ |
166 | static u32 alias_table_size; /* size of the alias table */ | |
167 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 168 | |
208ec8c9 JR |
169 | static inline void update_last_devid(u16 devid) |
170 | { | |
171 | if (devid > amd_iommu_last_bdf) | |
172 | amd_iommu_last_bdf = devid; | |
173 | } | |
174 | ||
c571484e JR |
175 | static inline unsigned long tbl_size(int entry_size) |
176 | { | |
177 | unsigned shift = PAGE_SHIFT + | |
178 | get_order(amd_iommu_last_bdf * entry_size); | |
179 | ||
180 | return 1UL << shift; | |
181 | } | |
182 | ||
b65233a9 JR |
183 | /**************************************************************************** |
184 | * | |
185 | * AMD IOMMU MMIO register space handling functions | |
186 | * | |
187 | * These functions are used to program the IOMMU device registers in | |
188 | * MMIO space required for that driver. | |
189 | * | |
190 | ****************************************************************************/ | |
3e8064ba | 191 | |
b65233a9 JR |
192 | /* |
193 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
194 | * exclusion range are passed through untranslated | |
195 | */ | |
b2026aa2 JR |
196 | static void __init iommu_set_exclusion_range(struct amd_iommu *iommu) |
197 | { | |
198 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
199 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
200 | u64 entry; | |
201 | ||
202 | if (!iommu->exclusion_start) | |
203 | return; | |
204 | ||
205 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
206 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
207 | &entry, sizeof(entry)); | |
208 | ||
209 | entry = limit; | |
210 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
211 | &entry, sizeof(entry)); | |
212 | } | |
213 | ||
b65233a9 | 214 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
215 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
216 | { | |
f609891f | 217 | u64 entry; |
b2026aa2 JR |
218 | |
219 | BUG_ON(iommu->mmio_base == NULL); | |
220 | ||
221 | entry = virt_to_phys(amd_iommu_dev_table); | |
222 | entry |= (dev_table_size >> 12) - 1; | |
223 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
224 | &entry, sizeof(entry)); | |
225 | } | |
226 | ||
b65233a9 | 227 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
b2026aa2 JR |
228 | static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
229 | { | |
230 | u32 ctrl; | |
231 | ||
232 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
233 | ctrl |= (1 << bit); | |
234 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
235 | } | |
236 | ||
237 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
238 | { | |
239 | u32 ctrl; | |
240 | ||
199d0d50 | 241 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
242 | ctrl &= ~(1 << bit); |
243 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
244 | } | |
245 | ||
b65233a9 | 246 | /* Function to enable the hardware */ |
412a1be2 | 247 | static void __init iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 248 | { |
a4e267c8 JR |
249 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n", |
250 | dev_name(&iommu->dev->dev), iommu->cap_ptr); | |
b2026aa2 JR |
251 | |
252 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
253 | } |
254 | ||
b65233a9 JR |
255 | /* |
256 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
257 | * the system has one. | |
258 | */ | |
6c56747b JR |
259 | static u8 * __init iommu_map_mmio_space(u64 address) |
260 | { | |
261 | u8 *ret; | |
262 | ||
263 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
264 | return NULL; | |
265 | ||
266 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
267 | if (ret != NULL) | |
268 | return ret; | |
269 | ||
270 | release_mem_region(address, MMIO_REGION_LENGTH); | |
271 | ||
272 | return NULL; | |
273 | } | |
274 | ||
275 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
276 | { | |
277 | if (iommu->mmio_base) | |
278 | iounmap(iommu->mmio_base); | |
279 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
280 | } | |
281 | ||
b65233a9 JR |
282 | /**************************************************************************** |
283 | * | |
284 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
285 | * parsing. In this pass we try to find out the highest device id this | |
286 | * code has to handle. Upon this information the size of the shared data | |
287 | * structures is determined later. | |
288 | * | |
289 | ****************************************************************************/ | |
290 | ||
b514e555 JR |
291 | /* |
292 | * This function calculates the length of a given IVHD entry | |
293 | */ | |
294 | static inline int ivhd_entry_length(u8 *ivhd) | |
295 | { | |
296 | return 0x04 << (*ivhd >> 6); | |
297 | } | |
298 | ||
b65233a9 JR |
299 | /* |
300 | * This function reads the last device id the IOMMU has to handle from the PCI | |
301 | * capability header for this IOMMU | |
302 | */ | |
3e8064ba JR |
303 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
304 | { | |
305 | u32 cap; | |
306 | ||
307 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 308 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
309 | |
310 | return 0; | |
311 | } | |
312 | ||
b65233a9 JR |
313 | /* |
314 | * After reading the highest device id from the IOMMU PCI capability header | |
315 | * this function looks if there is a higher device id defined in the ACPI table | |
316 | */ | |
3e8064ba JR |
317 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
318 | { | |
319 | u8 *p = (void *)h, *end = (void *)h; | |
320 | struct ivhd_entry *dev; | |
321 | ||
322 | p += sizeof(*h); | |
323 | end += h->length; | |
324 | ||
325 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
326 | PCI_SLOT(h->devid), | |
327 | PCI_FUNC(h->devid), | |
328 | h->cap_ptr); | |
329 | ||
330 | while (p < end) { | |
331 | dev = (struct ivhd_entry *)p; | |
332 | switch (dev->type) { | |
333 | case IVHD_DEV_SELECT: | |
334 | case IVHD_DEV_RANGE_END: | |
335 | case IVHD_DEV_ALIAS: | |
336 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 337 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 338 | update_last_devid(dev->devid); |
3e8064ba JR |
339 | break; |
340 | default: | |
341 | break; | |
342 | } | |
b514e555 | 343 | p += ivhd_entry_length(p); |
3e8064ba JR |
344 | } |
345 | ||
346 | WARN_ON(p != end); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
b65233a9 JR |
351 | /* |
352 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
353 | * id which we need to handle. This is the first of three functions which parse | |
354 | * the ACPI table. So we check the checksum here. | |
355 | */ | |
3e8064ba JR |
356 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
357 | { | |
358 | int i; | |
359 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
360 | struct ivhd_header *h; | |
361 | ||
362 | /* | |
363 | * Validate checksum here so we don't need to do it when | |
364 | * we actually parse the table | |
365 | */ | |
366 | for (i = 0; i < table->length; ++i) | |
367 | checksum += p[i]; | |
368 | if (checksum != 0) | |
369 | /* ACPI table corrupt */ | |
370 | return -ENODEV; | |
371 | ||
372 | p += IVRS_HEADER_LENGTH; | |
373 | ||
374 | end += table->length; | |
375 | while (p < end) { | |
376 | h = (struct ivhd_header *)p; | |
377 | switch (h->type) { | |
378 | case ACPI_IVHD_TYPE: | |
379 | find_last_devid_from_ivhd(h); | |
380 | break; | |
381 | default: | |
382 | break; | |
383 | } | |
384 | p += h->length; | |
385 | } | |
386 | WARN_ON(p != end); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
b65233a9 JR |
391 | /**************************************************************************** |
392 | * | |
393 | * The following functions belong the the code path which parses the ACPI table | |
394 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
395 | * data structures, initialize the device/alias/rlookup table and also | |
396 | * basically initialize the hardware. | |
397 | * | |
398 | ****************************************************************************/ | |
399 | ||
400 | /* | |
401 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
402 | * write commands to that buffer later and the IOMMU will execute them | |
403 | * asynchronously | |
404 | */ | |
b36ca91e JR |
405 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
406 | { | |
d0312b21 | 407 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 408 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
409 | |
410 | if (cmd_buf == NULL) | |
411 | return NULL; | |
412 | ||
413 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
414 | ||
58492e12 JR |
415 | return cmd_buf; |
416 | } | |
417 | ||
418 | /* | |
419 | * This function writes the command buffer address to the hardware and | |
420 | * enables it. | |
421 | */ | |
422 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
423 | { | |
424 | u64 entry; | |
425 | ||
426 | BUG_ON(iommu->cmd_buf == NULL); | |
427 | ||
428 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 429 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 430 | |
b36ca91e | 431 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 432 | &entry, sizeof(entry)); |
b36ca91e | 433 | |
cf558d25 JR |
434 | /* set head and tail to zero manually */ |
435 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
436 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
437 | ||
b36ca91e | 438 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); |
b36ca91e JR |
439 | } |
440 | ||
441 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
442 | { | |
23c1713f JR |
443 | free_pages((unsigned long)iommu->cmd_buf, |
444 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
445 | } |
446 | ||
335503e5 JR |
447 | /* allocates the memory where the IOMMU will log its events to */ |
448 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
449 | { | |
335503e5 JR |
450 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
451 | get_order(EVT_BUFFER_SIZE)); | |
452 | ||
453 | if (iommu->evt_buf == NULL) | |
454 | return NULL; | |
455 | ||
58492e12 JR |
456 | return iommu->evt_buf; |
457 | } | |
458 | ||
459 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
460 | { | |
461 | u64 entry; | |
462 | ||
463 | BUG_ON(iommu->evt_buf == NULL); | |
464 | ||
335503e5 | 465 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 466 | |
335503e5 JR |
467 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
468 | &entry, sizeof(entry)); | |
469 | ||
58492e12 | 470 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
471 | } |
472 | ||
473 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
474 | { | |
475 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
476 | } | |
477 | ||
b65233a9 | 478 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
479 | static void set_dev_entry_bit(u16 devid, u8 bit) |
480 | { | |
481 | int i = (bit >> 5) & 0x07; | |
482 | int _bit = bit & 0x1f; | |
483 | ||
484 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
485 | } | |
486 | ||
5ff4789d JR |
487 | /* Writes the specific IOMMU for a device into the rlookup table */ |
488 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
489 | { | |
490 | amd_iommu_rlookup_table[devid] = iommu; | |
491 | } | |
492 | ||
b65233a9 JR |
493 | /* |
494 | * This function takes the device specific flags read from the ACPI | |
495 | * table and sets up the device table entry with that information | |
496 | */ | |
5ff4789d JR |
497 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
498 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
499 | { |
500 | if (flags & ACPI_DEVFLAG_INITPASS) | |
501 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
502 | if (flags & ACPI_DEVFLAG_EXTINT) | |
503 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
504 | if (flags & ACPI_DEVFLAG_NMI) | |
505 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
506 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
507 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
508 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
509 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
510 | if (flags & ACPI_DEVFLAG_LINT0) | |
511 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
512 | if (flags & ACPI_DEVFLAG_LINT1) | |
513 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 514 | |
5ff4789d | 515 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
516 | } |
517 | ||
b65233a9 JR |
518 | /* |
519 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
520 | * it | |
521 | */ | |
3566b778 JR |
522 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
523 | { | |
524 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
525 | ||
526 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
527 | return; | |
528 | ||
529 | if (iommu) { | |
b65233a9 JR |
530 | /* |
531 | * We only can configure exclusion ranges per IOMMU, not | |
532 | * per device. But we can enable the exclusion range per | |
533 | * device. This is done here | |
534 | */ | |
3566b778 JR |
535 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
536 | iommu->exclusion_start = m->range_start; | |
537 | iommu->exclusion_length = m->range_length; | |
538 | } | |
539 | } | |
540 | ||
b65233a9 JR |
541 | /* |
542 | * This function reads some important data from the IOMMU PCI space and | |
543 | * initializes the driver data structure with it. It reads the hardware | |
544 | * capabilities and the first/last device entries | |
545 | */ | |
5d0c8e49 JR |
546 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
547 | { | |
5d0c8e49 | 548 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 549 | u32 range, misc; |
5d0c8e49 | 550 | |
3eaf28a1 JR |
551 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
552 | &iommu->cap); | |
553 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
554 | &range); | |
a80dc3e0 JR |
555 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
556 | &misc); | |
5d0c8e49 | 557 | |
d591b0a3 JR |
558 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
559 | MMIO_GET_FD(range)); | |
560 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
561 | MMIO_GET_LD(range)); | |
a80dc3e0 | 562 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
563 | } |
564 | ||
b65233a9 JR |
565 | /* |
566 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
567 | * initializes the hardware and our data structures with it. | |
568 | */ | |
5d0c8e49 JR |
569 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
570 | struct ivhd_header *h) | |
571 | { | |
572 | u8 *p = (u8 *)h; | |
573 | u8 *end = p, flags = 0; | |
574 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
575 | u32 ext_flags = 0; | |
58a3bee5 | 576 | bool alias = false; |
5d0c8e49 JR |
577 | struct ivhd_entry *e; |
578 | ||
579 | /* | |
580 | * First set the recommended feature enable bits from ACPI | |
581 | * into the IOMMU control registers | |
582 | */ | |
6da7342f | 583 | h->flags & IVHD_FLAG_HT_TUN_EN_MASK ? |
5d0c8e49 JR |
584 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : |
585 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
586 | ||
6da7342f | 587 | h->flags & IVHD_FLAG_PASSPW_EN_MASK ? |
5d0c8e49 JR |
588 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : |
589 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
590 | ||
6da7342f | 591 | h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ? |
5d0c8e49 JR |
592 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : |
593 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
594 | ||
6da7342f | 595 | h->flags & IVHD_FLAG_ISOC_EN_MASK ? |
5d0c8e49 JR |
596 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : |
597 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
598 | ||
599 | /* | |
600 | * make IOMMU memory accesses cache coherent | |
601 | */ | |
602 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
603 | ||
604 | /* | |
605 | * Done. Now parse the device entries | |
606 | */ | |
607 | p += sizeof(struct ivhd_header); | |
608 | end += h->length; | |
609 | ||
610 | while (p < end) { | |
611 | e = (struct ivhd_entry *)p; | |
612 | switch (e->type) { | |
613 | case IVHD_DEV_ALL: | |
614 | for (dev_i = iommu->first_device; | |
615 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
616 | set_dev_entry_from_acpi(iommu, dev_i, |
617 | e->flags, 0); | |
5d0c8e49 JR |
618 | break; |
619 | case IVHD_DEV_SELECT: | |
620 | devid = e->devid; | |
5ff4789d | 621 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
622 | break; |
623 | case IVHD_DEV_SELECT_RANGE_START: | |
624 | devid_start = e->devid; | |
625 | flags = e->flags; | |
626 | ext_flags = 0; | |
58a3bee5 | 627 | alias = false; |
5d0c8e49 JR |
628 | break; |
629 | case IVHD_DEV_ALIAS: | |
630 | devid = e->devid; | |
631 | devid_to = e->ext >> 8; | |
5ff4789d | 632 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
633 | amd_iommu_alias_table[devid] = devid_to; |
634 | break; | |
635 | case IVHD_DEV_ALIAS_RANGE: | |
636 | devid_start = e->devid; | |
637 | flags = e->flags; | |
638 | devid_to = e->ext >> 8; | |
639 | ext_flags = 0; | |
58a3bee5 | 640 | alias = true; |
5d0c8e49 JR |
641 | break; |
642 | case IVHD_DEV_EXT_SELECT: | |
643 | devid = e->devid; | |
5ff4789d JR |
644 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
645 | e->ext); | |
5d0c8e49 JR |
646 | break; |
647 | case IVHD_DEV_EXT_SELECT_RANGE: | |
648 | devid_start = e->devid; | |
649 | flags = e->flags; | |
650 | ext_flags = e->ext; | |
58a3bee5 | 651 | alias = false; |
5d0c8e49 JR |
652 | break; |
653 | case IVHD_DEV_RANGE_END: | |
654 | devid = e->devid; | |
655 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
656 | if (alias) | |
657 | amd_iommu_alias_table[dev_i] = devid_to; | |
5ff4789d | 658 | set_dev_entry_from_acpi(iommu, |
5d0c8e49 JR |
659 | amd_iommu_alias_table[dev_i], |
660 | flags, ext_flags); | |
661 | } | |
662 | break; | |
663 | default: | |
664 | break; | |
665 | } | |
666 | ||
b514e555 | 667 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
668 | } |
669 | } | |
670 | ||
b65233a9 | 671 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
672 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
673 | { | |
674 | u16 i; | |
675 | ||
676 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
677 | set_iommu_for_device(iommu, i); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
e47d402d JR |
682 | static void __init free_iommu_one(struct amd_iommu *iommu) |
683 | { | |
684 | free_command_buffer(iommu); | |
335503e5 | 685 | free_event_buffer(iommu); |
e47d402d JR |
686 | iommu_unmap_mmio_space(iommu); |
687 | } | |
688 | ||
689 | static void __init free_iommu_all(void) | |
690 | { | |
691 | struct amd_iommu *iommu, *next; | |
692 | ||
3bd22172 | 693 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
694 | list_del(&iommu->list); |
695 | free_iommu_one(iommu); | |
696 | kfree(iommu); | |
697 | } | |
698 | } | |
699 | ||
b65233a9 JR |
700 | /* |
701 | * This function clues the initialization function for one IOMMU | |
702 | * together and also allocates the command buffer and programs the | |
703 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
704 | */ | |
e47d402d JR |
705 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
706 | { | |
707 | spin_lock_init(&iommu->lock); | |
708 | list_add_tail(&iommu->list, &amd_iommu_list); | |
709 | ||
710 | /* | |
711 | * Copy data from ACPI table entry to the iommu struct | |
712 | */ | |
3eaf28a1 JR |
713 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
714 | if (!iommu->dev) | |
715 | return 1; | |
716 | ||
e47d402d | 717 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 718 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
719 | iommu->mmio_phys = h->mmio_phys; |
720 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
721 | if (!iommu->mmio_base) | |
722 | return -ENOMEM; | |
723 | ||
e47d402d JR |
724 | iommu->cmd_buf = alloc_command_buffer(iommu); |
725 | if (!iommu->cmd_buf) | |
726 | return -ENOMEM; | |
727 | ||
335503e5 JR |
728 | iommu->evt_buf = alloc_event_buffer(iommu); |
729 | if (!iommu->evt_buf) | |
730 | return -ENOMEM; | |
731 | ||
a80dc3e0 JR |
732 | iommu->int_enabled = false; |
733 | ||
e47d402d JR |
734 | init_iommu_from_pci(iommu); |
735 | init_iommu_from_acpi(iommu, h); | |
736 | init_iommu_devices(iommu); | |
737 | ||
8a66712b | 738 | return pci_enable_device(iommu->dev); |
e47d402d JR |
739 | } |
740 | ||
b65233a9 JR |
741 | /* |
742 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
743 | * IOMMU structure and initializes it with init_iommu_one() | |
744 | */ | |
e47d402d JR |
745 | static int __init init_iommu_all(struct acpi_table_header *table) |
746 | { | |
747 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
748 | struct ivhd_header *h; | |
749 | struct amd_iommu *iommu; | |
750 | int ret; | |
751 | ||
e47d402d JR |
752 | end += table->length; |
753 | p += IVRS_HEADER_LENGTH; | |
754 | ||
755 | while (p < end) { | |
756 | h = (struct ivhd_header *)p; | |
757 | switch (*p) { | |
758 | case ACPI_IVHD_TYPE: | |
759 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
760 | if (iommu == NULL) | |
761 | return -ENOMEM; | |
762 | ret = init_iommu_one(iommu, h); | |
763 | if (ret) | |
764 | return ret; | |
765 | break; | |
766 | default: | |
767 | break; | |
768 | } | |
769 | p += h->length; | |
770 | ||
771 | } | |
772 | WARN_ON(p != end); | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
a80dc3e0 JR |
777 | /**************************************************************************** |
778 | * | |
779 | * The following functions initialize the MSI interrupts for all IOMMUs | |
780 | * in the system. Its a bit challenging because there could be multiple | |
781 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
782 | * pci_dev. | |
783 | * | |
784 | ****************************************************************************/ | |
785 | ||
a80dc3e0 JR |
786 | static int __init iommu_setup_msi(struct amd_iommu *iommu) |
787 | { | |
788 | int r; | |
a80dc3e0 JR |
789 | |
790 | if (pci_enable_msi(iommu->dev)) | |
791 | return 1; | |
792 | ||
793 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
794 | IRQF_SAMPLE_RANDOM, | |
795 | "AMD IOMMU", | |
796 | NULL); | |
797 | ||
798 | if (r) { | |
799 | pci_disable_msi(iommu->dev); | |
800 | return 1; | |
801 | } | |
802 | ||
fab6afa3 | 803 | iommu->int_enabled = true; |
58492e12 JR |
804 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
805 | ||
a80dc3e0 JR |
806 | return 0; |
807 | } | |
808 | ||
809 | static int __init iommu_init_msi(struct amd_iommu *iommu) | |
810 | { | |
811 | if (iommu->int_enabled) | |
812 | return 0; | |
813 | ||
d91cecdd | 814 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
815 | return iommu_setup_msi(iommu); |
816 | ||
817 | return 1; | |
818 | } | |
819 | ||
b65233a9 JR |
820 | /**************************************************************************** |
821 | * | |
822 | * The next functions belong to the third pass of parsing the ACPI | |
823 | * table. In this last pass the memory mapping requirements are | |
824 | * gathered (like exclusion and unity mapping reanges). | |
825 | * | |
826 | ****************************************************************************/ | |
827 | ||
be2a022c JR |
828 | static void __init free_unity_maps(void) |
829 | { | |
830 | struct unity_map_entry *entry, *next; | |
831 | ||
832 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
833 | list_del(&entry->list); | |
834 | kfree(entry); | |
835 | } | |
836 | } | |
837 | ||
b65233a9 | 838 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
839 | static int __init init_exclusion_range(struct ivmd_header *m) |
840 | { | |
841 | int i; | |
842 | ||
843 | switch (m->type) { | |
844 | case ACPI_IVMD_TYPE: | |
845 | set_device_exclusion_range(m->devid, m); | |
846 | break; | |
847 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 848 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
849 | set_device_exclusion_range(i, m); |
850 | break; | |
851 | case ACPI_IVMD_TYPE_RANGE: | |
852 | for (i = m->devid; i <= m->aux; ++i) | |
853 | set_device_exclusion_range(i, m); | |
854 | break; | |
855 | default: | |
856 | break; | |
857 | } | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
b65233a9 | 862 | /* called for unity map ACPI definition */ |
be2a022c JR |
863 | static int __init init_unity_map_range(struct ivmd_header *m) |
864 | { | |
865 | struct unity_map_entry *e = 0; | |
866 | ||
867 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
868 | if (e == NULL) | |
869 | return -ENOMEM; | |
870 | ||
871 | switch (m->type) { | |
872 | default: | |
873 | case ACPI_IVMD_TYPE: | |
874 | e->devid_start = e->devid_end = m->devid; | |
875 | break; | |
876 | case ACPI_IVMD_TYPE_ALL: | |
877 | e->devid_start = 0; | |
878 | e->devid_end = amd_iommu_last_bdf; | |
879 | break; | |
880 | case ACPI_IVMD_TYPE_RANGE: | |
881 | e->devid_start = m->devid; | |
882 | e->devid_end = m->aux; | |
883 | break; | |
884 | } | |
885 | e->address_start = PAGE_ALIGN(m->range_start); | |
886 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
887 | e->prot = m->flags >> 1; | |
888 | ||
889 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
b65233a9 | 894 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
895 | static int __init init_memory_definitions(struct acpi_table_header *table) |
896 | { | |
897 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
898 | struct ivmd_header *m; | |
899 | ||
be2a022c JR |
900 | end += table->length; |
901 | p += IVRS_HEADER_LENGTH; | |
902 | ||
903 | while (p < end) { | |
904 | m = (struct ivmd_header *)p; | |
905 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
906 | init_exclusion_range(m); | |
907 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
908 | init_unity_map_range(m); | |
909 | ||
910 | p += m->length; | |
911 | } | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
9f5f5fb3 JR |
916 | /* |
917 | * Init the device table to not allow DMA access for devices and | |
918 | * suppress all page faults | |
919 | */ | |
920 | static void init_device_table(void) | |
921 | { | |
922 | u16 devid; | |
923 | ||
924 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
925 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
926 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
927 | } |
928 | } | |
929 | ||
b65233a9 JR |
930 | /* |
931 | * This function finally enables all IOMMUs found in the system after | |
932 | * they have been initialized | |
933 | */ | |
8736197b JR |
934 | static void __init enable_iommus(void) |
935 | { | |
936 | struct amd_iommu *iommu; | |
937 | ||
3bd22172 | 938 | for_each_iommu(iommu) { |
58492e12 JR |
939 | iommu_set_device_table(iommu); |
940 | iommu_enable_command_buffer(iommu); | |
941 | iommu_enable_event_buffer(iommu); | |
8736197b | 942 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 943 | iommu_init_msi(iommu); |
8736197b JR |
944 | iommu_enable(iommu); |
945 | } | |
946 | } | |
947 | ||
7441e9cb JR |
948 | /* |
949 | * Suspend/Resume support | |
950 | * disable suspend until real resume implemented | |
951 | */ | |
952 | ||
953 | static int amd_iommu_resume(struct sys_device *dev) | |
954 | { | |
955 | return 0; | |
956 | } | |
957 | ||
958 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
959 | { | |
960 | return -EINVAL; | |
961 | } | |
962 | ||
963 | static struct sysdev_class amd_iommu_sysdev_class = { | |
964 | .name = "amd_iommu", | |
965 | .suspend = amd_iommu_suspend, | |
966 | .resume = amd_iommu_resume, | |
967 | }; | |
968 | ||
969 | static struct sys_device device_amd_iommu = { | |
970 | .id = 0, | |
971 | .cls = &amd_iommu_sysdev_class, | |
972 | }; | |
973 | ||
b65233a9 JR |
974 | /* |
975 | * This is the core init function for AMD IOMMU hardware in the system. | |
976 | * This function is called from the generic x86 DMA layer initialization | |
977 | * code. | |
978 | * | |
979 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
980 | * three times: | |
981 | * | |
982 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
983 | * Upon this information the size of the data structures is | |
984 | * determined that needs to be allocated. | |
985 | * | |
986 | * 2 pass) Initialize the data structures just allocated with the | |
987 | * information in the ACPI table about available AMD IOMMUs | |
988 | * in the system. It also maps the PCI devices in the | |
989 | * system to specific IOMMUs | |
990 | * | |
991 | * 3 pass) After the basic data structures are allocated and | |
992 | * initialized we update them with information about memory | |
993 | * remapping requirements parsed out of the ACPI table in | |
994 | * this last pass. | |
995 | * | |
996 | * After that the hardware is initialized and ready to go. In the last | |
997 | * step we do some Linux specific things like registering the driver in | |
998 | * the dma_ops interface and initializing the suspend/resume support | |
999 | * functions. Finally it prints some information about AMD IOMMUs and | |
1000 | * the driver state and enables the hardware. | |
1001 | */ | |
fe74c9cf JR |
1002 | int __init amd_iommu_init(void) |
1003 | { | |
1004 | int i, ret = 0; | |
1005 | ||
1006 | ||
8b14518f | 1007 | if (no_iommu) { |
fe74c9cf JR |
1008 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
1009 | return 0; | |
1010 | } | |
1011 | ||
c1cbebee JR |
1012 | if (!amd_iommu_detected) |
1013 | return -ENODEV; | |
1014 | ||
fe74c9cf JR |
1015 | /* |
1016 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1017 | * we need to handle. Upon this information the shared data | |
1018 | * structures for the IOMMUs in the system will be allocated | |
1019 | */ | |
1020 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1021 | return -ENODEV; | |
1022 | ||
c571484e JR |
1023 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1024 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1025 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1026 | |
1027 | ret = -ENOMEM; | |
1028 | ||
1029 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1030 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1031 | get_order(dev_table_size)); |
1032 | if (amd_iommu_dev_table == NULL) | |
1033 | goto out; | |
1034 | ||
1035 | /* | |
1036 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1037 | * IOMMU see for that device | |
1038 | */ | |
1039 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1040 | get_order(alias_table_size)); | |
1041 | if (amd_iommu_alias_table == NULL) | |
1042 | goto free; | |
1043 | ||
1044 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1045 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1046 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1047 | get_order(rlookup_table_size)); |
1048 | if (amd_iommu_rlookup_table == NULL) | |
1049 | goto free; | |
1050 | ||
1051 | /* | |
1052 | * Protection Domain table - maps devices to protection domains | |
1053 | * This table has the same size as the rlookup_table | |
1054 | */ | |
5dc8bff0 | 1055 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1056 | get_order(rlookup_table_size)); |
1057 | if (amd_iommu_pd_table == NULL) | |
1058 | goto free; | |
1059 | ||
5dc8bff0 JR |
1060 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1061 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1062 | get_order(MAX_DOMAIN_ID/8)); |
1063 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1064 | goto free; | |
1065 | ||
9f5f5fb3 JR |
1066 | /* init the device table */ |
1067 | init_device_table(); | |
1068 | ||
fe74c9cf | 1069 | /* |
5dc8bff0 | 1070 | * let all alias entries point to itself |
fe74c9cf | 1071 | */ |
3a61ec38 | 1072 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1073 | amd_iommu_alias_table[i] = i; |
1074 | ||
fe74c9cf JR |
1075 | /* |
1076 | * never allocate domain 0 because its used as the non-allocated and | |
1077 | * error value placeholder | |
1078 | */ | |
1079 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1080 | ||
1081 | /* | |
1082 | * now the data structures are allocated and basically initialized | |
1083 | * start the real acpi table scan | |
1084 | */ | |
1085 | ret = -ENODEV; | |
1086 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1087 | goto free; | |
1088 | ||
1089 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1090 | goto free; | |
1091 | ||
129d6aba | 1092 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1093 | if (ret) |
1094 | goto free; | |
1095 | ||
129d6aba | 1096 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1097 | if (ret) |
1098 | goto free; | |
1099 | ||
129d6aba | 1100 | ret = amd_iommu_init_dma_ops(); |
7441e9cb JR |
1101 | if (ret) |
1102 | goto free; | |
1103 | ||
8736197b JR |
1104 | enable_iommus(); |
1105 | ||
fe74c9cf JR |
1106 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
1107 | (1 << (amd_iommu_aperture_order-20))); | |
1108 | ||
1109 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
1110 | if (amd_iommu_isolate) | |
1111 | printk("enabled\n"); | |
1112 | else | |
1113 | printk("disabled\n"); | |
1114 | ||
afa9fdc2 | 1115 | if (amd_iommu_unmap_flush) |
1c655773 JR |
1116 | printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n"); |
1117 | else | |
1118 | printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n"); | |
1119 | ||
fe74c9cf JR |
1120 | out: |
1121 | return ret; | |
1122 | ||
1123 | free: | |
d58befd3 JR |
1124 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1125 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1126 | |
9a836de0 JR |
1127 | free_pages((unsigned long)amd_iommu_pd_table, |
1128 | get_order(rlookup_table_size)); | |
fe74c9cf | 1129 | |
9a836de0 JR |
1130 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1131 | get_order(rlookup_table_size)); | |
fe74c9cf | 1132 | |
9a836de0 JR |
1133 | free_pages((unsigned long)amd_iommu_alias_table, |
1134 | get_order(alias_table_size)); | |
fe74c9cf | 1135 | |
9a836de0 JR |
1136 | free_pages((unsigned long)amd_iommu_dev_table, |
1137 | get_order(dev_table_size)); | |
fe74c9cf JR |
1138 | |
1139 | free_iommu_all(); | |
1140 | ||
1141 | free_unity_maps(); | |
1142 | ||
1143 | goto out; | |
1144 | } | |
1145 | ||
b65233a9 JR |
1146 | /**************************************************************************** |
1147 | * | |
1148 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1149 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1150 | * IOMMUs | |
1151 | * | |
1152 | ****************************************************************************/ | |
ae7877de JR |
1153 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1154 | { | |
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | void __init amd_iommu_detect(void) | |
1159 | { | |
299a140d | 1160 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1161 | return; |
1162 | ||
ae7877de JR |
1163 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1164 | iommu_detected = 1; | |
c1cbebee | 1165 | amd_iommu_detected = 1; |
92af4e29 | 1166 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1167 | gart_iommu_aperture_disabled = 1; |
1168 | gart_iommu_aperture = 0; | |
92af4e29 | 1169 | #endif |
ae7877de JR |
1170 | } |
1171 | } | |
1172 | ||
b65233a9 JR |
1173 | /**************************************************************************** |
1174 | * | |
1175 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1176 | * options. | |
1177 | * | |
1178 | ****************************************************************************/ | |
1179 | ||
918ad6c5 JR |
1180 | static int __init parse_amd_iommu_options(char *str) |
1181 | { | |
1182 | for (; *str; ++str) { | |
1c655773 | 1183 | if (strncmp(str, "isolate", 7) == 0) |
c226f853 | 1184 | amd_iommu_isolate = true; |
e5e1f606 | 1185 | if (strncmp(str, "share", 5) == 0) |
c226f853 | 1186 | amd_iommu_isolate = false; |
695b5676 | 1187 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1188 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1189 | } |
1190 | ||
1191 | return 1; | |
1192 | } | |
1193 | ||
1194 | static int __init parse_amd_iommu_size_options(char *str) | |
1195 | { | |
0906372e JR |
1196 | unsigned order = PAGE_SHIFT + get_order(memparse(str, &str)); |
1197 | ||
1198 | if ((order > 24) && (order < 31)) | |
1199 | amd_iommu_aperture_order = order; | |
918ad6c5 JR |
1200 | |
1201 | return 1; | |
1202 | } | |
1203 | ||
1204 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1205 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |