[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / amd_nb.c

/*
 * Shared support code for AMD K8 northbridges and derivates.
 * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/types.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <asm/amd_nb.h>

#define PCI_DEVICE_ID_AMD_17H_ROOT	0x1450
#define PCI_DEVICE_ID_AMD_17H_DF_F3	0x1463
#define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464

/* Protect the PCI config register pairs used for SMN and DF indirect access. */
static DEFINE_MUTEX(smn_mutex);

static u32 *flush_words;

static const struct pci_device_id amd_root_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
	{}
};

const struct pci_device_id amd_nb_misc_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{}
};
EXPORT_SYMBOL_GPL(amd_nb_misc_ids);

static const struct pci_device_id amd_nb_link_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
	{}
};

const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
	{ 0x00, 0x18, 0x20 },
	{ 0xff, 0x00, 0x20 },
	{ 0xfe, 0x00, 0x20 },
	{ }
};

static struct amd_northbridge_info amd_northbridges;

u16 amd_nb_num(void)
{
	return amd_northbridges.num;
}
EXPORT_SYMBOL_GPL(amd_nb_num);

bool amd_nb_has_feature(unsigned int feature)
{
	return ((amd_northbridges.flags & feature) == feature);
}
EXPORT_SYMBOL_GPL(amd_nb_has_feature);

struct amd_northbridge *node_to_amd_nb(int node)
{
	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
}
EXPORT_SYMBOL_GPL(node_to_amd_nb);

static struct pci_dev *next_northbridge(struct pci_dev *dev,
					const struct pci_device_id *ids)
{
	do {
		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
		if (!dev)
			break;
	} while (!pci_match_id(ids, dev));
	return dev;
}

static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
{
	struct pci_dev *root;
	int err = -ENODEV;

	if (node >= amd_northbridges.num)
		goto out;

	root = node_to_amd_nb(node)->root;
	if (!root)
		goto out;

	mutex_lock(&smn_mutex);

	err = pci_write_config_dword(root, 0x60, address);
	if (err) {
		pr_warn("Error programming SMN address 0x%x.\n", address);
		goto out_unlock;
	}

	err = (write ? pci_write_config_dword(root, 0x64, *value)
		     : pci_read_config_dword(root, 0x64, value));
	if (err)
		pr_warn("Error %s SMN address 0x%x.\n",
			(write ? "writing to" : "reading from"), address);

out_unlock:
	mutex_unlock(&smn_mutex);

out:
	return err;
}

int amd_smn_read(u16 node, u32 address, u32 *value)
{
	return __amd_smn_rw(node, address, value, false);
}
EXPORT_SYMBOL_GPL(amd_smn_read);

int amd_smn_write(u16 node, u32 address, u32 value)
{
	return __amd_smn_rw(node, address, &value, true);
}
EXPORT_SYMBOL_GPL(amd_smn_write);

/*
 * Data Fabric Indirect Access uses FICAA/FICAD.
 *
 * Fabric Indirect Configuration Access Address (FICAA): Constructed based
 * on the device's Instance Id and the PCI function and register offset of
 * the desired register.
 *
 * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
 * and FICAD HI registers but so far we only need the LO register.
 */
int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
{
	struct pci_dev *F4;
	u32 ficaa;
	int err = -ENODEV;

	if (node >= amd_northbridges.num)
		goto out;

	F4 = node_to_amd_nb(node)->link;
	if (!F4)
		goto out;

	ficaa  = 1;
	ficaa |= reg & 0x3FC;
	ficaa |= (func & 0x7) << 11;
	ficaa |= instance_id << 16;

	mutex_lock(&smn_mutex);

	err = pci_write_config_dword(F4, 0x5C, ficaa);
	if (err) {
		pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
		goto out_unlock;
	}

	err = pci_read_config_dword(F4, 0x98, lo);
	if (err)
		pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);

out_unlock:
	mutex_unlock(&smn_mutex);

out:
	return err;
}
EXPORT_SYMBOL_GPL(amd_df_indirect_read);

int amd_cache_northbridges(void)
{
	u16 i = 0;
	struct amd_northbridge *nb;
	struct pci_dev *root, *misc, *link;

	if (amd_northbridges.num)
		return 0;

	misc = NULL;
	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
		i++;

	if (!i)
		return -ENODEV;

	nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
	if (!nb)
		return -ENOMEM;

	amd_northbridges.nb = nb;
	amd_northbridges.num = i;

	link = misc = root = NULL;
	for (i = 0; i != amd_northbridges.num; i++) {
		node_to_amd_nb(i)->root = root =
			next_northbridge(root, amd_root_ids);
		node_to_amd_nb(i)->misc = misc =
			next_northbridge(misc, amd_nb_misc_ids);
		node_to_amd_nb(i)->link = link =
			next_northbridge(link, amd_nb_link_ids);
	}

	if (amd_gart_present())
		amd_northbridges.flags |= AMD_NB_GART;

	/*
	 * Check for L3 cache presence.
	 */
	if (!cpuid_edx(0x80000006))
		return 0;

	/*
	 * Some CPU families support L3 Cache Index Disable. There are some
	 * limitations because of E382 and E388 on family 0x10.
	 */
	if (boot_cpu_data.x86 == 0x10 &&
	    boot_cpu_data.x86_model >= 0x8 &&
	    (boot_cpu_data.x86_model > 0x9 ||
	     boot_cpu_data.x86_mask >= 0x1))
		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;

	if (boot_cpu_data.x86 == 0x15)
		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;

	/* L3 cache partitioning is supported on family 0x15 */
	if (boot_cpu_data.x86 == 0x15)
		amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;

	return 0;
}
EXPORT_SYMBOL_GPL(amd_cache_northbridges);

/*
 * Ignores subdevice/subvendor but as far as I can figure out
 * they're useless anyways
 */
bool __init early_is_amd_nb(u32 device)
{
	const struct pci_device_id *id;
	u32 vendor = device & 0xffff;

	device >>= 16;
	for (id = amd_nb_misc_ids; id->vendor; id++)
		if (vendor == id->vendor && device == id->device)
			return true;
	return false;
}

struct resource *amd_get_mmconfig_range(struct resource *res)
{
	u32 address;
	u64 base, msr;
	unsigned int segn_busn_bits;

	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return NULL;

	/* assume all cpus from fam10h have mmconfig */
	if (boot_cpu_data.x86 < 0x10)
		return NULL;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	rdmsrl(address, msr);

	/* mmconfig is not enabled */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	res->flags = IORESOURCE_MEM;
	res->start = base;
	res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	return res;
}

int amd_get_subcaches(int cpu)
{
	struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
	unsigned int mask;

	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
		return 0;

	pci_read_config_dword(link, 0x1d4, &mask);

	return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
}

int amd_set_subcaches(int cpu, unsigned long mask)
{
	static unsigned int reset, ban;
	struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
	unsigned int reg;
	int cuid;

	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
		return -EINVAL;

	/* if necessary, collect reset state of L3 partitioning and BAN mode */
	if (reset == 0) {
		pci_read_config_dword(nb->link, 0x1d4, &reset);
		pci_read_config_dword(nb->misc, 0x1b8, &ban);
		ban &= 0x180000;
	}

	/* deactivate BAN mode if any subcaches are to be disabled */
	if (mask != 0xf) {
		pci_read_config_dword(nb->misc, 0x1b8, &reg);
		pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
	}

	cuid = cpu_data(cpu).cpu_core_id;
	mask <<= 4 * cuid;
	mask |= (0xf ^ (1 << cuid)) << 26;

	pci_write_config_dword(nb->link, 0x1d4, mask);

	/* reset BAN mode if L3 partitioning returned to reset state */
	pci_read_config_dword(nb->link, 0x1d4, &reg);
	if (reg == reset) {
		pci_read_config_dword(nb->misc, 0x1b8, &reg);
		reg &= ~0x180000;
		pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
	}

	return 0;
}

static void amd_cache_gart(void)
{
	u16 i;

	if (!amd_nb_has_feature(AMD_NB_GART))
		return;

	flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
	if (!flush_words) {
		amd_northbridges.flags &= ~AMD_NB_GART;
		pr_notice("Cannot initialize GART flush words, GART support disabled\n");
		return;
	}

	for (i = 0; i != amd_northbridges.num; i++)
		pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
}

void amd_flush_garts(void)
{
	int flushed, i;
	unsigned long flags;
	static DEFINE_SPINLOCK(gart_lock);

	if (!amd_nb_has_feature(AMD_NB_GART))
		return;

	/*
	 * Avoid races between AGP and IOMMU. In theory it's not needed
	 * but I'm not sure if the hardware won't lose flush requests
	 * when another is pending. This whole thing is so expensive anyways
	 * that it doesn't matter to serialize more. -AK
	 */
	spin_lock_irqsave(&gart_lock, flags);
	flushed = 0;
	for (i = 0; i < amd_northbridges.num; i++) {
		pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
				       flush_words[i] | 1);
		flushed++;
	}
	for (i = 0; i < amd_northbridges.num; i++) {
		u32 w;
		/* Make sure the hardware actually executed the flush*/
		for (;;) {
			pci_read_config_dword(node_to_amd_nb(i)->misc,
					      0x9c, &w);
			if (!(w & 1))
				break;
			cpu_relax();
		}
	}
	spin_unlock_irqrestore(&gart_lock, flags);
	if (!flushed)
		pr_notice("nothing to flush?\n");
}
EXPORT_SYMBOL_GPL(amd_flush_garts);

static __init int init_amd_nbs(void)
{
	amd_cache_northbridges();
	amd_cache_gart();

	return 0;
}

/* This has to go after the PCI subsystem */
fs_initcall(init_amd_nbs);
Commit	Line	Data
a32073bf AK	1	/*
	2	* Shared support code for AMD K8 northbridges and derivates.
	3	* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
	4	*/
c767a54b JP	5
	6	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	7
a32073bf	8	#include <linux/types.h>
5a0e3ad6	9	#include <linux/slab.h>
a32073bf AK	10	#include <linux/init.h>
a32073bf AK	11	#include <linux/errno.h>
186f4360	12	#include <linux/export.h>
a32073bf	13	#include <linux/spinlock.h>
23ac4ae8	14	#include <asm/amd_nb.h>
a32073bf	15
ddfe43cd	16	#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
b791c6b6 YG	17	#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
	18	#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
	19
ddfe43cd YG	20	/* Protect the PCI config register pairs used for SMN and DF indirect access. */
	21	static DEFINE_MUTEX(smn_mutex);
	22
a32073bf AK	23	static u32 *flush_words;
a32073bf AK	24
ddfe43cd YG	25	static const struct pci_device_id amd_root_ids[] = {
	26	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
	27	{}
	28	};
	29
691269f0	30	const struct pci_device_id amd_nb_misc_ids[] = {
cf169702 JR	31	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
cf169702 JR	32	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
cb293250	33	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	34	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
7d64ac64	35	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
15895a72	36	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
94c1acf2	37	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
85a8885b	38	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
b791c6b6	39	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
a32073bf AK	40	{}
a32073bf AK	41	};
de6bd083	42	EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
a32073bf	43
c391c788	44	static const struct pci_device_id amd_nb_link_ids[] = {
cb6c8520	45	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
7d64ac64	46	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
15895a72	47	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
94c1acf2	48	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
85a8885b	49	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
b791c6b6	50	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
41b2610c HR	51	{}
	52	};
	53
24d9b70b JB	54	const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
	55	{ 0x00, 0x18, 0x20 },
	56	{ 0xff, 0x00, 0x20 },
	57	{ 0xfe, 0x00, 0x20 },
	58	{ }
	59	};
	60
c7993890 YG	61	static struct amd_northbridge_info amd_northbridges;
	62
	63	u16 amd_nb_num(void)
	64	{
	65	return amd_northbridges.num;
	66	}
de6bd083	67	EXPORT_SYMBOL_GPL(amd_nb_num);
c7993890 YG	68
	69	bool amd_nb_has_feature(unsigned int feature)
	70	{
	71	return ((amd_northbridges.flags & feature) == feature);
	72	}
de6bd083	73	EXPORT_SYMBOL_GPL(amd_nb_has_feature);
c7993890 YG	74
	75	struct amd_northbridge *node_to_amd_nb(int node)
	76	{
	77	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
	78	}
de6bd083	79	EXPORT_SYMBOL_GPL(node_to_amd_nb);
a32073bf	80
9653a5c7	81	static struct pci_dev next_northbridge(struct pci_dev dev,
691269f0	82	const struct pci_device_id *ids)
a32073bf AK	83	{
	84	do {
	85	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	86	if (!dev)
	87	break;
9653a5c7	88	} while (!pci_match_id(ids, dev));
a32073bf AK	89	return dev;
	90	}
	91
ddfe43cd YG	92	static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
	93	{
	94	struct pci_dev *root;
	95	int err = -ENODEV;
	96
	97	if (node >= amd_northbridges.num)
	98	goto out;
	99
	100	root = node_to_amd_nb(node)->root;
	101	if (!root)
	102	goto out;
	103
	104	mutex_lock(&smn_mutex);
	105
	106	err = pci_write_config_dword(root, 0x60, address);
	107	if (err) {
	108	pr_warn("Error programming SMN address 0x%x.\n", address);
	109	goto out_unlock;
	110	}
	111
	112	err = (write ? pci_write_config_dword(root, 0x64, *value)
	113	: pci_read_config_dword(root, 0x64, value));
	114	if (err)
	115	pr_warn("Error %s SMN address 0x%x.\n",
	116	(write ? "writing to" : "reading from"), address);
	117
	118	out_unlock:
	119	mutex_unlock(&smn_mutex);
	120
	121	out:
	122	return err;
	123	}
	124
	125	int amd_smn_read(u16 node, u32 address, u32 *value)
	126	{
	127	return __amd_smn_rw(node, address, value, false);
	128	}
	129	EXPORT_SYMBOL_GPL(amd_smn_read);
	130
	131	int amd_smn_write(u16 node, u32 address, u32 value)
	132	{
	133	return __amd_smn_rw(node, address, &value, true);
	134	}
	135	EXPORT_SYMBOL_GPL(amd_smn_write);
	136
	137	/*
	138	* Data Fabric Indirect Access uses FICAA/FICAD.
	139	*
	140	* Fabric Indirect Configuration Access Address (FICAA): Constructed based
	141	* on the device's Instance Id and the PCI function and register offset of
	142	* the desired register.
	143	*
	144	* Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
	145	* and FICAD HI registers but so far we only need the LO register.
	146	*/
	147	int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
	148	{
	149	struct pci_dev *F4;
	150	u32 ficaa;
	151	int err = -ENODEV;
	152
	153	if (node >= amd_northbridges.num)
	154	goto out;
	155
156	F4 = node_to_amd_nb(node)->link;
157	if (!F4)
158	goto out;
159
160	ficaa = 1;
161	ficaa \|= reg & 0x3FC;
162	ficaa \|= (func & 0x7) << 11;
163	ficaa \|= instance_id << 16;
164
165	mutex_lock(&smn_mutex);
166
167	err = pci_write_config_dword(F4, 0x5C, ficaa);
168	if (err) {
169	pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
170	goto out_unlock;
171	}
172
173	err = pci_read_config_dword(F4, 0x98, lo);
174	if (err)
175	pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
176
177	out_unlock:
178	mutex_unlock(&smn_mutex);
179
180	out:
181	return err;
182	}
183	EXPORT_SYMBOL_GPL(amd_df_indirect_read);
184
9653a5c7	185	int amd_cache_northbridges(void)
a32073bf	186	{
84fd1d35	187	u16 i = 0;
9653a5c7	188	struct amd_northbridge *nb;
ddfe43cd	189	struct pci_dev root, misc, *link;
3c6df2a9	190
c7993890	191	if (amd_northbridges.num)
a32073bf AK	192	return 0;
a32073bf AK	193
9653a5c7 HR	194	misc = NULL;
	195	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
	196	i++;
900f9ac9	197
1ead852d BP	198	if (!i)
1ead852d BP	199	return -ENODEV;
a32073bf	200
de6bd083	201	nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
9653a5c7	202	if (!nb)
a32073bf AK	203	return -ENOMEM;
a32073bf AK	204
9653a5c7 HR	205	amd_northbridges.nb = nb;
9653a5c7 HR	206	amd_northbridges.num = i;
3c6df2a9	207
ddfe43cd	208	link = misc = root = NULL;
c7993890	209	for (i = 0; i != amd_northbridges.num; i++) {
ddfe43cd YG	210	node_to_amd_nb(i)->root = root =
ddfe43cd YG	211	next_northbridge(root, amd_root_ids);
9653a5c7 HR	212	node_to_amd_nb(i)->misc = misc =
9653a5c7 HR	213	next_northbridge(misc, amd_nb_misc_ids);
41b2610c HR	214	node_to_amd_nb(i)->link = link =
41b2610c HR	215	next_northbridge(link, amd_nb_link_ids);
7d64ac64	216	}
9653a5c7	217
1b457429	218	if (amd_gart_present())
9653a5c7	219	amd_northbridges.flags \|= AMD_NB_GART;
a32073bf	220
7d64ac64 AG	221	/*
	222	* Check for L3 cache presence.
	223	*/
	224	if (!cpuid_edx(0x80000006))
	225	return 0;
	226
f658bcfb HR	227	/*
	228	* Some CPU families support L3 Cache Index Disable. There are some
	229	* limitations because of E382 and E388 on family 0x10.
	230	*/
	231	if (boot_cpu_data.x86 == 0x10 &&
	232	boot_cpu_data.x86_model >= 0x8 &&
	233	(boot_cpu_data.x86_model > 0x9 \|\|
	234	boot_cpu_data.x86_mask >= 0x1))
	235	amd_northbridges.flags \|= AMD_NB_L3_INDEX_DISABLE;
	236
b453de02 HR	237	if (boot_cpu_data.x86 == 0x15)
	238	amd_northbridges.flags \|= AMD_NB_L3_INDEX_DISABLE;
	239
cabb5bd7 HR	240	/* L3 cache partitioning is supported on family 0x15 */
	241	if (boot_cpu_data.x86 == 0x15)
	242	amd_northbridges.flags \|= AMD_NB_L3_PARTITIONING;
	243
a32073bf AK	244	return 0;
a32073bf AK	245	}
9653a5c7	246	EXPORT_SYMBOL_GPL(amd_cache_northbridges);
a32073bf	247
84fd1d35 BP	248	/*
	249	* Ignores subdevice/subvendor but as far as I can figure out
	250	* they're useless anyways
	251	*/
	252	bool __init early_is_amd_nb(u32 device)
a32073bf	253	{
691269f0	254	const struct pci_device_id *id;
a32073bf	255	u32 vendor = device & 0xffff;
691269f0	256
a32073bf	257	device >>= 16;
9653a5c7	258	for (id = amd_nb_misc_ids; id->vendor; id++)
a32073bf	259	if (vendor == id->vendor && device == id->device)
84fd1d35 BP	260	return true;
84fd1d35 BP	261	return false;
a32073bf AK	262	}
a32073bf AK	263
24d25dbf BH	264	struct resource amd_get_mmconfig_range(struct resource res)
	265	{
	266	u32 address;
	267	u64 base, msr;
de6bd083	268	unsigned int segn_busn_bits;
24d25dbf BH	269
	270	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	271	return NULL;
	272
	273	/* assume all cpus from fam10h have mmconfig */
de6bd083	274	if (boot_cpu_data.x86 < 0x10)
24d25dbf BH	275	return NULL;
	276
	277	address = MSR_FAM10H_MMIO_CONF_BASE;
	278	rdmsrl(address, msr);
	279
	280	/* mmconfig is not enabled */
	281	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	282	return NULL;
	283
	284	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	285
	286	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	287	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	288
	289	res->flags = IORESOURCE_MEM;
	290	res->start = base;
	291	res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	292	return res;
	293	}
	294
cabb5bd7 HR	295	int amd_get_subcaches(int cpu)
	296	{
	297	struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
	298	unsigned int mask;
cabb5bd7 HR	299
	300	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
	301	return 0;
	302
	303	pci_read_config_dword(link, 0x1d4, &mask);
	304
8196dab4	305	return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
cabb5bd7 HR	306	}
cabb5bd7 HR	307
2993ae33	308	int amd_set_subcaches(int cpu, unsigned long mask)
cabb5bd7 HR	309	{
	310	static unsigned int reset, ban;
	311	struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
	312	unsigned int reg;
141168c3	313	int cuid;
cabb5bd7 HR	314
	315	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) \|\| mask > 0xf)
	316	return -EINVAL;
	317
	318	/* if necessary, collect reset state of L3 partitioning and BAN mode */
	319	if (reset == 0) {
	320	pci_read_config_dword(nb->link, 0x1d4, &reset);
	321	pci_read_config_dword(nb->misc, 0x1b8, &ban);
	322	ban &= 0x180000;
	323	}
	324
	325	/* deactivate BAN mode if any subcaches are to be disabled */
	326	if (mask != 0xf) {
	327	pci_read_config_dword(nb->misc, 0x1b8, &reg);
	328	pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
	329	}
	330
8196dab4	331	cuid = cpu_data(cpu).cpu_core_id;
cabb5bd7 HR	332	mask <<= 4 * cuid;
	333	mask \|= (0xf ^ (1 << cuid)) << 26;
	334
	335	pci_write_config_dword(nb->link, 0x1d4, mask);
	336
	337	/* reset BAN mode if L3 partitioning returned to reset state */
	338	pci_read_config_dword(nb->link, 0x1d4, &reg);
	339	if (reg == reset) {
	340	pci_read_config_dword(nb->misc, 0x1b8, &reg);
	341	reg &= ~0x180000;
	342	pci_write_config_dword(nb->misc, 0x1b8, reg \| ban);
	343	}
	344
	345	return 0;
	346	}
	347
09c6c30e	348	static void amd_cache_gart(void)
9653a5c7	349	{
84fd1d35	350	u16 i;
9653a5c7	351
09c6c30e BP	352	if (!amd_nb_has_feature(AMD_NB_GART))
09c6c30e BP	353	return;
9653a5c7	354
c7993890	355	flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
09c6c30e BP	356	if (!flush_words) {
	357	amd_northbridges.flags &= ~AMD_NB_GART;
	358	pr_notice("Cannot initialize GART flush words, GART support disabled\n");
	359	return;
	360	}
9653a5c7	361
c7993890	362	for (i = 0; i != amd_northbridges.num; i++)
09c6c30e	363	pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
9653a5c7 HR	364	}
9653a5c7 HR	365
eec1d4fa	366	void amd_flush_garts(void)
a32073bf AK	367	{
	368	int flushed, i;
	369	unsigned long flags;
	370	static DEFINE_SPINLOCK(gart_lock);
	371
9653a5c7	372	if (!amd_nb_has_feature(AMD_NB_GART))
900f9ac9 AH	373	return;
900f9ac9 AH	374
de6bd083 YG	375	/*
	376	* Avoid races between AGP and IOMMU. In theory it's not needed
	377	* but I'm not sure if the hardware won't lose flush requests
	378	* when another is pending. This whole thing is so expensive anyways
	379	* that it doesn't matter to serialize more. -AK
	380	*/
a32073bf AK	381	spin_lock_irqsave(&gart_lock, flags);
a32073bf AK	382	flushed = 0;
c7993890	383	for (i = 0; i < amd_northbridges.num; i++) {
9653a5c7 HR	384	pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
9653a5c7 HR	385	flush_words[i] \| 1);
a32073bf AK	386	flushed++;
a32073bf AK	387	}
c7993890	388	for (i = 0; i < amd_northbridges.num; i++) {
a32073bf AK	389	u32 w;
	390	/* Make sure the hardware actually executed the flush*/
	391	for (;;) {
9653a5c7	392	pci_read_config_dword(node_to_amd_nb(i)->misc,
a32073bf AK	393	0x9c, &w);
	394	if (!(w & 1))
	395	break;
	396	cpu_relax();
	397	}
	398	}
	399	spin_unlock_irqrestore(&gart_lock, flags);
	400	if (!flushed)
c767a54b	401	pr_notice("nothing to flush?\n");
a32073bf	402	}
eec1d4fa	403	EXPORT_SYMBOL_GPL(amd_flush_garts);
a32073bf	404
eec1d4fa	405	static __init int init_amd_nbs(void)
0e152cd7	406	{
09c6c30e BP	407	amd_cache_northbridges();
09c6c30e BP	408	amd_cache_gart();
0e152cd7	409
09c6c30e	410	return 0;
0e152cd7 BP	411	}
	412
	413	/* This has to go after the PCI subsystem */
eec1d4fa	414	fs_initcall(init_amd_nbs);