[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / amd_nb.c

/*
 * Shared support code for AMD K8 northbridges and derivates.
 * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/types.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <asm/amd_nb.h>

#define PCI_DEVICE_ID_AMD_17H_ROOT	0x1450
#define PCI_DEVICE_ID_AMD_17H_DF_F3	0x1463
#define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464

/* Protect the PCI config register pairs used for SMN and DF indirect access. */
static DEFINE_MUTEX(smn_mutex);

static u32 *flush_words;

static const struct pci_device_id amd_root_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
	{}
};

#define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704

const struct pci_device_id amd_nb_misc_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
	{}
};
EXPORT_SYMBOL_GPL(amd_nb_misc_ids);

static const struct pci_device_id amd_nb_link_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
	{}
};

const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
	{ 0x00, 0x18, 0x20 },
	{ 0xff, 0x00, 0x20 },
	{ 0xfe, 0x00, 0x20 },
	{ }
};

static struct amd_northbridge_info amd_northbridges;

u16 amd_nb_num(void)
{
	return amd_northbridges.num;
}
EXPORT_SYMBOL_GPL(amd_nb_num);

bool amd_nb_has_feature(unsigned int feature)
{
	return ((amd_northbridges.flags & feature) == feature);
}
EXPORT_SYMBOL_GPL(amd_nb_has_feature);

struct amd_northbridge *node_to_amd_nb(int node)
{
	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
}
EXPORT_SYMBOL_GPL(node_to_amd_nb);

static struct pci_dev *next_northbridge(struct pci_dev *dev,
					const struct pci_device_id *ids)
{
	do {
		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
		if (!dev)
			break;
	} while (!pci_match_id(ids, dev));
	return dev;
}

static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
{
	struct pci_dev *root;
	int err = -ENODEV;

	if (node >= amd_northbridges.num)
		goto out;

	root = node_to_amd_nb(node)->root;
	if (!root)
		goto out;

	mutex_lock(&smn_mutex);

	err = pci_write_config_dword(root, 0x60, address);
	if (err) {
		pr_warn("Error programming SMN address 0x%x.\n", address);
		goto out_unlock;
	}

	err = (write ? pci_write_config_dword(root, 0x64, *value)
		     : pci_read_config_dword(root, 0x64, value));
	if (err)
		pr_warn("Error %s SMN address 0x%x.\n",
			(write ? "writing to" : "reading from"), address);

out_unlock:
	mutex_unlock(&smn_mutex);

out:
	return err;
}

int amd_smn_read(u16 node, u32 address, u32 *value)
{
	return __amd_smn_rw(node, address, value, false);
}
EXPORT_SYMBOL_GPL(amd_smn_read);

int amd_smn_write(u16 node, u32 address, u32 value)
{
	return __amd_smn_rw(node, address, &value, true);
}
EXPORT_SYMBOL_GPL(amd_smn_write);

/*
 * Data Fabric Indirect Access uses FICAA/FICAD.
 *
 * Fabric Indirect Configuration Access Address (FICAA): Constructed based
 * on the device's Instance Id and the PCI function and register offset of
 * the desired register.
 *
 * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
 * and FICAD HI registers but so far we only need the LO register.
 */
int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
{
	struct pci_dev *F4;
	u32 ficaa;
	int err = -ENODEV;

	if (node >= amd_northbridges.num)
		goto out;

	F4 = node_to_amd_nb(node)->link;
	if (!F4)
		goto out;

	ficaa  = 1;
	ficaa |= reg & 0x3FC;
	ficaa |= (func & 0x7) << 11;
	ficaa |= instance_id << 16;

	mutex_lock(&smn_mutex);

	err = pci_write_config_dword(F4, 0x5C, ficaa);
	if (err) {
		pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
		goto out_unlock;
	}

	err = pci_read_config_dword(F4, 0x98, lo);
	if (err)
		pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);

out_unlock:
	mutex_unlock(&smn_mutex);

out:
	return err;
}
EXPORT_SYMBOL_GPL(amd_df_indirect_read);

int amd_cache_northbridges(void)
{
	u16 i = 0;
	struct amd_northbridge *nb;
	struct pci_dev *root, *misc, *link;

	if (amd_northbridges.num)
		return 0;

	misc = NULL;
	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
		i++;

	if (!i)
		return -ENODEV;

	nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
	if (!nb)
		return -ENOMEM;

	amd_northbridges.nb = nb;
	amd_northbridges.num = i;

	link = misc = root = NULL;
	for (i = 0; i != amd_northbridges.num; i++) {
		node_to_amd_nb(i)->root = root =
			next_northbridge(root, amd_root_ids);
		node_to_amd_nb(i)->misc = misc =
			next_northbridge(misc, amd_nb_misc_ids);
		node_to_amd_nb(i)->link = link =
			next_northbridge(link, amd_nb_link_ids);
	}

	if (amd_gart_present())
		amd_northbridges.flags |= AMD_NB_GART;

	/*
	 * Check for L3 cache presence.
	 */
	if (!cpuid_edx(0x80000006))
		return 0;

	/*
	 * Some CPU families support L3 Cache Index Disable. There are some
	 * limitations because of E382 and E388 on family 0x10.
	 */
	if (boot_cpu_data.x86 == 0x10 &&
	    boot_cpu_data.x86_model >= 0x8 &&
	    (boot_cpu_data.x86_model > 0x9 ||
	     boot_cpu_data.x86_mask >= 0x1))
		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;

	if (boot_cpu_data.x86 == 0x15)
		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;

	/* L3 cache partitioning is supported on family 0x15 */
	if (boot_cpu_data.x86 == 0x15)
		amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;

	return 0;
}
EXPORT_SYMBOL_GPL(amd_cache_northbridges);

/*
 * Ignores subdevice/subvendor but as far as I can figure out
 * they're useless anyways
 */
bool __init early_is_amd_nb(u32 device)
{
	const struct pci_device_id *id;
	u32 vendor = device & 0xffff;

	device >>= 16;
	for (id = amd_nb_misc_ids; id->vendor; id++)
		if (vendor == id->vendor && device == id->device)
			return true;
	return false;
}

struct resource *amd_get_mmconfig_range(struct resource *res)
{
	u32 address;
	u64 base, msr;
	unsigned int segn_busn_bits;

	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return NULL;

	/* assume all cpus from fam10h have mmconfig */
	if (boot_cpu_data.x86 < 0x10)
		return NULL;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	rdmsrl(address, msr);

	/* mmconfig is not enabled */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	res->flags = IORESOURCE_MEM;
	res->start = base;
	res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	return res;
}

int amd_get_subcaches(int cpu)
{
	struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
	unsigned int mask;

	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
		return 0;

	pci_read_config_dword(link, 0x1d4, &mask);

	return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
}

int amd_set_subcaches(int cpu, unsigned long mask)
{
	static unsigned int reset, ban;
	struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
	unsigned int reg;
	int cuid;

	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
		return -EINVAL;

	/* if necessary, collect reset state of L3 partitioning and BAN mode */
	if (reset == 0) {
		pci_read_config_dword(nb->link, 0x1d4, &reset);
		pci_read_config_dword(nb->misc, 0x1b8, &ban);
		ban &= 0x180000;
	}

	/* deactivate BAN mode if any subcaches are to be disabled */
	if (mask != 0xf) {
		pci_read_config_dword(nb->misc, 0x1b8, &reg);
		pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
	}

	cuid = cpu_data(cpu).cpu_core_id;
	mask <<= 4 * cuid;
	mask |= (0xf ^ (1 << cuid)) << 26;

	pci_write_config_dword(nb->link, 0x1d4, mask);

	/* reset BAN mode if L3 partitioning returned to reset state */
	pci_read_config_dword(nb->link, 0x1d4, &reg);
	if (reg == reset) {
		pci_read_config_dword(nb->misc, 0x1b8, &reg);
		reg &= ~0x180000;
		pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
	}

	return 0;
}

static void amd_cache_gart(void)
{
	u16 i;

	if (!amd_nb_has_feature(AMD_NB_GART))
		return;

	flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
	if (!flush_words) {
		amd_northbridges.flags &= ~AMD_NB_GART;
		pr_notice("Cannot initialize GART flush words, GART support disabled\n");
		return;
	}

	for (i = 0; i != amd_northbridges.num; i++)
		pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
}

void amd_flush_garts(void)
{
	int flushed, i;
	unsigned long flags;
	static DEFINE_SPINLOCK(gart_lock);

	if (!amd_nb_has_feature(AMD_NB_GART))
		return;

	/*
	 * Avoid races between AGP and IOMMU. In theory it's not needed
	 * but I'm not sure if the hardware won't lose flush requests
	 * when another is pending. This whole thing is so expensive anyways
	 * that it doesn't matter to serialize more. -AK
	 */
	spin_lock_irqsave(&gart_lock, flags);
	flushed = 0;
	for (i = 0; i < amd_northbridges.num; i++) {
		pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
				       flush_words[i] | 1);
		flushed++;
	}
	for (i = 0; i < amd_northbridges.num; i++) {
		u32 w;
		/* Make sure the hardware actually executed the flush*/
		for (;;) {
			pci_read_config_dword(node_to_amd_nb(i)->misc,
					      0x9c, &w);
			if (!(w & 1))
				break;
			cpu_relax();
		}
	}
	spin_unlock_irqrestore(&gart_lock, flags);
	if (!flushed)
		pr_notice("nothing to flush?\n");
}
EXPORT_SYMBOL_GPL(amd_flush_garts);

static void __fix_erratum_688(void *info)
{
#define MSR_AMD64_IC_CFG 0xC0011021

	msr_set_bit(MSR_AMD64_IC_CFG, 3);
	msr_set_bit(MSR_AMD64_IC_CFG, 14);
}

/* Apply erratum 688 fix so machines without a BIOS fix work. */
static __init void fix_erratum_688(void)
{
	struct pci_dev *F4;
	u32 val;

	if (boot_cpu_data.x86 != 0x14)
		return;

	if (!amd_northbridges.num)
		return;

	F4 = node_to_amd_nb(0)->link;
	if (!F4)
		return;

	if (pci_read_config_dword(F4, 0x164, &val))
		return;

	if (val & BIT(2))
		return;

	on_each_cpu(__fix_erratum_688, NULL, 0);

	pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
}

static __init int init_amd_nbs(void)
{
	amd_cache_northbridges();
	amd_cache_gart();

	fix_erratum_688();

	return 0;
}

/* This has to go after the PCI subsystem */
fs_initcall(init_amd_nbs);
Commit	Line	Data
a32073bf AK	1	/*
	2	* Shared support code for AMD K8 northbridges and derivates.
	3	* Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
	4	*/
c767a54b JP	5
	6	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	7
a32073bf	8	#include <linux/types.h>
5a0e3ad6	9	#include <linux/slab.h>
a32073bf AK	10	#include <linux/init.h>
a32073bf AK	11	#include <linux/errno.h>
186f4360	12	#include <linux/export.h>
a32073bf	13	#include <linux/spinlock.h>
23ac4ae8	14	#include <asm/amd_nb.h>
a32073bf	15
ddfe43cd	16	#define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
b791c6b6 YG	17	#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
	18	#define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
	19
ddfe43cd YG	20	/* Protect the PCI config register pairs used for SMN and DF indirect access. */
	21	static DEFINE_MUTEX(smn_mutex);
	22
a32073bf AK	23	static u32 *flush_words;
a32073bf AK	24
ddfe43cd YG	25	static const struct pci_device_id amd_root_ids[] = {
	26	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
	27	{}
	28	};
	29
58ccfdba BP	30	#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
58ccfdba BP	31
691269f0	32	const struct pci_device_id amd_nb_misc_ids[] = {
cf169702 JR	33	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
cf169702 JR	34	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
cb293250	35	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
24214449	36	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
7d64ac64	37	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
15895a72	38	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
94c1acf2	39	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
85a8885b	40	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
b791c6b6	41	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
58ccfdba	42	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
a32073bf AK	43	{}
a32073bf AK	44	};
de6bd083	45	EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
a32073bf	46
c391c788	47	static const struct pci_device_id amd_nb_link_ids[] = {
cb6c8520	48	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
7d64ac64	49	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
15895a72	50	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
94c1acf2	51	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
85a8885b	52	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
b791c6b6	53	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
58ccfdba	54	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
41b2610c HR	55	{}
	56	};
	57
24d9b70b JB	58	const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
	59	{ 0x00, 0x18, 0x20 },
	60	{ 0xff, 0x00, 0x20 },
	61	{ 0xfe, 0x00, 0x20 },
	62	{ }
	63	};
	64
c7993890 YG	65	static struct amd_northbridge_info amd_northbridges;
	66
	67	u16 amd_nb_num(void)
	68	{
	69	return amd_northbridges.num;
	70	}
de6bd083	71	EXPORT_SYMBOL_GPL(amd_nb_num);
c7993890 YG	72
	73	bool amd_nb_has_feature(unsigned int feature)
	74	{
	75	return ((amd_northbridges.flags & feature) == feature);
	76	}
de6bd083	77	EXPORT_SYMBOL_GPL(amd_nb_has_feature);
c7993890 YG	78
	79	struct amd_northbridge *node_to_amd_nb(int node)
	80	{
	81	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
	82	}
de6bd083	83	EXPORT_SYMBOL_GPL(node_to_amd_nb);
a32073bf	84
9653a5c7	85	static struct pci_dev next_northbridge(struct pci_dev dev,
691269f0	86	const struct pci_device_id *ids)
a32073bf AK	87	{
	88	do {
	89	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	90	if (!dev)
	91	break;
9653a5c7	92	} while (!pci_match_id(ids, dev));
a32073bf AK	93	return dev;
	94	}
	95
ddfe43cd YG	96	static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
	97	{
	98	struct pci_dev *root;
	99	int err = -ENODEV;
	100
	101	if (node >= amd_northbridges.num)
	102	goto out;
	103
	104	root = node_to_amd_nb(node)->root;
	105	if (!root)
	106	goto out;
	107
	108	mutex_lock(&smn_mutex);
	109
	110	err = pci_write_config_dword(root, 0x60, address);
	111	if (err) {
	112	pr_warn("Error programming SMN address 0x%x.\n", address);
	113	goto out_unlock;
	114	}
	115
	116	err = (write ? pci_write_config_dword(root, 0x64, *value)
	117	: pci_read_config_dword(root, 0x64, value));
	118	if (err)
	119	pr_warn("Error %s SMN address 0x%x.\n",
	120	(write ? "writing to" : "reading from"), address);
	121
	122	out_unlock:
	123	mutex_unlock(&smn_mutex);
	124
	125	out:
	126	return err;
	127	}
	128
	129	int amd_smn_read(u16 node, u32 address, u32 *value)
	130	{
	131	return __amd_smn_rw(node, address, value, false);
	132	}
	133	EXPORT_SYMBOL_GPL(amd_smn_read);
	134
	135	int amd_smn_write(u16 node, u32 address, u32 value)
	136	{
	137	return __amd_smn_rw(node, address, &value, true);
	138	}
	139	EXPORT_SYMBOL_GPL(amd_smn_write);
	140
	141	/*
	142	* Data Fabric Indirect Access uses FICAA/FICAD.
	143	*
	144	* Fabric Indirect Configuration Access Address (FICAA): Constructed based
	145	* on the device's Instance Id and the PCI function and register offset of
	146	* the desired register.
	147	*
	148	* Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
	149	* and FICAD HI registers but so far we only need the LO register.
	150	*/
	151	int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
	152	{
	153	struct pci_dev *F4;
	154	u32 ficaa;
	155	int err = -ENODEV;
	156
	157	if (node >= amd_northbridges.num)
	158	goto out;
	159
160	F4 = node_to_amd_nb(node)->link;
161	if (!F4)
162	goto out;
163
164	ficaa = 1;
165	ficaa \|= reg & 0x3FC;
166	ficaa \|= (func & 0x7) << 11;
167	ficaa \|= instance_id << 16;
168
169	mutex_lock(&smn_mutex);
170
171	err = pci_write_config_dword(F4, 0x5C, ficaa);
172	if (err) {
173	pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
174	goto out_unlock;
175	}
176
177	err = pci_read_config_dword(F4, 0x98, lo);
178	if (err)
179	pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
180
181	out_unlock:
182	mutex_unlock(&smn_mutex);
183
184	out:
185	return err;
186	}
187	EXPORT_SYMBOL_GPL(amd_df_indirect_read);
188
9653a5c7	189	int amd_cache_northbridges(void)
a32073bf	190	{
84fd1d35	191	u16 i = 0;
9653a5c7	192	struct amd_northbridge *nb;
ddfe43cd	193	struct pci_dev root, misc, *link;
3c6df2a9	194
c7993890	195	if (amd_northbridges.num)
a32073bf AK	196	return 0;
a32073bf AK	197
9653a5c7 HR	198	misc = NULL;
	199	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
	200	i++;
900f9ac9	201
1ead852d BP	202	if (!i)
1ead852d BP	203	return -ENODEV;
a32073bf	204
de6bd083	205	nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
9653a5c7	206	if (!nb)
a32073bf AK	207	return -ENOMEM;
a32073bf AK	208
9653a5c7 HR	209	amd_northbridges.nb = nb;
9653a5c7 HR	210	amd_northbridges.num = i;
3c6df2a9	211
ddfe43cd	212	link = misc = root = NULL;
c7993890	213	for (i = 0; i != amd_northbridges.num; i++) {
ddfe43cd YG	214	node_to_amd_nb(i)->root = root =
ddfe43cd YG	215	next_northbridge(root, amd_root_ids);
9653a5c7 HR	216	node_to_amd_nb(i)->misc = misc =
9653a5c7 HR	217	next_northbridge(misc, amd_nb_misc_ids);
41b2610c HR	218	node_to_amd_nb(i)->link = link =
41b2610c HR	219	next_northbridge(link, amd_nb_link_ids);
7d64ac64	220	}
9653a5c7	221
1b457429	222	if (amd_gart_present())
9653a5c7	223	amd_northbridges.flags \|= AMD_NB_GART;
a32073bf	224
7d64ac64 AG	225	/*
	226	* Check for L3 cache presence.
	227	*/
	228	if (!cpuid_edx(0x80000006))
	229	return 0;
	230
f658bcfb HR	231	/*
	232	* Some CPU families support L3 Cache Index Disable. There are some
	233	* limitations because of E382 and E388 on family 0x10.
	234	*/
	235	if (boot_cpu_data.x86 == 0x10 &&
	236	boot_cpu_data.x86_model >= 0x8 &&
	237	(boot_cpu_data.x86_model > 0x9 \|\|
	238	boot_cpu_data.x86_mask >= 0x1))
	239	amd_northbridges.flags \|= AMD_NB_L3_INDEX_DISABLE;
	240
b453de02 HR	241	if (boot_cpu_data.x86 == 0x15)
	242	amd_northbridges.flags \|= AMD_NB_L3_INDEX_DISABLE;
	243
cabb5bd7 HR	244	/* L3 cache partitioning is supported on family 0x15 */
	245	if (boot_cpu_data.x86 == 0x15)
	246	amd_northbridges.flags \|= AMD_NB_L3_PARTITIONING;
	247
a32073bf AK	248	return 0;
a32073bf AK	249	}
9653a5c7	250	EXPORT_SYMBOL_GPL(amd_cache_northbridges);
a32073bf	251
84fd1d35 BP	252	/*
	253	* Ignores subdevice/subvendor but as far as I can figure out
	254	* they're useless anyways
	255	*/
	256	bool __init early_is_amd_nb(u32 device)
a32073bf	257	{
691269f0	258	const struct pci_device_id *id;
a32073bf	259	u32 vendor = device & 0xffff;
691269f0	260
a32073bf	261	device >>= 16;
9653a5c7	262	for (id = amd_nb_misc_ids; id->vendor; id++)
a32073bf	263	if (vendor == id->vendor && device == id->device)
84fd1d35 BP	264	return true;
84fd1d35 BP	265	return false;
a32073bf AK	266	}
a32073bf AK	267
24d25dbf BH	268	struct resource amd_get_mmconfig_range(struct resource res)
	269	{
	270	u32 address;
	271	u64 base, msr;
de6bd083	272	unsigned int segn_busn_bits;
24d25dbf BH	273
	274	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	275	return NULL;
	276
	277	/* assume all cpus from fam10h have mmconfig */
de6bd083	278	if (boot_cpu_data.x86 < 0x10)
24d25dbf BH	279	return NULL;
	280
	281	address = MSR_FAM10H_MMIO_CONF_BASE;
	282	rdmsrl(address, msr);
	283
	284	/* mmconfig is not enabled */
	285	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	286	return NULL;
	287
	288	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	289
	290	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	291	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	292
	293	res->flags = IORESOURCE_MEM;
	294	res->start = base;
	295	res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	296	return res;
	297	}
	298
cabb5bd7 HR	299	int amd_get_subcaches(int cpu)
	300	{
	301	struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
	302	unsigned int mask;
cabb5bd7 HR	303
	304	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
	305	return 0;
	306
	307	pci_read_config_dword(link, 0x1d4, &mask);
	308
8196dab4	309	return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
cabb5bd7 HR	310	}
cabb5bd7 HR	311
2993ae33	312	int amd_set_subcaches(int cpu, unsigned long mask)
cabb5bd7 HR	313	{
	314	static unsigned int reset, ban;
	315	struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
	316	unsigned int reg;
141168c3	317	int cuid;
cabb5bd7 HR	318
	319	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) \|\| mask > 0xf)
	320	return -EINVAL;
	321
	322	/* if necessary, collect reset state of L3 partitioning and BAN mode */
	323	if (reset == 0) {
	324	pci_read_config_dword(nb->link, 0x1d4, &reset);
	325	pci_read_config_dword(nb->misc, 0x1b8, &ban);
	326	ban &= 0x180000;
	327	}
	328
	329	/* deactivate BAN mode if any subcaches are to be disabled */
	330	if (mask != 0xf) {
	331	pci_read_config_dword(nb->misc, 0x1b8, &reg);
	332	pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
	333	}
	334
8196dab4	335	cuid = cpu_data(cpu).cpu_core_id;
cabb5bd7 HR	336	mask <<= 4 * cuid;
	337	mask \|= (0xf ^ (1 << cuid)) << 26;
	338
	339	pci_write_config_dword(nb->link, 0x1d4, mask);
	340
	341	/* reset BAN mode if L3 partitioning returned to reset state */
	342	pci_read_config_dword(nb->link, 0x1d4, &reg);
	343	if (reg == reset) {
	344	pci_read_config_dword(nb->misc, 0x1b8, &reg);
	345	reg &= ~0x180000;
	346	pci_write_config_dword(nb->misc, 0x1b8, reg \| ban);
	347	}
	348
	349	return 0;
	350	}
	351
09c6c30e	352	static void amd_cache_gart(void)
9653a5c7	353	{
84fd1d35	354	u16 i;
9653a5c7	355
09c6c30e BP	356	if (!amd_nb_has_feature(AMD_NB_GART))
09c6c30e BP	357	return;
9653a5c7	358
c7993890	359	flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
09c6c30e BP	360	if (!flush_words) {
	361	amd_northbridges.flags &= ~AMD_NB_GART;
	362	pr_notice("Cannot initialize GART flush words, GART support disabled\n");
	363	return;
	364	}
9653a5c7	365
c7993890	366	for (i = 0; i != amd_northbridges.num; i++)
09c6c30e	367	pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
9653a5c7 HR	368	}
9653a5c7 HR	369
eec1d4fa	370	void amd_flush_garts(void)
a32073bf AK	371	{
	372	int flushed, i;
	373	unsigned long flags;
	374	static DEFINE_SPINLOCK(gart_lock);
	375
9653a5c7	376	if (!amd_nb_has_feature(AMD_NB_GART))
900f9ac9 AH	377	return;
900f9ac9 AH	378
de6bd083 YG	379	/*
	380	* Avoid races between AGP and IOMMU. In theory it's not needed
	381	* but I'm not sure if the hardware won't lose flush requests
	382	* when another is pending. This whole thing is so expensive anyways
	383	* that it doesn't matter to serialize more. -AK
	384	*/
a32073bf AK	385	spin_lock_irqsave(&gart_lock, flags);
a32073bf AK	386	flushed = 0;
c7993890	387	for (i = 0; i < amd_northbridges.num; i++) {
9653a5c7 HR	388	pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
9653a5c7 HR	389	flush_words[i] \| 1);
a32073bf AK	390	flushed++;
a32073bf AK	391	}
c7993890	392	for (i = 0; i < amd_northbridges.num; i++) {
a32073bf AK	393	u32 w;
	394	/* Make sure the hardware actually executed the flush*/
	395	for (;;) {
9653a5c7	396	pci_read_config_dword(node_to_amd_nb(i)->misc,
a32073bf AK	397	0x9c, &w);
	398	if (!(w & 1))
	399	break;
	400	cpu_relax();
	401	}
	402	}
	403	spin_unlock_irqrestore(&gart_lock, flags);
	404	if (!flushed)
c767a54b	405	pr_notice("nothing to flush?\n");
a32073bf	406	}
eec1d4fa	407	EXPORT_SYMBOL_GPL(amd_flush_garts);
a32073bf	408
58ccfdba BP	409	static void __fix_erratum_688(void *info)
	410	{
	411	#define MSR_AMD64_IC_CFG 0xC0011021
	412
	413	msr_set_bit(MSR_AMD64_IC_CFG, 3);
	414	msr_set_bit(MSR_AMD64_IC_CFG, 14);
	415	}
	416
	417	/* Apply erratum 688 fix so machines without a BIOS fix work. */
	418	static __init void fix_erratum_688(void)
	419	{
	420	struct pci_dev *F4;
	421	u32 val;
	422
	423	if (boot_cpu_data.x86 != 0x14)
	424	return;
	425
	426	if (!amd_northbridges.num)
	427	return;
	428
	429	F4 = node_to_amd_nb(0)->link;
	430	if (!F4)
	431	return;
	432
	433	if (pci_read_config_dword(F4, 0x164, &val))
	434	return;
	435
	436	if (val & BIT(2))
	437	return;
	438
	439	on_each_cpu(__fix_erratum_688, NULL, 0);
	440
	441	pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
	442	}
	443
eec1d4fa	444	static __init int init_amd_nbs(void)
0e152cd7	445	{
09c6c30e BP	446	amd_cache_northbridges();
09c6c30e BP	447	amd_cache_gart();
0e152cd7	448
58ccfdba BP	449	fix_erratum_688();
58ccfdba BP	450
09c6c30e	451	return 0;
0e152cd7 BP	452	}
	453
	454	/* This has to go after the PCI subsystem */
eec1d4fa	455	fs_initcall(init_amd_nbs);