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bb24c471 JP |
1 | /* |
2 | * apb_timer.c: Driver for Langwell APB timers | |
3 | * | |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * Note: | |
13 | * Langwell is the south complex of Intel Moorestown MID platform. There are | |
14 | * eight external timers in total that can be used by the operating system. | |
15 | * The timer information, such as frequency and addresses, is provided to the | |
16 | * OS via SFI tables. | |
17 | * Timer interrupts are routed via FW/HW emulated IOAPIC independently via | |
18 | * individual redirection table entries (RTE). | |
19 | * Unlike HPET, there is no master counter, therefore one of the timers are | |
20 | * used as clocksource. The overall allocation looks like: | |
21 | * - timer 0 - NR_CPUs for per cpu timer | |
22 | * - one timer for clocksource | |
23 | * - one timer for watchdog driver. | |
24 | * It is also worth notice that APB timer does not support true one-shot mode, | |
25 | * free-running mode will be used here to emulate one-shot mode. | |
26 | * APB timer can also be used as broadcast timer along with per cpu local APIC | |
27 | * timer, but by default APB timer has higher rating than local APIC timers. | |
28 | */ | |
29 | ||
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/sysdev.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bb24c471 JP |
37 | #include <linux/pm.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/sfi.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/cpu.h> | |
42 | #include <linux/irq.h> | |
43 | ||
44 | #include <asm/fixmap.h> | |
45 | #include <asm/apb_timer.h> | |
a875c019 | 46 | #include <asm/mrst.h> |
bb24c471 | 47 | |
c7bbf52a PA |
48 | #define APBT_MASK CLOCKSOURCE_MASK(32) |
49 | #define APBT_SHIFT 22 | |
a875c019 | 50 | #define APBT_CLOCKEVENT_RATING 110 |
c7bbf52a PA |
51 | #define APBT_CLOCKSOURCE_RATING 250 |
52 | #define APBT_MIN_DELTA_USEC 200 | |
bb24c471 JP |
53 | |
54 | #define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt) | |
55 | #define APBT_CLOCKEVENT0_NUM (0) | |
56 | #define APBT_CLOCKEVENT1_NUM (1) | |
57 | #define APBT_CLOCKSOURCE_NUM (2) | |
58 | ||
59 | static unsigned long apbt_address; | |
60 | static int apb_timer_block_enabled; | |
61 | static void __iomem *apbt_virt_address; | |
62 | static int phy_cs_timer_id; | |
63 | ||
64 | /* | |
65 | * Common DW APB timer info | |
66 | */ | |
67 | static uint64_t apbt_freq; | |
68 | ||
69 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 70 | struct clock_event_device *evt); |
bb24c471 | 71 | static int apbt_next_event(unsigned long delta, |
c7bbf52a | 72 | struct clock_event_device *evt); |
bb24c471 | 73 | static cycle_t apbt_read_clocksource(struct clocksource *cs); |
322aafa6 | 74 | static void apbt_restart_clocksource(struct clocksource *cs); |
bb24c471 JP |
75 | |
76 | struct apbt_dev { | |
c7bbf52a PA |
77 | struct clock_event_device evt; |
78 | unsigned int num; | |
79 | int cpu; | |
80 | unsigned int irq; | |
81 | unsigned int tick; | |
82 | unsigned int count; | |
83 | unsigned int flags; | |
84 | char name[10]; | |
bb24c471 JP |
85 | }; |
86 | ||
3010673e JP |
87 | static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev); |
88 | ||
bb24c471 JP |
89 | #ifdef CONFIG_SMP |
90 | static unsigned int apbt_num_timers_used; | |
bb24c471 JP |
91 | static struct apbt_dev *apbt_devs; |
92 | #endif | |
93 | ||
c7bbf52a | 94 | static inline unsigned long apbt_readl_reg(unsigned long a) |
bb24c471 | 95 | { |
c7bbf52a | 96 | return readl(apbt_virt_address + a); |
bb24c471 JP |
97 | } |
98 | ||
99 | static inline void apbt_writel_reg(unsigned long d, unsigned long a) | |
100 | { | |
c7bbf52a | 101 | writel(d, apbt_virt_address + a); |
bb24c471 JP |
102 | } |
103 | ||
104 | static inline unsigned long apbt_readl(int n, unsigned long a) | |
105 | { | |
c7bbf52a | 106 | return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
107 | } |
108 | ||
109 | static inline void apbt_writel(int n, unsigned long d, unsigned long a) | |
110 | { | |
c7bbf52a | 111 | writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
112 | } |
113 | ||
114 | static inline void apbt_set_mapping(void) | |
115 | { | |
c7bbf52a PA |
116 | struct sfi_timer_table_entry *mtmr; |
117 | ||
118 | if (apbt_virt_address) { | |
119 | pr_debug("APBT base already mapped\n"); | |
120 | return; | |
121 | } | |
122 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
123 | if (mtmr == NULL) { | |
124 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
125 | APBT_CLOCKEVENT0_NUM); | |
126 | return; | |
127 | } | |
128 | apbt_address = (unsigned long)mtmr->phys_addr; | |
129 | if (!apbt_address) { | |
130 | printk(KERN_WARNING "No timer base from SFI, use default\n"); | |
131 | apbt_address = APBT_DEFAULT_BASE; | |
132 | } | |
133 | apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE); | |
134 | if (apbt_virt_address) { | |
135 | pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\ | |
136 | (void *)apbt_address, (void *)apbt_virt_address); | |
137 | } else { | |
138 | pr_debug("Failed mapping APBT phy address at %p\n",\ | |
139 | (void *)apbt_address); | |
140 | goto panic_noapbt; | |
141 | } | |
142 | apbt_freq = mtmr->freq_hz / USEC_PER_SEC; | |
143 | sfi_free_mtmr(mtmr); | |
144 | ||
145 | /* Now figure out the physical timer id for clocksource device */ | |
146 | mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM); | |
147 | if (mtmr == NULL) | |
148 | goto panic_noapbt; | |
149 | ||
150 | /* Now figure out the physical timer id */ | |
151 | phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) | |
152 | / APBTMRS_REG_SIZE; | |
153 | pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id); | |
154 | return; | |
bb24c471 JP |
155 | |
156 | panic_noapbt: | |
c7bbf52a | 157 | panic("Failed to setup APB system timer\n"); |
bb24c471 JP |
158 | |
159 | } | |
160 | ||
161 | static inline void apbt_clear_mapping(void) | |
162 | { | |
c7bbf52a PA |
163 | iounmap(apbt_virt_address); |
164 | apbt_virt_address = NULL; | |
bb24c471 JP |
165 | } |
166 | ||
167 | /* | |
168 | * APBT timer interrupt enable / disable | |
169 | */ | |
170 | static inline int is_apbt_capable(void) | |
171 | { | |
c7bbf52a | 172 | return apbt_virt_address ? 1 : 0; |
bb24c471 JP |
173 | } |
174 | ||
175 | static struct clocksource clocksource_apbt = { | |
c7bbf52a PA |
176 | .name = "apbt", |
177 | .rating = APBT_CLOCKSOURCE_RATING, | |
178 | .read = apbt_read_clocksource, | |
179 | .mask = APBT_MASK, | |
180 | .shift = APBT_SHIFT, | |
181 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
182 | .resume = apbt_restart_clocksource, | |
bb24c471 JP |
183 | }; |
184 | ||
185 | /* boot APB clock event device */ | |
186 | static struct clock_event_device apbt_clockevent = { | |
c7bbf52a PA |
187 | .name = "apbt0", |
188 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
189 | .set_mode = apbt_set_mode, | |
190 | .set_next_event = apbt_next_event, | |
191 | .shift = APBT_SHIFT, | |
192 | .irq = 0, | |
193 | .rating = APBT_CLOCKEVENT_RATING, | |
bb24c471 JP |
194 | }; |
195 | ||
bb24c471 JP |
196 | /* |
197 | * start count down from 0xffff_ffff. this is done by toggling the enable bit | |
198 | * then load initial load count to ~0. | |
199 | */ | |
200 | static void apbt_start_counter(int n) | |
201 | { | |
c7bbf52a PA |
202 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
203 | ||
204 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
205 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
206 | apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT); | |
207 | /* enable, mask interrupt */ | |
208 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
209 | ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); | |
210 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
211 | /* read it once to get cached counter value initialized */ | |
212 | apbt_read_clocksource(&clocksource_apbt); | |
bb24c471 JP |
213 | } |
214 | ||
215 | static irqreturn_t apbt_interrupt_handler(int irq, void *data) | |
216 | { | |
c7bbf52a PA |
217 | struct apbt_dev *dev = (struct apbt_dev *)data; |
218 | struct clock_event_device *aevt = &dev->evt; | |
219 | ||
220 | if (!aevt->event_handler) { | |
221 | printk(KERN_INFO "Spurious APBT timer interrupt on %d\n", | |
222 | dev->num); | |
223 | return IRQ_NONE; | |
224 | } | |
225 | aevt->event_handler(aevt); | |
226 | return IRQ_HANDLED; | |
bb24c471 JP |
227 | } |
228 | ||
322aafa6 | 229 | static void apbt_restart_clocksource(struct clocksource *cs) |
bb24c471 | 230 | { |
c7bbf52a | 231 | apbt_start_counter(phy_cs_timer_id); |
bb24c471 JP |
232 | } |
233 | ||
234 | /* Setup IRQ routing via IOAPIC */ | |
235 | #ifdef CONFIG_SMP | |
236 | static void apbt_setup_irq(struct apbt_dev *adev) | |
237 | { | |
c7bbf52a PA |
238 | struct irq_chip *chip; |
239 | struct irq_desc *desc; | |
240 | ||
241 | /* timer0 irq has been setup early */ | |
242 | if (adev->irq == 0) | |
243 | return; | |
244 | desc = irq_to_desc(adev->irq); | |
245 | chip = get_irq_chip(adev->irq); | |
246 | disable_irq(adev->irq); | |
247 | desc->status |= IRQ_MOVE_PCNTXT; | |
248 | irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); | |
249 | /* APB timer irqs are set up as mp_irqs, timer is edge triggerred */ | |
250 | set_irq_chip_and_handler_name(adev->irq, chip, handle_edge_irq, "edge"); | |
251 | enable_irq(adev->irq); | |
252 | if (system_state == SYSTEM_BOOTING) | |
253 | if (request_irq(adev->irq, apbt_interrupt_handler, | |
254 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
255 | adev->name, adev)) { | |
256 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
257 | adev->num); | |
258 | } | |
bb24c471 JP |
259 | } |
260 | #endif | |
261 | ||
262 | static void apbt_enable_int(int n) | |
263 | { | |
c7bbf52a PA |
264 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
265 | /* clear pending intr */ | |
266 | apbt_readl(n, APBTMR_N_EOI); | |
267 | ctrl &= ~APBTMR_CONTROL_INT; | |
268 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
269 | } |
270 | ||
271 | static void apbt_disable_int(int n) | |
272 | { | |
c7bbf52a | 273 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
bb24c471 | 274 | |
c7bbf52a PA |
275 | ctrl |= APBTMR_CONTROL_INT; |
276 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
277 | } |
278 | ||
279 | ||
280 | static int __init apbt_clockevent_register(void) | |
281 | { | |
c7bbf52a PA |
282 | struct sfi_timer_table_entry *mtmr; |
283 | struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev); | |
284 | ||
285 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
286 | if (mtmr == NULL) { | |
287 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
288 | APBT_CLOCKEVENT0_NUM); | |
289 | return -ENODEV; | |
290 | } | |
291 | ||
292 | /* | |
293 | * We need to calculate the scaled math multiplication factor for | |
294 | * nanosecond to apbt tick conversion. | |
295 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
296 | */ | |
297 | apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz | |
298 | , NSEC_PER_SEC, APBT_SHIFT); | |
299 | ||
300 | /* Calculate the min / max delta */ | |
301 | apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
302 | &apbt_clockevent); | |
303 | apbt_clockevent.min_delta_ns = clockevent_delta2ns( | |
304 | APBT_MIN_DELTA_USEC*apbt_freq, | |
305 | &apbt_clockevent); | |
306 | /* | |
307 | * Start apbt with the boot cpu mask and make it | |
308 | * global if not used for per cpu timer. | |
309 | */ | |
310 | apbt_clockevent.cpumask = cpumask_of(smp_processor_id()); | |
311 | adev->num = smp_processor_id(); | |
312 | memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device)); | |
313 | ||
a875c019 | 314 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { |
c7bbf52a | 315 | apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100; |
3010673e | 316 | global_clock_event = &adev->evt; |
c7bbf52a PA |
317 | printk(KERN_DEBUG "%s clockevent registered as global\n", |
318 | global_clock_event->name); | |
319 | } | |
320 | ||
321 | if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler, | |
322 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
323 | apbt_clockevent.name, adev)) { | |
324 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
325 | apbt_clockevent.irq); | |
326 | } | |
327 | ||
328 | clockevents_register_device(&adev->evt); | |
329 | /* Start APBT 0 interrupts */ | |
330 | apbt_enable_int(APBT_CLOCKEVENT0_NUM); | |
331 | ||
332 | sfi_free_mtmr(mtmr); | |
333 | return 0; | |
bb24c471 JP |
334 | } |
335 | ||
336 | #ifdef CONFIG_SMP | |
337 | /* Should be called with per cpu */ | |
338 | void apbt_setup_secondary_clock(void) | |
339 | { | |
c7bbf52a PA |
340 | struct apbt_dev *adev; |
341 | struct clock_event_device *aevt; | |
342 | int cpu; | |
343 | ||
344 | /* Don't register boot CPU clockevent */ | |
345 | cpu = smp_processor_id(); | |
f6e9456c | 346 | if (!cpu) |
c7bbf52a PA |
347 | return; |
348 | /* | |
349 | * We need to calculate the scaled math multiplication factor for | |
350 | * nanosecond to apbt tick conversion. | |
351 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
352 | */ | |
353 | printk(KERN_INFO "Init per CPU clockevent %d\n", cpu); | |
354 | adev = &per_cpu(cpu_apbt_dev, cpu); | |
355 | aevt = &adev->evt; | |
356 | ||
357 | memcpy(aevt, &apbt_clockevent, sizeof(*aevt)); | |
358 | aevt->cpumask = cpumask_of(cpu); | |
359 | aevt->name = adev->name; | |
360 | aevt->mode = CLOCK_EVT_MODE_UNUSED; | |
361 | ||
362 | printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n", | |
363 | cpu, aevt->name, *(u32 *)aevt->cpumask); | |
364 | ||
365 | apbt_setup_irq(adev); | |
366 | ||
367 | clockevents_register_device(aevt); | |
368 | ||
369 | apbt_enable_int(cpu); | |
370 | ||
371 | return; | |
bb24c471 JP |
372 | } |
373 | ||
374 | /* | |
375 | * this notify handler process CPU hotplug events. in case of S0i3, nonboot | |
376 | * cpus are disabled/enabled frequently, for performance reasons, we keep the | |
377 | * per cpu timer irq registered so that we do need to do free_irq/request_irq. | |
378 | * | |
379 | * TODO: it might be more reliable to directly disable percpu clockevent device | |
380 | * without the notifier chain. currently, cpu 0 may get interrupts from other | |
381 | * cpu timers during the offline process due to the ordering of notification. | |
382 | * the extra interrupt is harmless. | |
383 | */ | |
384 | static int apbt_cpuhp_notify(struct notifier_block *n, | |
c7bbf52a | 385 | unsigned long action, void *hcpu) |
bb24c471 | 386 | { |
c7bbf52a PA |
387 | unsigned long cpu = (unsigned long)hcpu; |
388 | struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu); | |
389 | ||
390 | switch (action & 0xf) { | |
391 | case CPU_DEAD: | |
392 | apbt_disable_int(cpu); | |
393 | if (system_state == SYSTEM_RUNNING) | |
394 | pr_debug("skipping APBT CPU %lu offline\n", cpu); | |
395 | else if (adev) { | |
396 | pr_debug("APBT clockevent for cpu %lu offline\n", cpu); | |
397 | free_irq(adev->irq, adev); | |
398 | } | |
399 | break; | |
400 | default: | |
401 | pr_debug(KERN_INFO "APBT notified %lu, no action\n", action); | |
402 | } | |
403 | return NOTIFY_OK; | |
bb24c471 JP |
404 | } |
405 | ||
406 | static __init int apbt_late_init(void) | |
407 | { | |
a875c019 JP |
408 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT || |
409 | !apb_timer_block_enabled) | |
c7bbf52a PA |
410 | return 0; |
411 | /* This notifier should be called after workqueue is ready */ | |
412 | hotcpu_notifier(apbt_cpuhp_notify, -20); | |
413 | return 0; | |
bb24c471 JP |
414 | } |
415 | fs_initcall(apbt_late_init); | |
416 | #else | |
417 | ||
418 | void apbt_setup_secondary_clock(void) {} | |
419 | ||
420 | #endif /* CONFIG_SMP */ | |
421 | ||
422 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 423 | struct clock_event_device *evt) |
bb24c471 | 424 | { |
c7bbf52a PA |
425 | unsigned long ctrl; |
426 | uint64_t delta; | |
427 | int timer_num; | |
428 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
429 | ||
a875c019 JP |
430 | BUG_ON(!apbt_virt_address); |
431 | ||
c7bbf52a PA |
432 | timer_num = adev->num; |
433 | pr_debug("%s CPU %d timer %d mode=%d\n", | |
434 | __func__, first_cpu(*evt->cpumask), timer_num, mode); | |
435 | ||
436 | switch (mode) { | |
437 | case CLOCK_EVT_MODE_PERIODIC: | |
438 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult; | |
439 | delta >>= apbt_clockevent.shift; | |
440 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
441 | ctrl |= APBTMR_CONTROL_MODE_PERIODIC; | |
442 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
443 | /* | |
444 | * DW APB p. 46, have to disable timer before load counter, | |
445 | * may cause sync problem. | |
446 | */ | |
447 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
448 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
449 | udelay(1); | |
450 | pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ); | |
451 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
452 | ctrl |= APBTMR_CONTROL_ENABLE; | |
453 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
454 | break; | |
455 | /* APB timer does not have one-shot mode, use free running mode */ | |
456 | case CLOCK_EVT_MODE_ONESHOT: | |
457 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
458 | /* | |
459 | * set free running mode, this mode will let timer reload max | |
460 | * timeout which will give time (3min on 25MHz clock) to rearm | |
461 | * the next event, therefore emulate the one-shot mode. | |
462 | */ | |
463 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
464 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
465 | ||
466 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
467 | /* write again to set free running mode */ | |
468 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
469 | ||
470 | /* | |
471 | * DW APB p. 46, load counter with all 1s before starting free | |
472 | * running mode. | |
473 | */ | |
474 | apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT); | |
475 | ctrl &= ~APBTMR_CONTROL_INT; | |
476 | ctrl |= APBTMR_CONTROL_ENABLE; | |
477 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
478 | break; | |
479 | ||
480 | case CLOCK_EVT_MODE_UNUSED: | |
481 | case CLOCK_EVT_MODE_SHUTDOWN: | |
482 | apbt_disable_int(timer_num); | |
483 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
484 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
485 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
486 | break; | |
487 | ||
488 | case CLOCK_EVT_MODE_RESUME: | |
489 | apbt_enable_int(timer_num); | |
490 | break; | |
491 | } | |
bb24c471 JP |
492 | } |
493 | ||
494 | static int apbt_next_event(unsigned long delta, | |
c7bbf52a | 495 | struct clock_event_device *evt) |
bb24c471 | 496 | { |
c7bbf52a PA |
497 | unsigned long ctrl; |
498 | int timer_num; | |
499 | ||
500 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
501 | ||
502 | timer_num = adev->num; | |
503 | /* Disable timer */ | |
504 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
505 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
506 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
507 | /* write new count */ | |
508 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
509 | ctrl |= APBTMR_CONTROL_ENABLE; | |
510 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
511 | return 0; | |
bb24c471 JP |
512 | } |
513 | ||
514 | /* | |
515 | * APB timer clock is not in sync with pclk on Langwell, which translates to | |
516 | * unreliable read value caused by sampling error. the error does not add up | |
517 | * overtime and only happens when sampling a 0 as a 1 by mistake. so the time | |
518 | * would go backwards. the following code is trying to prevent time traveling | |
519 | * backwards. little bit paranoid. | |
520 | */ | |
521 | static cycle_t apbt_read_clocksource(struct clocksource *cs) | |
522 | { | |
c7bbf52a PA |
523 | unsigned long t0, t1, t2; |
524 | static unsigned long last_read; | |
bb24c471 JP |
525 | |
526 | bad_count: | |
c7bbf52a PA |
527 | t1 = apbt_readl(phy_cs_timer_id, |
528 | APBTMR_N_CURRENT_VALUE); | |
529 | t2 = apbt_readl(phy_cs_timer_id, | |
530 | APBTMR_N_CURRENT_VALUE); | |
531 | if (unlikely(t1 < t2)) { | |
532 | pr_debug("APBT: read current count error %lx:%lx:%lx\n", | |
533 | t1, t2, t2 - t1); | |
534 | goto bad_count; | |
535 | } | |
536 | /* | |
537 | * check against cached last read, makes sure time does not go back. | |
538 | * it could be a normal rollover but we will do tripple check anyway | |
539 | */ | |
540 | if (unlikely(t2 > last_read)) { | |
541 | /* check if we have a normal rollover */ | |
542 | unsigned long raw_intr_status = | |
543 | apbt_readl_reg(APBTMRS_RAW_INT_STATUS); | |
544 | /* | |
545 | * cs timer interrupt is masked but raw intr bit is set if | |
546 | * rollover occurs. then we read EOI reg to clear it. | |
547 | */ | |
548 | if (raw_intr_status & (1 << phy_cs_timer_id)) { | |
549 | apbt_readl(phy_cs_timer_id, APBTMR_N_EOI); | |
550 | goto out; | |
551 | } | |
552 | pr_debug("APB CS going back %lx:%lx:%lx ", | |
553 | t2, last_read, t2 - last_read); | |
bb24c471 | 554 | bad_count_x3: |
c7bbf52a PA |
555 | pr_debug(KERN_INFO "tripple check enforced\n"); |
556 | t0 = apbt_readl(phy_cs_timer_id, | |
557 | APBTMR_N_CURRENT_VALUE); | |
558 | udelay(1); | |
559 | t1 = apbt_readl(phy_cs_timer_id, | |
560 | APBTMR_N_CURRENT_VALUE); | |
561 | udelay(1); | |
562 | t2 = apbt_readl(phy_cs_timer_id, | |
563 | APBTMR_N_CURRENT_VALUE); | |
564 | if ((t2 > t1) || (t1 > t0)) { | |
565 | printk(KERN_ERR "Error: APB CS tripple check failed\n"); | |
566 | goto bad_count_x3; | |
567 | } | |
568 | } | |
bb24c471 | 569 | out: |
c7bbf52a PA |
570 | last_read = t2; |
571 | return (cycle_t)~t2; | |
bb24c471 JP |
572 | } |
573 | ||
574 | static int apbt_clocksource_register(void) | |
575 | { | |
c7bbf52a PA |
576 | u64 start, now; |
577 | cycle_t t1; | |
578 | ||
579 | /* Start the counter, use timer 2 as source, timer 0/1 for event */ | |
580 | apbt_start_counter(phy_cs_timer_id); | |
581 | ||
582 | /* Verify whether apbt counter works */ | |
583 | t1 = apbt_read_clocksource(&clocksource_apbt); | |
584 | rdtscll(start); | |
585 | ||
586 | /* | |
587 | * We don't know the TSC frequency yet, but waiting for | |
588 | * 200000 TSC cycles is safe: | |
589 | * 4 GHz == 50us | |
590 | * 1 GHz == 200us | |
591 | */ | |
592 | do { | |
593 | rep_nop(); | |
594 | rdtscll(now); | |
595 | } while ((now - start) < 200000UL); | |
596 | ||
597 | /* APBT is the only always on clocksource, it has to work! */ | |
598 | if (t1 == apbt_read_clocksource(&clocksource_apbt)) | |
599 | panic("APBT counter not counting. APBT disabled\n"); | |
600 | ||
601 | /* | |
602 | * initialize and register APBT clocksource | |
603 | * convert that to ns/clock cycle | |
604 | * mult = (ns/c) * 2^APBT_SHIFT | |
605 | */ | |
606 | clocksource_apbt.mult = div_sc(MSEC_PER_SEC, | |
607 | (unsigned long) apbt_freq, APBT_SHIFT); | |
608 | clocksource_register(&clocksource_apbt); | |
609 | ||
610 | return 0; | |
bb24c471 JP |
611 | } |
612 | ||
613 | /* | |
614 | * Early setup the APBT timer, only use timer 0 for booting then switch to | |
615 | * per CPU timer if possible. | |
616 | * returns 1 if per cpu apbt is setup | |
617 | * returns 0 if no per cpu apbt is chosen | |
618 | * panic if set up failed, this is the only platform timer on Moorestown. | |
619 | */ | |
620 | void __init apbt_time_init(void) | |
621 | { | |
622 | #ifdef CONFIG_SMP | |
c7bbf52a PA |
623 | int i; |
624 | struct sfi_timer_table_entry *p_mtmr; | |
625 | unsigned int percpu_timer; | |
626 | struct apbt_dev *adev; | |
bb24c471 JP |
627 | #endif |
628 | ||
c7bbf52a PA |
629 | if (apb_timer_block_enabled) |
630 | return; | |
631 | apbt_set_mapping(); | |
632 | if (apbt_virt_address) { | |
633 | pr_debug("Found APBT version 0x%lx\n",\ | |
634 | apbt_readl_reg(APBTMRS_COMP_VERSION)); | |
635 | } else | |
636 | goto out_noapbt; | |
637 | /* | |
638 | * Read the frequency and check for a sane value, for ESL model | |
639 | * we extend the possible clock range to allow time scaling. | |
640 | */ | |
641 | ||
642 | if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) { | |
643 | pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq); | |
644 | goto out_noapbt; | |
645 | } | |
646 | if (apbt_clocksource_register()) { | |
647 | pr_debug("APBT has failed to register clocksource\n"); | |
648 | goto out_noapbt; | |
649 | } | |
650 | if (!apbt_clockevent_register()) | |
651 | apb_timer_block_enabled = 1; | |
652 | else { | |
653 | pr_debug("APBT has failed to register clockevent\n"); | |
654 | goto out_noapbt; | |
655 | } | |
bb24c471 | 656 | #ifdef CONFIG_SMP |
c7bbf52a | 657 | /* kernel cmdline disable apb timer, so we will use lapic timers */ |
a875c019 | 658 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { |
c7bbf52a PA |
659 | printk(KERN_INFO "apbt: disabled per cpu timer\n"); |
660 | return; | |
661 | } | |
662 | pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus()); | |
663 | if (num_possible_cpus() <= sfi_mtimer_num) { | |
664 | percpu_timer = 1; | |
665 | apbt_num_timers_used = num_possible_cpus(); | |
666 | } else { | |
667 | percpu_timer = 0; | |
668 | apbt_num_timers_used = 1; | |
669 | adev = &per_cpu(cpu_apbt_dev, 0); | |
670 | adev->flags &= ~APBT_DEV_USED; | |
671 | } | |
672 | pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used); | |
673 | ||
674 | /* here we set up per CPU timer data structure */ | |
675 | apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used, | |
676 | GFP_KERNEL); | |
677 | if (!apbt_devs) { | |
678 | printk(KERN_ERR "Failed to allocate APB timer devices\n"); | |
679 | return; | |
680 | } | |
681 | for (i = 0; i < apbt_num_timers_used; i++) { | |
682 | adev = &per_cpu(cpu_apbt_dev, i); | |
683 | adev->num = i; | |
684 | adev->cpu = i; | |
685 | p_mtmr = sfi_get_mtmr(i); | |
686 | if (p_mtmr) { | |
687 | adev->tick = p_mtmr->freq_hz; | |
688 | adev->irq = p_mtmr->irq; | |
689 | } else | |
690 | printk(KERN_ERR "Failed to get timer for cpu %d\n", i); | |
691 | adev->count = 0; | |
692 | sprintf(adev->name, "apbt%d", i); | |
693 | } | |
bb24c471 JP |
694 | #endif |
695 | ||
c7bbf52a | 696 | return; |
bb24c471 JP |
697 | |
698 | out_noapbt: | |
c7bbf52a PA |
699 | apbt_clear_mapping(); |
700 | apb_timer_block_enabled = 0; | |
701 | panic("failed to enable APB timer\n"); | |
bb24c471 JP |
702 | } |
703 | ||
704 | static inline void apbt_disable(int n) | |
705 | { | |
c7bbf52a PA |
706 | if (is_apbt_capable()) { |
707 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); | |
708 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
709 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
710 | } | |
bb24c471 JP |
711 | } |
712 | ||
713 | /* called before apb_timer_enable, use early map */ | |
714 | unsigned long apbt_quick_calibrate() | |
715 | { | |
c7bbf52a PA |
716 | int i, scale; |
717 | u64 old, new; | |
718 | cycle_t t1, t2; | |
719 | unsigned long khz = 0; | |
720 | u32 loop, shift; | |
721 | ||
722 | apbt_set_mapping(); | |
723 | apbt_start_counter(phy_cs_timer_id); | |
724 | ||
725 | /* check if the timer can count down, otherwise return */ | |
726 | old = apbt_read_clocksource(&clocksource_apbt); | |
727 | i = 10000; | |
728 | while (--i) { | |
729 | if (old != apbt_read_clocksource(&clocksource_apbt)) | |
730 | break; | |
731 | } | |
732 | if (!i) | |
733 | goto failed; | |
734 | ||
735 | /* count 16 ms */ | |
736 | loop = (apbt_freq * 1000) << 4; | |
737 | ||
738 | /* restart the timer to ensure it won't get to 0 in the calibration */ | |
739 | apbt_start_counter(phy_cs_timer_id); | |
740 | ||
741 | old = apbt_read_clocksource(&clocksource_apbt); | |
742 | old += loop; | |
743 | ||
744 | t1 = __native_read_tsc(); | |
745 | ||
746 | do { | |
747 | new = apbt_read_clocksource(&clocksource_apbt); | |
748 | } while (new < old); | |
749 | ||
750 | t2 = __native_read_tsc(); | |
751 | ||
752 | shift = 5; | |
753 | if (unlikely(loop >> shift == 0)) { | |
754 | printk(KERN_INFO | |
755 | "APBT TSC calibration failed, not enough resolution\n"); | |
756 | return 0; | |
757 | } | |
758 | scale = (int)div_u64((t2 - t1), loop >> shift); | |
759 | khz = (scale * apbt_freq * 1000) >> shift; | |
760 | printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); | |
761 | return khz; | |
bb24c471 | 762 | failed: |
c7bbf52a | 763 | return 0; |
bb24c471 | 764 | } |