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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c140df97 | 2 | /* |
1da177e4 | 3 | * Firmware replacement code. |
c140df97 | 4 | * |
8caac563 PM |
5 | * Work around broken BIOSes that don't set an aperture, only set the |
6 | * aperture in the AGP bridge, or set too small aperture. | |
7 | * | |
c140df97 IM |
8 | * If all fails map the aperture over some low memory. This is cheaper than |
9 | * doing bounce buffering. The memory is lost. This is done at early boot | |
10 | * because only the bootmem allocator can allocate 32+MB. | |
11 | * | |
1da177e4 | 12 | * Copyright 2002 Andi Kleen, SuSE Labs. |
1da177e4 | 13 | */ |
a5d3244a BH |
14 | #define pr_fmt(fmt) "AGP: " fmt |
15 | ||
1da177e4 | 16 | #include <linux/kernel.h> |
ffc8599a | 17 | #include <linux/kcore.h> |
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/init.h> | |
32e3f2b0 | 20 | #include <linux/memblock.h> |
1da177e4 LT |
21 | #include <linux/mmzone.h> |
22 | #include <linux/pci_ids.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/bitops.h> | |
2050d45d | 25 | #include <linux/suspend.h> |
66441bd3 | 26 | #include <asm/e820/api.h> |
1da177e4 | 27 | #include <asm/io.h> |
46a7fa27 | 28 | #include <asm/iommu.h> |
395624fc | 29 | #include <asm/gart.h> |
1da177e4 | 30 | #include <asm/pci-direct.h> |
ca8642f6 | 31 | #include <asm/dma.h> |
23ac4ae8 | 32 | #include <asm/amd_nb.h> |
de957628 | 33 | #include <asm/x86_init.h> |
2a3e83c6 | 34 | #include <linux/crash_dump.h> |
1da177e4 | 35 | |
c387aa3a JR |
36 | /* |
37 | * Using 512M as goal, in case kexec will load kernel_big | |
38 | * that will do the on-position decompress, and could overlap with | |
39 | * with the gart aperture that is used. | |
40 | * Sequence: | |
41 | * kernel_small | |
42 | * ==> kexec (with kdump trigger path or gart still enabled) | |
43 | * ==> kernel_small (gart area become e820_reserved) | |
44 | * ==> kexec (with kdump trigger path or gart still enabled) | |
45 | * ==> kerne_big (uncompressed size will be big than 64M or 128M) | |
46 | * So don't use 512M below as gart iommu, leave the space for kernel | |
47 | * code for safe. | |
48 | */ | |
49 | #define GART_MIN_ADDR (512ULL << 20) | |
50 | #define GART_MAX_ADDR (1ULL << 32) | |
51 | ||
0440d4c0 | 52 | int gart_iommu_aperture; |
7de6a4cd PM |
53 | int gart_iommu_aperture_disabled __initdata; |
54 | int gart_iommu_aperture_allowed __initdata; | |
1da177e4 LT |
55 | |
56 | int fallback_aper_order __initdata = 1; /* 64MB */ | |
7de6a4cd | 57 | int fallback_aper_force __initdata; |
1da177e4 LT |
58 | |
59 | int fix_aperture __initdata = 1; | |
60 | ||
ffc8599a | 61 | #if defined(CONFIG_PROC_VMCORE) || defined(CONFIG_PROC_KCORE) |
2a3e83c6 JB |
62 | /* |
63 | * If the first kernel maps the aperture over e820 RAM, the kdump kernel will | |
64 | * use the same range because it will remain configured in the northbridge. | |
65 | * Trying to dump this area via /proc/vmcore may crash the machine, so exclude | |
66 | * it from vmcore. | |
67 | */ | |
68 | static unsigned long aperture_pfn_start, aperture_page_count; | |
69 | ||
ffc8599a | 70 | static int gart_mem_pfn_is_ram(unsigned long pfn) |
2a3e83c6 JB |
71 | { |
72 | return likely((pfn < aperture_pfn_start) || | |
73 | (pfn >= aperture_pfn_start + aperture_page_count)); | |
74 | } | |
75 | ||
ffc8599a | 76 | static void __init exclude_from_core(u64 aper_base, u32 aper_order) |
2a3e83c6 JB |
77 | { |
78 | aperture_pfn_start = aper_base >> PAGE_SHIFT; | |
79 | aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT; | |
ffc8599a KS |
80 | #ifdef CONFIG_PROC_VMCORE |
81 | WARN_ON(register_oldmem_pfn_is_ram(&gart_mem_pfn_is_ram)); | |
82 | #endif | |
83 | #ifdef CONFIG_PROC_KCORE | |
84 | WARN_ON(register_mem_pfn_is_ram(&gart_mem_pfn_is_ram)); | |
85 | #endif | |
2a3e83c6 JB |
86 | } |
87 | #else | |
ffc8599a | 88 | static void exclude_from_core(u64 aper_base, u32 aper_order) |
2a3e83c6 JB |
89 | { |
90 | } | |
91 | #endif | |
92 | ||
42442ed5 AM |
93 | /* This code runs before the PCI subsystem is initialized, so just |
94 | access the northbridge directly. */ | |
1da177e4 | 95 | |
c140df97 | 96 | static u32 __init allocate_aperture(void) |
1da177e4 | 97 | { |
1da177e4 | 98 | u32 aper_size; |
32e3f2b0 | 99 | unsigned long addr; |
1da177e4 | 100 | |
7677b2ef YL |
101 | /* aper_size should <= 1G */ |
102 | if (fallback_aper_order > 5) | |
103 | fallback_aper_order = 5; | |
c140df97 | 104 | aper_size = (32 * 1024 * 1024) << fallback_aper_order; |
1da177e4 | 105 | |
c140df97 IM |
106 | /* |
107 | * Aperture has to be naturally aligned. This means a 2GB aperture | |
108 | * won't have much chance of finding a place in the lower 4GB of | |
109 | * memory. Unfortunately we cannot move it up because that would | |
110 | * make the IOMMU useless. | |
1da177e4 | 111 | */ |
a7259df7 MR |
112 | addr = memblock_phys_alloc_range(aper_size, aper_size, |
113 | GART_MIN_ADDR, GART_MAX_ADDR); | |
26bfc540 | 114 | if (!addr) { |
c96ec953 BH |
115 | pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n", |
116 | addr, addr + aper_size - 1, aper_size >> 10); | |
32e3f2b0 YL |
117 | return 0; |
118 | } | |
c96ec953 BH |
119 | pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n", |
120 | addr, addr + aper_size - 1, aper_size >> 10); | |
32e3f2b0 YL |
121 | register_nosave_region(addr >> PAGE_SHIFT, |
122 | (addr+aper_size) >> PAGE_SHIFT); | |
c140df97 | 123 | |
32e3f2b0 | 124 | return (u32)addr; |
1da177e4 LT |
125 | } |
126 | ||
1da177e4 | 127 | |
1da177e4 | 128 | /* Read a standard AGPv3 bridge header */ |
dd564d0c | 129 | static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) |
c140df97 | 130 | { |
1da177e4 LT |
131 | u32 apsize; |
132 | u32 apsizereg; | |
133 | int nbits; | |
134 | u32 aper_low, aper_hi; | |
135 | u64 aper; | |
1edc1ab3 | 136 | u32 old_order; |
1da177e4 | 137 | |
c96ec953 | 138 | pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func); |
55c0d721 | 139 | apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); |
1da177e4 | 140 | if (apsizereg == 0xffffffff) { |
c96ec953 BH |
141 | pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n", |
142 | bus, slot, func); | |
1da177e4 LT |
143 | return 0; |
144 | } | |
145 | ||
1edc1ab3 YL |
146 | /* old_order could be the value from NB gart setting */ |
147 | old_order = *order; | |
148 | ||
1da177e4 LT |
149 | apsize = apsizereg & 0xfff; |
150 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
c140df97 IM |
151 | if (apsize & 0xff) |
152 | apsize |= 0xf00; | |
1da177e4 LT |
153 | nbits = hweight16(apsize); |
154 | *order = 7 - nbits; | |
155 | if ((int)*order < 0) /* < 32MB */ | |
156 | *order = 0; | |
c140df97 | 157 | |
55c0d721 YL |
158 | aper_low = read_pci_config(bus, slot, func, 0x10); |
159 | aper_hi = read_pci_config(bus, slot, func, 0x14); | |
1da177e4 LT |
160 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); |
161 | ||
1edc1ab3 YL |
162 | /* |
163 | * On some sick chips, APSIZE is 0. It means it wants 4G | |
164 | * so let double check that order, and lets trust AMD NB settings: | |
165 | */ | |
c96ec953 BH |
166 | pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n", |
167 | bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1, | |
168 | 32 << old_order); | |
8c9fd91a | 169 | if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) { |
c96ec953 BH |
170 | pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n", |
171 | bus, slot, func, 32 << *order, apsizereg); | |
1edc1ab3 YL |
172 | *order = old_order; |
173 | } | |
174 | ||
c96ec953 BH |
175 | pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n", |
176 | bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1, | |
a5d3244a | 177 | 32 << *order, apsizereg); |
1da177e4 | 178 | |
8c9fd91a | 179 | if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20)) |
c140df97 IM |
180 | return 0; |
181 | return (u32)aper; | |
182 | } | |
1da177e4 | 183 | |
c140df97 IM |
184 | /* |
185 | * Look for an AGP bridge. Windows only expects the aperture in the | |
186 | * AGP bridge and some BIOS forget to initialize the Northbridge too. | |
187 | * Work around this here. | |
188 | * | |
189 | * Do an PCI bus scan by hand because we're running before the PCI | |
190 | * subsystem. | |
191 | * | |
eec1d4fa | 192 | * All AMD AGP bridges are AGPv3 compliant, so we can do this scan |
c140df97 IM |
193 | * generically. It's probably overkill to always scan all slots because |
194 | * the AGP bridges should be always an own bus on the HT hierarchy, | |
195 | * but do it here for future safety. | |
196 | */ | |
dd564d0c | 197 | static u32 __init search_agp_bridge(u32 *order, int *valid_agp) |
1da177e4 | 198 | { |
55c0d721 | 199 | int bus, slot, func; |
1da177e4 LT |
200 | |
201 | /* Poor man's PCI discovery */ | |
55c0d721 | 202 | for (bus = 0; bus < 256; bus++) { |
c140df97 IM |
203 | for (slot = 0; slot < 32; slot++) { |
204 | for (func = 0; func < 8; func++) { | |
1da177e4 LT |
205 | u32 class, cap; |
206 | u8 type; | |
55c0d721 | 207 | class = read_pci_config(bus, slot, func, |
1da177e4 LT |
208 | PCI_CLASS_REVISION); |
209 | if (class == 0xffffffff) | |
c140df97 IM |
210 | break; |
211 | ||
212 | switch (class >> 16) { | |
1da177e4 LT |
213 | case PCI_CLASS_BRIDGE_HOST: |
214 | case PCI_CLASS_BRIDGE_OTHER: /* needed? */ | |
215 | /* AGP bridge? */ | |
2a6f1225 GP |
216 | cap = pci_early_find_cap(bus, slot, |
217 | func, PCI_CAP_ID_AGP); | |
1da177e4 LT |
218 | if (!cap) |
219 | break; | |
c140df97 | 220 | *valid_agp = 1; |
55c0d721 | 221 | return read_agp(bus, slot, func, cap, |
c140df97 IM |
222 | order); |
223 | } | |
224 | ||
1da177e4 | 225 | /* No multi-function device? */ |
55c0d721 | 226 | type = read_pci_config_byte(bus, slot, func, |
1da177e4 LT |
227 | PCI_HEADER_TYPE); |
228 | if (!(type & 0x80)) | |
229 | break; | |
c140df97 IM |
230 | } |
231 | } | |
1da177e4 | 232 | } |
a5d3244a | 233 | pr_info("No AGP bridge found\n"); |
c140df97 | 234 | |
1da177e4 LT |
235 | return 0; |
236 | } | |
237 | ||
4cc7ecb7 | 238 | static bool gart_fix_e820 __initdata = true; |
aaf23042 YL |
239 | |
240 | static int __init parse_gart_mem(char *p) | |
241 | { | |
4cc7ecb7 | 242 | return kstrtobool(p, &gart_fix_e820); |
aaf23042 YL |
243 | } |
244 | early_param("gart_fix_e820", parse_gart_mem); | |
245 | ||
63ecd3b1 BP |
246 | /* |
247 | * With kexec/kdump, if the first kernel doesn't shut down the GART and the | |
248 | * second kernel allocates a different GART region, there might be two | |
249 | * overlapping GART regions present: | |
250 | * | |
251 | * - the first still used by the GART initialized in the first kernel. | |
252 | * - (sub-)set of it used as normal RAM by the second kernel. | |
253 | * | |
254 | * which leads to memory corruptions and a kernel panic eventually. | |
255 | * | |
256 | * This can also happen if the BIOS has forgotten to mark the GART region | |
257 | * as reserved. | |
258 | * | |
259 | * Try to update the e820 map to mark that new region as reserved. | |
260 | */ | |
aaf23042 YL |
261 | void __init early_gart_iommu_check(void) |
262 | { | |
fa10ba64 | 263 | u32 agp_aper_order = 0; |
f3eee542 | 264 | int i, fix, slot, valid_agp = 0; |
aaf23042 YL |
265 | u32 ctl; |
266 | u32 aper_size = 0, aper_order = 0, last_aper_order = 0; | |
267 | u64 aper_base = 0, last_aper_base = 0; | |
fa5b8a30 | 268 | int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0; |
aaf23042 | 269 | |
1b457429 AG |
270 | if (!amd_gart_present()) |
271 | return; | |
272 | ||
aaf23042 YL |
273 | if (!early_pci_allowed()) |
274 | return; | |
275 | ||
fa5b8a30 | 276 | /* This is mostly duplicate of iommu_hole_init */ |
fa10ba64 | 277 | search_agp_bridge(&agp_aper_order, &valid_agp); |
f3eee542 | 278 | |
aaf23042 | 279 | fix = 0; |
24d9b70b | 280 | for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
55c0d721 YL |
281 | int bus; |
282 | int dev_base, dev_limit; | |
283 | ||
24d9b70b JB |
284 | bus = amd_nb_bus_dev_ranges[i].bus; |
285 | dev_base = amd_nb_bus_dev_ranges[i].dev_base; | |
286 | dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; | |
55c0d721 YL |
287 | |
288 | for (slot = dev_base; slot < dev_limit; slot++) { | |
eec1d4fa | 289 | if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
55c0d721 YL |
290 | continue; |
291 | ||
292 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
57ab43e3 | 293 | aper_enabled = ctl & GARTEN; |
55c0d721 YL |
294 | aper_order = (ctl >> 1) & 7; |
295 | aper_size = (32 * 1024 * 1024) << aper_order; | |
296 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
297 | aper_base <<= 25; | |
298 | ||
fa5b8a30 PM |
299 | if (last_valid) { |
300 | if ((aper_order != last_aper_order) || | |
301 | (aper_base != last_aper_base) || | |
302 | (aper_enabled != last_aper_enabled)) { | |
303 | fix = 1; | |
304 | break; | |
305 | } | |
55c0d721 | 306 | } |
fa5b8a30 | 307 | |
55c0d721 YL |
308 | last_aper_order = aper_order; |
309 | last_aper_base = aper_base; | |
310 | last_aper_enabled = aper_enabled; | |
fa5b8a30 | 311 | last_valid = 1; |
aaf23042 | 312 | } |
aaf23042 YL |
313 | } |
314 | ||
315 | if (!fix && !aper_enabled) | |
316 | return; | |
317 | ||
318 | if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) | |
319 | fix = 1; | |
320 | ||
321 | if (gart_fix_e820 && !fix && aper_enabled) { | |
3bce64f0 | 322 | if (e820__mapped_any(aper_base, aper_base + aper_size, |
09821ff1 | 323 | E820_TYPE_RAM)) { |
0abbc78a | 324 | /* reserve it, so we can reuse it in second kernel */ |
c96ec953 BH |
325 | pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n", |
326 | aper_base, aper_base + aper_size - 1); | |
09821ff1 | 327 | e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED); |
6464d294 | 328 | e820__update_table_print(); |
aaf23042 | 329 | } |
aaf23042 YL |
330 | } |
331 | ||
f3eee542 | 332 | if (valid_agp) |
4f384f8b PM |
333 | return; |
334 | ||
f3eee542 | 335 | /* disable them all at first */ |
24d9b70b | 336 | for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
55c0d721 YL |
337 | int bus; |
338 | int dev_base, dev_limit; | |
339 | ||
24d9b70b JB |
340 | bus = amd_nb_bus_dev_ranges[i].bus; |
341 | dev_base = amd_nb_bus_dev_ranges[i].dev_base; | |
342 | dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; | |
aaf23042 | 343 | |
55c0d721 | 344 | for (slot = dev_base; slot < dev_limit; slot++) { |
eec1d4fa | 345 | if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
55c0d721 YL |
346 | continue; |
347 | ||
348 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
57ab43e3 | 349 | ctl &= ~GARTEN; |
55c0d721 YL |
350 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); |
351 | } | |
aaf23042 YL |
352 | } |
353 | ||
354 | } | |
355 | ||
8c9fd91a YL |
356 | static int __initdata printed_gart_size_msg; |
357 | ||
480125ba | 358 | int __init gart_iommu_hole_init(void) |
c140df97 | 359 | { |
8c9fd91a | 360 | u32 agp_aper_base = 0, agp_aper_order = 0; |
50895c5d | 361 | u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; |
1da177e4 | 362 | u64 aper_base, last_aper_base = 0; |
55c0d721 YL |
363 | int fix, slot, valid_agp = 0; |
364 | int i, node; | |
1da177e4 | 365 | |
1b457429 AG |
366 | if (!amd_gart_present()) |
367 | return -ENODEV; | |
368 | ||
0440d4c0 JR |
369 | if (gart_iommu_aperture_disabled || !fix_aperture || |
370 | !early_pci_allowed()) | |
480125ba | 371 | return -ENODEV; |
1da177e4 | 372 | |
a5d3244a | 373 | pr_info("Checking aperture...\n"); |
1da177e4 | 374 | |
8c9fd91a YL |
375 | if (!fallback_aper_force) |
376 | agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); | |
377 | ||
1da177e4 | 378 | fix = 0; |
47db4c3e | 379 | node = 0; |
24d9b70b | 380 | for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
55c0d721 YL |
381 | int bus; |
382 | int dev_base, dev_limit; | |
4b83873d | 383 | u32 ctl; |
55c0d721 | 384 | |
24d9b70b JB |
385 | bus = amd_nb_bus_dev_ranges[i].bus; |
386 | dev_base = amd_nb_bus_dev_ranges[i].dev_base; | |
387 | dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; | |
55c0d721 YL |
388 | |
389 | for (slot = dev_base; slot < dev_limit; slot++) { | |
eec1d4fa | 390 | if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
55c0d721 YL |
391 | continue; |
392 | ||
393 | iommu_detected = 1; | |
394 | gart_iommu_aperture = 1; | |
de957628 | 395 | x86_init.iommu.iommu_init = gart_iommu_init; |
55c0d721 | 396 | |
4b83873d JR |
397 | ctl = read_pci_config(bus, slot, 3, |
398 | AMD64_GARTAPERTURECTL); | |
399 | ||
400 | /* | |
401 | * Before we do anything else disable the GART. It may | |
402 | * still be enabled if we boot into a crash-kernel here. | |
403 | * Reconfiguring the GART while it is enabled could have | |
404 | * unknown side-effects. | |
405 | */ | |
406 | ctl &= ~GARTEN; | |
407 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); | |
408 | ||
409 | aper_order = (ctl >> 1) & 7; | |
55c0d721 YL |
410 | aper_size = (32 * 1024 * 1024) << aper_order; |
411 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
412 | aper_base <<= 25; | |
413 | ||
c96ec953 BH |
414 | pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n", |
415 | node, aper_base, aper_base + aper_size - 1, | |
416 | aper_size >> 20); | |
55c0d721 YL |
417 | node++; |
418 | ||
419 | if (!aperture_valid(aper_base, aper_size, 64<<20)) { | |
420 | if (valid_agp && agp_aper_base && | |
421 | agp_aper_base == aper_base && | |
422 | agp_aper_order == aper_order) { | |
423 | /* the same between two setting from NB and agp */ | |
c987d12f YL |
424 | if (!no_iommu && |
425 | max_pfn > MAX_DMA32_PFN && | |
426 | !printed_gart_size_msg) { | |
c96ec953 | 427 | pr_err("you are using iommu with agp, but GART size is less than 64MB\n"); |
a5d3244a BH |
428 | pr_err("please increase GART size in your BIOS setup\n"); |
429 | pr_err("if BIOS doesn't have that option, contact your HW vendor!\n"); | |
55c0d721 YL |
430 | printed_gart_size_msg = 1; |
431 | } | |
432 | } else { | |
433 | fix = 1; | |
434 | goto out; | |
8c9fd91a | 435 | } |
8c9fd91a | 436 | } |
1da177e4 | 437 | |
55c0d721 YL |
438 | if ((last_aper_order && aper_order != last_aper_order) || |
439 | (last_aper_base && aper_base != last_aper_base)) { | |
440 | fix = 1; | |
441 | goto out; | |
442 | } | |
443 | last_aper_order = aper_order; | |
444 | last_aper_base = aper_base; | |
1da177e4 | 445 | } |
c140df97 | 446 | } |
1da177e4 | 447 | |
55c0d721 | 448 | out: |
56dd669a | 449 | if (!fix && !fallback_aper_force) { |
2a3e83c6 JB |
450 | if (last_aper_base) { |
451 | /* | |
452 | * If this is the kdump kernel, the first kernel | |
453 | * may have allocated the range over its e820 RAM | |
454 | * and fixed up the northbridge | |
455 | */ | |
ffc8599a | 456 | exclude_from_core(last_aper_base, last_aper_order); |
2a3e83c6 | 457 | |
480125ba | 458 | return 1; |
2a3e83c6 | 459 | } |
480125ba | 460 | return 0; |
56dd669a | 461 | } |
1da177e4 | 462 | |
8c9fd91a YL |
463 | if (!fallback_aper_force) { |
464 | aper_alloc = agp_aper_base; | |
465 | aper_order = agp_aper_order; | |
466 | } | |
c140df97 IM |
467 | |
468 | if (aper_alloc) { | |
1da177e4 | 469 | /* Got the aperture from the AGP bridge */ |
c987d12f | 470 | } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) || |
1da177e4 LT |
471 | force_iommu || |
472 | valid_agp || | |
c140df97 | 473 | fallback_aper_force) { |
1b457429 | 474 | pr_info("Your BIOS doesn't leave an aperture memory hole\n"); |
a5d3244a | 475 | pr_info("Please enable the IOMMU option in the BIOS setup\n"); |
c96ec953 | 476 | pr_info("This costs you %dMB of RAM\n", |
a5d3244a | 477 | 32 << fallback_aper_order); |
1da177e4 LT |
478 | |
479 | aper_order = fallback_aper_order; | |
480 | aper_alloc = allocate_aperture(); | |
c140df97 IM |
481 | if (!aper_alloc) { |
482 | /* | |
483 | * Could disable AGP and IOMMU here, but it's | |
484 | * probably not worth it. But the later users | |
485 | * cannot deal with bad apertures and turning | |
486 | * on the aperture over memory causes very | |
487 | * strange problems, so it's better to panic | |
488 | * early. | |
489 | */ | |
1da177e4 LT |
490 | panic("Not enough memory for aperture"); |
491 | } | |
c140df97 | 492 | } else { |
480125ba | 493 | return 0; |
c140df97 | 494 | } |
1da177e4 | 495 | |
2a3e83c6 JB |
496 | /* |
497 | * If this is the kdump kernel _and_ the first kernel did not | |
498 | * configure the aperture in the northbridge, this range may | |
499 | * overlap with the first kernel's memory. We can't access the | |
500 | * range through vmcore even though it should be part of the dump. | |
501 | */ | |
ffc8599a | 502 | exclude_from_core(aper_alloc, aper_order); |
2a3e83c6 | 503 | |
1da177e4 | 504 | /* Fix up the north bridges */ |
24d9b70b | 505 | for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) { |
260133ab BP |
506 | int bus, dev_base, dev_limit; |
507 | ||
508 | /* | |
509 | * Don't enable translation yet but enable GART IO and CPU | |
510 | * accesses and set DISTLBWALKPRB since GART table memory is UC. | |
511 | */ | |
c34151a7 | 512 | u32 ctl = aper_order << 1; |
55c0d721 | 513 | |
24d9b70b JB |
514 | bus = amd_nb_bus_dev_ranges[i].bus; |
515 | dev_base = amd_nb_bus_dev_ranges[i].dev_base; | |
516 | dev_limit = amd_nb_bus_dev_ranges[i].dev_limit; | |
55c0d721 | 517 | for (slot = dev_base; slot < dev_limit; slot++) { |
eec1d4fa | 518 | if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00))) |
55c0d721 YL |
519 | continue; |
520 | ||
260133ab | 521 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); |
55c0d721 YL |
522 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); |
523 | } | |
c140df97 | 524 | } |
6703f6d1 RW |
525 | |
526 | set_up_gart_resume(aper_order, aper_alloc); | |
480125ba KRW |
527 | |
528 | return 1; | |
c140df97 | 529 | } |