]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
e83a5fdc | 26 | #include <linux/module.h> |
d1de36f5 IM |
27 | #include <linux/sysdev.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/timex.h> | |
6e1cb38a | 30 | #include <linux/dmar.h> |
d1de36f5 IM |
31 | #include <linux/init.h> |
32 | #include <linux/cpu.h> | |
33 | #include <linux/dmi.h> | |
e423e33e | 34 | #include <linux/nmi.h> |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
cdd6c482 | 38 | #include <asm/perf_event.h> |
736decac | 39 | #include <asm/x86_init.h> |
1da177e4 | 40 | #include <asm/pgalloc.h> |
1da177e4 | 41 | #include <asm/atomic.h> |
1da177e4 | 42 | #include <asm/mpspec.h> |
773763df | 43 | #include <asm/i8253.h> |
d1de36f5 | 44 | #include <asm/i8259.h> |
73dea47f | 45 | #include <asm/proto.h> |
2c8c0e6b | 46 | #include <asm/apic.h> |
d1de36f5 IM |
47 | #include <asm/desc.h> |
48 | #include <asm/hpet.h> | |
49 | #include <asm/idle.h> | |
50 | #include <asm/mtrr.h> | |
2bc13797 | 51 | #include <asm/smp.h> |
be71b855 | 52 | #include <asm/mce.h> |
ce69a784 | 53 | #include <asm/kvm_para.h> |
8c3ba8d0 | 54 | #include <asm/tsc.h> |
1da177e4 | 55 | |
ec70de8b | 56 | unsigned int num_processors; |
fdbecd9f | 57 | |
ec70de8b | 58 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 59 | |
ec70de8b BG |
60 | /* Processor that is doing the boot up */ |
61 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 62 | |
80e5609c | 63 | /* |
fdbecd9f | 64 | * The highest APIC ID seen during enumeration. |
80e5609c | 65 | */ |
ec70de8b | 66 | unsigned int max_physical_apicid; |
5af5573e | 67 | |
80e5609c | 68 | /* |
fdbecd9f | 69 | * Bitmask of physically existing CPUs: |
80e5609c | 70 | */ |
ec70de8b BG |
71 | physid_mask_t phys_cpu_present_map; |
72 | ||
73 | /* | |
74 | * Map cpu index to physical APIC ID | |
75 | */ | |
76 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
77 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
78 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
79 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 80 | |
b3c51170 YL |
81 | #ifdef CONFIG_X86_32 |
82 | /* | |
83 | * Knob to control our willingness to enable the local APIC. | |
84 | * | |
85 | * +1=force-enable | |
86 | */ | |
87 | static int force_enable_local_apic; | |
88 | /* | |
89 | * APIC command line parameters | |
90 | */ | |
91 | static int __init parse_lapic(char *arg) | |
92 | { | |
93 | force_enable_local_apic = 1; | |
94 | return 0; | |
95 | } | |
96 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
97 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
98 | static int enabled_via_apicbase; | |
99 | ||
c0eaa453 CG |
100 | /* |
101 | * Handle interrupt mode configuration register (IMCR). | |
102 | * This register controls whether the interrupt signals | |
103 | * that reach the BSP come from the master PIC or from the | |
104 | * local APIC. Before entering Symmetric I/O Mode, either | |
105 | * the BIOS or the operating system must switch out of | |
106 | * PIC Mode by changing the IMCR. | |
107 | */ | |
5cda395f | 108 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
109 | { |
110 | /* select IMCR register */ | |
111 | outb(0x70, 0x22); | |
112 | /* NMI and 8259 INTR go through APIC */ | |
113 | outb(0x01, 0x23); | |
114 | } | |
115 | ||
5cda395f | 116 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
117 | { |
118 | /* select IMCR register */ | |
119 | outb(0x70, 0x22); | |
120 | /* NMI and 8259 INTR go directly to BSP */ | |
121 | outb(0x00, 0x23); | |
122 | } | |
b3c51170 YL |
123 | #endif |
124 | ||
125 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 126 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
127 | static __init int setup_apicpmtimer(char *s) |
128 | { | |
129 | apic_calibrate_pmtmr = 1; | |
130 | notsc_setup(NULL); | |
131 | return 0; | |
132 | } | |
133 | __setup("apicpmtimer", setup_apicpmtimer); | |
134 | #endif | |
135 | ||
fc1edaf9 | 136 | int x2apic_mode; |
06cd9a7d | 137 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a | 138 | /* x2apic enabled before OS handover */ |
b6b301aa | 139 | static int x2apic_preenabled; |
49899eac YL |
140 | static __init int setup_nox2apic(char *str) |
141 | { | |
39d83a5d SS |
142 | if (x2apic_enabled()) { |
143 | pr_warning("Bios already enabled x2apic, " | |
144 | "can't enforce nox2apic"); | |
145 | return 0; | |
146 | } | |
147 | ||
49899eac YL |
148 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
149 | return 0; | |
150 | } | |
151 | early_param("nox2apic", setup_nox2apic); | |
152 | #endif | |
1da177e4 | 153 | |
b3c51170 YL |
154 | unsigned long mp_lapic_addr; |
155 | int disable_apic; | |
156 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
157 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 158 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
159 | int local_apic_timer_c2_ok; |
160 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
161 | ||
efa2559f YL |
162 | int first_system_vector = 0xfe; |
163 | ||
e83a5fdc HS |
164 | /* |
165 | * Debug level, exported for io_apic.c | |
166 | */ | |
baa13188 | 167 | unsigned int apic_verbosity; |
e83a5fdc | 168 | |
89c38c28 CG |
169 | int pic_mode; |
170 | ||
bab4b27c AS |
171 | /* Have we found an MP table */ |
172 | int smp_found_config; | |
173 | ||
39928722 AD |
174 | static struct resource lapic_resource = { |
175 | .name = "Local APIC", | |
176 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
177 | }; | |
178 | ||
d03030e9 TG |
179 | static unsigned int calibration_result; |
180 | ||
ba7eda4c TG |
181 | static int lapic_next_event(unsigned long delta, |
182 | struct clock_event_device *evt); | |
183 | static void lapic_timer_setup(enum clock_event_mode mode, | |
184 | struct clock_event_device *evt); | |
9628937d | 185 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 186 | static void apic_pm_activate(void); |
ba7eda4c | 187 | |
274cfe59 CG |
188 | /* |
189 | * The local apic timer can be used for any function which is CPU local. | |
190 | */ | |
ba7eda4c TG |
191 | static struct clock_event_device lapic_clockevent = { |
192 | .name = "lapic", | |
193 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
194 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
195 | .shift = 32, | |
196 | .set_mode = lapic_timer_setup, | |
197 | .set_next_event = lapic_next_event, | |
198 | .broadcast = lapic_timer_broadcast, | |
199 | .rating = 100, | |
200 | .irq = -1, | |
201 | }; | |
202 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
203 | ||
d3432896 AK |
204 | static unsigned long apic_phys; |
205 | ||
0e078e2f TG |
206 | /* |
207 | * Get the LAPIC version | |
208 | */ | |
209 | static inline int lapic_get_version(void) | |
ba7eda4c | 210 | { |
0e078e2f | 211 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
212 | } |
213 | ||
0e078e2f | 214 | /* |
9c803869 | 215 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
216 | */ |
217 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 218 | { |
9c803869 | 219 | #ifdef CONFIG_X86_64 |
0e078e2f | 220 | return 1; |
9c803869 CG |
221 | #else |
222 | return APIC_INTEGRATED(lapic_get_version()); | |
223 | #endif | |
ba7eda4c TG |
224 | } |
225 | ||
226 | /* | |
0e078e2f | 227 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 228 | */ |
0e078e2f | 229 | static int modern_apic(void) |
ba7eda4c | 230 | { |
0e078e2f TG |
231 | /* AMD systems use old APIC versions, so check the CPU */ |
232 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
233 | boot_cpu_data.x86 >= 0xf) | |
234 | return 1; | |
235 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
236 | } |
237 | ||
08306ce6 | 238 | /* |
a933c618 CG |
239 | * right after this call apic become NOOP driven |
240 | * so apic->write/read doesn't do anything | |
08306ce6 CG |
241 | */ |
242 | void apic_disable(void) | |
243 | { | |
f88f2b4f | 244 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 245 | apic = &apic_noop; |
08306ce6 CG |
246 | } |
247 | ||
c1eeb2de | 248 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
249 | { |
250 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
251 | cpu_relax(); | |
252 | } | |
253 | ||
c1eeb2de | 254 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 255 | { |
3c6bb07a | 256 | u32 send_status; |
8339e9fb FLV |
257 | int timeout; |
258 | ||
259 | timeout = 0; | |
260 | do { | |
261 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
262 | if (!send_status) | |
263 | break; | |
264 | udelay(100); | |
265 | } while (timeout++ < 1000); | |
266 | ||
267 | return send_status; | |
268 | } | |
269 | ||
c1eeb2de | 270 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 271 | { |
ed4e5ec1 | 272 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
273 | apic_write(APIC_ICR, low); |
274 | } | |
275 | ||
c1eeb2de | 276 | u64 native_apic_icr_read(void) |
1b374e4d SS |
277 | { |
278 | u32 icr1, icr2; | |
279 | ||
280 | icr2 = apic_read(APIC_ICR2); | |
281 | icr1 = apic_read(APIC_ICR); | |
282 | ||
cf9768d7 | 283 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
284 | } |
285 | ||
0e078e2f TG |
286 | /** |
287 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
288 | */ | |
e9427101 | 289 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 290 | { |
11a8e778 | 291 | unsigned int v; |
6935d1f9 TG |
292 | |
293 | /* unmask and set to NMI */ | |
294 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
295 | |
296 | /* Level triggered for 82489DX (32bit mode) */ | |
297 | if (!lapic_is_integrated()) | |
298 | v |= APIC_LVT_LEVEL_TRIGGER; | |
299 | ||
11a8e778 | 300 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
301 | } |
302 | ||
7c37e48b CG |
303 | #ifdef CONFIG_X86_32 |
304 | /** | |
305 | * get_physical_broadcast - Get number of physical broadcast IDs | |
306 | */ | |
307 | int get_physical_broadcast(void) | |
308 | { | |
309 | return modern_apic() ? 0xff : 0xf; | |
310 | } | |
311 | #endif | |
312 | ||
0e078e2f TG |
313 | /** |
314 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
315 | */ | |
37e650c7 | 316 | int lapic_get_maxlvt(void) |
1da177e4 | 317 | { |
36a028de | 318 | unsigned int v; |
1da177e4 LT |
319 | |
320 | v = apic_read(APIC_LVR); | |
36a028de CG |
321 | /* |
322 | * - we always have APIC integrated on 64bit mode | |
323 | * - 82489DXs do not report # of LVT entries | |
324 | */ | |
325 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
326 | } |
327 | ||
274cfe59 CG |
328 | /* |
329 | * Local APIC timer | |
330 | */ | |
331 | ||
c40aaec6 | 332 | /* Clock divisor */ |
c40aaec6 | 333 | #define APIC_DIVISOR 16 |
f07f4f90 | 334 | |
0e078e2f TG |
335 | /* |
336 | * This function sets up the local APIC timer, with a timeout of | |
337 | * 'clocks' APIC bus clock. During calibration we actually call | |
338 | * this function twice on the boot CPU, once with a bogus timeout | |
339 | * value, second time for real. The other (noncalibrating) CPUs | |
340 | * call this function only once, with the real, calibrated value. | |
341 | * | |
342 | * We do reads before writes even if unnecessary, to get around the | |
343 | * P5 APIC double write bug. | |
344 | */ | |
0e078e2f | 345 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 346 | { |
0e078e2f | 347 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 348 | |
0e078e2f TG |
349 | lvtt_value = LOCAL_TIMER_VECTOR; |
350 | if (!oneshot) | |
351 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
352 | if (!lapic_is_integrated()) |
353 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
354 | ||
0e078e2f TG |
355 | if (!irqen) |
356 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 357 | |
0e078e2f | 358 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
359 | |
360 | /* | |
0e078e2f | 361 | * Divide PICLK by 16 |
1da177e4 | 362 | */ |
0e078e2f | 363 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
364 | apic_write(APIC_TDCR, |
365 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
366 | APIC_TDR_DIV_16); | |
0e078e2f TG |
367 | |
368 | if (!oneshot) | |
f07f4f90 | 369 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
370 | } |
371 | ||
0e078e2f | 372 | /* |
7b83dae7 RR |
373 | * Setup extended LVT, AMD specific (K8, family 10h) |
374 | * | |
375 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
376 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
377 | * |
378 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
379 | * enables the vector. See also the BKDGs. | |
0e078e2f | 380 | */ |
7b83dae7 RR |
381 | |
382 | #define APIC_EILVT_LVTOFF_MCE 0 | |
383 | #define APIC_EILVT_LVTOFF_IBS 1 | |
384 | ||
385 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 386 | { |
97a52714 | 387 | unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); |
0e078e2f | 388 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 389 | |
0e078e2f | 390 | apic_write(reg, v); |
1da177e4 LT |
391 | } |
392 | ||
7b83dae7 RR |
393 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
394 | { | |
395 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
396 | return APIC_EILVT_LVTOFF_MCE; | |
397 | } | |
398 | ||
399 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
400 | { | |
401 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
402 | return APIC_EILVT_LVTOFF_IBS; | |
403 | } | |
6aa360e6 | 404 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 405 | |
0e078e2f TG |
406 | /* |
407 | * Program the next event, relative to now | |
408 | */ | |
409 | static int lapic_next_event(unsigned long delta, | |
410 | struct clock_event_device *evt) | |
1da177e4 | 411 | { |
0e078e2f TG |
412 | apic_write(APIC_TMICT, delta); |
413 | return 0; | |
1da177e4 LT |
414 | } |
415 | ||
0e078e2f TG |
416 | /* |
417 | * Setup the lapic timer in periodic or oneshot mode | |
418 | */ | |
419 | static void lapic_timer_setup(enum clock_event_mode mode, | |
420 | struct clock_event_device *evt) | |
9b7711f0 HS |
421 | { |
422 | unsigned long flags; | |
0e078e2f | 423 | unsigned int v; |
9b7711f0 | 424 | |
0e078e2f TG |
425 | /* Lapic used as dummy for broadcast ? */ |
426 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
427 | return; |
428 | ||
429 | local_irq_save(flags); | |
430 | ||
0e078e2f TG |
431 | switch (mode) { |
432 | case CLOCK_EVT_MODE_PERIODIC: | |
433 | case CLOCK_EVT_MODE_ONESHOT: | |
434 | __setup_APIC_LVTT(calibration_result, | |
435 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
436 | break; | |
437 | case CLOCK_EVT_MODE_UNUSED: | |
438 | case CLOCK_EVT_MODE_SHUTDOWN: | |
439 | v = apic_read(APIC_LVTT); | |
440 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
441 | apic_write(APIC_LVTT, v); | |
6f9b4100 | 442 | apic_write(APIC_TMICT, 0); |
0e078e2f TG |
443 | break; |
444 | case CLOCK_EVT_MODE_RESUME: | |
445 | /* Nothing to do here */ | |
446 | break; | |
447 | } | |
9b7711f0 HS |
448 | |
449 | local_irq_restore(flags); | |
450 | } | |
451 | ||
1da177e4 | 452 | /* |
0e078e2f | 453 | * Local APIC timer broadcast function |
1da177e4 | 454 | */ |
9628937d | 455 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 456 | { |
0e078e2f | 457 | #ifdef CONFIG_SMP |
dac5f412 | 458 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
459 | #endif |
460 | } | |
1da177e4 | 461 | |
0e078e2f TG |
462 | /* |
463 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
464 | * of the boot CPU and register the clock event in the framework. | |
465 | */ | |
db4b5525 | 466 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
467 | { |
468 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 469 | |
db954b58 VP |
470 | if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { |
471 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; | |
472 | /* Make LAPIC timer preferrable over percpu HPET */ | |
473 | lapic_clockevent.rating = 150; | |
474 | } | |
475 | ||
0e078e2f | 476 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 477 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 478 | |
0e078e2f TG |
479 | clockevents_register_device(levt); |
480 | } | |
1da177e4 | 481 | |
2f04fa88 YL |
482 | /* |
483 | * In this functions we calibrate APIC bus clocks to the external timer. | |
484 | * | |
485 | * We want to do the calibration only once since we want to have local timer | |
486 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
487 | * frequency. | |
488 | * | |
489 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
490 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
491 | * readout is broken, so it never gets out of the wait loop again. This was | |
492 | * also reported by others. | |
493 | * | |
494 | * Monitoring the jiffies value is inaccurate and the clockevents | |
495 | * infrastructure allows us to do a simple substitution of the interrupt | |
496 | * handler. | |
497 | * | |
498 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
499 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
500 | * back to normal later in the boot process). | |
501 | */ | |
502 | ||
503 | #define LAPIC_CAL_LOOPS (HZ/10) | |
504 | ||
505 | static __initdata int lapic_cal_loops = -1; | |
506 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
507 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
508 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
509 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
510 | ||
511 | /* | |
512 | * Temporary interrupt handler. | |
513 | */ | |
514 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
515 | { | |
516 | unsigned long long tsc = 0; | |
517 | long tapic = apic_read(APIC_TMCCT); | |
518 | unsigned long pm = acpi_pm_read_early(); | |
519 | ||
520 | if (cpu_has_tsc) | |
521 | rdtscll(tsc); | |
522 | ||
523 | switch (lapic_cal_loops++) { | |
524 | case 0: | |
525 | lapic_cal_t1 = tapic; | |
526 | lapic_cal_tsc1 = tsc; | |
527 | lapic_cal_pm1 = pm; | |
528 | lapic_cal_j1 = jiffies; | |
529 | break; | |
530 | ||
531 | case LAPIC_CAL_LOOPS: | |
532 | lapic_cal_t2 = tapic; | |
533 | lapic_cal_tsc2 = tsc; | |
534 | if (pm < lapic_cal_pm1) | |
535 | pm += ACPI_PM_OVRRUN; | |
536 | lapic_cal_pm2 = pm; | |
537 | lapic_cal_j2 = jiffies; | |
538 | break; | |
539 | } | |
540 | } | |
541 | ||
754ef0cd YI |
542 | static int __init |
543 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
544 | { |
545 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
546 | const long pm_thresh = pm_100ms / 100; | |
547 | unsigned long mult; | |
548 | u64 res; | |
549 | ||
550 | #ifndef CONFIG_X86_PM_TIMER | |
551 | return -1; | |
552 | #endif | |
553 | ||
39ba5d43 | 554 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
555 | |
556 | /* Check, if the PM timer is available */ | |
557 | if (!deltapm) | |
558 | return -1; | |
559 | ||
560 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
561 | ||
562 | if (deltapm > (pm_100ms - pm_thresh) && | |
563 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 564 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
565 | return 0; |
566 | } | |
567 | ||
568 | res = (((u64)deltapm) * mult) >> 22; | |
569 | do_div(res, 1000000); | |
570 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 571 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
572 | |
573 | /* Correct the lapic counter value */ | |
574 | res = (((u64)(*delta)) * pm_100ms); | |
575 | do_div(res, deltapm); | |
576 | pr_info("APIC delta adjusted to PM-Timer: " | |
577 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
578 | *delta = (long)res; | |
579 | ||
580 | /* Correct the tsc counter value */ | |
581 | if (cpu_has_tsc) { | |
582 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 583 | do_div(res, deltapm); |
754ef0cd | 584 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 585 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
586 | (unsigned long)res, *deltatsc); |
587 | *deltatsc = (long)res; | |
b189892d CG |
588 | } |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
2f04fa88 YL |
593 | static int __init calibrate_APIC_clock(void) |
594 | { | |
595 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
596 | void (*real_handler)(struct clock_event_device *dev); |
597 | unsigned long deltaj; | |
754ef0cd | 598 | long delta, deltatsc; |
2f04fa88 YL |
599 | int pm_referenced = 0; |
600 | ||
601 | local_irq_disable(); | |
602 | ||
603 | /* Replace the global interrupt handler */ | |
604 | real_handler = global_clock_event->event_handler; | |
605 | global_clock_event->event_handler = lapic_cal_handler; | |
606 | ||
607 | /* | |
81608f3c | 608 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
609 | * can underflow in the 100ms detection time frame |
610 | */ | |
81608f3c | 611 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
612 | |
613 | /* Let the interrupts run */ | |
614 | local_irq_enable(); | |
615 | ||
616 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
617 | cpu_relax(); | |
618 | ||
619 | local_irq_disable(); | |
620 | ||
621 | /* Restore the real event handler */ | |
622 | global_clock_event->event_handler = real_handler; | |
623 | ||
624 | /* Build delta t1-t2 as apic timer counts down */ | |
625 | delta = lapic_cal_t1 - lapic_cal_t2; | |
626 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
627 | ||
754ef0cd YI |
628 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
629 | ||
b189892d CG |
630 | /* we trust the PM based calibration if possible */ |
631 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 632 | &delta, &deltatsc); |
2f04fa88 YL |
633 | |
634 | /* Calculate the scaled math multiplication factor */ | |
635 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
636 | lapic_clockevent.shift); | |
637 | lapic_clockevent.max_delta_ns = | |
638 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
639 | lapic_clockevent.min_delta_ns = | |
640 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
641 | ||
642 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
643 | ||
644 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 645 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 YL |
646 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
647 | calibration_result); | |
648 | ||
649 | if (cpu_has_tsc) { | |
2f04fa88 YL |
650 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
651 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
652 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
653 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
654 | } |
655 | ||
656 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
657 | "%u.%04u MHz.\n", | |
658 | calibration_result / (1000000 / HZ), | |
659 | calibration_result % (1000000 / HZ)); | |
660 | ||
661 | /* | |
662 | * Do a sanity check on the APIC calibration result | |
663 | */ | |
664 | if (calibration_result < (1000000 / HZ)) { | |
665 | local_irq_enable(); | |
ba21ebb6 | 666 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
667 | return -1; |
668 | } | |
669 | ||
670 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
671 | ||
b189892d CG |
672 | /* |
673 | * PM timer calibration failed or not turned on | |
674 | * so lets try APIC timer based calibration | |
675 | */ | |
2f04fa88 YL |
676 | if (!pm_referenced) { |
677 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
678 | ||
679 | /* | |
680 | * Setup the apic timer manually | |
681 | */ | |
682 | levt->event_handler = lapic_cal_handler; | |
683 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
684 | lapic_cal_loops = -1; | |
685 | ||
686 | /* Let the interrupts run */ | |
687 | local_irq_enable(); | |
688 | ||
689 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
690 | cpu_relax(); | |
691 | ||
2f04fa88 YL |
692 | /* Stop the lapic timer */ |
693 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
694 | ||
2f04fa88 YL |
695 | /* Jiffies delta */ |
696 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
697 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
698 | ||
699 | /* Check, if the jiffies result is consistent */ | |
700 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
701 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
702 | else | |
703 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
704 | } else | |
705 | local_irq_enable(); | |
706 | ||
707 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 708 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
709 | return -1; |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
e83a5fdc HS |
715 | /* |
716 | * Setup the boot APIC | |
717 | * | |
718 | * Calibrate and verify the result. | |
719 | */ | |
0e078e2f TG |
720 | void __init setup_boot_APIC_clock(void) |
721 | { | |
722 | /* | |
274cfe59 CG |
723 | * The local apic timer can be disabled via the kernel |
724 | * commandline or from the CPU detection code. Register the lapic | |
725 | * timer as a dummy clock event source on SMP systems, so the | |
726 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
727 | */ |
728 | if (disable_apic_timer) { | |
ba21ebb6 | 729 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 730 | /* No broadcast on UP ! */ |
9d09951d TG |
731 | if (num_possible_cpus() > 1) { |
732 | lapic_clockevent.mult = 1; | |
0e078e2f | 733 | setup_APIC_timer(); |
9d09951d | 734 | } |
0e078e2f TG |
735 | return; |
736 | } | |
737 | ||
274cfe59 CG |
738 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
739 | "calibrating APIC timer ...\n"); | |
740 | ||
89b3b1f4 | 741 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
742 | /* No broadcast on UP ! */ |
743 | if (num_possible_cpus() > 1) | |
744 | setup_APIC_timer(); | |
745 | return; | |
746 | } | |
747 | ||
0e078e2f TG |
748 | /* |
749 | * If nmi_watchdog is set to IO_APIC, we need the | |
750 | * PIT/HPET going. Otherwise register lapic as a dummy | |
751 | * device. | |
752 | */ | |
753 | if (nmi_watchdog != NMI_IO_APIC) | |
754 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
755 | else | |
ba21ebb6 | 756 | pr_warning("APIC timer registered as dummy," |
116f570e | 757 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 758 | |
274cfe59 | 759 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
760 | setup_APIC_timer(); |
761 | } | |
762 | ||
0e078e2f TG |
763 | void __cpuinit setup_secondary_APIC_clock(void) |
764 | { | |
0e078e2f TG |
765 | setup_APIC_timer(); |
766 | } | |
767 | ||
768 | /* | |
769 | * The guts of the apic timer interrupt | |
770 | */ | |
771 | static void local_apic_timer_interrupt(void) | |
772 | { | |
773 | int cpu = smp_processor_id(); | |
774 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
775 | ||
776 | /* | |
777 | * Normally we should not be here till LAPIC has been initialized but | |
778 | * in some cases like kdump, its possible that there is a pending LAPIC | |
779 | * timer interrupt from previous kernel's context and is delivered in | |
780 | * new kernel the moment interrupts are enabled. | |
781 | * | |
782 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
783 | * its possible that when we get here evt->event_handler is NULL. | |
784 | * Check for event_handler being NULL and discard the interrupt as | |
785 | * spurious. | |
786 | */ | |
787 | if (!evt->event_handler) { | |
ba21ebb6 | 788 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
789 | /* Switch it off */ |
790 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
791 | return; | |
792 | } | |
793 | ||
794 | /* | |
795 | * the NMI deadlock-detector uses this. | |
796 | */ | |
915b0d01 | 797 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
798 | |
799 | evt->event_handler(evt); | |
800 | } | |
801 | ||
802 | /* | |
803 | * Local APIC timer interrupt. This is the most natural way for doing | |
804 | * local interrupts, but local timer interrupts can be emulated by | |
805 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
806 | * | |
807 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
808 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
809 | */ | |
bcbc4f20 | 810 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
811 | { |
812 | struct pt_regs *old_regs = set_irq_regs(regs); | |
813 | ||
814 | /* | |
815 | * NOTE! We'd better ACK the irq immediately, | |
816 | * because timer handling can be slow. | |
817 | */ | |
818 | ack_APIC_irq(); | |
819 | /* | |
820 | * update_process_times() expects us to have done irq_enter(). | |
821 | * Besides, if we don't timer interrupts ignore the global | |
822 | * interrupt lock, which is the WrongThing (tm) to do. | |
823 | */ | |
824 | exit_idle(); | |
825 | irq_enter(); | |
826 | local_apic_timer_interrupt(); | |
827 | irq_exit(); | |
274cfe59 | 828 | |
0e078e2f TG |
829 | set_irq_regs(old_regs); |
830 | } | |
831 | ||
832 | int setup_profiling_timer(unsigned int multiplier) | |
833 | { | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
0e078e2f TG |
837 | /* |
838 | * Local APIC start and shutdown | |
839 | */ | |
840 | ||
841 | /** | |
842 | * clear_local_APIC - shutdown the local APIC | |
843 | * | |
844 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
845 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
846 | * leftovers during boot. | |
847 | */ | |
848 | void clear_local_APIC(void) | |
849 | { | |
2584a82d | 850 | int maxlvt; |
0e078e2f TG |
851 | u32 v; |
852 | ||
d3432896 | 853 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 854 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
855 | return; |
856 | ||
857 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
858 | /* |
859 | * Masking an LVT entry can trigger a local APIC error | |
860 | * if the vector is zero. Mask LVTERR first to prevent this. | |
861 | */ | |
862 | if (maxlvt >= 3) { | |
863 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
864 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
865 | } | |
866 | /* | |
867 | * Careful: we have to set masks only first to deassert | |
868 | * any level-triggered sources. | |
869 | */ | |
870 | v = apic_read(APIC_LVTT); | |
871 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
872 | v = apic_read(APIC_LVT0); | |
873 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
874 | v = apic_read(APIC_LVT1); | |
875 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
876 | if (maxlvt >= 4) { | |
877 | v = apic_read(APIC_LVTPC); | |
878 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
879 | } | |
880 | ||
6764014b | 881 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 882 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
883 | if (maxlvt >= 5) { |
884 | v = apic_read(APIC_LVTTHMR); | |
885 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
886 | } | |
887 | #endif | |
5ca8681c AK |
888 | #ifdef CONFIG_X86_MCE_INTEL |
889 | if (maxlvt >= 6) { | |
890 | v = apic_read(APIC_LVTCMCI); | |
891 | if (!(v & APIC_LVT_MASKED)) | |
892 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
893 | } | |
894 | #endif | |
895 | ||
0e078e2f TG |
896 | /* |
897 | * Clean APIC state for other OSs: | |
898 | */ | |
899 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
900 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
901 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
902 | if (maxlvt >= 3) | |
903 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
904 | if (maxlvt >= 4) | |
905 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
906 | |
907 | /* Integrated APIC (!82489DX) ? */ | |
908 | if (lapic_is_integrated()) { | |
909 | if (maxlvt > 3) | |
910 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
911 | apic_write(APIC_ESR, 0); | |
912 | apic_read(APIC_ESR); | |
913 | } | |
0e078e2f TG |
914 | } |
915 | ||
916 | /** | |
917 | * disable_local_APIC - clear and disable the local APIC | |
918 | */ | |
919 | void disable_local_APIC(void) | |
920 | { | |
921 | unsigned int value; | |
922 | ||
4a13ad0b | 923 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 924 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
925 | return; |
926 | ||
0e078e2f TG |
927 | clear_local_APIC(); |
928 | ||
929 | /* | |
930 | * Disable APIC (implies clearing of registers | |
931 | * for 82489DX!). | |
932 | */ | |
933 | value = apic_read(APIC_SPIV); | |
934 | value &= ~APIC_SPIV_APIC_ENABLED; | |
935 | apic_write(APIC_SPIV, value); | |
990b183e CG |
936 | |
937 | #ifdef CONFIG_X86_32 | |
938 | /* | |
939 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
940 | * restore the disabled state. | |
941 | */ | |
942 | if (enabled_via_apicbase) { | |
943 | unsigned int l, h; | |
944 | ||
945 | rdmsr(MSR_IA32_APICBASE, l, h); | |
946 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
947 | wrmsr(MSR_IA32_APICBASE, l, h); | |
948 | } | |
949 | #endif | |
0e078e2f TG |
950 | } |
951 | ||
fe4024dc CG |
952 | /* |
953 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
954 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
955 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
956 | * for the case where Linux didn't enable the LAPIC. | |
957 | */ | |
0e078e2f TG |
958 | void lapic_shutdown(void) |
959 | { | |
960 | unsigned long flags; | |
961 | ||
8312136f | 962 | if (!cpu_has_apic && !apic_from_smp_config()) |
0e078e2f TG |
963 | return; |
964 | ||
965 | local_irq_save(flags); | |
966 | ||
fe4024dc CG |
967 | #ifdef CONFIG_X86_32 |
968 | if (!enabled_via_apicbase) | |
969 | clear_local_APIC(); | |
970 | else | |
971 | #endif | |
972 | disable_local_APIC(); | |
973 | ||
0e078e2f TG |
974 | |
975 | local_irq_restore(flags); | |
976 | } | |
977 | ||
978 | /* | |
979 | * This is to verify that we're looking at a real local APIC. | |
980 | * Check these against your board if the CPUs aren't getting | |
981 | * started for no apparent reason. | |
982 | */ | |
983 | int __init verify_local_APIC(void) | |
984 | { | |
985 | unsigned int reg0, reg1; | |
986 | ||
987 | /* | |
988 | * The version register is read-only in a real APIC. | |
989 | */ | |
990 | reg0 = apic_read(APIC_LVR); | |
991 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
992 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
993 | reg1 = apic_read(APIC_LVR); | |
994 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
995 | ||
996 | /* | |
997 | * The two version reads above should print the same | |
998 | * numbers. If the second one is different, then we | |
999 | * poke at a non-APIC. | |
1000 | */ | |
1001 | if (reg1 != reg0) | |
1002 | return 0; | |
1003 | ||
1004 | /* | |
1005 | * Check if the version looks reasonably. | |
1006 | */ | |
1007 | reg1 = GET_APIC_VERSION(reg0); | |
1008 | if (reg1 == 0x00 || reg1 == 0xff) | |
1009 | return 0; | |
1010 | reg1 = lapic_get_maxlvt(); | |
1011 | if (reg1 < 0x02 || reg1 == 0xff) | |
1012 | return 0; | |
1013 | ||
1014 | /* | |
1015 | * The ID register is read/write in a real APIC. | |
1016 | */ | |
2d7a66d0 | 1017 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1018 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1019 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1020 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1021 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1022 | apic_write(APIC_ID, reg0); | |
5b812727 | 1023 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1024 | return 0; |
1025 | ||
1026 | /* | |
1da177e4 LT |
1027 | * The next two are just to see if we have sane values. |
1028 | * They're only really relevant if we're in Virtual Wire | |
1029 | * compatibility mode, but most boxes are anymore. | |
1030 | */ | |
1031 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1032 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1033 | reg1 = apic_read(APIC_LVT1); |
1034 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1035 | ||
1036 | return 1; | |
1037 | } | |
1038 | ||
0e078e2f TG |
1039 | /** |
1040 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1041 | */ | |
1da177e4 LT |
1042 | void __init sync_Arb_IDs(void) |
1043 | { | |
296cb951 CG |
1044 | /* |
1045 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1046 | * needed on AMD. | |
1047 | */ | |
1048 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1049 | return; |
1050 | ||
1051 | /* | |
1052 | * Wait for idle. | |
1053 | */ | |
1054 | apic_wait_icr_idle(); | |
1055 | ||
1056 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1057 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1058 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1059 | } |
1060 | ||
1da177e4 LT |
1061 | /* |
1062 | * An initial setup of the virtual wire mode. | |
1063 | */ | |
1064 | void __init init_bsp_APIC(void) | |
1065 | { | |
11a8e778 | 1066 | unsigned int value; |
1da177e4 LT |
1067 | |
1068 | /* | |
1069 | * Don't do the setup now if we have a SMP BIOS as the | |
1070 | * through-I/O-APIC virtual wire mode might be active. | |
1071 | */ | |
1072 | if (smp_found_config || !cpu_has_apic) | |
1073 | return; | |
1074 | ||
1da177e4 LT |
1075 | /* |
1076 | * Do not trust the local APIC being empty at bootup. | |
1077 | */ | |
1078 | clear_local_APIC(); | |
1079 | ||
1080 | /* | |
1081 | * Enable APIC. | |
1082 | */ | |
1083 | value = apic_read(APIC_SPIV); | |
1084 | value &= ~APIC_VECTOR_MASK; | |
1085 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1086 | |
1087 | #ifdef CONFIG_X86_32 | |
1088 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1089 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1090 | (boot_cpu_data.x86 == 15)) | |
1091 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1092 | else | |
1093 | #endif | |
1094 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1095 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1096 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1097 | |
1098 | /* | |
1099 | * Set up the virtual wire mode. | |
1100 | */ | |
11a8e778 | 1101 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1102 | value = APIC_DM_NMI; |
638c0411 CG |
1103 | if (!lapic_is_integrated()) /* 82489DX */ |
1104 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1105 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1106 | } |
1107 | ||
c43da2f5 CG |
1108 | static void __cpuinit lapic_setup_esr(void) |
1109 | { | |
9df08f10 CG |
1110 | unsigned int oldvalue, value, maxlvt; |
1111 | ||
1112 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1113 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1114 | return; |
1115 | } | |
c43da2f5 | 1116 | |
08125d3e | 1117 | if (apic->disable_esr) { |
c43da2f5 | 1118 | /* |
9df08f10 CG |
1119 | * Something untraceable is creating bad interrupts on |
1120 | * secondary quads ... for the moment, just leave the | |
1121 | * ESR disabled - we can't do anything useful with the | |
1122 | * errors anyway - mbligh | |
c43da2f5 | 1123 | */ |
ba21ebb6 | 1124 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1125 | return; |
c43da2f5 | 1126 | } |
9df08f10 CG |
1127 | |
1128 | maxlvt = lapic_get_maxlvt(); | |
1129 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1130 | apic_write(APIC_ESR, 0); | |
1131 | oldvalue = apic_read(APIC_ESR); | |
1132 | ||
1133 | /* enables sending errors */ | |
1134 | value = ERROR_APIC_VECTOR; | |
1135 | apic_write(APIC_LVTERR, value); | |
1136 | ||
1137 | /* | |
1138 | * spec says clear errors after enabling vector. | |
1139 | */ | |
1140 | if (maxlvt > 3) | |
1141 | apic_write(APIC_ESR, 0); | |
1142 | value = apic_read(APIC_ESR); | |
1143 | if (value != oldvalue) | |
1144 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1145 | "vector: 0x%08x after: 0x%08x\n", | |
1146 | oldvalue, value); | |
c43da2f5 CG |
1147 | } |
1148 | ||
1149 | ||
0e078e2f TG |
1150 | /** |
1151 | * setup_local_APIC - setup the local APIC | |
1152 | */ | |
1153 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1154 | { |
8c3ba8d0 KJ |
1155 | unsigned int value, queued; |
1156 | int i, j, acked = 0; | |
1157 | unsigned long long tsc = 0, ntsc; | |
1158 | long long max_loops = cpu_khz; | |
1159 | ||
1160 | if (cpu_has_tsc) | |
1161 | rdtscll(tsc); | |
1da177e4 | 1162 | |
f1182638 | 1163 | if (disable_apic) { |
65a4e574 | 1164 | arch_disable_smp_support(); |
f1182638 JB |
1165 | return; |
1166 | } | |
1167 | ||
89c38c28 CG |
1168 | #ifdef CONFIG_X86_32 |
1169 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1170 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1171 | apic_write(APIC_ESR, 0); |
1172 | apic_write(APIC_ESR, 0); | |
1173 | apic_write(APIC_ESR, 0); | |
1174 | apic_write(APIC_ESR, 0); | |
1175 | } | |
1176 | #endif | |
cdd6c482 | 1177 | perf_events_lapic_init(); |
89c38c28 | 1178 | |
ac23d4ee | 1179 | preempt_disable(); |
1da177e4 | 1180 | |
1da177e4 LT |
1181 | /* |
1182 | * Double-check whether this APIC is really registered. | |
1183 | * This is meaningless in clustered apic mode, so we skip it. | |
1184 | */ | |
c2777f98 | 1185 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1186 | |
1187 | /* | |
1188 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1189 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1190 | * document number 292116). So here it goes... | |
1191 | */ | |
a5c43296 | 1192 | apic->init_apic_ldr(); |
1da177e4 LT |
1193 | |
1194 | /* | |
1195 | * Set Task Priority to 'accept all'. We never change this | |
1196 | * later on. | |
1197 | */ | |
1198 | value = apic_read(APIC_TASKPRI); | |
1199 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1200 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1201 | |
da7ed9f9 VG |
1202 | /* |
1203 | * After a crash, we no longer service the interrupts and a pending | |
1204 | * interrupt from previous kernel might still have ISR bit set. | |
1205 | * | |
1206 | * Most probably by now CPU has serviced that pending interrupt and | |
1207 | * it might not have done the ack_APIC_irq() because it thought, | |
1208 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1209 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1210 | * the interrupt. Hence a vector might get locked. It was noticed | |
1211 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1212 | */ | |
8c3ba8d0 KJ |
1213 | do { |
1214 | queued = 0; | |
1215 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1216 | queued |= apic_read(APIC_IRR + i*0x10); | |
1217 | ||
1218 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1219 | value = apic_read(APIC_ISR + i*0x10); | |
1220 | for (j = 31; j >= 0; j--) { | |
1221 | if (value & (1<<j)) { | |
1222 | ack_APIC_irq(); | |
1223 | acked++; | |
1224 | } | |
1225 | } | |
da7ed9f9 | 1226 | } |
8c3ba8d0 KJ |
1227 | if (acked > 256) { |
1228 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1229 | acked); | |
1230 | break; | |
1231 | } | |
1232 | if (cpu_has_tsc) { | |
1233 | rdtscll(ntsc); | |
1234 | max_loops = (cpu_khz << 10) - (ntsc - tsc); | |
1235 | } else | |
1236 | max_loops--; | |
1237 | } while (queued && max_loops > 0); | |
1238 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1239 | |
1da177e4 LT |
1240 | /* |
1241 | * Now that we are all set up, enable the APIC | |
1242 | */ | |
1243 | value = apic_read(APIC_SPIV); | |
1244 | value &= ~APIC_VECTOR_MASK; | |
1245 | /* | |
1246 | * Enable APIC | |
1247 | */ | |
1248 | value |= APIC_SPIV_APIC_ENABLED; | |
1249 | ||
89c38c28 CG |
1250 | #ifdef CONFIG_X86_32 |
1251 | /* | |
1252 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1253 | * certain networking cards. If high frequency interrupts are | |
1254 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1255 | * entry is masked/unmasked at a high rate as well then sooner or | |
1256 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1257 | * from the device. If focus CPU is disabled then the hang goes | |
1258 | * away, oh well :-( | |
1259 | * | |
1260 | * [ This bug can be reproduced easily with a level-triggered | |
1261 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1262 | * BX chipset. ] | |
1263 | */ | |
1264 | /* | |
1265 | * Actually disabling the focus CPU check just makes the hang less | |
1266 | * frequent as it makes the interrupt distributon model be more | |
1267 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1268 | * See also the comment in end_level_ioapic_irq(). --macro | |
1269 | */ | |
1270 | ||
1271 | /* | |
1272 | * - enable focus processor (bit==0) | |
1273 | * - 64bit mode always use processor focus | |
1274 | * so no need to set it | |
1275 | */ | |
1276 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1277 | #endif | |
3f14c746 | 1278 | |
1da177e4 LT |
1279 | /* |
1280 | * Set spurious IRQ vector | |
1281 | */ | |
1282 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1283 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1284 | |
1285 | /* | |
1286 | * Set up LVT0, LVT1: | |
1287 | * | |
1288 | * set up through-local-APIC on the BP's LINT0. This is not | |
1289 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1290 | * we delegate interrupts to the 8259A. | |
1291 | */ | |
1292 | /* | |
1293 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1294 | */ | |
1295 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1296 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1297 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1298 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1299 | smp_processor_id()); |
1da177e4 LT |
1300 | } else { |
1301 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1302 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1303 | smp_processor_id()); |
1da177e4 | 1304 | } |
11a8e778 | 1305 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1306 | |
1307 | /* | |
1308 | * only the BP should see the LINT1 NMI signal, obviously. | |
1309 | */ | |
1310 | if (!smp_processor_id()) | |
1311 | value = APIC_DM_NMI; | |
1312 | else | |
1313 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1314 | if (!lapic_is_integrated()) /* 82489DX */ |
1315 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1316 | apic_write(APIC_LVT1, value); |
89c38c28 | 1317 | |
ac23d4ee | 1318 | preempt_enable(); |
be71b855 AK |
1319 | |
1320 | #ifdef CONFIG_X86_MCE_INTEL | |
1321 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
1322 | if (smp_processor_id() == 0) | |
1323 | cmci_recheck(); | |
1324 | #endif | |
739f33b3 | 1325 | } |
1da177e4 | 1326 | |
739f33b3 AK |
1327 | void __cpuinit end_local_APIC_setup(void) |
1328 | { | |
1329 | lapic_setup_esr(); | |
fa6b95fc CG |
1330 | |
1331 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1332 | { |
1333 | unsigned int value; | |
1334 | /* Disable the local apic timer */ | |
1335 | value = apic_read(APIC_LVTT); | |
1336 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1337 | apic_write(APIC_LVTT, value); | |
1338 | } | |
fa6b95fc CG |
1339 | #endif |
1340 | ||
f2802e7f | 1341 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1342 | apic_pm_activate(); |
1da177e4 | 1343 | } |
1da177e4 | 1344 | |
06cd9a7d | 1345 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a SS |
1346 | void check_x2apic(void) |
1347 | { | |
ef1f87aa | 1348 | if (x2apic_enabled()) { |
ba21ebb6 | 1349 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
fc1edaf9 | 1350 | x2apic_preenabled = x2apic_mode = 1; |
6e1cb38a SS |
1351 | } |
1352 | } | |
1353 | ||
1354 | void enable_x2apic(void) | |
1355 | { | |
1356 | int msr, msr2; | |
1357 | ||
fc1edaf9 | 1358 | if (!x2apic_mode) |
06cd9a7d YL |
1359 | return; |
1360 | ||
6e1cb38a SS |
1361 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1362 | if (!(msr & X2APIC_ENABLE)) { | |
450b1e8d | 1363 | printk_once(KERN_INFO "Enabling x2apic\n"); |
6e1cb38a SS |
1364 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1365 | } | |
1366 | } | |
93758238 | 1367 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1368 | |
ce69a784 | 1369 | int __init enable_IR(void) |
6e1cb38a SS |
1370 | { |
1371 | #ifdef CONFIG_INTR_REMAP | |
93758238 WH |
1372 | if (!intr_remapping_supported()) { |
1373 | pr_debug("intr-remapping not supported\n"); | |
ce69a784 | 1374 | return 0; |
6e1cb38a SS |
1375 | } |
1376 | ||
93758238 WH |
1377 | if (!x2apic_preenabled && skip_ioapic_setup) { |
1378 | pr_info("Skipped enabling intr-remap because of skipping " | |
1379 | "io-apic setup\n"); | |
ce69a784 | 1380 | return 0; |
6e1cb38a SS |
1381 | } |
1382 | ||
ce69a784 GN |
1383 | if (enable_intr_remapping(x2apic_supported())) |
1384 | return 0; | |
1385 | ||
1386 | pr_info("Enabled Interrupt-remapping\n"); | |
1387 | ||
1388 | return 1; | |
1389 | ||
1390 | #endif | |
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | void __init enable_IR_x2apic(void) | |
1395 | { | |
1396 | unsigned long flags; | |
1397 | struct IO_APIC_route_entry **ioapic_entries = NULL; | |
1398 | int ret, x2apic_enabled = 0; | |
e670761f | 1399 | int dmar_table_init_ret; |
b7f42ab2 | 1400 | |
b7f42ab2 | 1401 | dmar_table_init_ret = dmar_table_init(); |
e670761f YL |
1402 | if (dmar_table_init_ret && !x2apic_supported()) |
1403 | return; | |
ce69a784 | 1404 | |
b24696bc FY |
1405 | ioapic_entries = alloc_ioapic_entries(); |
1406 | if (!ioapic_entries) { | |
ce69a784 GN |
1407 | pr_err("Allocate ioapic_entries failed\n"); |
1408 | goto out; | |
b24696bc FY |
1409 | } |
1410 | ||
1411 | ret = save_IO_APIC_setup(ioapic_entries); | |
5ffa4eb2 | 1412 | if (ret) { |
ba21ebb6 | 1413 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
ce69a784 | 1414 | goto out; |
5ffa4eb2 | 1415 | } |
6e1cb38a | 1416 | |
05c3dc2c | 1417 | local_irq_save(flags); |
b81bb373 | 1418 | legacy_pic->mask_all(); |
ce69a784 | 1419 | mask_IO_APIC_setup(ioapic_entries); |
05c3dc2c | 1420 | |
b7f42ab2 YL |
1421 | if (dmar_table_init_ret) |
1422 | ret = 0; | |
1423 | else | |
1424 | ret = enable_IR(); | |
1425 | ||
ce69a784 GN |
1426 | if (!ret) { |
1427 | /* IR is required if there is APIC ID > 255 even when running | |
1428 | * under KVM | |
1429 | */ | |
1430 | if (max_physical_apicid > 255 || !kvm_para_available()) | |
1431 | goto nox2apic; | |
1432 | /* | |
1433 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1434 | * only in physical mode | |
1435 | */ | |
1436 | x2apic_force_phys(); | |
1437 | } | |
6e1cb38a | 1438 | |
ce69a784 | 1439 | x2apic_enabled = 1; |
93758238 | 1440 | |
fc1edaf9 SS |
1441 | if (x2apic_supported() && !x2apic_mode) { |
1442 | x2apic_mode = 1; | |
6e1cb38a | 1443 | enable_x2apic(); |
93758238 | 1444 | pr_info("Enabled x2apic\n"); |
6e1cb38a | 1445 | } |
5ffa4eb2 | 1446 | |
ce69a784 GN |
1447 | nox2apic: |
1448 | if (!ret) /* IR enabling failed */ | |
b24696bc | 1449 | restore_IO_APIC_setup(ioapic_entries); |
b81bb373 | 1450 | legacy_pic->restore_mask(); |
6e1cb38a SS |
1451 | local_irq_restore(flags); |
1452 | ||
ce69a784 | 1453 | out: |
b24696bc FY |
1454 | if (ioapic_entries) |
1455 | free_ioapic_entries(ioapic_entries); | |
93758238 | 1456 | |
ce69a784 | 1457 | if (x2apic_enabled) |
93758238 WH |
1458 | return; |
1459 | ||
93758238 | 1460 | if (x2apic_preenabled) |
ce69a784 | 1461 | panic("x2apic: enabled by BIOS but kernel init failed."); |
93758238 | 1462 | else if (cpu_has_x2apic) |
ce69a784 | 1463 | pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); |
6e1cb38a | 1464 | } |
93758238 | 1465 | |
be7a656f | 1466 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1467 | /* |
1468 | * Detect and enable local APICs on non-SMP boards. | |
1469 | * Original code written by Keir Fraser. | |
1470 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1471 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1472 | */ |
0e078e2f | 1473 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1474 | { |
1475 | if (!cpu_has_apic) { | |
ba21ebb6 | 1476 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1477 | return -1; |
1478 | } | |
1479 | ||
1480 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1481 | return 0; |
1482 | } | |
be7a656f YL |
1483 | #else |
1484 | /* | |
1485 | * Detect and initialize APIC | |
1486 | */ | |
1487 | static int __init detect_init_APIC(void) | |
1488 | { | |
1489 | u32 h, l, features; | |
1490 | ||
1491 | /* Disabled by kernel option? */ | |
1492 | if (disable_apic) | |
1493 | return -1; | |
1494 | ||
1495 | switch (boot_cpu_data.x86_vendor) { | |
1496 | case X86_VENDOR_AMD: | |
1497 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1498 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1499 | break; |
1500 | goto no_apic; | |
1501 | case X86_VENDOR_INTEL: | |
1502 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1503 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1504 | break; | |
1505 | goto no_apic; | |
1506 | default: | |
1507 | goto no_apic; | |
1508 | } | |
1509 | ||
1510 | if (!cpu_has_apic) { | |
1511 | /* | |
1512 | * Over-ride BIOS and try to enable the local APIC only if | |
1513 | * "lapic" specified. | |
1514 | */ | |
1515 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1516 | pr_info("Local APIC disabled by BIOS -- " |
1517 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1518 | return -1; |
1519 | } | |
1520 | /* | |
1521 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1522 | * MSR. This can only be done in software for Intel P6 or later | |
1523 | * and AMD K7 (Model > 1) or later. | |
1524 | */ | |
1525 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1526 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1527 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1528 | l &= ~MSR_IA32_APICBASE_BASE; |
1529 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1530 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1531 | enabled_via_apicbase = 1; | |
1532 | } | |
1533 | } | |
1534 | /* | |
1535 | * The APIC feature bit should now be enabled | |
1536 | * in `cpuid' | |
1537 | */ | |
1538 | features = cpuid_edx(1); | |
1539 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1540 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1541 | return -1; |
1542 | } | |
1543 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1544 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1545 | ||
1546 | /* The BIOS may have set up the APIC at some other address */ | |
1547 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1548 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1549 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1550 | ||
ba21ebb6 | 1551 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1552 | |
1553 | apic_pm_activate(); | |
1554 | ||
1555 | return 0; | |
1556 | ||
1557 | no_apic: | |
ba21ebb6 | 1558 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1559 | return -1; |
1560 | } | |
1561 | #endif | |
1da177e4 | 1562 | |
f28c0ae2 | 1563 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1564 | void __init early_init_lapic_mapping(void) |
1565 | { | |
8643f9d0 YL |
1566 | /* |
1567 | * If no local APIC can be found then go out | |
1568 | * : it means there is no mpatable and MADT | |
1569 | */ | |
1570 | if (!smp_found_config) | |
1571 | return; | |
1572 | ||
d3a247bf | 1573 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
8643f9d0 | 1574 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
d3a247bf | 1575 | APIC_BASE, mp_lapic_addr); |
8643f9d0 YL |
1576 | |
1577 | /* | |
1578 | * Fetch the APIC ID of the BSP in case we have a | |
1579 | * default configuration (or the MP table is broken). | |
1580 | */ | |
4c9961d5 | 1581 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1582 | } |
f28c0ae2 | 1583 | #endif |
8643f9d0 | 1584 | |
0e078e2f TG |
1585 | /** |
1586 | * init_apic_mappings - initialize APIC mappings | |
1587 | */ | |
1da177e4 LT |
1588 | void __init init_apic_mappings(void) |
1589 | { | |
4401da61 YL |
1590 | unsigned int new_apicid; |
1591 | ||
fc1edaf9 | 1592 | if (x2apic_mode) { |
4c9961d5 | 1593 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1594 | return; |
1595 | } | |
1596 | ||
4797f6b0 | 1597 | /* If no local APIC can be found return early */ |
1da177e4 | 1598 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1599 | /* lets NOP'ify apic operations */ |
1600 | pr_info("APIC: disable apic facility\n"); | |
1601 | apic_disable(); | |
1602 | } else { | |
1da177e4 LT |
1603 | apic_phys = mp_lapic_addr; |
1604 | ||
4797f6b0 YL |
1605 | /* |
1606 | * acpi lapic path already maps that address in | |
1607 | * acpi_register_lapic_address() | |
1608 | */ | |
1609 | if (!acpi_lapic) | |
1610 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
cec6be6d | 1611 | |
4797f6b0 YL |
1612 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
1613 | APIC_BASE, apic_phys); | |
cec6be6d | 1614 | } |
1da177e4 LT |
1615 | |
1616 | /* | |
1617 | * Fetch the APIC ID of the BSP in case we have a | |
1618 | * default configuration (or the MP table is broken). | |
1619 | */ | |
4401da61 YL |
1620 | new_apicid = read_apic_id(); |
1621 | if (boot_cpu_physical_apicid != new_apicid) { | |
1622 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1623 | /* |
1624 | * yeah -- we lie about apic_version | |
1625 | * in case if apic was disabled via boot option | |
1626 | * but it's not a problem for SMP compiled kernel | |
1627 | * since smp_sanity_check is prepared for such a case | |
1628 | * and disable smp mode | |
1629 | */ | |
4401da61 YL |
1630 | apic_version[new_apicid] = |
1631 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1632 | } |
1da177e4 LT |
1633 | } |
1634 | ||
1635 | /* | |
0e078e2f TG |
1636 | * This initializes the IO-APIC and APIC hardware if this is |
1637 | * a UP kernel. | |
1da177e4 | 1638 | */ |
1b313f4a CG |
1639 | int apic_version[MAX_APICS]; |
1640 | ||
0e078e2f | 1641 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1642 | { |
0e078e2f | 1643 | if (disable_apic) { |
ba21ebb6 | 1644 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1645 | return -1; |
1646 | } | |
f1182638 | 1647 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1648 | if (!cpu_has_apic) { |
1649 | disable_apic = 1; | |
ba21ebb6 | 1650 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1651 | return -1; |
1652 | } | |
fa2bd35a YL |
1653 | #else |
1654 | if (!smp_found_config && !cpu_has_apic) | |
1655 | return -1; | |
1656 | ||
1657 | /* | |
1658 | * Complain if the BIOS pretends there is one. | |
1659 | */ | |
1660 | if (!cpu_has_apic && | |
1661 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1662 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1663 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1664 | return -1; |
1665 | } | |
1666 | #endif | |
1667 | ||
472a474c | 1668 | #ifndef CONFIG_SMP |
6e1cb38a | 1669 | enable_IR_x2apic(); |
72ce0165 | 1670 | default_setup_apic_routing(); |
472a474c | 1671 | #endif |
6e1cb38a | 1672 | |
0e078e2f | 1673 | verify_local_APIC(); |
b5841765 GC |
1674 | connect_bsp_APIC(); |
1675 | ||
fa2bd35a | 1676 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1677 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1678 | #else |
1679 | /* | |
1680 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1681 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1682 | * might be zero if read from MP tables. Get it from LAPIC. | |
1683 | */ | |
1684 | # ifdef CONFIG_CRASH_DUMP | |
1685 | boot_cpu_physical_apicid = read_apic_id(); | |
1686 | # endif | |
1687 | #endif | |
1688 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1689 | setup_local_APIC(); |
1da177e4 | 1690 | |
88d0f550 | 1691 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1692 | /* |
1693 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1694 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1695 | */ |
1696 | if (!skip_ioapic_setup && nr_ioapics) | |
1697 | enable_IO_APIC(); | |
fa2bd35a | 1698 | #endif |
739f33b3 AK |
1699 | |
1700 | end_local_APIC_setup(); | |
1701 | ||
fa2bd35a | 1702 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1703 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1704 | setup_IO_APIC(); | |
98c061b6 | 1705 | else { |
0e078e2f | 1706 | nr_ioapics = 0; |
98c061b6 YL |
1707 | localise_nmi_watchdog(); |
1708 | } | |
1709 | #else | |
1710 | localise_nmi_watchdog(); | |
fa2bd35a YL |
1711 | #endif |
1712 | ||
736decac | 1713 | x86_init.timers.setup_percpu_clockev(); |
fa2bd35a | 1714 | #ifdef CONFIG_X86_64 |
0e078e2f | 1715 | check_nmi_watchdog(); |
fa2bd35a YL |
1716 | #endif |
1717 | ||
0e078e2f | 1718 | return 0; |
1da177e4 LT |
1719 | } |
1720 | ||
1721 | /* | |
0e078e2f | 1722 | * Local APIC interrupts |
1da177e4 LT |
1723 | */ |
1724 | ||
0e078e2f TG |
1725 | /* |
1726 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1727 | */ | |
dc1528dd | 1728 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1729 | { |
dc1528dd YL |
1730 | u32 v; |
1731 | ||
0e078e2f TG |
1732 | exit_idle(); |
1733 | irq_enter(); | |
1da177e4 | 1734 | /* |
0e078e2f TG |
1735 | * Check if this really is a spurious interrupt and ACK it |
1736 | * if it is a vectored one. Just in case... | |
1737 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1738 | */ |
0e078e2f TG |
1739 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1740 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1741 | ack_APIC_irq(); | |
c4d58cbd | 1742 | |
915b0d01 HS |
1743 | inc_irq_stat(irq_spurious_count); |
1744 | ||
dc1528dd | 1745 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1746 | pr_info("spurious APIC interrupt on CPU#%d, " |
1747 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1748 | irq_exit(); |
1749 | } | |
1da177e4 | 1750 | |
0e078e2f TG |
1751 | /* |
1752 | * This interrupt should never happen with our APIC/SMP architecture | |
1753 | */ | |
dc1528dd | 1754 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1755 | { |
dc1528dd | 1756 | u32 v, v1; |
1da177e4 | 1757 | |
0e078e2f TG |
1758 | exit_idle(); |
1759 | irq_enter(); | |
1760 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1761 | v = apic_read(APIC_ESR); | |
1762 | apic_write(APIC_ESR, 0); | |
1763 | v1 = apic_read(APIC_ESR); | |
1764 | ack_APIC_irq(); | |
1765 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1766 | |
ba21ebb6 CG |
1767 | /* |
1768 | * Here is what the APIC error bits mean: | |
1769 | * 0: Send CS error | |
1770 | * 1: Receive CS error | |
1771 | * 2: Send accept error | |
1772 | * 3: Receive accept error | |
1773 | * 4: Reserved | |
1774 | * 5: Send illegal vector | |
1775 | * 6: Received illegal vector | |
1776 | * 7: Illegal register address | |
1777 | */ | |
1778 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1779 | smp_processor_id(), v , v1); |
1780 | irq_exit(); | |
1da177e4 LT |
1781 | } |
1782 | ||
b5841765 | 1783 | /** |
36c9d674 CG |
1784 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1785 | */ | |
b5841765 GC |
1786 | void __init connect_bsp_APIC(void) |
1787 | { | |
36c9d674 CG |
1788 | #ifdef CONFIG_X86_32 |
1789 | if (pic_mode) { | |
1790 | /* | |
1791 | * Do not trust the local APIC being empty at bootup. | |
1792 | */ | |
1793 | clear_local_APIC(); | |
1794 | /* | |
1795 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1796 | * local APIC to INT and NMI lines. | |
1797 | */ | |
1798 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1799 | "enabling APIC mode.\n"); | |
c0eaa453 | 1800 | imcr_pic_to_apic(); |
36c9d674 CG |
1801 | } |
1802 | #endif | |
49040333 IM |
1803 | if (apic->enable_apic_mode) |
1804 | apic->enable_apic_mode(); | |
b5841765 GC |
1805 | } |
1806 | ||
274cfe59 CG |
1807 | /** |
1808 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1809 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1810 | * | |
1811 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1812 | * APIC is disabled. | |
1813 | */ | |
0e078e2f | 1814 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1815 | { |
1b4ee4e4 CG |
1816 | unsigned int value; |
1817 | ||
c177b0bc CG |
1818 | #ifdef CONFIG_X86_32 |
1819 | if (pic_mode) { | |
1820 | /* | |
1821 | * Put the board back into PIC mode (has an effect only on | |
1822 | * certain older boards). Note that APIC interrupts, including | |
1823 | * IPIs, won't work beyond this point! The only exception are | |
1824 | * INIT IPIs. | |
1825 | */ | |
1826 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1827 | "entering PIC mode.\n"); | |
c0eaa453 | 1828 | imcr_apic_to_pic(); |
c177b0bc CG |
1829 | return; |
1830 | } | |
1831 | #endif | |
1832 | ||
0e078e2f | 1833 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1834 | |
0e078e2f TG |
1835 | /* For the spurious interrupt use vector F, and enable it */ |
1836 | value = apic_read(APIC_SPIV); | |
1837 | value &= ~APIC_VECTOR_MASK; | |
1838 | value |= APIC_SPIV_APIC_ENABLED; | |
1839 | value |= 0xf; | |
1840 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1841 | |
0e078e2f TG |
1842 | if (!virt_wire_setup) { |
1843 | /* | |
1844 | * For LVT0 make it edge triggered, active high, | |
1845 | * external and enabled | |
1846 | */ | |
1847 | value = apic_read(APIC_LVT0); | |
1848 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1849 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1850 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1851 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1852 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1853 | apic_write(APIC_LVT0, value); | |
1854 | } else { | |
1855 | /* Disable LVT0 */ | |
1856 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1857 | } | |
b8ce3359 | 1858 | |
c177b0bc CG |
1859 | /* |
1860 | * For LVT1 make it edge triggered, active high, | |
1861 | * nmi and enabled | |
1862 | */ | |
0e078e2f TG |
1863 | value = apic_read(APIC_LVT1); |
1864 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1865 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1866 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1867 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1868 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1869 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1870 | } |
1871 | ||
be8a5685 AS |
1872 | void __cpuinit generic_processor_info(int apicid, int version) |
1873 | { | |
1874 | int cpu; | |
be8a5685 | 1875 | |
1b313f4a CG |
1876 | /* |
1877 | * Validate version | |
1878 | */ | |
1879 | if (version == 0x0) { | |
ba21ebb6 | 1880 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1881 | "fixing up to 0x10. (tell your hw vendor)\n", |
1882 | version); | |
1b313f4a | 1883 | version = 0x10; |
be8a5685 | 1884 | } |
1b313f4a | 1885 | apic_version[apicid] = version; |
be8a5685 | 1886 | |
3b11ce7f MT |
1887 | if (num_processors >= nr_cpu_ids) { |
1888 | int max = nr_cpu_ids; | |
1889 | int thiscpu = max + disabled_cpus; | |
1890 | ||
1891 | pr_warning( | |
1892 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1893 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1894 | ||
1895 | disabled_cpus++; | |
be8a5685 AS |
1896 | return; |
1897 | } | |
1898 | ||
1899 | num_processors++; | |
3b11ce7f | 1900 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1901 | |
b2b815d8 MT |
1902 | if (version != apic_version[boot_cpu_physical_apicid]) |
1903 | WARN_ONCE(1, | |
1904 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1905 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1906 | ||
be8a5685 AS |
1907 | physid_set(apicid, phys_cpu_present_map); |
1908 | if (apicid == boot_cpu_physical_apicid) { | |
1909 | /* | |
1910 | * x86_bios_cpu_apicid is required to have processors listed | |
1911 | * in same order as logical cpu numbers. Hence the first | |
1912 | * entry is BSP, and so on. | |
1913 | */ | |
1914 | cpu = 0; | |
1915 | } | |
e0da3364 YL |
1916 | if (apicid > max_physical_apicid) |
1917 | max_physical_apicid = apicid; | |
1918 | ||
3e5095d1 | 1919 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
1920 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1921 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 1922 | #endif |
be8a5685 | 1923 | |
1de88cd4 MT |
1924 | set_cpu_possible(cpu, true); |
1925 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1926 | } |
1927 | ||
0c81c746 SS |
1928 | int hard_smp_processor_id(void) |
1929 | { | |
1930 | return read_apic_id(); | |
1931 | } | |
1dcdd3d1 IM |
1932 | |
1933 | void default_init_apic_ldr(void) | |
1934 | { | |
1935 | unsigned long val; | |
1936 | ||
1937 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
1938 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
1939 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
1940 | apic_write(APIC_LDR, val); | |
1941 | } | |
1942 | ||
1943 | #ifdef CONFIG_X86_32 | |
1944 | int default_apicid_to_node(int logical_apicid) | |
1945 | { | |
1946 | #ifdef CONFIG_SMP | |
1947 | return apicid_2_node[hard_smp_processor_id()]; | |
1948 | #else | |
1949 | return 0; | |
1950 | #endif | |
1951 | } | |
3491998d | 1952 | #endif |
0c81c746 | 1953 | |
89039b37 | 1954 | /* |
0e078e2f | 1955 | * Power management |
89039b37 | 1956 | */ |
0e078e2f TG |
1957 | #ifdef CONFIG_PM |
1958 | ||
1959 | static struct { | |
274cfe59 CG |
1960 | /* |
1961 | * 'active' is true if the local APIC was enabled by us and | |
1962 | * not the BIOS; this signifies that we are also responsible | |
1963 | * for disabling it before entering apm/acpi suspend | |
1964 | */ | |
0e078e2f TG |
1965 | int active; |
1966 | /* r/w apic fields */ | |
1967 | unsigned int apic_id; | |
1968 | unsigned int apic_taskpri; | |
1969 | unsigned int apic_ldr; | |
1970 | unsigned int apic_dfr; | |
1971 | unsigned int apic_spiv; | |
1972 | unsigned int apic_lvtt; | |
1973 | unsigned int apic_lvtpc; | |
1974 | unsigned int apic_lvt0; | |
1975 | unsigned int apic_lvt1; | |
1976 | unsigned int apic_lvterr; | |
1977 | unsigned int apic_tmict; | |
1978 | unsigned int apic_tdcr; | |
1979 | unsigned int apic_thmr; | |
1980 | } apic_pm_state; | |
1981 | ||
1982 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1983 | { | |
1984 | unsigned long flags; | |
1985 | int maxlvt; | |
89039b37 | 1986 | |
0e078e2f TG |
1987 | if (!apic_pm_state.active) |
1988 | return 0; | |
89039b37 | 1989 | |
0e078e2f | 1990 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1991 | |
2d7a66d0 | 1992 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1993 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1994 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1995 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1996 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1997 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1998 | if (maxlvt >= 4) | |
1999 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2000 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2001 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2002 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2003 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2004 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2005 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2006 | if (maxlvt >= 5) |
2007 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2008 | #endif | |
24968cfd | 2009 | |
0e078e2f TG |
2010 | local_irq_save(flags); |
2011 | disable_local_APIC(); | |
fc1edaf9 | 2012 | |
b24696bc FY |
2013 | if (intr_remapping_enabled) |
2014 | disable_intr_remapping(); | |
fc1edaf9 | 2015 | |
0e078e2f TG |
2016 | local_irq_restore(flags); |
2017 | return 0; | |
1da177e4 LT |
2018 | } |
2019 | ||
0e078e2f | 2020 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 2021 | { |
0e078e2f TG |
2022 | unsigned int l, h; |
2023 | unsigned long flags; | |
2024 | int maxlvt; | |
3d58829b | 2025 | int ret = 0; |
b24696bc FY |
2026 | struct IO_APIC_route_entry **ioapic_entries = NULL; |
2027 | ||
0e078e2f TG |
2028 | if (!apic_pm_state.active) |
2029 | return 0; | |
89b831ef | 2030 | |
0e078e2f | 2031 | local_irq_save(flags); |
9a2755c3 | 2032 | if (intr_remapping_enabled) { |
b24696bc FY |
2033 | ioapic_entries = alloc_ioapic_entries(); |
2034 | if (!ioapic_entries) { | |
2035 | WARN(1, "Alloc ioapic_entries in lapic resume failed."); | |
3d58829b JS |
2036 | ret = -ENOMEM; |
2037 | goto restore; | |
b24696bc FY |
2038 | } |
2039 | ||
2040 | ret = save_IO_APIC_setup(ioapic_entries); | |
2041 | if (ret) { | |
2042 | WARN(1, "Saving IO-APIC state failed: %d\n", ret); | |
2043 | free_ioapic_entries(ioapic_entries); | |
3d58829b | 2044 | goto restore; |
b24696bc FY |
2045 | } |
2046 | ||
2047 | mask_IO_APIC_setup(ioapic_entries); | |
b81bb373 | 2048 | legacy_pic->mask_all(); |
b24696bc | 2049 | } |
92206c90 | 2050 | |
fc1edaf9 | 2051 | if (x2apic_mode) |
92206c90 | 2052 | enable_x2apic(); |
cf6567fe | 2053 | else { |
92206c90 CG |
2054 | /* |
2055 | * Make sure the APICBASE points to the right address | |
2056 | * | |
2057 | * FIXME! This will be wrong if we ever support suspend on | |
2058 | * SMP! We'll need to do this as part of the CPU restore! | |
2059 | */ | |
6e1cb38a SS |
2060 | rdmsr(MSR_IA32_APICBASE, l, h); |
2061 | l &= ~MSR_IA32_APICBASE_BASE; | |
2062 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2063 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2064 | } |
6e1cb38a | 2065 | |
b24696bc | 2066 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2067 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2068 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2069 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2070 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2071 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2072 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2073 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2074 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2075 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2076 | if (maxlvt >= 5) |
2077 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2078 | #endif | |
2079 | if (maxlvt >= 4) | |
2080 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2081 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2082 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2083 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2084 | apic_write(APIC_ESR, 0); | |
2085 | apic_read(APIC_ESR); | |
2086 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2087 | apic_write(APIC_ESR, 0); | |
2088 | apic_read(APIC_ESR); | |
92206c90 | 2089 | |
9a2755c3 | 2090 | if (intr_remapping_enabled) { |
fc1edaf9 | 2091 | reenable_intr_remapping(x2apic_mode); |
b81bb373 | 2092 | legacy_pic->restore_mask(); |
b24696bc FY |
2093 | restore_IO_APIC_setup(ioapic_entries); |
2094 | free_ioapic_entries(ioapic_entries); | |
2095 | } | |
3d58829b | 2096 | restore: |
0e078e2f | 2097 | local_irq_restore(flags); |
92206c90 | 2098 | |
3d58829b | 2099 | return ret; |
0e078e2f | 2100 | } |
b8ce3359 | 2101 | |
274cfe59 CG |
2102 | /* |
2103 | * This device has no shutdown method - fully functioning local APICs | |
2104 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2105 | */ | |
2106 | ||
0e078e2f TG |
2107 | static struct sysdev_class lapic_sysclass = { |
2108 | .name = "lapic", | |
2109 | .resume = lapic_resume, | |
2110 | .suspend = lapic_suspend, | |
2111 | }; | |
b8ce3359 | 2112 | |
0e078e2f | 2113 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2114 | .id = 0, |
2115 | .cls = &lapic_sysclass, | |
0e078e2f | 2116 | }; |
b8ce3359 | 2117 | |
0e078e2f TG |
2118 | static void __cpuinit apic_pm_activate(void) |
2119 | { | |
2120 | apic_pm_state.active = 1; | |
1da177e4 LT |
2121 | } |
2122 | ||
0e078e2f | 2123 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2124 | { |
0e078e2f | 2125 | int error; |
e83a5fdc | 2126 | |
0e078e2f TG |
2127 | if (!cpu_has_apic) |
2128 | return 0; | |
2129 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2130 | |
0e078e2f TG |
2131 | error = sysdev_class_register(&lapic_sysclass); |
2132 | if (!error) | |
2133 | error = sysdev_register(&device_lapic); | |
2134 | return error; | |
1da177e4 | 2135 | } |
b24696bc FY |
2136 | |
2137 | /* local apic needs to resume before other devices access its registers. */ | |
2138 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2139 | |
2140 | #else /* CONFIG_PM */ | |
2141 | ||
2142 | static void apic_pm_activate(void) { } | |
2143 | ||
2144 | #endif /* CONFIG_PM */ | |
1da177e4 | 2145 | |
f28c0ae2 | 2146 | #ifdef CONFIG_X86_64 |
e0e42142 YL |
2147 | |
2148 | static int __cpuinit apic_cluster_num(void) | |
1da177e4 LT |
2149 | { |
2150 | int i, clusters, zeros; | |
2151 | unsigned id; | |
322850af | 2152 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2153 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2154 | ||
23ca4bba | 2155 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2156 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2157 | |
168ef543 | 2158 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2159 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2160 | if (bios_cpu_apicid) { |
2161 | id = bios_cpu_apicid[i]; | |
e423e33e | 2162 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2163 | if (cpu_present(i)) |
2164 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2165 | else | |
2166 | continue; | |
e423e33e | 2167 | } else |
e8c10ef9 | 2168 | break; |
2169 | ||
1da177e4 LT |
2170 | if (id != BAD_APICID) |
2171 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2172 | } | |
2173 | ||
2174 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2175 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2176 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2177 | * Since clusters are allocated sequentially, count zeros only if | |
2178 | * they are bounded by ones. | |
1da177e4 LT |
2179 | */ |
2180 | clusters = 0; | |
2181 | zeros = 0; | |
2182 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2183 | if (test_bit(i, clustermap)) { | |
2184 | clusters += 1 + zeros; | |
2185 | zeros = 0; | |
2186 | } else | |
2187 | ++zeros; | |
2188 | } | |
2189 | ||
e0e42142 YL |
2190 | return clusters; |
2191 | } | |
2192 | ||
2193 | static int __cpuinitdata multi_checked; | |
2194 | static int __cpuinitdata multi; | |
2195 | ||
2196 | static int __cpuinit set_multi(const struct dmi_system_id *d) | |
2197 | { | |
2198 | if (multi) | |
2199 | return 0; | |
6f0aced6 | 2200 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2201 | multi = 1; |
2202 | return 0; | |
2203 | } | |
2204 | ||
2205 | static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { | |
2206 | { | |
2207 | .callback = set_multi, | |
2208 | .ident = "IBM System Summit2", | |
2209 | .matches = { | |
2210 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2211 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2212 | }, | |
2213 | }, | |
2214 | {} | |
2215 | }; | |
2216 | ||
2217 | static void __cpuinit dmi_check_multi(void) | |
2218 | { | |
2219 | if (multi_checked) | |
2220 | return; | |
2221 | ||
2222 | dmi_check_system(multi_dmi_table); | |
2223 | multi_checked = 1; | |
2224 | } | |
2225 | ||
2226 | /* | |
2227 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2228 | * | |
2229 | * Thus far, the major user of this is IBM's Summit2 series: | |
2230 | * Clustered boxes may have unsynced TSC problems if they are | |
2231 | * multi-chassis. | |
2232 | * Use DMI to check them | |
2233 | */ | |
2234 | __cpuinit int apic_is_clustered_box(void) | |
2235 | { | |
2236 | dmi_check_multi(); | |
2237 | if (multi) | |
1cb68487 RT |
2238 | return 1; |
2239 | ||
e0e42142 YL |
2240 | if (!is_vsmp_box()) |
2241 | return 0; | |
2242 | ||
1da177e4 | 2243 | /* |
e0e42142 YL |
2244 | * ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2245 | * not guaranteed to be synced between boards | |
1da177e4 | 2246 | */ |
e0e42142 YL |
2247 | if (apic_cluster_num() > 1) |
2248 | return 1; | |
2249 | ||
2250 | return 0; | |
1da177e4 | 2251 | } |
f28c0ae2 | 2252 | #endif |
1da177e4 LT |
2253 | |
2254 | /* | |
0e078e2f | 2255 | * APIC command line parameters |
1da177e4 | 2256 | */ |
789fa735 | 2257 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2258 | { |
1da177e4 | 2259 | disable_apic = 1; |
9175fc06 | 2260 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2261 | return 0; |
2262 | } | |
2263 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2264 | |
2c8c0e6b | 2265 | /* same as disableapic, for compatibility */ |
789fa735 | 2266 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2267 | { |
789fa735 | 2268 | return setup_disableapic(arg); |
6935d1f9 | 2269 | } |
2c8c0e6b | 2270 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2271 | |
2e7c2838 LT |
2272 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2273 | { | |
2274 | local_apic_timer_c2_ok = 1; | |
2275 | return 0; | |
2276 | } | |
2277 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2278 | ||
36fef094 | 2279 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2280 | { |
1da177e4 | 2281 | disable_apic_timer = 1; |
36fef094 | 2282 | return 0; |
6935d1f9 | 2283 | } |
36fef094 CG |
2284 | early_param("noapictimer", parse_disable_apic_timer); |
2285 | ||
2286 | static int __init parse_nolapic_timer(char *arg) | |
2287 | { | |
2288 | disable_apic_timer = 1; | |
2289 | return 0; | |
6935d1f9 | 2290 | } |
36fef094 | 2291 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2292 | |
79af9bec CG |
2293 | static int __init apic_set_verbosity(char *arg) |
2294 | { | |
2295 | if (!arg) { | |
2296 | #ifdef CONFIG_X86_64 | |
2297 | skip_ioapic_setup = 0; | |
79af9bec CG |
2298 | return 0; |
2299 | #endif | |
2300 | return -EINVAL; | |
2301 | } | |
2302 | ||
2303 | if (strcmp("debug", arg) == 0) | |
2304 | apic_verbosity = APIC_DEBUG; | |
2305 | else if (strcmp("verbose", arg) == 0) | |
2306 | apic_verbosity = APIC_VERBOSE; | |
2307 | else { | |
ba21ebb6 | 2308 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2309 | " use apic=verbose or apic=debug\n", arg); |
2310 | return -EINVAL; | |
2311 | } | |
2312 | ||
2313 | return 0; | |
2314 | } | |
2315 | early_param("apic", apic_set_verbosity); | |
2316 | ||
1e934dda YL |
2317 | static int __init lapic_insert_resource(void) |
2318 | { | |
2319 | if (!apic_phys) | |
2320 | return -1; | |
2321 | ||
2322 | /* Put local APIC into the resource map. */ | |
2323 | lapic_resource.start = apic_phys; | |
2324 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2325 | insert_resource(&iomem_resource, &lapic_resource); | |
2326 | ||
2327 | return 0; | |
2328 | } | |
2329 | ||
2330 | /* | |
2331 | * need call insert after e820_reserve_resources() | |
2332 | * that is using request_resource | |
2333 | */ | |
2334 | late_initcall(lapic_insert_resource); |