]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
186f4360 | 26 | #include <linux/export.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
83ab8514 | 38 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 39 | #include <asm/irq_remapping.h> |
cdd6c482 | 40 | #include <asm/perf_event.h> |
736decac | 41 | #include <asm/x86_init.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
60063497 | 43 | #include <linux/atomic.h> |
1da177e4 | 44 | #include <asm/mpspec.h> |
d1de36f5 | 45 | #include <asm/i8259.h> |
73dea47f | 46 | #include <asm/proto.h> |
2c8c0e6b | 47 | #include <asm/apic.h> |
7167d08e | 48 | #include <asm/io_apic.h> |
d1de36f5 IM |
49 | #include <asm/desc.h> |
50 | #include <asm/hpet.h> | |
d1de36f5 | 51 | #include <asm/mtrr.h> |
16f871bc | 52 | #include <asm/time.h> |
2bc13797 | 53 | #include <asm/smp.h> |
be71b855 | 54 | #include <asm/mce.h> |
8c3ba8d0 | 55 | #include <asm/tsc.h> |
2904ed8d | 56 | #include <asm/hypervisor.h> |
1da177e4 | 57 | |
ec70de8b | 58 | unsigned int num_processors; |
fdbecd9f | 59 | |
148f9bb8 | 60 | unsigned disabled_cpus; |
fdbecd9f | 61 | |
ec70de8b BG |
62 | /* Processor that is doing the boot up */ |
63 | unsigned int boot_cpu_physical_apicid = -1U; | |
cc08e04c | 64 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 65 | |
cff9ab2b DV |
66 | u8 boot_cpu_apic_version; |
67 | ||
80e5609c | 68 | /* |
fdbecd9f | 69 | * The highest APIC ID seen during enumeration. |
80e5609c | 70 | */ |
a491cc90 | 71 | static unsigned int max_physical_apicid; |
5af5573e | 72 | |
80e5609c | 73 | /* |
fdbecd9f | 74 | * Bitmask of physically existing CPUs: |
80e5609c | 75 | */ |
ec70de8b BG |
76 | physid_mask_t phys_cpu_present_map; |
77 | ||
151e0c7d HD |
78 | /* |
79 | * Processor to be disabled specified by kernel parameter | |
80 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
81 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
82 | */ | |
5b4d1dbc | 83 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
151e0c7d | 84 | |
b7c4948e HK |
85 | /* |
86 | * This variable controls which CPUs receive external NMIs. By default, | |
87 | * external NMIs are delivered only to the BSP. | |
88 | */ | |
89 | static int apic_extnmi = APIC_EXTNMI_BSP; | |
90 | ||
ec70de8b BG |
91 | /* |
92 | * Map cpu index to physical APIC ID | |
93 | */ | |
0816b0f0 VZ |
94 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
95 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); | |
3e9e57fa | 96 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); |
ec70de8b BG |
97 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
98 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
3e9e57fa | 99 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); |
80e5609c | 100 | |
b3c51170 | 101 | #ifdef CONFIG_X86_32 |
4c321ff8 | 102 | |
4c321ff8 TH |
103 | /* |
104 | * On x86_32, the mapping between cpu and logical apicid may vary | |
105 | * depending on apic in use. The following early percpu variable is | |
106 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
107 | * actually diverge. Let's keep it ugly for now. | |
108 | */ | |
0816b0f0 | 109 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 110 | |
f28c0ae2 YL |
111 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
112 | static int enabled_via_apicbase; | |
113 | ||
c0eaa453 CG |
114 | /* |
115 | * Handle interrupt mode configuration register (IMCR). | |
116 | * This register controls whether the interrupt signals | |
117 | * that reach the BSP come from the master PIC or from the | |
118 | * local APIC. Before entering Symmetric I/O Mode, either | |
119 | * the BIOS or the operating system must switch out of | |
120 | * PIC Mode by changing the IMCR. | |
121 | */ | |
5cda395f | 122 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
123 | { |
124 | /* select IMCR register */ | |
125 | outb(0x70, 0x22); | |
126 | /* NMI and 8259 INTR go through APIC */ | |
127 | outb(0x01, 0x23); | |
128 | } | |
129 | ||
5cda395f | 130 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
131 | { |
132 | /* select IMCR register */ | |
133 | outb(0x70, 0x22); | |
134 | /* NMI and 8259 INTR go directly to BSP */ | |
135 | outb(0x00, 0x23); | |
136 | } | |
b3c51170 YL |
137 | #endif |
138 | ||
279f1461 SS |
139 | /* |
140 | * Knob to control our willingness to enable the local APIC. | |
141 | * | |
142 | * +1=force-enable | |
143 | */ | |
144 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 145 | |
279f1461 SS |
146 | /* |
147 | * APIC command line parameters | |
148 | */ | |
149 | static int __init parse_lapic(char *arg) | |
150 | { | |
97f2645f | 151 | if (IS_ENABLED(CONFIG_X86_32) && !arg) |
279f1461 | 152 | force_enable_local_apic = 1; |
27cf9298 | 153 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
154 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
155 | return 0; | |
156 | } | |
157 | early_param("lapic", parse_lapic); | |
158 | ||
b3c51170 | 159 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 160 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
161 | static __init int setup_apicpmtimer(char *s) |
162 | { | |
163 | apic_calibrate_pmtmr = 1; | |
164 | notsc_setup(NULL); | |
165 | return 0; | |
166 | } | |
167 | __setup("apicpmtimer", setup_apicpmtimer); | |
168 | #endif | |
169 | ||
b3c51170 YL |
170 | unsigned long mp_lapic_addr; |
171 | int disable_apic; | |
172 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 173 | static int disable_apic_timer __initdata; |
e83a5fdc | 174 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
175 | int local_apic_timer_c2_ok; |
176 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
177 | ||
2414e021 | 178 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
efa2559f | 179 | |
e83a5fdc HS |
180 | /* |
181 | * Debug level, exported for io_apic.c | |
182 | */ | |
baa13188 | 183 | unsigned int apic_verbosity; |
e83a5fdc | 184 | |
89c38c28 CG |
185 | int pic_mode; |
186 | ||
bab4b27c AS |
187 | /* Have we found an MP table */ |
188 | int smp_found_config; | |
189 | ||
39928722 AD |
190 | static struct resource lapic_resource = { |
191 | .name = "Local APIC", | |
192 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
193 | }; | |
194 | ||
1ade93ef | 195 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 196 | |
0e078e2f | 197 | static void apic_pm_activate(void); |
ba7eda4c | 198 | |
d3432896 AK |
199 | static unsigned long apic_phys; |
200 | ||
0e078e2f TG |
201 | /* |
202 | * Get the LAPIC version | |
203 | */ | |
204 | static inline int lapic_get_version(void) | |
ba7eda4c | 205 | { |
0e078e2f | 206 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
207 | } |
208 | ||
0e078e2f | 209 | /* |
9c803869 | 210 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
211 | */ |
212 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 213 | { |
9c803869 | 214 | #ifdef CONFIG_X86_64 |
0e078e2f | 215 | return 1; |
9c803869 CG |
216 | #else |
217 | return APIC_INTEGRATED(lapic_get_version()); | |
218 | #endif | |
ba7eda4c TG |
219 | } |
220 | ||
221 | /* | |
0e078e2f | 222 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 223 | */ |
0e078e2f | 224 | static int modern_apic(void) |
ba7eda4c | 225 | { |
0e078e2f TG |
226 | /* AMD systems use old APIC versions, so check the CPU */ |
227 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
228 | boot_cpu_data.x86 >= 0xf) | |
229 | return 1; | |
230 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
231 | } |
232 | ||
08306ce6 | 233 | /* |
a933c618 CG |
234 | * right after this call apic become NOOP driven |
235 | * so apic->write/read doesn't do anything | |
08306ce6 | 236 | */ |
25874a29 | 237 | static void __init apic_disable(void) |
08306ce6 | 238 | { |
f88f2b4f | 239 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 240 | apic = &apic_noop; |
08306ce6 CG |
241 | } |
242 | ||
c1eeb2de | 243 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
244 | { |
245 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
246 | cpu_relax(); | |
247 | } | |
248 | ||
c1eeb2de | 249 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 250 | { |
3c6bb07a | 251 | u32 send_status; |
8339e9fb FLV |
252 | int timeout; |
253 | ||
254 | timeout = 0; | |
255 | do { | |
256 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
257 | if (!send_status) | |
258 | break; | |
b49d7d87 | 259 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
260 | udelay(100); |
261 | } while (timeout++ < 1000); | |
262 | ||
263 | return send_status; | |
264 | } | |
265 | ||
c1eeb2de | 266 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 267 | { |
ea7bdc65 JK |
268 | unsigned long flags; |
269 | ||
270 | local_irq_save(flags); | |
ed4e5ec1 | 271 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d | 272 | apic_write(APIC_ICR, low); |
ea7bdc65 | 273 | local_irq_restore(flags); |
1b374e4d SS |
274 | } |
275 | ||
c1eeb2de | 276 | u64 native_apic_icr_read(void) |
1b374e4d SS |
277 | { |
278 | u32 icr1, icr2; | |
279 | ||
280 | icr2 = apic_read(APIC_ICR2); | |
281 | icr1 = apic_read(APIC_ICR); | |
282 | ||
cf9768d7 | 283 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
284 | } |
285 | ||
7c37e48b CG |
286 | #ifdef CONFIG_X86_32 |
287 | /** | |
288 | * get_physical_broadcast - Get number of physical broadcast IDs | |
289 | */ | |
290 | int get_physical_broadcast(void) | |
291 | { | |
292 | return modern_apic() ? 0xff : 0xf; | |
293 | } | |
294 | #endif | |
295 | ||
0e078e2f TG |
296 | /** |
297 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
298 | */ | |
37e650c7 | 299 | int lapic_get_maxlvt(void) |
1da177e4 | 300 | { |
36a028de | 301 | unsigned int v; |
1da177e4 LT |
302 | |
303 | v = apic_read(APIC_LVR); | |
36a028de CG |
304 | /* |
305 | * - we always have APIC integrated on 64bit mode | |
306 | * - 82489DXs do not report # of LVT entries | |
307 | */ | |
308 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
309 | } |
310 | ||
274cfe59 CG |
311 | /* |
312 | * Local APIC timer | |
313 | */ | |
314 | ||
c40aaec6 | 315 | /* Clock divisor */ |
c40aaec6 | 316 | #define APIC_DIVISOR 16 |
1a9e4c56 | 317 | #define TSC_DIVISOR 8 |
f07f4f90 | 318 | |
0e078e2f TG |
319 | /* |
320 | * This function sets up the local APIC timer, with a timeout of | |
321 | * 'clocks' APIC bus clock. During calibration we actually call | |
322 | * this function twice on the boot CPU, once with a bogus timeout | |
323 | * value, second time for real. The other (noncalibrating) CPUs | |
324 | * call this function only once, with the real, calibrated value. | |
325 | * | |
326 | * We do reads before writes even if unnecessary, to get around the | |
327 | * P5 APIC double write bug. | |
328 | */ | |
0e078e2f | 329 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 330 | { |
0e078e2f | 331 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 332 | |
0e078e2f TG |
333 | lvtt_value = LOCAL_TIMER_VECTOR; |
334 | if (!oneshot) | |
335 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
336 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
337 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
338 | ||
f07f4f90 CG |
339 | if (!lapic_is_integrated()) |
340 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
341 | ||
0e078e2f TG |
342 | if (!irqen) |
343 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 344 | |
0e078e2f | 345 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 346 | |
279f1461 | 347 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
348 | /* |
349 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
350 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
351 | * According to Intel, MFENCE can do the serialization here. | |
352 | */ | |
353 | asm volatile("mfence" : : : "memory"); | |
354 | ||
279f1461 SS |
355 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); |
356 | return; | |
357 | } | |
358 | ||
1da177e4 | 359 | /* |
0e078e2f | 360 | * Divide PICLK by 16 |
1da177e4 | 361 | */ |
0e078e2f | 362 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
363 | apic_write(APIC_TDCR, |
364 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
365 | APIC_TDR_DIV_16); | |
0e078e2f TG |
366 | |
367 | if (!oneshot) | |
f07f4f90 | 368 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
369 | } |
370 | ||
0e078e2f | 371 | /* |
a68c439b | 372 | * Setup extended LVT, AMD specific |
7b83dae7 | 373 | * |
a68c439b RR |
374 | * Software should use the LVT offsets the BIOS provides. The offsets |
375 | * are determined by the subsystems using it like those for MCE | |
376 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
377 | * are supported. Beginning with family 10h at least 4 offsets are | |
378 | * available. | |
286f5718 | 379 | * |
a68c439b RR |
380 | * Since the offsets must be consistent for all cores, we keep track |
381 | * of the LVT offsets in software and reserve the offset for the same | |
382 | * vector also to be used on other cores. An offset is freed by | |
383 | * setting the entry to APIC_EILVT_MASKED. | |
384 | * | |
385 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
386 | * "[Firmware Bug]: ..." error message is generated. However, if | |
387 | * software does not properly determines the offsets, it is not | |
388 | * necessarily a BIOS bug. | |
0e078e2f | 389 | */ |
7b83dae7 | 390 | |
a68c439b RR |
391 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
392 | ||
393 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
394 | { | |
395 | return (old & APIC_EILVT_MASKED) | |
396 | || (new == APIC_EILVT_MASKED) | |
397 | || ((new & ~APIC_EILVT_MASKED) == old); | |
398 | } | |
399 | ||
400 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
401 | { | |
8abc3122 | 402 | unsigned int rsvd, vector; |
a68c439b RR |
403 | |
404 | if (offset >= APIC_EILVT_NR_MAX) | |
405 | return ~0; | |
406 | ||
8abc3122 | 407 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 408 | do { |
8abc3122 RR |
409 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
410 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
411 | /* may not change if vectors are different */ |
412 | return rsvd; | |
413 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
414 | } while (rsvd != new); | |
415 | ||
8abc3122 RR |
416 | rsvd &= ~APIC_EILVT_MASKED; |
417 | if (rsvd && rsvd != vector) | |
418 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
419 | offset, rsvd); | |
420 | ||
a68c439b RR |
421 | return new; |
422 | } | |
423 | ||
424 | /* | |
425 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
426 | * enables the vector. See also the BKDGs. Must be called with |
427 | * preemption disabled. | |
a68c439b RR |
428 | */ |
429 | ||
27afdf20 | 430 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 431 | { |
a68c439b RR |
432 | unsigned long reg = APIC_EILVTn(offset); |
433 | unsigned int new, old, reserved; | |
434 | ||
435 | new = (mask << 16) | (msg_type << 8) | vector; | |
436 | old = apic_read(reg); | |
437 | reserved = reserve_eilvt_offset(offset, new); | |
438 | ||
439 | if (reserved != new) { | |
eb48c9cb RR |
440 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
441 | "vector 0x%x, but the register is already in use for " | |
442 | "vector 0x%x on another cpu\n", | |
443 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
444 | return -EINVAL; |
445 | } | |
446 | ||
447 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
448 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
449 | "vector 0x%x, but the register is already in use for " | |
450 | "vector 0x%x on this cpu\n", | |
451 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
452 | return -EBUSY; |
453 | } | |
454 | ||
455 | apic_write(reg, new); | |
a8fcf1a2 | 456 | |
a68c439b | 457 | return 0; |
1da177e4 | 458 | } |
27afdf20 | 459 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 460 | |
0e078e2f TG |
461 | /* |
462 | * Program the next event, relative to now | |
463 | */ | |
464 | static int lapic_next_event(unsigned long delta, | |
465 | struct clock_event_device *evt) | |
1da177e4 | 466 | { |
0e078e2f TG |
467 | apic_write(APIC_TMICT, delta); |
468 | return 0; | |
1da177e4 LT |
469 | } |
470 | ||
279f1461 SS |
471 | static int lapic_next_deadline(unsigned long delta, |
472 | struct clock_event_device *evt) | |
473 | { | |
474 | u64 tsc; | |
475 | ||
4ea1636b | 476 | tsc = rdtsc(); |
279f1461 SS |
477 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
478 | return 0; | |
479 | } | |
480 | ||
b23d8e52 | 481 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 482 | { |
0e078e2f | 483 | unsigned int v; |
9b7711f0 | 484 | |
0e078e2f TG |
485 | /* Lapic used as dummy for broadcast ? */ |
486 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 487 | return 0; |
9b7711f0 | 488 | |
b23d8e52 VK |
489 | v = apic_read(APIC_LVTT); |
490 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
491 | apic_write(APIC_LVTT, v); | |
492 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
493 | return 0; |
494 | } | |
9b7711f0 | 495 | |
b23d8e52 VK |
496 | static inline int |
497 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
498 | { | |
b23d8e52 VK |
499 | /* Lapic used as dummy for broadcast ? */ |
500 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
501 | return 0; | |
9b7711f0 | 502 | |
b23d8e52 | 503 | __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); |
b23d8e52 VK |
504 | return 0; |
505 | } | |
506 | ||
507 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
508 | { | |
509 | return lapic_timer_set_periodic_oneshot(evt, false); | |
510 | } | |
511 | ||
512 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
513 | { | |
514 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
515 | } |
516 | ||
1da177e4 | 517 | /* |
0e078e2f | 518 | * Local APIC timer broadcast function |
1da177e4 | 519 | */ |
9628937d | 520 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 521 | { |
0e078e2f | 522 | #ifdef CONFIG_SMP |
dac5f412 | 523 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
524 | #endif |
525 | } | |
1da177e4 | 526 | |
25874a29 HK |
527 | |
528 | /* | |
529 | * The local apic timer can be used for any function which is CPU local. | |
530 | */ | |
531 | static struct clock_event_device lapic_clockevent = { | |
914122c3 FW |
532 | .name = "lapic", |
533 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
534 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
535 | | CLOCK_EVT_FEAT_DUMMY, | |
536 | .shift = 32, | |
537 | .set_state_shutdown = lapic_timer_shutdown, | |
538 | .set_state_periodic = lapic_timer_set_periodic, | |
539 | .set_state_oneshot = lapic_timer_set_oneshot, | |
540 | .set_state_oneshot_stopped = lapic_timer_shutdown, | |
541 | .set_next_event = lapic_next_event, | |
542 | .broadcast = lapic_timer_broadcast, | |
543 | .rating = 100, | |
544 | .irq = -1, | |
25874a29 HK |
545 | }; |
546 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
547 | ||
0e078e2f | 548 | /* |
421f91d2 | 549 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
550 | * of the boot CPU and register the clock event in the framework. |
551 | */ | |
148f9bb8 | 552 | static void setup_APIC_timer(void) |
0e078e2f | 553 | { |
89cbc767 | 554 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 555 | |
349c004e | 556 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
557 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
558 | /* Make LAPIC timer preferrable over percpu HPET */ | |
559 | lapic_clockevent.rating = 150; | |
560 | } | |
561 | ||
0e078e2f | 562 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 563 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 564 | |
279f1461 SS |
565 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
566 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | | |
567 | CLOCK_EVT_FEAT_DUMMY); | |
568 | levt->set_next_event = lapic_next_deadline; | |
569 | clockevents_config_and_register(levt, | |
1a9e4c56 | 570 | tsc_khz * (1000 / TSC_DIVISOR), |
279f1461 SS |
571 | 0xF, ~0UL); |
572 | } else | |
573 | clockevents_register_device(levt); | |
0e078e2f | 574 | } |
1da177e4 | 575 | |
6731b0d6 NS |
576 | /* |
577 | * Install the updated TSC frequency from recalibration at the TSC | |
578 | * deadline clockevent devices. | |
579 | */ | |
580 | static void __lapic_update_tsc_freq(void *info) | |
581 | { | |
582 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); | |
583 | ||
584 | if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
585 | return; | |
586 | ||
587 | clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); | |
588 | } | |
589 | ||
590 | void lapic_update_tsc_freq(void) | |
591 | { | |
592 | /* | |
593 | * The clockevent device's ->mult and ->shift can both be | |
594 | * changed. In order to avoid races, schedule the frequency | |
595 | * update code on each CPU. | |
596 | */ | |
597 | on_each_cpu(__lapic_update_tsc_freq, NULL, 0); | |
598 | } | |
599 | ||
2f04fa88 YL |
600 | /* |
601 | * In this functions we calibrate APIC bus clocks to the external timer. | |
602 | * | |
603 | * We want to do the calibration only once since we want to have local timer | |
604 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
605 | * frequency. | |
606 | * | |
607 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
608 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
609 | * readout is broken, so it never gets out of the wait loop again. This was | |
610 | * also reported by others. | |
611 | * | |
612 | * Monitoring the jiffies value is inaccurate and the clockevents | |
613 | * infrastructure allows us to do a simple substitution of the interrupt | |
614 | * handler. | |
615 | * | |
616 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
617 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
618 | * back to normal later in the boot process). | |
619 | */ | |
620 | ||
621 | #define LAPIC_CAL_LOOPS (HZ/10) | |
622 | ||
623 | static __initdata int lapic_cal_loops = -1; | |
624 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
625 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
626 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
627 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
628 | ||
629 | /* | |
630 | * Temporary interrupt handler. | |
631 | */ | |
632 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
633 | { | |
634 | unsigned long long tsc = 0; | |
635 | long tapic = apic_read(APIC_TMCCT); | |
636 | unsigned long pm = acpi_pm_read_early(); | |
637 | ||
59e21e3d | 638 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 639 | tsc = rdtsc(); |
2f04fa88 YL |
640 | |
641 | switch (lapic_cal_loops++) { | |
642 | case 0: | |
643 | lapic_cal_t1 = tapic; | |
644 | lapic_cal_tsc1 = tsc; | |
645 | lapic_cal_pm1 = pm; | |
646 | lapic_cal_j1 = jiffies; | |
647 | break; | |
648 | ||
649 | case LAPIC_CAL_LOOPS: | |
650 | lapic_cal_t2 = tapic; | |
651 | lapic_cal_tsc2 = tsc; | |
652 | if (pm < lapic_cal_pm1) | |
653 | pm += ACPI_PM_OVRRUN; | |
654 | lapic_cal_pm2 = pm; | |
655 | lapic_cal_j2 = jiffies; | |
656 | break; | |
657 | } | |
658 | } | |
659 | ||
754ef0cd YI |
660 | static int __init |
661 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
662 | { |
663 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
664 | const long pm_thresh = pm_100ms / 100; | |
665 | unsigned long mult; | |
666 | u64 res; | |
667 | ||
668 | #ifndef CONFIG_X86_PM_TIMER | |
669 | return -1; | |
670 | #endif | |
671 | ||
39ba5d43 | 672 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
673 | |
674 | /* Check, if the PM timer is available */ | |
675 | if (!deltapm) | |
676 | return -1; | |
677 | ||
678 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
679 | ||
680 | if (deltapm > (pm_100ms - pm_thresh) && | |
681 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 682 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
683 | return 0; |
684 | } | |
685 | ||
686 | res = (((u64)deltapm) * mult) >> 22; | |
687 | do_div(res, 1000000); | |
688 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 689 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
690 | |
691 | /* Correct the lapic counter value */ | |
692 | res = (((u64)(*delta)) * pm_100ms); | |
693 | do_div(res, deltapm); | |
694 | pr_info("APIC delta adjusted to PM-Timer: " | |
695 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
696 | *delta = (long)res; | |
697 | ||
698 | /* Correct the tsc counter value */ | |
59e21e3d | 699 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
754ef0cd | 700 | res = (((u64)(*deltatsc)) * pm_100ms); |
b189892d | 701 | do_div(res, deltapm); |
754ef0cd | 702 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 703 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
704 | (unsigned long)res, *deltatsc); |
705 | *deltatsc = (long)res; | |
b189892d CG |
706 | } |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
2f04fa88 YL |
711 | static int __init calibrate_APIC_clock(void) |
712 | { | |
89cbc767 | 713 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
2f04fa88 YL |
714 | void (*real_handler)(struct clock_event_device *dev); |
715 | unsigned long deltaj; | |
754ef0cd | 716 | long delta, deltatsc; |
2f04fa88 YL |
717 | int pm_referenced = 0; |
718 | ||
1ade93ef JP |
719 | /** |
720 | * check if lapic timer has already been calibrated by platform | |
721 | * specific routine, such as tsc calibration code. if so, we just fill | |
722 | * in the clockevent structure and return. | |
723 | */ | |
724 | ||
279f1461 SS |
725 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
726 | return 0; | |
727 | } else if (lapic_timer_frequency) { | |
1ade93ef JP |
728 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
729 | lapic_timer_frequency); | |
730 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
731 | TICK_NSEC, lapic_clockevent.shift); | |
732 | lapic_clockevent.max_delta_ns = | |
733 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
734 | lapic_clockevent.min_delta_ns = | |
735 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
736 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
737 | return 0; | |
738 | } | |
739 | ||
279f1461 SS |
740 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
741 | "calibrating APIC timer ...\n"); | |
742 | ||
2f04fa88 YL |
743 | local_irq_disable(); |
744 | ||
745 | /* Replace the global interrupt handler */ | |
746 | real_handler = global_clock_event->event_handler; | |
747 | global_clock_event->event_handler = lapic_cal_handler; | |
748 | ||
749 | /* | |
81608f3c | 750 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
751 | * can underflow in the 100ms detection time frame |
752 | */ | |
81608f3c | 753 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
754 | |
755 | /* Let the interrupts run */ | |
756 | local_irq_enable(); | |
757 | ||
758 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
759 | cpu_relax(); | |
760 | ||
761 | local_irq_disable(); | |
762 | ||
763 | /* Restore the real event handler */ | |
764 | global_clock_event->event_handler = real_handler; | |
765 | ||
766 | /* Build delta t1-t2 as apic timer counts down */ | |
767 | delta = lapic_cal_t1 - lapic_cal_t2; | |
768 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
769 | ||
754ef0cd YI |
770 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
771 | ||
b189892d CG |
772 | /* we trust the PM based calibration if possible */ |
773 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 774 | &delta, &deltatsc); |
2f04fa88 YL |
775 | |
776 | /* Calculate the scaled math multiplication factor */ | |
777 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
778 | lapic_clockevent.shift); | |
779 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 780 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
781 | lapic_clockevent.min_delta_ns = |
782 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
783 | ||
1ade93ef | 784 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
785 | |
786 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 787 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 788 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 789 | lapic_timer_frequency); |
2f04fa88 | 790 | |
59e21e3d | 791 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
2f04fa88 YL |
792 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
793 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
794 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
795 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
796 | } |
797 | ||
798 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
799 | "%u.%04u MHz.\n", | |
1ade93ef JP |
800 | lapic_timer_frequency / (1000000 / HZ), |
801 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
802 | |
803 | /* | |
804 | * Do a sanity check on the APIC calibration result | |
805 | */ | |
1ade93ef | 806 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 807 | local_irq_enable(); |
ba21ebb6 | 808 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
809 | return -1; |
810 | } | |
811 | ||
812 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
813 | ||
b189892d CG |
814 | /* |
815 | * PM timer calibration failed or not turned on | |
816 | * so lets try APIC timer based calibration | |
817 | */ | |
2f04fa88 YL |
818 | if (!pm_referenced) { |
819 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
820 | ||
821 | /* | |
822 | * Setup the apic timer manually | |
823 | */ | |
824 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 825 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
826 | lapic_cal_loops = -1; |
827 | ||
828 | /* Let the interrupts run */ | |
829 | local_irq_enable(); | |
830 | ||
831 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
832 | cpu_relax(); | |
833 | ||
2f04fa88 | 834 | /* Stop the lapic timer */ |
c948c260 | 835 | local_irq_disable(); |
b23d8e52 | 836 | lapic_timer_shutdown(levt); |
2f04fa88 | 837 | |
2f04fa88 YL |
838 | /* Jiffies delta */ |
839 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
840 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
841 | ||
842 | /* Check, if the jiffies result is consistent */ | |
843 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
844 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
845 | else | |
846 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
847 | } |
848 | local_irq_enable(); | |
2f04fa88 YL |
849 | |
850 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 851 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
852 | return -1; |
853 | } | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
e83a5fdc HS |
858 | /* |
859 | * Setup the boot APIC | |
860 | * | |
861 | * Calibrate and verify the result. | |
862 | */ | |
0e078e2f TG |
863 | void __init setup_boot_APIC_clock(void) |
864 | { | |
865 | /* | |
274cfe59 CG |
866 | * The local apic timer can be disabled via the kernel |
867 | * commandline or from the CPU detection code. Register the lapic | |
868 | * timer as a dummy clock event source on SMP systems, so the | |
869 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
870 | */ |
871 | if (disable_apic_timer) { | |
ba21ebb6 | 872 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 873 | /* No broadcast on UP ! */ |
9d09951d TG |
874 | if (num_possible_cpus() > 1) { |
875 | lapic_clockevent.mult = 1; | |
0e078e2f | 876 | setup_APIC_timer(); |
9d09951d | 877 | } |
0e078e2f TG |
878 | return; |
879 | } | |
880 | ||
89b3b1f4 | 881 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
882 | /* No broadcast on UP ! */ |
883 | if (num_possible_cpus() > 1) | |
884 | setup_APIC_timer(); | |
885 | return; | |
886 | } | |
887 | ||
0e078e2f TG |
888 | /* |
889 | * If nmi_watchdog is set to IO_APIC, we need the | |
890 | * PIT/HPET going. Otherwise register lapic as a dummy | |
891 | * device. | |
892 | */ | |
072b198a | 893 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 894 | |
274cfe59 | 895 | /* Setup the lapic or request the broadcast */ |
0e078e2f | 896 | setup_APIC_timer(); |
07c94a38 | 897 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
898 | } |
899 | ||
148f9bb8 | 900 | void setup_secondary_APIC_clock(void) |
0e078e2f | 901 | { |
0e078e2f | 902 | setup_APIC_timer(); |
07c94a38 | 903 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
904 | } |
905 | ||
906 | /* | |
907 | * The guts of the apic timer interrupt | |
908 | */ | |
909 | static void local_apic_timer_interrupt(void) | |
910 | { | |
911 | int cpu = smp_processor_id(); | |
912 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
913 | ||
914 | /* | |
915 | * Normally we should not be here till LAPIC has been initialized but | |
916 | * in some cases like kdump, its possible that there is a pending LAPIC | |
917 | * timer interrupt from previous kernel's context and is delivered in | |
918 | * new kernel the moment interrupts are enabled. | |
919 | * | |
920 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
921 | * its possible that when we get here evt->event_handler is NULL. | |
922 | * Check for event_handler being NULL and discard the interrupt as | |
923 | * spurious. | |
924 | */ | |
925 | if (!evt->event_handler) { | |
ba21ebb6 | 926 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f | 927 | /* Switch it off */ |
b23d8e52 | 928 | lapic_timer_shutdown(evt); |
0e078e2f TG |
929 | return; |
930 | } | |
931 | ||
932 | /* | |
933 | * the NMI deadlock-detector uses this. | |
934 | */ | |
915b0d01 | 935 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
936 | |
937 | evt->event_handler(evt); | |
938 | } | |
939 | ||
940 | /* | |
941 | * Local APIC timer interrupt. This is the most natural way for doing | |
942 | * local interrupts, but local timer interrupts can be emulated by | |
943 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
944 | * | |
945 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
946 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
947 | */ | |
1d9090e2 | 948 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
949 | { |
950 | struct pt_regs *old_regs = set_irq_regs(regs); | |
951 | ||
952 | /* | |
953 | * NOTE! We'd better ACK the irq immediately, | |
954 | * because timer handling can be slow. | |
eddc0e92 | 955 | * |
0e078e2f TG |
956 | * update_process_times() expects us to have done irq_enter(). |
957 | * Besides, if we don't timer interrupts ignore the global | |
958 | * interrupt lock, which is the WrongThing (tm) to do. | |
0e078e2f | 959 | */ |
eddc0e92 | 960 | entering_ack_irq(); |
0e078e2f | 961 | local_apic_timer_interrupt(); |
eddc0e92 | 962 | exiting_irq(); |
274cfe59 | 963 | |
0e078e2f TG |
964 | set_irq_regs(old_regs); |
965 | } | |
966 | ||
1d9090e2 | 967 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
cf910e83 SA |
968 | { |
969 | struct pt_regs *old_regs = set_irq_regs(regs); | |
970 | ||
0e078e2f | 971 | /* |
cf910e83 SA |
972 | * NOTE! We'd better ACK the irq immediately, |
973 | * because timer handling can be slow. | |
974 | * | |
0e078e2f TG |
975 | * update_process_times() expects us to have done irq_enter(). |
976 | * Besides, if we don't timer interrupts ignore the global | |
977 | * interrupt lock, which is the WrongThing (tm) to do. | |
978 | */ | |
cf910e83 SA |
979 | entering_ack_irq(); |
980 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); | |
0e078e2f | 981 | local_apic_timer_interrupt(); |
cf910e83 SA |
982 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
983 | exiting_irq(); | |
274cfe59 | 984 | |
0e078e2f TG |
985 | set_irq_regs(old_regs); |
986 | } | |
987 | ||
988 | int setup_profiling_timer(unsigned int multiplier) | |
989 | { | |
990 | return -EINVAL; | |
991 | } | |
992 | ||
0e078e2f TG |
993 | /* |
994 | * Local APIC start and shutdown | |
995 | */ | |
996 | ||
997 | /** | |
998 | * clear_local_APIC - shutdown the local APIC | |
999 | * | |
1000 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
1001 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
1002 | * leftovers during boot. | |
1003 | */ | |
1004 | void clear_local_APIC(void) | |
1005 | { | |
2584a82d | 1006 | int maxlvt; |
0e078e2f TG |
1007 | u32 v; |
1008 | ||
d3432896 | 1009 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 1010 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
1011 | return; |
1012 | ||
1013 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
1014 | /* |
1015 | * Masking an LVT entry can trigger a local APIC error | |
1016 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1017 | */ | |
1018 | if (maxlvt >= 3) { | |
1019 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
1020 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
1021 | } | |
1022 | /* | |
1023 | * Careful: we have to set masks only first to deassert | |
1024 | * any level-triggered sources. | |
1025 | */ | |
1026 | v = apic_read(APIC_LVTT); | |
1027 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
1028 | v = apic_read(APIC_LVT0); | |
1029 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
1030 | v = apic_read(APIC_LVT1); | |
1031 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1032 | if (maxlvt >= 4) { | |
1033 | v = apic_read(APIC_LVTPC); | |
1034 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1035 | } | |
1036 | ||
6764014b | 1037 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1038 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1039 | if (maxlvt >= 5) { |
1040 | v = apic_read(APIC_LVTTHMR); | |
1041 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1042 | } | |
1043 | #endif | |
5ca8681c AK |
1044 | #ifdef CONFIG_X86_MCE_INTEL |
1045 | if (maxlvt >= 6) { | |
1046 | v = apic_read(APIC_LVTCMCI); | |
1047 | if (!(v & APIC_LVT_MASKED)) | |
1048 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1049 | } | |
1050 | #endif | |
1051 | ||
0e078e2f TG |
1052 | /* |
1053 | * Clean APIC state for other OSs: | |
1054 | */ | |
1055 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1056 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1057 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1058 | if (maxlvt >= 3) | |
1059 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1060 | if (maxlvt >= 4) | |
1061 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1062 | |
1063 | /* Integrated APIC (!82489DX) ? */ | |
1064 | if (lapic_is_integrated()) { | |
1065 | if (maxlvt > 3) | |
1066 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1067 | apic_write(APIC_ESR, 0); | |
1068 | apic_read(APIC_ESR); | |
1069 | } | |
0e078e2f TG |
1070 | } |
1071 | ||
1072 | /** | |
1073 | * disable_local_APIC - clear and disable the local APIC | |
1074 | */ | |
1075 | void disable_local_APIC(void) | |
1076 | { | |
1077 | unsigned int value; | |
1078 | ||
4a13ad0b | 1079 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 1080 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
1081 | return; |
1082 | ||
0e078e2f TG |
1083 | clear_local_APIC(); |
1084 | ||
1085 | /* | |
1086 | * Disable APIC (implies clearing of registers | |
1087 | * for 82489DX!). | |
1088 | */ | |
1089 | value = apic_read(APIC_SPIV); | |
1090 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1091 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1092 | |
1093 | #ifdef CONFIG_X86_32 | |
1094 | /* | |
1095 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1096 | * restore the disabled state. | |
1097 | */ | |
1098 | if (enabled_via_apicbase) { | |
1099 | unsigned int l, h; | |
1100 | ||
1101 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1102 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1103 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1104 | } | |
1105 | #endif | |
0e078e2f TG |
1106 | } |
1107 | ||
fe4024dc CG |
1108 | /* |
1109 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1110 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1111 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1112 | * for the case where Linux didn't enable the LAPIC. | |
1113 | */ | |
0e078e2f TG |
1114 | void lapic_shutdown(void) |
1115 | { | |
1116 | unsigned long flags; | |
1117 | ||
93984fbd | 1118 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
0e078e2f TG |
1119 | return; |
1120 | ||
1121 | local_irq_save(flags); | |
1122 | ||
fe4024dc CG |
1123 | #ifdef CONFIG_X86_32 |
1124 | if (!enabled_via_apicbase) | |
1125 | clear_local_APIC(); | |
1126 | else | |
1127 | #endif | |
1128 | disable_local_APIC(); | |
1129 | ||
0e078e2f TG |
1130 | |
1131 | local_irq_restore(flags); | |
1132 | } | |
1133 | ||
0e078e2f TG |
1134 | /** |
1135 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1136 | */ | |
1da177e4 LT |
1137 | void __init sync_Arb_IDs(void) |
1138 | { | |
296cb951 CG |
1139 | /* |
1140 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1141 | * needed on AMD. | |
1142 | */ | |
1143 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1144 | return; |
1145 | ||
1146 | /* | |
1147 | * Wait for idle. | |
1148 | */ | |
1149 | apic_wait_icr_idle(); | |
1150 | ||
1151 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1152 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1153 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1154 | } |
1155 | ||
1da177e4 LT |
1156 | /* |
1157 | * An initial setup of the virtual wire mode. | |
1158 | */ | |
1159 | void __init init_bsp_APIC(void) | |
1160 | { | |
11a8e778 | 1161 | unsigned int value; |
1da177e4 LT |
1162 | |
1163 | /* | |
1164 | * Don't do the setup now if we have a SMP BIOS as the | |
1165 | * through-I/O-APIC virtual wire mode might be active. | |
1166 | */ | |
93984fbd | 1167 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) |
1da177e4 LT |
1168 | return; |
1169 | ||
1da177e4 LT |
1170 | /* |
1171 | * Do not trust the local APIC being empty at bootup. | |
1172 | */ | |
1173 | clear_local_APIC(); | |
1174 | ||
1175 | /* | |
1176 | * Enable APIC. | |
1177 | */ | |
1178 | value = apic_read(APIC_SPIV); | |
1179 | value &= ~APIC_VECTOR_MASK; | |
1180 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1181 | |
1182 | #ifdef CONFIG_X86_32 | |
1183 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1184 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1185 | (boot_cpu_data.x86 == 15)) | |
1186 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1187 | else | |
1188 | #endif | |
1189 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1190 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1191 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1192 | |
1193 | /* | |
1194 | * Set up the virtual wire mode. | |
1195 | */ | |
11a8e778 | 1196 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1197 | value = APIC_DM_NMI; |
638c0411 CG |
1198 | if (!lapic_is_integrated()) /* 82489DX */ |
1199 | value |= APIC_LVT_LEVEL_TRIGGER; | |
b7c4948e HK |
1200 | if (apic_extnmi == APIC_EXTNMI_NONE) |
1201 | value |= APIC_LVT_MASKED; | |
11a8e778 | 1202 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1203 | } |
1204 | ||
148f9bb8 | 1205 | static void lapic_setup_esr(void) |
c43da2f5 | 1206 | { |
9df08f10 CG |
1207 | unsigned int oldvalue, value, maxlvt; |
1208 | ||
1209 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1210 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1211 | return; |
1212 | } | |
c43da2f5 | 1213 | |
08125d3e | 1214 | if (apic->disable_esr) { |
c43da2f5 | 1215 | /* |
9df08f10 CG |
1216 | * Something untraceable is creating bad interrupts on |
1217 | * secondary quads ... for the moment, just leave the | |
1218 | * ESR disabled - we can't do anything useful with the | |
1219 | * errors anyway - mbligh | |
c43da2f5 | 1220 | */ |
ba21ebb6 | 1221 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1222 | return; |
c43da2f5 | 1223 | } |
9df08f10 CG |
1224 | |
1225 | maxlvt = lapic_get_maxlvt(); | |
1226 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1227 | apic_write(APIC_ESR, 0); | |
1228 | oldvalue = apic_read(APIC_ESR); | |
1229 | ||
1230 | /* enables sending errors */ | |
1231 | value = ERROR_APIC_VECTOR; | |
1232 | apic_write(APIC_LVTERR, value); | |
1233 | ||
1234 | /* | |
1235 | * spec says clear errors after enabling vector. | |
1236 | */ | |
1237 | if (maxlvt > 3) | |
1238 | apic_write(APIC_ESR, 0); | |
1239 | value = apic_read(APIC_ESR); | |
1240 | if (value != oldvalue) | |
1241 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1242 | "vector: 0x%08x after: 0x%08x\n", | |
1243 | oldvalue, value); | |
c43da2f5 CG |
1244 | } |
1245 | ||
0e078e2f TG |
1246 | /** |
1247 | * setup_local_APIC - setup the local APIC | |
0aa002fe | 1248 | * |
543113d2 | 1249 | * Used to setup local APIC while initializing BSP or bringing up APs. |
0aa002fe | 1250 | * Always called with preemption disabled. |
0e078e2f | 1251 | */ |
148f9bb8 | 1252 | void setup_local_APIC(void) |
1da177e4 | 1253 | { |
0aa002fe | 1254 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1255 | unsigned int value, queued; |
1256 | int i, j, acked = 0; | |
1257 | unsigned long long tsc = 0, ntsc; | |
b47dcbdc | 1258 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
8c3ba8d0 | 1259 | |
59e21e3d | 1260 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 1261 | tsc = rdtsc(); |
1da177e4 | 1262 | |
f1182638 | 1263 | if (disable_apic) { |
7167d08e | 1264 | disable_ioapic_support(); |
f1182638 JB |
1265 | return; |
1266 | } | |
1267 | ||
89c38c28 CG |
1268 | #ifdef CONFIG_X86_32 |
1269 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1270 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1271 | apic_write(APIC_ESR, 0); |
1272 | apic_write(APIC_ESR, 0); | |
1273 | apic_write(APIC_ESR, 0); | |
1274 | apic_write(APIC_ESR, 0); | |
1275 | } | |
1276 | #endif | |
cdd6c482 | 1277 | perf_events_lapic_init(); |
89c38c28 | 1278 | |
1da177e4 LT |
1279 | /* |
1280 | * Double-check whether this APIC is really registered. | |
1281 | * This is meaningless in clustered apic mode, so we skip it. | |
1282 | */ | |
c2777f98 | 1283 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1284 | |
1285 | /* | |
1286 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1287 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1288 | * document number 292116). So here it goes... | |
1289 | */ | |
a5c43296 | 1290 | apic->init_apic_ldr(); |
1da177e4 | 1291 | |
6f802c4b TH |
1292 | #ifdef CONFIG_X86_32 |
1293 | /* | |
acb8bc09 TH |
1294 | * APIC LDR is initialized. If logical_apicid mapping was |
1295 | * initialized during get_smp_config(), make sure it matches the | |
1296 | * actual value. | |
6f802c4b | 1297 | */ |
acb8bc09 TH |
1298 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1299 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1300 | /* always use the value from LDR */ | |
6f802c4b TH |
1301 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1302 | logical_smp_processor_id(); | |
1303 | #endif | |
1304 | ||
1da177e4 LT |
1305 | /* |
1306 | * Set Task Priority to 'accept all'. We never change this | |
1307 | * later on. | |
1308 | */ | |
1309 | value = apic_read(APIC_TASKPRI); | |
1310 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1311 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1312 | |
da7ed9f9 VG |
1313 | /* |
1314 | * After a crash, we no longer service the interrupts and a pending | |
1315 | * interrupt from previous kernel might still have ISR bit set. | |
1316 | * | |
1317 | * Most probably by now CPU has serviced that pending interrupt and | |
1318 | * it might not have done the ack_APIC_irq() because it thought, | |
1319 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1320 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1321 | * the interrupt. Hence a vector might get locked. It was noticed | |
1322 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1323 | */ | |
8c3ba8d0 KJ |
1324 | do { |
1325 | queued = 0; | |
1326 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1327 | queued |= apic_read(APIC_IRR + i*0x10); | |
1328 | ||
1329 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1330 | value = apic_read(APIC_ISR + i*0x10); | |
1331 | for (j = 31; j >= 0; j--) { | |
1332 | if (value & (1<<j)) { | |
1333 | ack_APIC_irq(); | |
1334 | acked++; | |
1335 | } | |
1336 | } | |
da7ed9f9 | 1337 | } |
8c3ba8d0 KJ |
1338 | if (acked > 256) { |
1339 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1340 | acked); | |
1341 | break; | |
1342 | } | |
42fa4250 | 1343 | if (queued) { |
59e21e3d | 1344 | if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { |
4ea1636b | 1345 | ntsc = rdtsc(); |
42fa4250 SF |
1346 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
1347 | } else | |
1348 | max_loops--; | |
1349 | } | |
8c3ba8d0 KJ |
1350 | } while (queued && max_loops > 0); |
1351 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1352 | |
1da177e4 LT |
1353 | /* |
1354 | * Now that we are all set up, enable the APIC | |
1355 | */ | |
1356 | value = apic_read(APIC_SPIV); | |
1357 | value &= ~APIC_VECTOR_MASK; | |
1358 | /* | |
1359 | * Enable APIC | |
1360 | */ | |
1361 | value |= APIC_SPIV_APIC_ENABLED; | |
1362 | ||
89c38c28 CG |
1363 | #ifdef CONFIG_X86_32 |
1364 | /* | |
1365 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1366 | * certain networking cards. If high frequency interrupts are | |
1367 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1368 | * entry is masked/unmasked at a high rate as well then sooner or | |
1369 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1370 | * from the device. If focus CPU is disabled then the hang goes | |
1371 | * away, oh well :-( | |
1372 | * | |
1373 | * [ This bug can be reproduced easily with a level-triggered | |
1374 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1375 | * BX chipset. ] | |
1376 | */ | |
1377 | /* | |
1378 | * Actually disabling the focus CPU check just makes the hang less | |
1379 | * frequent as it makes the interrupt distributon model be more | |
1380 | * like LRU than MRU (the short-term load is more even across CPUs). | |
89c38c28 CG |
1381 | */ |
1382 | ||
1383 | /* | |
1384 | * - enable focus processor (bit==0) | |
1385 | * - 64bit mode always use processor focus | |
1386 | * so no need to set it | |
1387 | */ | |
1388 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1389 | #endif | |
3f14c746 | 1390 | |
1da177e4 LT |
1391 | /* |
1392 | * Set spurious IRQ vector | |
1393 | */ | |
1394 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1395 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1396 | |
1397 | /* | |
1398 | * Set up LVT0, LVT1: | |
1399 | * | |
1400 | * set up through-local-APIC on the BP's LINT0. This is not | |
1401 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1402 | * we delegate interrupts to the 8259A. | |
1403 | */ | |
1404 | /* | |
1405 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1406 | */ | |
1407 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1408 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1409 | value = APIC_DM_EXTINT; |
0aa002fe | 1410 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1411 | } else { |
1412 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1413 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1414 | } |
11a8e778 | 1415 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1416 | |
1417 | /* | |
b7c4948e HK |
1418 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
1419 | * modified by apic_extnmi= boot option. | |
1da177e4 | 1420 | */ |
b7c4948e HK |
1421 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
1422 | apic_extnmi == APIC_EXTNMI_ALL) | |
1da177e4 LT |
1423 | value = APIC_DM_NMI; |
1424 | else | |
1425 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1426 | if (!lapic_is_integrated()) /* 82489DX */ |
1427 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1428 | apic_write(APIC_LVT1, value); |
89c38c28 | 1429 | |
be71b855 AK |
1430 | #ifdef CONFIG_X86_MCE_INTEL |
1431 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1432 | if (!cpu) |
be71b855 AK |
1433 | cmci_recheck(); |
1434 | #endif | |
739f33b3 | 1435 | } |
1da177e4 | 1436 | |
05f7e46d | 1437 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1438 | { |
1439 | lapic_setup_esr(); | |
fa6b95fc CG |
1440 | |
1441 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1442 | { |
1443 | unsigned int value; | |
1444 | /* Disable the local apic timer */ | |
1445 | value = apic_read(APIC_LVTT); | |
1446 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1447 | apic_write(APIC_LVTT, value); | |
1448 | } | |
fa6b95fc CG |
1449 | #endif |
1450 | ||
0e078e2f | 1451 | apic_pm_activate(); |
2fb270f3 JB |
1452 | } |
1453 | ||
05f7e46d TG |
1454 | /* |
1455 | * APIC setup function for application processors. Called from smpboot.c | |
1456 | */ | |
1457 | void apic_ap_setup(void) | |
2fb270f3 | 1458 | { |
05f7e46d | 1459 | setup_local_APIC(); |
2fb270f3 | 1460 | end_local_APIC_setup(); |
1da177e4 | 1461 | } |
1da177e4 | 1462 | |
06cd9a7d | 1463 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1464 | int x2apic_mode; |
12e189d3 TG |
1465 | |
1466 | enum { | |
1467 | X2APIC_OFF, | |
1468 | X2APIC_ON, | |
1469 | X2APIC_DISABLED, | |
1470 | }; | |
1471 | static int x2apic_state; | |
1472 | ||
d786ad32 | 1473 | static void __x2apic_disable(void) |
44e25ff9 TG |
1474 | { |
1475 | u64 msr; | |
1476 | ||
93984fbd | 1477 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
659006bf TG |
1478 | return; |
1479 | ||
44e25ff9 TG |
1480 | rdmsrl(MSR_IA32_APICBASE, msr); |
1481 | if (!(msr & X2APIC_ENABLE)) | |
1482 | return; | |
1483 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1484 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1485 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1486 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1487 | } | |
1488 | ||
d786ad32 | 1489 | static void __x2apic_enable(void) |
659006bf TG |
1490 | { |
1491 | u64 msr; | |
1492 | ||
1493 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1494 | if (msr & X2APIC_ENABLE) | |
1495 | return; | |
1496 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1497 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1498 | } | |
1499 | ||
bfb05070 TG |
1500 | static int __init setup_nox2apic(char *str) |
1501 | { | |
1502 | if (x2apic_enabled()) { | |
1503 | int apicid = native_apic_msr_read(APIC_ID); | |
1504 | ||
1505 | if (apicid >= 255) { | |
1506 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
1507 | apicid); | |
1508 | return 0; | |
1509 | } | |
44e25ff9 TG |
1510 | pr_warning("x2apic already enabled.\n"); |
1511 | __x2apic_disable(); | |
1512 | } | |
1513 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1514 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1515 | x2apic_mode = 0; |
bfb05070 TG |
1516 | return 0; |
1517 | } | |
1518 | early_param("nox2apic", setup_nox2apic); | |
1519 | ||
659006bf TG |
1520 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1521 | void x2apic_setup(void) | |
1522 | { | |
1523 | /* | |
1524 | * If x2apic is not in ON state, disable it if already enabled | |
1525 | * from BIOS. | |
1526 | */ | |
1527 | if (x2apic_state != X2APIC_ON) { | |
1528 | __x2apic_disable(); | |
1529 | return; | |
1530 | } | |
1531 | __x2apic_enable(); | |
1532 | } | |
1533 | ||
44e25ff9 | 1534 | static __init void x2apic_disable(void) |
fb209bd8 | 1535 | { |
a57e456a | 1536 | u32 x2apic_id, state = x2apic_state; |
fb209bd8 | 1537 | |
a57e456a TG |
1538 | x2apic_mode = 0; |
1539 | x2apic_state = X2APIC_DISABLED; | |
1540 | ||
1541 | if (state != X2APIC_ON) | |
1542 | return; | |
fb209bd8 | 1543 | |
6d2d49d2 TG |
1544 | x2apic_id = read_apic_id(); |
1545 | if (x2apic_id >= 255) | |
1546 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1547 | |
6d2d49d2 TG |
1548 | __x2apic_disable(); |
1549 | register_lapic_address(mp_lapic_addr); | |
fb209bd8 YL |
1550 | } |
1551 | ||
659006bf | 1552 | static __init void x2apic_enable(void) |
6e1cb38a | 1553 | { |
659006bf | 1554 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1555 | return; |
1556 | ||
659006bf | 1557 | x2apic_mode = 1; |
12e189d3 | 1558 | x2apic_state = X2APIC_ON; |
659006bf | 1559 | __x2apic_enable(); |
6e1cb38a | 1560 | } |
d524165c | 1561 | |
62e61633 | 1562 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1563 | { |
659006bf | 1564 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1565 | return; |
1566 | ||
62e61633 | 1567 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
07806c50 JL |
1568 | /* IR is required if there is APIC ID > 255 even when running |
1569 | * under KVM | |
1570 | */ | |
1571 | if (max_physical_apicid > 255 || | |
8329aa9f | 1572 | !hypervisor_x2apic_available()) { |
62e61633 | 1573 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1574 | x2apic_disable(); |
07806c50 JL |
1575 | return; |
1576 | } | |
1577 | ||
1578 | /* | |
1579 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1580 | * only in physical mode | |
1581 | */ | |
55eae7de | 1582 | x2apic_phys = 1; |
07806c50 | 1583 | } |
659006bf | 1584 | x2apic_enable(); |
55eae7de TG |
1585 | } |
1586 | ||
1587 | void __init check_x2apic(void) | |
1588 | { | |
1589 | if (x2apic_enabled()) { | |
1590 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1591 | x2apic_mode = 1; | |
12e189d3 | 1592 | x2apic_state = X2APIC_ON; |
62436a4d | 1593 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
12e189d3 | 1594 | x2apic_state = X2APIC_DISABLED; |
55eae7de TG |
1595 | } |
1596 | } | |
1597 | #else /* CONFIG_X86_X2APIC */ | |
1598 | static int __init validate_x2apic(void) | |
1599 | { | |
1600 | if (!apic_is_x2apic_enabled()) | |
1601 | return 0; | |
1602 | /* | |
1603 | * Checkme: Can we simply turn off x2apic here instead of panic? | |
1604 | */ | |
1605 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); | |
1606 | } | |
1607 | early_initcall(validate_x2apic); | |
1608 | ||
62e61633 | 1609 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1610 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1611 | #endif /* !CONFIG_X86_X2APIC */ |
1612 | ||
1613 | static int __init try_to_enable_IR(void) | |
1614 | { | |
1615 | #ifdef CONFIG_X86_IO_APIC | |
1616 | if (!x2apic_enabled() && skip_ioapic_setup) { | |
1617 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); | |
1618 | return -1; | |
1619 | } | |
ce69a784 | 1620 | #endif |
55eae7de | 1621 | return irq_remapping_enable(); |
ce69a784 GN |
1622 | } |
1623 | ||
1624 | void __init enable_IR_x2apic(void) | |
1625 | { | |
1626 | unsigned long flags; | |
07806c50 | 1627 | int ret, ir_stat; |
b7f42ab2 | 1628 | |
2e63ad4b WL |
1629 | if (skip_ioapic_setup) |
1630 | return; | |
1631 | ||
07806c50 JL |
1632 | ir_stat = irq_remapping_prepare(); |
1633 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1634 | return; |
ce69a784 | 1635 | |
31dce14a | 1636 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1637 | if (ret) { |
ba21ebb6 | 1638 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1639 | return; |
5ffa4eb2 | 1640 | } |
6e1cb38a | 1641 | |
05c3dc2c | 1642 | local_irq_save(flags); |
b81bb373 | 1643 | legacy_pic->mask_all(); |
31dce14a | 1644 | mask_ioapic_entries(); |
05c3dc2c | 1645 | |
6a6256f9 | 1646 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
07806c50 JL |
1647 | if (ir_stat >= 0) |
1648 | ir_stat = try_to_enable_IR(); | |
1649 | /* ir_stat contains the remap mode or an error code */ | |
1650 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1651 | |
07806c50 | 1652 | if (ir_stat < 0) |
31dce14a | 1653 | restore_ioapic_entries(); |
b81bb373 | 1654 | legacy_pic->restore_mask(); |
6e1cb38a | 1655 | local_irq_restore(flags); |
6e1cb38a | 1656 | } |
93758238 | 1657 | |
be7a656f | 1658 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1659 | /* |
1660 | * Detect and enable local APICs on non-SMP boards. | |
1661 | * Original code written by Keir Fraser. | |
1662 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1663 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1664 | */ |
0e078e2f | 1665 | static int __init detect_init_APIC(void) |
1da177e4 | 1666 | { |
93984fbd | 1667 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
ba21ebb6 | 1668 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1669 | return -1; |
1670 | } | |
1671 | ||
1672 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1673 | return 0; |
1674 | } | |
be7a656f | 1675 | #else |
5a7ae78f | 1676 | |
25874a29 | 1677 | static int __init apic_verify(void) |
5a7ae78f TG |
1678 | { |
1679 | u32 features, h, l; | |
1680 | ||
1681 | /* | |
1682 | * The APIC feature bit should now be enabled | |
1683 | * in `cpuid' | |
1684 | */ | |
1685 | features = cpuid_edx(1); | |
1686 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1687 | pr_warning("Could not enable APIC!\n"); | |
1688 | return -1; | |
1689 | } | |
1690 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1691 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1692 | ||
1693 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1694 | if (boot_cpu_data.x86 >= 6) { |
1695 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1696 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1697 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1698 | } | |
5a7ae78f TG |
1699 | |
1700 | pr_info("Found and enabled local APIC!\n"); | |
1701 | return 0; | |
1702 | } | |
1703 | ||
25874a29 | 1704 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1705 | { |
1706 | u32 h, l; | |
1707 | ||
1708 | if (disable_apic) | |
1709 | return -1; | |
1710 | ||
1711 | /* | |
1712 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1713 | * MSR. This can only be done in software for Intel P6 or later | |
1714 | * and AMD K7 (Model > 1) or later. | |
1715 | */ | |
cbf2829b BD |
1716 | if (boot_cpu_data.x86 >= 6) { |
1717 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1718 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1719 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1720 | l &= ~MSR_IA32_APICBASE_BASE; | |
1721 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1722 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1723 | enabled_via_apicbase = 1; | |
1724 | } | |
5a7ae78f TG |
1725 | } |
1726 | return apic_verify(); | |
1727 | } | |
1728 | ||
be7a656f YL |
1729 | /* |
1730 | * Detect and initialize APIC | |
1731 | */ | |
1732 | static int __init detect_init_APIC(void) | |
1733 | { | |
be7a656f YL |
1734 | /* Disabled by kernel option? */ |
1735 | if (disable_apic) | |
1736 | return -1; | |
1737 | ||
1738 | switch (boot_cpu_data.x86_vendor) { | |
1739 | case X86_VENDOR_AMD: | |
1740 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1741 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1742 | break; |
1743 | goto no_apic; | |
1744 | case X86_VENDOR_INTEL: | |
1745 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
93984fbd | 1746 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
be7a656f YL |
1747 | break; |
1748 | goto no_apic; | |
1749 | default: | |
1750 | goto no_apic; | |
1751 | } | |
1752 | ||
93984fbd | 1753 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
be7a656f YL |
1754 | /* |
1755 | * Over-ride BIOS and try to enable the local APIC only if | |
1756 | * "lapic" specified. | |
1757 | */ | |
1758 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1759 | pr_info("Local APIC disabled by BIOS -- " |
1760 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1761 | return -1; |
1762 | } | |
a906fdaa | 1763 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1764 | return -1; |
1765 | } else { | |
1766 | if (apic_verify()) | |
1767 | return -1; | |
be7a656f | 1768 | } |
be7a656f YL |
1769 | |
1770 | apic_pm_activate(); | |
1771 | ||
1772 | return 0; | |
1773 | ||
1774 | no_apic: | |
ba21ebb6 | 1775 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1776 | return -1; |
1777 | } | |
1778 | #endif | |
1da177e4 | 1779 | |
0e078e2f TG |
1780 | /** |
1781 | * init_apic_mappings - initialize APIC mappings | |
1782 | */ | |
1da177e4 LT |
1783 | void __init init_apic_mappings(void) |
1784 | { | |
4401da61 YL |
1785 | unsigned int new_apicid; |
1786 | ||
fc1edaf9 | 1787 | if (x2apic_mode) { |
4c9961d5 | 1788 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1789 | return; |
1790 | } | |
1791 | ||
4797f6b0 | 1792 | /* If no local APIC can be found return early */ |
1da177e4 | 1793 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1794 | /* lets NOP'ify apic operations */ |
1795 | pr_info("APIC: disable apic facility\n"); | |
1796 | apic_disable(); | |
1797 | } else { | |
1da177e4 LT |
1798 | apic_phys = mp_lapic_addr; |
1799 | ||
4797f6b0 YL |
1800 | /* |
1801 | * acpi lapic path already maps that address in | |
1802 | * acpi_register_lapic_address() | |
1803 | */ | |
5989cd6a | 1804 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1805 | register_lapic_address(apic_phys); |
cec6be6d | 1806 | } |
1da177e4 LT |
1807 | |
1808 | /* | |
1809 | * Fetch the APIC ID of the BSP in case we have a | |
1810 | * default configuration (or the MP table is broken). | |
1811 | */ | |
4401da61 YL |
1812 | new_apicid = read_apic_id(); |
1813 | if (boot_cpu_physical_apicid != new_apicid) { | |
1814 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1815 | /* |
1816 | * yeah -- we lie about apic_version | |
1817 | * in case if apic was disabled via boot option | |
1818 | * but it's not a problem for SMP compiled kernel | |
1819 | * since smp_sanity_check is prepared for such a case | |
1820 | * and disable smp mode | |
1821 | */ | |
cff9ab2b | 1822 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); |
08306ce6 | 1823 | } |
1da177e4 LT |
1824 | } |
1825 | ||
c0104d38 YL |
1826 | void __init register_lapic_address(unsigned long address) |
1827 | { | |
1828 | mp_lapic_addr = address; | |
1829 | ||
0450193b YL |
1830 | if (!x2apic_mode) { |
1831 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1832 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
6de42119 | 1833 | APIC_BASE, address); |
0450193b | 1834 | } |
c0104d38 YL |
1835 | if (boot_cpu_physical_apicid == -1U) { |
1836 | boot_cpu_physical_apicid = read_apic_id(); | |
cff9ab2b | 1837 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); |
c0104d38 YL |
1838 | } |
1839 | } | |
1840 | ||
1da177e4 | 1841 | /* |
0e078e2f | 1842 | * Local APIC interrupts |
1da177e4 LT |
1843 | */ |
1844 | ||
0e078e2f TG |
1845 | /* |
1846 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1847 | */ | |
d786ad32 | 1848 | static void __smp_spurious_interrupt(u8 vector) |
1da177e4 | 1849 | { |
dc1528dd YL |
1850 | u32 v; |
1851 | ||
1da177e4 | 1852 | /* |
0e078e2f TG |
1853 | * Check if this really is a spurious interrupt and ACK it |
1854 | * if it is a vectored one. Just in case... | |
1855 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1856 | */ |
2414e021 JB |
1857 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
1858 | if (v & (1 << (vector & 0x1f))) | |
0e078e2f | 1859 | ack_APIC_irq(); |
c4d58cbd | 1860 | |
915b0d01 HS |
1861 | inc_irq_stat(irq_spurious_count); |
1862 | ||
dc1528dd | 1863 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
2414e021 JB |
1864 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
1865 | "should never happen.\n", vector, smp_processor_id()); | |
eddc0e92 SA |
1866 | } |
1867 | ||
1d9090e2 | 1868 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1869 | { |
1870 | entering_irq(); | |
2414e021 | 1871 | __smp_spurious_interrupt(~regs->orig_ax); |
eddc0e92 | 1872 | exiting_irq(); |
0e078e2f | 1873 | } |
1da177e4 | 1874 | |
1d9090e2 | 1875 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
cf910e83 | 1876 | { |
2414e021 JB |
1877 | u8 vector = ~regs->orig_ax; |
1878 | ||
cf910e83 | 1879 | entering_irq(); |
2414e021 JB |
1880 | trace_spurious_apic_entry(vector); |
1881 | __smp_spurious_interrupt(vector); | |
1882 | trace_spurious_apic_exit(vector); | |
cf910e83 | 1883 | exiting_irq(); |
0e078e2f | 1884 | } |
1da177e4 | 1885 | |
0e078e2f TG |
1886 | /* |
1887 | * This interrupt should never happen with our APIC/SMP architecture | |
1888 | */ | |
d786ad32 | 1889 | static void __smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1890 | { |
60283df7 | 1891 | u32 v; |
2b398bd9 YS |
1892 | u32 i = 0; |
1893 | static const char * const error_interrupt_reason[] = { | |
1894 | "Send CS error", /* APIC Error Bit 0 */ | |
1895 | "Receive CS error", /* APIC Error Bit 1 */ | |
1896 | "Send accept error", /* APIC Error Bit 2 */ | |
1897 | "Receive accept error", /* APIC Error Bit 3 */ | |
1898 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1899 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1900 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1901 | "Illegal register address", /* APIC Error Bit 7 */ | |
1902 | }; | |
1da177e4 | 1903 | |
0e078e2f | 1904 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
1905 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
1906 | apic_write(APIC_ESR, 0); | |
60283df7 | 1907 | v = apic_read(APIC_ESR); |
0e078e2f TG |
1908 | ack_APIC_irq(); |
1909 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1910 | |
60283df7 RW |
1911 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
1912 | smp_processor_id(), v); | |
2b398bd9 | 1913 | |
60283df7 RW |
1914 | v &= 0xff; |
1915 | while (v) { | |
1916 | if (v & 0x1) | |
2b398bd9 YS |
1917 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
1918 | i++; | |
60283df7 | 1919 | v >>= 1; |
4b8073e4 | 1920 | } |
2b398bd9 YS |
1921 | |
1922 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
1923 | ||
eddc0e92 SA |
1924 | } |
1925 | ||
1d9090e2 | 1926 | __visible void smp_error_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1927 | { |
1928 | entering_irq(); | |
1929 | __smp_error_interrupt(regs); | |
1930 | exiting_irq(); | |
1da177e4 LT |
1931 | } |
1932 | ||
1d9090e2 | 1933 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
cf910e83 SA |
1934 | { |
1935 | entering_irq(); | |
1936 | trace_error_apic_entry(ERROR_APIC_VECTOR); | |
1937 | __smp_error_interrupt(regs); | |
1938 | trace_error_apic_exit(ERROR_APIC_VECTOR); | |
1939 | exiting_irq(); | |
1da177e4 LT |
1940 | } |
1941 | ||
b5841765 | 1942 | /** |
36c9d674 CG |
1943 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1944 | */ | |
05f7e46d | 1945 | static void __init connect_bsp_APIC(void) |
b5841765 | 1946 | { |
36c9d674 CG |
1947 | #ifdef CONFIG_X86_32 |
1948 | if (pic_mode) { | |
1949 | /* | |
1950 | * Do not trust the local APIC being empty at bootup. | |
1951 | */ | |
1952 | clear_local_APIC(); | |
1953 | /* | |
1954 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1955 | * local APIC to INT and NMI lines. | |
1956 | */ | |
1957 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1958 | "enabling APIC mode.\n"); | |
c0eaa453 | 1959 | imcr_pic_to_apic(); |
36c9d674 CG |
1960 | } |
1961 | #endif | |
b5841765 GC |
1962 | } |
1963 | ||
274cfe59 CG |
1964 | /** |
1965 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1966 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1967 | * | |
1968 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1969 | * APIC is disabled. | |
1970 | */ | |
0e078e2f | 1971 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1972 | { |
1b4ee4e4 CG |
1973 | unsigned int value; |
1974 | ||
c177b0bc CG |
1975 | #ifdef CONFIG_X86_32 |
1976 | if (pic_mode) { | |
1977 | /* | |
1978 | * Put the board back into PIC mode (has an effect only on | |
1979 | * certain older boards). Note that APIC interrupts, including | |
1980 | * IPIs, won't work beyond this point! The only exception are | |
1981 | * INIT IPIs. | |
1982 | */ | |
1983 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1984 | "entering PIC mode.\n"); | |
c0eaa453 | 1985 | imcr_apic_to_pic(); |
c177b0bc CG |
1986 | return; |
1987 | } | |
1988 | #endif | |
1989 | ||
0e078e2f | 1990 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1991 | |
0e078e2f TG |
1992 | /* For the spurious interrupt use vector F, and enable it */ |
1993 | value = apic_read(APIC_SPIV); | |
1994 | value &= ~APIC_VECTOR_MASK; | |
1995 | value |= APIC_SPIV_APIC_ENABLED; | |
1996 | value |= 0xf; | |
1997 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1998 | |
0e078e2f TG |
1999 | if (!virt_wire_setup) { |
2000 | /* | |
2001 | * For LVT0 make it edge triggered, active high, | |
2002 | * external and enabled | |
2003 | */ | |
2004 | value = apic_read(APIC_LVT0); | |
2005 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2006 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2007 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2008 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2009 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2010 | apic_write(APIC_LVT0, value); | |
2011 | } else { | |
2012 | /* Disable LVT0 */ | |
2013 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2014 | } | |
b8ce3359 | 2015 | |
c177b0bc CG |
2016 | /* |
2017 | * For LVT1 make it edge triggered, active high, | |
2018 | * nmi and enabled | |
2019 | */ | |
0e078e2f TG |
2020 | value = apic_read(APIC_LVT1); |
2021 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2022 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2023 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2024 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2025 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2026 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2027 | } |
2028 | ||
8f54969d GZ |
2029 | /* |
2030 | * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated | |
2031 | * contiguously, it equals to current allocated max logical CPU ID plus 1. | |
12bf98b9 DL |
2032 | * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, |
2033 | * so the maximum of nr_logical_cpuids is nr_cpu_ids. | |
8f54969d GZ |
2034 | * |
2035 | * NOTE: Reserve 0 for BSP. | |
2036 | */ | |
2037 | static int nr_logical_cpuids = 1; | |
2038 | ||
2039 | /* | |
2040 | * Used to store mapping between logical CPU IDs and APIC IDs. | |
2041 | */ | |
2042 | static int cpuid_to_apicid[] = { | |
2043 | [0 ... NR_CPUS - 1] = -1, | |
2044 | }; | |
2045 | ||
2046 | /* | |
2047 | * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids | |
2048 | * and cpuid_to_apicid[] synchronized. | |
2049 | */ | |
2050 | static int allocate_logical_cpuid(int apicid) | |
2051 | { | |
2052 | int i; | |
2053 | ||
2054 | /* | |
2055 | * cpuid <-> apicid mapping is persistent, so when a cpu is up, | |
2056 | * check if the kernel has allocated a cpuid for it. | |
2057 | */ | |
2058 | for (i = 0; i < nr_logical_cpuids; i++) { | |
2059 | if (cpuid_to_apicid[i] == apicid) | |
2060 | return i; | |
2061 | } | |
2062 | ||
2063 | /* Allocate a new cpuid. */ | |
2064 | if (nr_logical_cpuids >= nr_cpu_ids) { | |
2065 | WARN_ONCE(1, "Only %d processors supported." | |
2066 | "Processor %d/0x%x and the rest are ignored.\n", | |
2067 | nr_cpu_ids - 1, nr_logical_cpuids, apicid); | |
2068 | return -1; | |
2069 | } | |
2070 | ||
2071 | cpuid_to_apicid[nr_logical_cpuids] = apicid; | |
2072 | return nr_logical_cpuids++; | |
2073 | } | |
2074 | ||
2075 | int __generic_processor_info(int apicid, int version, bool enabled) | |
be8a5685 | 2076 | { |
14cb6dcf VG |
2077 | int cpu, max = nr_cpu_ids; |
2078 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2079 | phys_cpu_present_map); | |
2080 | ||
151e0c7d HD |
2081 | /* |
2082 | * boot_cpu_physical_apicid is designed to have the apicid | |
2083 | * returned by read_apic_id(), i.e, the apicid of the | |
2084 | * currently booting-up processor. However, on some platforms, | |
5b4d1dbc | 2085 | * it is temporarily modified by the apicid reported as BSP |
151e0c7d HD |
2086 | * through MP table. Concretely: |
2087 | * | |
2088 | * - arch/x86/kernel/mpparse.c: MP_processor_info() | |
2089 | * - arch/x86/mm/amdtopology.c: amd_numa_init() | |
151e0c7d HD |
2090 | * |
2091 | * This function is executed with the modified | |
2092 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel | |
2093 | * parameter doesn't work to disable APs on kdump 2nd kernel. | |
2094 | * | |
2095 | * Since fixing handling of boot_cpu_physical_apicid requires | |
2096 | * another discussion and tests on each platform, we leave it | |
2097 | * for now and here we use read_apic_id() directly in this | |
12bf98b9 | 2098 | * function, __generic_processor_info(). |
151e0c7d HD |
2099 | */ |
2100 | if (disabled_cpu_apicid != BAD_APICID && | |
2101 | disabled_cpu_apicid != read_apic_id() && | |
2102 | disabled_cpu_apicid == apicid) { | |
2103 | int thiscpu = num_processors + disabled_cpus; | |
2104 | ||
5b4d1dbc | 2105 | pr_warning("APIC: Disabling requested cpu." |
151e0c7d HD |
2106 | " Processor %d/0x%x ignored.\n", |
2107 | thiscpu, apicid); | |
2108 | ||
2109 | disabled_cpus++; | |
2110 | return -ENODEV; | |
2111 | } | |
2112 | ||
14cb6dcf VG |
2113 | /* |
2114 | * If boot cpu has not been detected yet, then only allow upto | |
2115 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2116 | */ | |
2117 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2118 | apicid != boot_cpu_physical_apicid) { | |
2119 | int thiscpu = max + disabled_cpus - 1; | |
2120 | ||
2121 | pr_warning( | |
3c8fad91 | 2122 | "APIC: NR_CPUS/possible_cpus limit of %i almost" |
14cb6dcf VG |
2123 | " reached. Keeping one slot for boot cpu." |
2124 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2125 | ||
2126 | disabled_cpus++; | |
7e1f85f9 | 2127 | return -ENODEV; |
14cb6dcf | 2128 | } |
be8a5685 | 2129 | |
3b11ce7f | 2130 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2131 | int thiscpu = max + disabled_cpus; |
2132 | ||
df610d67 TG |
2133 | if (enabled) { |
2134 | pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " | |
2135 | "reached. Processor %d/0x%x ignored.\n", | |
2136 | max, thiscpu, apicid); | |
2137 | } | |
3b11ce7f MT |
2138 | |
2139 | disabled_cpus++; | |
7e1f85f9 | 2140 | return -EINVAL; |
be8a5685 AS |
2141 | } |
2142 | ||
be8a5685 AS |
2143 | if (apicid == boot_cpu_physical_apicid) { |
2144 | /* | |
2145 | * x86_bios_cpu_apicid is required to have processors listed | |
2146 | * in same order as logical cpu numbers. Hence the first | |
2147 | * entry is BSP, and so on. | |
e5fea868 YL |
2148 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2149 | * for BSP. | |
be8a5685 AS |
2150 | */ |
2151 | cpu = 0; | |
8f54969d GZ |
2152 | |
2153 | /* Logical cpuid 0 is reserved for BSP. */ | |
2154 | cpuid_to_apicid[0] = apicid; | |
2155 | } else { | |
2156 | cpu = allocate_logical_cpuid(apicid); | |
2157 | if (cpu < 0) { | |
2158 | disabled_cpus++; | |
2159 | return -EINVAL; | |
2160 | } | |
2161 | } | |
e5fea868 YL |
2162 | |
2163 | /* | |
2164 | * Validate version | |
2165 | */ | |
2166 | if (version == 0x0) { | |
2167 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2168 | cpu, apicid); | |
2169 | version = 0x10; | |
be8a5685 | 2170 | } |
e5fea868 | 2171 | |
cff9ab2b | 2172 | if (version != boot_cpu_apic_version) { |
e5fea868 | 2173 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", |
cff9ab2b | 2174 | boot_cpu_apic_version, cpu, version); |
e5fea868 YL |
2175 | } |
2176 | ||
e0da3364 YL |
2177 | if (apicid > max_physical_apicid) |
2178 | max_physical_apicid = apicid; | |
2179 | ||
3e5095d1 | 2180 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2181 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2182 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2183 | #endif |
acb8bc09 TH |
2184 | #ifdef CONFIG_X86_32 |
2185 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2186 | apic->x86_32_early_logical_apicid(cpu); | |
2187 | #endif | |
1de88cd4 | 2188 | set_cpu_possible(cpu, true); |
f7c28833 GZ |
2189 | |
2190 | if (enabled) { | |
2191 | num_processors++; | |
2192 | physid_set(apicid, phys_cpu_present_map); | |
2193 | set_cpu_present(cpu, true); | |
2194 | } else { | |
2195 | disabled_cpus++; | |
2196 | } | |
7e1f85f9 JL |
2197 | |
2198 | return cpu; | |
be8a5685 AS |
2199 | } |
2200 | ||
f7c28833 GZ |
2201 | int generic_processor_info(int apicid, int version) |
2202 | { | |
2203 | return __generic_processor_info(apicid, version, true); | |
2204 | } | |
2205 | ||
0c81c746 SS |
2206 | int hard_smp_processor_id(void) |
2207 | { | |
2208 | return read_apic_id(); | |
2209 | } | |
1dcdd3d1 IM |
2210 | |
2211 | void default_init_apic_ldr(void) | |
2212 | { | |
2213 | unsigned long val; | |
2214 | ||
2215 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2216 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2217 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2218 | apic_write(APIC_LDR, val); | |
2219 | } | |
2220 | ||
ff164324 AG |
2221 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
2222 | const struct cpumask *andmask, | |
2223 | unsigned int *apicid) | |
6398268d | 2224 | { |
ea3807ea | 2225 | unsigned int cpu; |
6398268d AG |
2226 | |
2227 | for_each_cpu_and(cpu, cpumask, andmask) { | |
2228 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
2229 | break; | |
2230 | } | |
ff164324 | 2231 | |
ea3807ea | 2232 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
2233 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
2234 | return 0; | |
a5a39156 | 2235 | } |
ea3807ea AG |
2236 | |
2237 | return -EINVAL; | |
6398268d AG |
2238 | } |
2239 | ||
1551df64 MT |
2240 | /* |
2241 | * Override the generic EOI implementation with an optimized version. | |
2242 | * Only called during early boot when only one CPU is active and with | |
2243 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2244 | * use. | |
2245 | */ | |
2246 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2247 | { | |
2248 | struct apic **drv; | |
2249 | ||
2250 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2251 | /* Should happen once for each apic */ | |
2252 | WARN_ON((*drv)->eoi_write == eoi_write); | |
8ca22552 | 2253 | (*drv)->native_eoi_write = (*drv)->eoi_write; |
1551df64 MT |
2254 | (*drv)->eoi_write = eoi_write; |
2255 | } | |
2256 | } | |
2257 | ||
374aab33 | 2258 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2259 | { |
374aab33 TG |
2260 | #ifdef CONFIG_X86_64 |
2261 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
2262 | #else | |
05f7e46d | 2263 | /* |
374aab33 TG |
2264 | * Hack: In case of kdump, after a crash, kernel might be booting |
2265 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
2266 | * might be zero if read from MP tables. Get it from LAPIC. | |
05f7e46d | 2267 | */ |
374aab33 TG |
2268 | # ifdef CONFIG_CRASH_DUMP |
2269 | boot_cpu_physical_apicid = read_apic_id(); | |
2270 | # endif | |
2271 | #endif | |
2272 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
05f7e46d TG |
2273 | } |
2274 | ||
2275 | /** | |
2276 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2277 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d TG |
2278 | * |
2279 | * Returns: | |
2280 | * apic_id of BSP APIC | |
2281 | */ | |
374aab33 | 2282 | int __init apic_bsp_setup(bool upmode) |
05f7e46d TG |
2283 | { |
2284 | int id; | |
2285 | ||
2286 | connect_bsp_APIC(); | |
374aab33 TG |
2287 | if (upmode) |
2288 | apic_bsp_up_setup(); | |
05f7e46d TG |
2289 | setup_local_APIC(); |
2290 | ||
2291 | if (x2apic_mode) | |
2292 | id = apic_read(APIC_LDR); | |
2293 | else | |
2294 | id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
2295 | ||
2296 | enable_IO_APIC(); | |
374aab33 TG |
2297 | end_local_APIC_setup(); |
2298 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2299 | setup_IO_APIC(); |
9c4d9c73 TG |
2300 | /* Setup local timer */ |
2301 | x86_init.timers.setup_percpu_clockev(); | |
05f7e46d TG |
2302 | return id; |
2303 | } | |
2304 | ||
e714a91f TG |
2305 | /* |
2306 | * This initializes the IO-APIC and APIC hardware if this is | |
2307 | * a UP kernel. | |
2308 | */ | |
2309 | int __init APIC_init_uniprocessor(void) | |
2310 | { | |
2311 | if (disable_apic) { | |
2312 | pr_info("Apic disabled\n"); | |
2313 | return -1; | |
2314 | } | |
2315 | #ifdef CONFIG_X86_64 | |
93984fbd | 2316 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
e714a91f TG |
2317 | disable_apic = 1; |
2318 | pr_info("Apic disabled by BIOS\n"); | |
2319 | return -1; | |
2320 | } | |
2321 | #else | |
93984fbd | 2322 | if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) |
e714a91f TG |
2323 | return -1; |
2324 | ||
2325 | /* | |
2326 | * Complain if the BIOS pretends there is one. | |
2327 | */ | |
93984fbd | 2328 | if (!boot_cpu_has(X86_FEATURE_APIC) && |
cff9ab2b | 2329 | APIC_INTEGRATED(boot_cpu_apic_version)) { |
e714a91f TG |
2330 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
2331 | boot_cpu_physical_apicid); | |
2332 | return -1; | |
2333 | } | |
2334 | #endif | |
2335 | ||
374aab33 TG |
2336 | if (!smp_found_config) |
2337 | disable_ioapic_support(); | |
e714a91f | 2338 | |
374aab33 | 2339 | default_setup_apic_routing(); |
374aab33 | 2340 | apic_bsp_setup(true); |
e714a91f TG |
2341 | return 0; |
2342 | } | |
2343 | ||
30b8b006 TG |
2344 | #ifdef CONFIG_UP_LATE_INIT |
2345 | void __init up_late_init(void) | |
2346 | { | |
2347 | APIC_init_uniprocessor(); | |
2348 | } | |
2349 | #endif | |
2350 | ||
89039b37 | 2351 | /* |
0e078e2f | 2352 | * Power management |
89039b37 | 2353 | */ |
0e078e2f TG |
2354 | #ifdef CONFIG_PM |
2355 | ||
2356 | static struct { | |
274cfe59 CG |
2357 | /* |
2358 | * 'active' is true if the local APIC was enabled by us and | |
2359 | * not the BIOS; this signifies that we are also responsible | |
2360 | * for disabling it before entering apm/acpi suspend | |
2361 | */ | |
0e078e2f TG |
2362 | int active; |
2363 | /* r/w apic fields */ | |
2364 | unsigned int apic_id; | |
2365 | unsigned int apic_taskpri; | |
2366 | unsigned int apic_ldr; | |
2367 | unsigned int apic_dfr; | |
2368 | unsigned int apic_spiv; | |
2369 | unsigned int apic_lvtt; | |
2370 | unsigned int apic_lvtpc; | |
2371 | unsigned int apic_lvt0; | |
2372 | unsigned int apic_lvt1; | |
2373 | unsigned int apic_lvterr; | |
2374 | unsigned int apic_tmict; | |
2375 | unsigned int apic_tdcr; | |
2376 | unsigned int apic_thmr; | |
42baa258 | 2377 | unsigned int apic_cmci; |
0e078e2f TG |
2378 | } apic_pm_state; |
2379 | ||
f3c6ea1b | 2380 | static int lapic_suspend(void) |
0e078e2f TG |
2381 | { |
2382 | unsigned long flags; | |
2383 | int maxlvt; | |
89039b37 | 2384 | |
0e078e2f TG |
2385 | if (!apic_pm_state.active) |
2386 | return 0; | |
89039b37 | 2387 | |
0e078e2f | 2388 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2389 | |
2d7a66d0 | 2390 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2391 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2392 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2393 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2394 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2395 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2396 | if (maxlvt >= 4) | |
2397 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2398 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2399 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2400 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2401 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2402 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2403 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2404 | if (maxlvt >= 5) |
2405 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2406 | #endif | |
42baa258 JG |
2407 | #ifdef CONFIG_X86_MCE_INTEL |
2408 | if (maxlvt >= 6) | |
2409 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); | |
2410 | #endif | |
24968cfd | 2411 | |
0e078e2f TG |
2412 | local_irq_save(flags); |
2413 | disable_local_APIC(); | |
fc1edaf9 | 2414 | |
70733e0c | 2415 | irq_remapping_disable(); |
fc1edaf9 | 2416 | |
0e078e2f TG |
2417 | local_irq_restore(flags); |
2418 | return 0; | |
1da177e4 LT |
2419 | } |
2420 | ||
f3c6ea1b | 2421 | static void lapic_resume(void) |
1da177e4 | 2422 | { |
0e078e2f TG |
2423 | unsigned int l, h; |
2424 | unsigned long flags; | |
31dce14a | 2425 | int maxlvt; |
b24696bc | 2426 | |
0e078e2f | 2427 | if (!apic_pm_state.active) |
f3c6ea1b | 2428 | return; |
89b831ef | 2429 | |
0e078e2f | 2430 | local_irq_save(flags); |
336224ba JR |
2431 | |
2432 | /* | |
2433 | * IO-APIC and PIC have their own resume routines. | |
2434 | * We just mask them here to make sure the interrupt | |
2435 | * subsystem is completely quiet while we enable x2apic | |
2436 | * and interrupt-remapping. | |
2437 | */ | |
2438 | mask_ioapic_entries(); | |
2439 | legacy_pic->mask_all(); | |
92206c90 | 2440 | |
659006bf TG |
2441 | if (x2apic_mode) { |
2442 | __x2apic_enable(); | |
2443 | } else { | |
92206c90 CG |
2444 | /* |
2445 | * Make sure the APICBASE points to the right address | |
2446 | * | |
2447 | * FIXME! This will be wrong if we ever support suspend on | |
2448 | * SMP! We'll need to do this as part of the CPU restore! | |
2449 | */ | |
cbf2829b BD |
2450 | if (boot_cpu_data.x86 >= 6) { |
2451 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2452 | l &= ~MSR_IA32_APICBASE_BASE; | |
2453 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2454 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2455 | } | |
d5e629a6 | 2456 | } |
6e1cb38a | 2457 | |
b24696bc | 2458 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2459 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2460 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2461 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2462 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2463 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2464 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2465 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2466 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
42baa258 | 2467 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2468 | if (maxlvt >= 5) |
2469 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
42baa258 JG |
2470 | #endif |
2471 | #ifdef CONFIG_X86_MCE_INTEL | |
2472 | if (maxlvt >= 6) | |
2473 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); | |
0e078e2f TG |
2474 | #endif |
2475 | if (maxlvt >= 4) | |
2476 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2477 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2478 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2479 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2480 | apic_write(APIC_ESR, 0); | |
2481 | apic_read(APIC_ESR); | |
2482 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2483 | apic_write(APIC_ESR, 0); | |
2484 | apic_read(APIC_ESR); | |
92206c90 | 2485 | |
70733e0c | 2486 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2487 | |
0e078e2f | 2488 | local_irq_restore(flags); |
0e078e2f | 2489 | } |
b8ce3359 | 2490 | |
274cfe59 CG |
2491 | /* |
2492 | * This device has no shutdown method - fully functioning local APICs | |
2493 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2494 | */ | |
2495 | ||
f3c6ea1b | 2496 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2497 | .resume = lapic_resume, |
2498 | .suspend = lapic_suspend, | |
2499 | }; | |
b8ce3359 | 2500 | |
148f9bb8 | 2501 | static void apic_pm_activate(void) |
0e078e2f TG |
2502 | { |
2503 | apic_pm_state.active = 1; | |
1da177e4 LT |
2504 | } |
2505 | ||
0e078e2f | 2506 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2507 | { |
0e078e2f | 2508 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
93984fbd | 2509 | if (boot_cpu_has(X86_FEATURE_APIC)) |
f3c6ea1b | 2510 | register_syscore_ops(&lapic_syscore_ops); |
e83a5fdc | 2511 | |
f3c6ea1b | 2512 | return 0; |
1da177e4 | 2513 | } |
b24696bc FY |
2514 | |
2515 | /* local apic needs to resume before other devices access its registers. */ | |
2516 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2517 | |
2518 | #else /* CONFIG_PM */ | |
2519 | ||
2520 | static void apic_pm_activate(void) { } | |
2521 | ||
2522 | #endif /* CONFIG_PM */ | |
1da177e4 | 2523 | |
f28c0ae2 | 2524 | #ifdef CONFIG_X86_64 |
e0e42142 | 2525 | |
148f9bb8 PG |
2526 | static int multi_checked; |
2527 | static int multi; | |
e0e42142 | 2528 | |
148f9bb8 | 2529 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2530 | { |
2531 | if (multi) | |
2532 | return 0; | |
6f0aced6 | 2533 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2534 | multi = 1; |
2535 | return 0; | |
2536 | } | |
2537 | ||
148f9bb8 | 2538 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2539 | { |
2540 | .callback = set_multi, | |
2541 | .ident = "IBM System Summit2", | |
2542 | .matches = { | |
2543 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2544 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2545 | }, | |
2546 | }, | |
2547 | {} | |
2548 | }; | |
2549 | ||
148f9bb8 | 2550 | static void dmi_check_multi(void) |
e0e42142 YL |
2551 | { |
2552 | if (multi_checked) | |
2553 | return; | |
2554 | ||
2555 | dmi_check_system(multi_dmi_table); | |
2556 | multi_checked = 1; | |
2557 | } | |
2558 | ||
2559 | /* | |
2560 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2561 | * | |
2562 | * Thus far, the major user of this is IBM's Summit2 series: | |
2563 | * Clustered boxes may have unsynced TSC problems if they are | |
2564 | * multi-chassis. | |
2565 | * Use DMI to check them | |
2566 | */ | |
148f9bb8 | 2567 | int apic_is_clustered_box(void) |
e0e42142 YL |
2568 | { |
2569 | dmi_check_multi(); | |
411cf9ee | 2570 | return multi; |
1da177e4 | 2571 | } |
f28c0ae2 | 2572 | #endif |
1da177e4 LT |
2573 | |
2574 | /* | |
0e078e2f | 2575 | * APIC command line parameters |
1da177e4 | 2576 | */ |
789fa735 | 2577 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2578 | { |
1da177e4 | 2579 | disable_apic = 1; |
9175fc06 | 2580 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2581 | return 0; |
2582 | } | |
2583 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2584 | |
2c8c0e6b | 2585 | /* same as disableapic, for compatibility */ |
789fa735 | 2586 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2587 | { |
789fa735 | 2588 | return setup_disableapic(arg); |
6935d1f9 | 2589 | } |
2c8c0e6b | 2590 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2591 | |
2e7c2838 LT |
2592 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2593 | { | |
2594 | local_apic_timer_c2_ok = 1; | |
2595 | return 0; | |
2596 | } | |
2597 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2598 | ||
36fef094 | 2599 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2600 | { |
1da177e4 | 2601 | disable_apic_timer = 1; |
36fef094 | 2602 | return 0; |
6935d1f9 | 2603 | } |
36fef094 CG |
2604 | early_param("noapictimer", parse_disable_apic_timer); |
2605 | ||
2606 | static int __init parse_nolapic_timer(char *arg) | |
2607 | { | |
2608 | disable_apic_timer = 1; | |
2609 | return 0; | |
6935d1f9 | 2610 | } |
36fef094 | 2611 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2612 | |
79af9bec CG |
2613 | static int __init apic_set_verbosity(char *arg) |
2614 | { | |
2615 | if (!arg) { | |
2616 | #ifdef CONFIG_X86_64 | |
2617 | skip_ioapic_setup = 0; | |
79af9bec CG |
2618 | return 0; |
2619 | #endif | |
2620 | return -EINVAL; | |
2621 | } | |
2622 | ||
2623 | if (strcmp("debug", arg) == 0) | |
2624 | apic_verbosity = APIC_DEBUG; | |
2625 | else if (strcmp("verbose", arg) == 0) | |
2626 | apic_verbosity = APIC_VERBOSE; | |
2627 | else { | |
ba21ebb6 | 2628 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2629 | " use apic=verbose or apic=debug\n", arg); |
2630 | return -EINVAL; | |
2631 | } | |
2632 | ||
2633 | return 0; | |
2634 | } | |
2635 | early_param("apic", apic_set_verbosity); | |
2636 | ||
1e934dda YL |
2637 | static int __init lapic_insert_resource(void) |
2638 | { | |
2639 | if (!apic_phys) | |
2640 | return -1; | |
2641 | ||
2642 | /* Put local APIC into the resource map. */ | |
2643 | lapic_resource.start = apic_phys; | |
2644 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2645 | insert_resource(&iomem_resource, &lapic_resource); | |
2646 | ||
2647 | return 0; | |
2648 | } | |
2649 | ||
2650 | /* | |
2651 | * need call insert after e820_reserve_resources() | |
2652 | * that is using request_resource | |
2653 | */ | |
2654 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2655 | |
2656 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2657 | { | |
2658 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2659 | return -EINVAL; | |
2660 | ||
2661 | return 0; | |
2662 | } | |
2663 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); | |
b7c4948e HK |
2664 | |
2665 | static int __init apic_set_extnmi(char *arg) | |
2666 | { | |
2667 | if (!arg) | |
2668 | return -EINVAL; | |
2669 | ||
2670 | if (!strncmp("all", arg, 3)) | |
2671 | apic_extnmi = APIC_EXTNMI_ALL; | |
2672 | else if (!strncmp("none", arg, 4)) | |
2673 | apic_extnmi = APIC_EXTNMI_NONE; | |
2674 | else if (!strncmp("bsp", arg, 3)) | |
2675 | apic_extnmi = APIC_EXTNMI_BSP; | |
2676 | else { | |
2677 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); | |
2678 | return -EINVAL; | |
2679 | } | |
2680 | ||
2681 | return 0; | |
2682 | } | |
2683 | early_param("apic_extnmi", apic_set_extnmi); |