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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
e83a5fdc | 26 | #include <linux/module.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
83ab8514 | 38 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 39 | #include <asm/irq_remapping.h> |
cdd6c482 | 40 | #include <asm/perf_event.h> |
736decac | 41 | #include <asm/x86_init.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
60063497 | 43 | #include <linux/atomic.h> |
1da177e4 | 44 | #include <asm/mpspec.h> |
d1de36f5 | 45 | #include <asm/i8259.h> |
73dea47f | 46 | #include <asm/proto.h> |
2c8c0e6b | 47 | #include <asm/apic.h> |
7167d08e | 48 | #include <asm/io_apic.h> |
d1de36f5 IM |
49 | #include <asm/desc.h> |
50 | #include <asm/hpet.h> | |
51 | #include <asm/idle.h> | |
52 | #include <asm/mtrr.h> | |
16f871bc | 53 | #include <asm/time.h> |
2bc13797 | 54 | #include <asm/smp.h> |
be71b855 | 55 | #include <asm/mce.h> |
8c3ba8d0 | 56 | #include <asm/tsc.h> |
2904ed8d | 57 | #include <asm/hypervisor.h> |
1da177e4 | 58 | |
ec70de8b | 59 | unsigned int num_processors; |
fdbecd9f | 60 | |
148f9bb8 | 61 | unsigned disabled_cpus; |
fdbecd9f | 62 | |
ec70de8b BG |
63 | /* Processor that is doing the boot up */ |
64 | unsigned int boot_cpu_physical_apicid = -1U; | |
cc08e04c | 65 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 66 | |
80e5609c | 67 | /* |
fdbecd9f | 68 | * The highest APIC ID seen during enumeration. |
80e5609c | 69 | */ |
a491cc90 | 70 | static unsigned int max_physical_apicid; |
5af5573e | 71 | |
80e5609c | 72 | /* |
fdbecd9f | 73 | * Bitmask of physically existing CPUs: |
80e5609c | 74 | */ |
ec70de8b BG |
75 | physid_mask_t phys_cpu_present_map; |
76 | ||
151e0c7d HD |
77 | /* |
78 | * Processor to be disabled specified by kernel parameter | |
79 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
80 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
81 | */ | |
5b4d1dbc | 82 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
151e0c7d | 83 | |
ec70de8b BG |
84 | /* |
85 | * Map cpu index to physical APIC ID | |
86 | */ | |
0816b0f0 VZ |
87 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
88 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); | |
ec70de8b BG |
89 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
90 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 91 | |
b3c51170 | 92 | #ifdef CONFIG_X86_32 |
4c321ff8 | 93 | |
4c321ff8 TH |
94 | /* |
95 | * On x86_32, the mapping between cpu and logical apicid may vary | |
96 | * depending on apic in use. The following early percpu variable is | |
97 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
98 | * actually diverge. Let's keep it ugly for now. | |
99 | */ | |
0816b0f0 | 100 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 101 | |
f28c0ae2 YL |
102 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
103 | static int enabled_via_apicbase; | |
104 | ||
c0eaa453 CG |
105 | /* |
106 | * Handle interrupt mode configuration register (IMCR). | |
107 | * This register controls whether the interrupt signals | |
108 | * that reach the BSP come from the master PIC or from the | |
109 | * local APIC. Before entering Symmetric I/O Mode, either | |
110 | * the BIOS or the operating system must switch out of | |
111 | * PIC Mode by changing the IMCR. | |
112 | */ | |
5cda395f | 113 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
114 | { |
115 | /* select IMCR register */ | |
116 | outb(0x70, 0x22); | |
117 | /* NMI and 8259 INTR go through APIC */ | |
118 | outb(0x01, 0x23); | |
119 | } | |
120 | ||
5cda395f | 121 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
122 | { |
123 | /* select IMCR register */ | |
124 | outb(0x70, 0x22); | |
125 | /* NMI and 8259 INTR go directly to BSP */ | |
126 | outb(0x00, 0x23); | |
127 | } | |
b3c51170 YL |
128 | #endif |
129 | ||
279f1461 SS |
130 | /* |
131 | * Knob to control our willingness to enable the local APIC. | |
132 | * | |
133 | * +1=force-enable | |
134 | */ | |
135 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 136 | |
279f1461 SS |
137 | /* |
138 | * APIC command line parameters | |
139 | */ | |
140 | static int __init parse_lapic(char *arg) | |
141 | { | |
142 | if (config_enabled(CONFIG_X86_32) && !arg) | |
143 | force_enable_local_apic = 1; | |
27cf9298 | 144 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
145 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
146 | return 0; | |
147 | } | |
148 | early_param("lapic", parse_lapic); | |
149 | ||
b3c51170 | 150 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 151 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
152 | static __init int setup_apicpmtimer(char *s) |
153 | { | |
154 | apic_calibrate_pmtmr = 1; | |
155 | notsc_setup(NULL); | |
156 | return 0; | |
157 | } | |
158 | __setup("apicpmtimer", setup_apicpmtimer); | |
159 | #endif | |
160 | ||
b3c51170 YL |
161 | unsigned long mp_lapic_addr; |
162 | int disable_apic; | |
163 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 164 | static int disable_apic_timer __initdata; |
e83a5fdc | 165 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
166 | int local_apic_timer_c2_ok; |
167 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
168 | ||
2414e021 | 169 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
efa2559f | 170 | |
e83a5fdc HS |
171 | /* |
172 | * Debug level, exported for io_apic.c | |
173 | */ | |
baa13188 | 174 | unsigned int apic_verbosity; |
e83a5fdc | 175 | |
89c38c28 CG |
176 | int pic_mode; |
177 | ||
bab4b27c AS |
178 | /* Have we found an MP table */ |
179 | int smp_found_config; | |
180 | ||
39928722 AD |
181 | static struct resource lapic_resource = { |
182 | .name = "Local APIC", | |
183 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
184 | }; | |
185 | ||
1ade93ef | 186 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 187 | |
0e078e2f | 188 | static void apic_pm_activate(void); |
ba7eda4c | 189 | |
d3432896 AK |
190 | static unsigned long apic_phys; |
191 | ||
0e078e2f TG |
192 | /* |
193 | * Get the LAPIC version | |
194 | */ | |
195 | static inline int lapic_get_version(void) | |
ba7eda4c | 196 | { |
0e078e2f | 197 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
198 | } |
199 | ||
0e078e2f | 200 | /* |
9c803869 | 201 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
202 | */ |
203 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 204 | { |
9c803869 | 205 | #ifdef CONFIG_X86_64 |
0e078e2f | 206 | return 1; |
9c803869 CG |
207 | #else |
208 | return APIC_INTEGRATED(lapic_get_version()); | |
209 | #endif | |
ba7eda4c TG |
210 | } |
211 | ||
212 | /* | |
0e078e2f | 213 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 214 | */ |
0e078e2f | 215 | static int modern_apic(void) |
ba7eda4c | 216 | { |
0e078e2f TG |
217 | /* AMD systems use old APIC versions, so check the CPU */ |
218 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
219 | boot_cpu_data.x86 >= 0xf) | |
220 | return 1; | |
221 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
222 | } |
223 | ||
08306ce6 | 224 | /* |
a933c618 CG |
225 | * right after this call apic become NOOP driven |
226 | * so apic->write/read doesn't do anything | |
08306ce6 | 227 | */ |
25874a29 | 228 | static void __init apic_disable(void) |
08306ce6 | 229 | { |
f88f2b4f | 230 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 231 | apic = &apic_noop; |
08306ce6 CG |
232 | } |
233 | ||
c1eeb2de | 234 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
235 | { |
236 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
237 | cpu_relax(); | |
238 | } | |
239 | ||
c1eeb2de | 240 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 241 | { |
3c6bb07a | 242 | u32 send_status; |
8339e9fb FLV |
243 | int timeout; |
244 | ||
245 | timeout = 0; | |
246 | do { | |
247 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
248 | if (!send_status) | |
249 | break; | |
b49d7d87 | 250 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
251 | udelay(100); |
252 | } while (timeout++ < 1000); | |
253 | ||
254 | return send_status; | |
255 | } | |
256 | ||
c1eeb2de | 257 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 258 | { |
ea7bdc65 JK |
259 | unsigned long flags; |
260 | ||
261 | local_irq_save(flags); | |
ed4e5ec1 | 262 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d | 263 | apic_write(APIC_ICR, low); |
ea7bdc65 | 264 | local_irq_restore(flags); |
1b374e4d SS |
265 | } |
266 | ||
c1eeb2de | 267 | u64 native_apic_icr_read(void) |
1b374e4d SS |
268 | { |
269 | u32 icr1, icr2; | |
270 | ||
271 | icr2 = apic_read(APIC_ICR2); | |
272 | icr1 = apic_read(APIC_ICR); | |
273 | ||
cf9768d7 | 274 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
275 | } |
276 | ||
7c37e48b CG |
277 | #ifdef CONFIG_X86_32 |
278 | /** | |
279 | * get_physical_broadcast - Get number of physical broadcast IDs | |
280 | */ | |
281 | int get_physical_broadcast(void) | |
282 | { | |
283 | return modern_apic() ? 0xff : 0xf; | |
284 | } | |
285 | #endif | |
286 | ||
0e078e2f TG |
287 | /** |
288 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
289 | */ | |
37e650c7 | 290 | int lapic_get_maxlvt(void) |
1da177e4 | 291 | { |
36a028de | 292 | unsigned int v; |
1da177e4 LT |
293 | |
294 | v = apic_read(APIC_LVR); | |
36a028de CG |
295 | /* |
296 | * - we always have APIC integrated on 64bit mode | |
297 | * - 82489DXs do not report # of LVT entries | |
298 | */ | |
299 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
300 | } |
301 | ||
274cfe59 CG |
302 | /* |
303 | * Local APIC timer | |
304 | */ | |
305 | ||
c40aaec6 | 306 | /* Clock divisor */ |
c40aaec6 | 307 | #define APIC_DIVISOR 16 |
279f1461 | 308 | #define TSC_DIVISOR 32 |
f07f4f90 | 309 | |
0e078e2f TG |
310 | /* |
311 | * This function sets up the local APIC timer, with a timeout of | |
312 | * 'clocks' APIC bus clock. During calibration we actually call | |
313 | * this function twice on the boot CPU, once with a bogus timeout | |
314 | * value, second time for real. The other (noncalibrating) CPUs | |
315 | * call this function only once, with the real, calibrated value. | |
316 | * | |
317 | * We do reads before writes even if unnecessary, to get around the | |
318 | * P5 APIC double write bug. | |
319 | */ | |
0e078e2f | 320 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 321 | { |
0e078e2f | 322 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 323 | |
0e078e2f TG |
324 | lvtt_value = LOCAL_TIMER_VECTOR; |
325 | if (!oneshot) | |
326 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
327 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
328 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
329 | ||
f07f4f90 CG |
330 | if (!lapic_is_integrated()) |
331 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
332 | ||
0e078e2f TG |
333 | if (!irqen) |
334 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 335 | |
0e078e2f | 336 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 337 | |
279f1461 | 338 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
339 | /* |
340 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
341 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
342 | * According to Intel, MFENCE can do the serialization here. | |
343 | */ | |
344 | asm volatile("mfence" : : : "memory"); | |
345 | ||
279f1461 SS |
346 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); |
347 | return; | |
348 | } | |
349 | ||
1da177e4 | 350 | /* |
0e078e2f | 351 | * Divide PICLK by 16 |
1da177e4 | 352 | */ |
0e078e2f | 353 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
354 | apic_write(APIC_TDCR, |
355 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
356 | APIC_TDR_DIV_16); | |
0e078e2f TG |
357 | |
358 | if (!oneshot) | |
f07f4f90 | 359 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
360 | } |
361 | ||
0e078e2f | 362 | /* |
a68c439b | 363 | * Setup extended LVT, AMD specific |
7b83dae7 | 364 | * |
a68c439b RR |
365 | * Software should use the LVT offsets the BIOS provides. The offsets |
366 | * are determined by the subsystems using it like those for MCE | |
367 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
368 | * are supported. Beginning with family 10h at least 4 offsets are | |
369 | * available. | |
286f5718 | 370 | * |
a68c439b RR |
371 | * Since the offsets must be consistent for all cores, we keep track |
372 | * of the LVT offsets in software and reserve the offset for the same | |
373 | * vector also to be used on other cores. An offset is freed by | |
374 | * setting the entry to APIC_EILVT_MASKED. | |
375 | * | |
376 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
377 | * "[Firmware Bug]: ..." error message is generated. However, if | |
378 | * software does not properly determines the offsets, it is not | |
379 | * necessarily a BIOS bug. | |
0e078e2f | 380 | */ |
7b83dae7 | 381 | |
a68c439b RR |
382 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
383 | ||
384 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
385 | { | |
386 | return (old & APIC_EILVT_MASKED) | |
387 | || (new == APIC_EILVT_MASKED) | |
388 | || ((new & ~APIC_EILVT_MASKED) == old); | |
389 | } | |
390 | ||
391 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
392 | { | |
8abc3122 | 393 | unsigned int rsvd, vector; |
a68c439b RR |
394 | |
395 | if (offset >= APIC_EILVT_NR_MAX) | |
396 | return ~0; | |
397 | ||
8abc3122 | 398 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 399 | do { |
8abc3122 RR |
400 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
401 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
402 | /* may not change if vectors are different */ |
403 | return rsvd; | |
404 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
405 | } while (rsvd != new); | |
406 | ||
8abc3122 RR |
407 | rsvd &= ~APIC_EILVT_MASKED; |
408 | if (rsvd && rsvd != vector) | |
409 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
410 | offset, rsvd); | |
411 | ||
a68c439b RR |
412 | return new; |
413 | } | |
414 | ||
415 | /* | |
416 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
417 | * enables the vector. See also the BKDGs. Must be called with |
418 | * preemption disabled. | |
a68c439b RR |
419 | */ |
420 | ||
27afdf20 | 421 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 422 | { |
a68c439b RR |
423 | unsigned long reg = APIC_EILVTn(offset); |
424 | unsigned int new, old, reserved; | |
425 | ||
426 | new = (mask << 16) | (msg_type << 8) | vector; | |
427 | old = apic_read(reg); | |
428 | reserved = reserve_eilvt_offset(offset, new); | |
429 | ||
430 | if (reserved != new) { | |
eb48c9cb RR |
431 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
432 | "vector 0x%x, but the register is already in use for " | |
433 | "vector 0x%x on another cpu\n", | |
434 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
435 | return -EINVAL; |
436 | } | |
437 | ||
438 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
439 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
440 | "vector 0x%x, but the register is already in use for " | |
441 | "vector 0x%x on this cpu\n", | |
442 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
443 | return -EBUSY; |
444 | } | |
445 | ||
446 | apic_write(reg, new); | |
a8fcf1a2 | 447 | |
a68c439b | 448 | return 0; |
1da177e4 | 449 | } |
27afdf20 | 450 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 451 | |
0e078e2f TG |
452 | /* |
453 | * Program the next event, relative to now | |
454 | */ | |
455 | static int lapic_next_event(unsigned long delta, | |
456 | struct clock_event_device *evt) | |
1da177e4 | 457 | { |
0e078e2f TG |
458 | apic_write(APIC_TMICT, delta); |
459 | return 0; | |
1da177e4 LT |
460 | } |
461 | ||
279f1461 SS |
462 | static int lapic_next_deadline(unsigned long delta, |
463 | struct clock_event_device *evt) | |
464 | { | |
465 | u64 tsc; | |
466 | ||
4ea1636b | 467 | tsc = rdtsc(); |
279f1461 SS |
468 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
469 | return 0; | |
470 | } | |
471 | ||
b23d8e52 | 472 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 473 | { |
0e078e2f | 474 | unsigned int v; |
9b7711f0 | 475 | |
0e078e2f TG |
476 | /* Lapic used as dummy for broadcast ? */ |
477 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 478 | return 0; |
9b7711f0 | 479 | |
b23d8e52 VK |
480 | v = apic_read(APIC_LVTT); |
481 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
482 | apic_write(APIC_LVTT, v); | |
483 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
484 | return 0; |
485 | } | |
9b7711f0 | 486 | |
b23d8e52 VK |
487 | static inline int |
488 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
489 | { | |
b23d8e52 VK |
490 | /* Lapic used as dummy for broadcast ? */ |
491 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
492 | return 0; | |
9b7711f0 | 493 | |
b23d8e52 | 494 | __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); |
b23d8e52 VK |
495 | return 0; |
496 | } | |
497 | ||
498 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
499 | { | |
500 | return lapic_timer_set_periodic_oneshot(evt, false); | |
501 | } | |
502 | ||
503 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
504 | { | |
505 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
506 | } |
507 | ||
1da177e4 | 508 | /* |
0e078e2f | 509 | * Local APIC timer broadcast function |
1da177e4 | 510 | */ |
9628937d | 511 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 512 | { |
0e078e2f | 513 | #ifdef CONFIG_SMP |
dac5f412 | 514 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
515 | #endif |
516 | } | |
1da177e4 | 517 | |
25874a29 HK |
518 | |
519 | /* | |
520 | * The local apic timer can be used for any function which is CPU local. | |
521 | */ | |
522 | static struct clock_event_device lapic_clockevent = { | |
b23d8e52 VK |
523 | .name = "lapic", |
524 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
525 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
526 | | CLOCK_EVT_FEAT_DUMMY, | |
527 | .shift = 32, | |
528 | .set_state_shutdown = lapic_timer_shutdown, | |
529 | .set_state_periodic = lapic_timer_set_periodic, | |
530 | .set_state_oneshot = lapic_timer_set_oneshot, | |
531 | .set_next_event = lapic_next_event, | |
532 | .broadcast = lapic_timer_broadcast, | |
533 | .rating = 100, | |
534 | .irq = -1, | |
25874a29 HK |
535 | }; |
536 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
537 | ||
0e078e2f | 538 | /* |
421f91d2 | 539 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
540 | * of the boot CPU and register the clock event in the framework. |
541 | */ | |
148f9bb8 | 542 | static void setup_APIC_timer(void) |
0e078e2f | 543 | { |
89cbc767 | 544 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 545 | |
349c004e | 546 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
547 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
548 | /* Make LAPIC timer preferrable over percpu HPET */ | |
549 | lapic_clockevent.rating = 150; | |
550 | } | |
551 | ||
0e078e2f | 552 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 553 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 554 | |
279f1461 SS |
555 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
556 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | | |
557 | CLOCK_EVT_FEAT_DUMMY); | |
558 | levt->set_next_event = lapic_next_deadline; | |
559 | clockevents_config_and_register(levt, | |
560 | (tsc_khz / TSC_DIVISOR) * 1000, | |
561 | 0xF, ~0UL); | |
562 | } else | |
563 | clockevents_register_device(levt); | |
0e078e2f | 564 | } |
1da177e4 | 565 | |
2f04fa88 YL |
566 | /* |
567 | * In this functions we calibrate APIC bus clocks to the external timer. | |
568 | * | |
569 | * We want to do the calibration only once since we want to have local timer | |
570 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
571 | * frequency. | |
572 | * | |
573 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
574 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
575 | * readout is broken, so it never gets out of the wait loop again. This was | |
576 | * also reported by others. | |
577 | * | |
578 | * Monitoring the jiffies value is inaccurate and the clockevents | |
579 | * infrastructure allows us to do a simple substitution of the interrupt | |
580 | * handler. | |
581 | * | |
582 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
583 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
584 | * back to normal later in the boot process). | |
585 | */ | |
586 | ||
587 | #define LAPIC_CAL_LOOPS (HZ/10) | |
588 | ||
589 | static __initdata int lapic_cal_loops = -1; | |
590 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
591 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
592 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
593 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
594 | ||
595 | /* | |
596 | * Temporary interrupt handler. | |
597 | */ | |
598 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
599 | { | |
600 | unsigned long long tsc = 0; | |
601 | long tapic = apic_read(APIC_TMCCT); | |
602 | unsigned long pm = acpi_pm_read_early(); | |
603 | ||
604 | if (cpu_has_tsc) | |
4ea1636b | 605 | tsc = rdtsc(); |
2f04fa88 YL |
606 | |
607 | switch (lapic_cal_loops++) { | |
608 | case 0: | |
609 | lapic_cal_t1 = tapic; | |
610 | lapic_cal_tsc1 = tsc; | |
611 | lapic_cal_pm1 = pm; | |
612 | lapic_cal_j1 = jiffies; | |
613 | break; | |
614 | ||
615 | case LAPIC_CAL_LOOPS: | |
616 | lapic_cal_t2 = tapic; | |
617 | lapic_cal_tsc2 = tsc; | |
618 | if (pm < lapic_cal_pm1) | |
619 | pm += ACPI_PM_OVRRUN; | |
620 | lapic_cal_pm2 = pm; | |
621 | lapic_cal_j2 = jiffies; | |
622 | break; | |
623 | } | |
624 | } | |
625 | ||
754ef0cd YI |
626 | static int __init |
627 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
628 | { |
629 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
630 | const long pm_thresh = pm_100ms / 100; | |
631 | unsigned long mult; | |
632 | u64 res; | |
633 | ||
634 | #ifndef CONFIG_X86_PM_TIMER | |
635 | return -1; | |
636 | #endif | |
637 | ||
39ba5d43 | 638 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
639 | |
640 | /* Check, if the PM timer is available */ | |
641 | if (!deltapm) | |
642 | return -1; | |
643 | ||
644 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
645 | ||
646 | if (deltapm > (pm_100ms - pm_thresh) && | |
647 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 648 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
649 | return 0; |
650 | } | |
651 | ||
652 | res = (((u64)deltapm) * mult) >> 22; | |
653 | do_div(res, 1000000); | |
654 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 655 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
656 | |
657 | /* Correct the lapic counter value */ | |
658 | res = (((u64)(*delta)) * pm_100ms); | |
659 | do_div(res, deltapm); | |
660 | pr_info("APIC delta adjusted to PM-Timer: " | |
661 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
662 | *delta = (long)res; | |
663 | ||
664 | /* Correct the tsc counter value */ | |
665 | if (cpu_has_tsc) { | |
666 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 667 | do_div(res, deltapm); |
754ef0cd | 668 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 669 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
670 | (unsigned long)res, *deltatsc); |
671 | *deltatsc = (long)res; | |
b189892d CG |
672 | } |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
2f04fa88 YL |
677 | static int __init calibrate_APIC_clock(void) |
678 | { | |
89cbc767 | 679 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
2f04fa88 YL |
680 | void (*real_handler)(struct clock_event_device *dev); |
681 | unsigned long deltaj; | |
754ef0cd | 682 | long delta, deltatsc; |
2f04fa88 YL |
683 | int pm_referenced = 0; |
684 | ||
1ade93ef JP |
685 | /** |
686 | * check if lapic timer has already been calibrated by platform | |
687 | * specific routine, such as tsc calibration code. if so, we just fill | |
688 | * in the clockevent structure and return. | |
689 | */ | |
690 | ||
279f1461 SS |
691 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
692 | return 0; | |
693 | } else if (lapic_timer_frequency) { | |
1ade93ef JP |
694 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
695 | lapic_timer_frequency); | |
696 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
697 | TICK_NSEC, lapic_clockevent.shift); | |
698 | lapic_clockevent.max_delta_ns = | |
699 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
700 | lapic_clockevent.min_delta_ns = | |
701 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
702 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
703 | return 0; | |
704 | } | |
705 | ||
279f1461 SS |
706 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
707 | "calibrating APIC timer ...\n"); | |
708 | ||
2f04fa88 YL |
709 | local_irq_disable(); |
710 | ||
711 | /* Replace the global interrupt handler */ | |
712 | real_handler = global_clock_event->event_handler; | |
713 | global_clock_event->event_handler = lapic_cal_handler; | |
714 | ||
715 | /* | |
81608f3c | 716 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
717 | * can underflow in the 100ms detection time frame |
718 | */ | |
81608f3c | 719 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
720 | |
721 | /* Let the interrupts run */ | |
722 | local_irq_enable(); | |
723 | ||
724 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
725 | cpu_relax(); | |
726 | ||
727 | local_irq_disable(); | |
728 | ||
729 | /* Restore the real event handler */ | |
730 | global_clock_event->event_handler = real_handler; | |
731 | ||
732 | /* Build delta t1-t2 as apic timer counts down */ | |
733 | delta = lapic_cal_t1 - lapic_cal_t2; | |
734 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
735 | ||
754ef0cd YI |
736 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
737 | ||
b189892d CG |
738 | /* we trust the PM based calibration if possible */ |
739 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 740 | &delta, &deltatsc); |
2f04fa88 YL |
741 | |
742 | /* Calculate the scaled math multiplication factor */ | |
743 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
744 | lapic_clockevent.shift); | |
745 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 746 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
747 | lapic_clockevent.min_delta_ns = |
748 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
749 | ||
1ade93ef | 750 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
751 | |
752 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 753 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 754 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 755 | lapic_timer_frequency); |
2f04fa88 YL |
756 | |
757 | if (cpu_has_tsc) { | |
2f04fa88 YL |
758 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
759 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
760 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
761 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
762 | } |
763 | ||
764 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
765 | "%u.%04u MHz.\n", | |
1ade93ef JP |
766 | lapic_timer_frequency / (1000000 / HZ), |
767 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
768 | |
769 | /* | |
770 | * Do a sanity check on the APIC calibration result | |
771 | */ | |
1ade93ef | 772 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 773 | local_irq_enable(); |
ba21ebb6 | 774 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
775 | return -1; |
776 | } | |
777 | ||
778 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
779 | ||
b189892d CG |
780 | /* |
781 | * PM timer calibration failed or not turned on | |
782 | * so lets try APIC timer based calibration | |
783 | */ | |
2f04fa88 YL |
784 | if (!pm_referenced) { |
785 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
786 | ||
787 | /* | |
788 | * Setup the apic timer manually | |
789 | */ | |
790 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 791 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
792 | lapic_cal_loops = -1; |
793 | ||
794 | /* Let the interrupts run */ | |
795 | local_irq_enable(); | |
796 | ||
797 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
798 | cpu_relax(); | |
799 | ||
2f04fa88 | 800 | /* Stop the lapic timer */ |
c948c260 | 801 | local_irq_disable(); |
b23d8e52 | 802 | lapic_timer_shutdown(levt); |
2f04fa88 | 803 | |
2f04fa88 YL |
804 | /* Jiffies delta */ |
805 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
806 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
807 | ||
808 | /* Check, if the jiffies result is consistent */ | |
809 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
810 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
811 | else | |
812 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
813 | } |
814 | local_irq_enable(); | |
2f04fa88 YL |
815 | |
816 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 817 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
818 | return -1; |
819 | } | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
e83a5fdc HS |
824 | /* |
825 | * Setup the boot APIC | |
826 | * | |
827 | * Calibrate and verify the result. | |
828 | */ | |
0e078e2f TG |
829 | void __init setup_boot_APIC_clock(void) |
830 | { | |
831 | /* | |
274cfe59 CG |
832 | * The local apic timer can be disabled via the kernel |
833 | * commandline or from the CPU detection code. Register the lapic | |
834 | * timer as a dummy clock event source on SMP systems, so the | |
835 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
836 | */ |
837 | if (disable_apic_timer) { | |
ba21ebb6 | 838 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 839 | /* No broadcast on UP ! */ |
9d09951d TG |
840 | if (num_possible_cpus() > 1) { |
841 | lapic_clockevent.mult = 1; | |
0e078e2f | 842 | setup_APIC_timer(); |
9d09951d | 843 | } |
0e078e2f TG |
844 | return; |
845 | } | |
846 | ||
89b3b1f4 | 847 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
848 | /* No broadcast on UP ! */ |
849 | if (num_possible_cpus() > 1) | |
850 | setup_APIC_timer(); | |
851 | return; | |
852 | } | |
853 | ||
0e078e2f TG |
854 | /* |
855 | * If nmi_watchdog is set to IO_APIC, we need the | |
856 | * PIT/HPET going. Otherwise register lapic as a dummy | |
857 | * device. | |
858 | */ | |
072b198a | 859 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 860 | |
274cfe59 | 861 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
862 | setup_APIC_timer(); |
863 | } | |
864 | ||
148f9bb8 | 865 | void setup_secondary_APIC_clock(void) |
0e078e2f | 866 | { |
0e078e2f TG |
867 | setup_APIC_timer(); |
868 | } | |
869 | ||
870 | /* | |
871 | * The guts of the apic timer interrupt | |
872 | */ | |
873 | static void local_apic_timer_interrupt(void) | |
874 | { | |
875 | int cpu = smp_processor_id(); | |
876 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
877 | ||
878 | /* | |
879 | * Normally we should not be here till LAPIC has been initialized but | |
880 | * in some cases like kdump, its possible that there is a pending LAPIC | |
881 | * timer interrupt from previous kernel's context and is delivered in | |
882 | * new kernel the moment interrupts are enabled. | |
883 | * | |
884 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
885 | * its possible that when we get here evt->event_handler is NULL. | |
886 | * Check for event_handler being NULL and discard the interrupt as | |
887 | * spurious. | |
888 | */ | |
889 | if (!evt->event_handler) { | |
ba21ebb6 | 890 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f | 891 | /* Switch it off */ |
b23d8e52 | 892 | lapic_timer_shutdown(evt); |
0e078e2f TG |
893 | return; |
894 | } | |
895 | ||
896 | /* | |
897 | * the NMI deadlock-detector uses this. | |
898 | */ | |
915b0d01 | 899 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
900 | |
901 | evt->event_handler(evt); | |
902 | } | |
903 | ||
904 | /* | |
905 | * Local APIC timer interrupt. This is the most natural way for doing | |
906 | * local interrupts, but local timer interrupts can be emulated by | |
907 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
908 | * | |
909 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
910 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
911 | */ | |
1d9090e2 | 912 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
913 | { |
914 | struct pt_regs *old_regs = set_irq_regs(regs); | |
915 | ||
916 | /* | |
917 | * NOTE! We'd better ACK the irq immediately, | |
918 | * because timer handling can be slow. | |
eddc0e92 | 919 | * |
0e078e2f TG |
920 | * update_process_times() expects us to have done irq_enter(). |
921 | * Besides, if we don't timer interrupts ignore the global | |
922 | * interrupt lock, which is the WrongThing (tm) to do. | |
0e078e2f | 923 | */ |
eddc0e92 | 924 | entering_ack_irq(); |
0e078e2f | 925 | local_apic_timer_interrupt(); |
eddc0e92 | 926 | exiting_irq(); |
274cfe59 | 927 | |
0e078e2f TG |
928 | set_irq_regs(old_regs); |
929 | } | |
930 | ||
1d9090e2 | 931 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
cf910e83 SA |
932 | { |
933 | struct pt_regs *old_regs = set_irq_regs(regs); | |
934 | ||
0e078e2f | 935 | /* |
cf910e83 SA |
936 | * NOTE! We'd better ACK the irq immediately, |
937 | * because timer handling can be slow. | |
938 | * | |
0e078e2f TG |
939 | * update_process_times() expects us to have done irq_enter(). |
940 | * Besides, if we don't timer interrupts ignore the global | |
941 | * interrupt lock, which is the WrongThing (tm) to do. | |
942 | */ | |
cf910e83 SA |
943 | entering_ack_irq(); |
944 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); | |
0e078e2f | 945 | local_apic_timer_interrupt(); |
cf910e83 SA |
946 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
947 | exiting_irq(); | |
274cfe59 | 948 | |
0e078e2f TG |
949 | set_irq_regs(old_regs); |
950 | } | |
951 | ||
952 | int setup_profiling_timer(unsigned int multiplier) | |
953 | { | |
954 | return -EINVAL; | |
955 | } | |
956 | ||
0e078e2f TG |
957 | /* |
958 | * Local APIC start and shutdown | |
959 | */ | |
960 | ||
961 | /** | |
962 | * clear_local_APIC - shutdown the local APIC | |
963 | * | |
964 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
965 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
966 | * leftovers during boot. | |
967 | */ | |
968 | void clear_local_APIC(void) | |
969 | { | |
2584a82d | 970 | int maxlvt; |
0e078e2f TG |
971 | u32 v; |
972 | ||
d3432896 | 973 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 974 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
975 | return; |
976 | ||
977 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
978 | /* |
979 | * Masking an LVT entry can trigger a local APIC error | |
980 | * if the vector is zero. Mask LVTERR first to prevent this. | |
981 | */ | |
982 | if (maxlvt >= 3) { | |
983 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
984 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
985 | } | |
986 | /* | |
987 | * Careful: we have to set masks only first to deassert | |
988 | * any level-triggered sources. | |
989 | */ | |
990 | v = apic_read(APIC_LVTT); | |
991 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
992 | v = apic_read(APIC_LVT0); | |
993 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
994 | v = apic_read(APIC_LVT1); | |
995 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
996 | if (maxlvt >= 4) { | |
997 | v = apic_read(APIC_LVTPC); | |
998 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
999 | } | |
1000 | ||
6764014b | 1001 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1002 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1003 | if (maxlvt >= 5) { |
1004 | v = apic_read(APIC_LVTTHMR); | |
1005 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1006 | } | |
1007 | #endif | |
5ca8681c AK |
1008 | #ifdef CONFIG_X86_MCE_INTEL |
1009 | if (maxlvt >= 6) { | |
1010 | v = apic_read(APIC_LVTCMCI); | |
1011 | if (!(v & APIC_LVT_MASKED)) | |
1012 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1013 | } | |
1014 | #endif | |
1015 | ||
0e078e2f TG |
1016 | /* |
1017 | * Clean APIC state for other OSs: | |
1018 | */ | |
1019 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1020 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1021 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1022 | if (maxlvt >= 3) | |
1023 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1024 | if (maxlvt >= 4) | |
1025 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1026 | |
1027 | /* Integrated APIC (!82489DX) ? */ | |
1028 | if (lapic_is_integrated()) { | |
1029 | if (maxlvt > 3) | |
1030 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1031 | apic_write(APIC_ESR, 0); | |
1032 | apic_read(APIC_ESR); | |
1033 | } | |
0e078e2f TG |
1034 | } |
1035 | ||
1036 | /** | |
1037 | * disable_local_APIC - clear and disable the local APIC | |
1038 | */ | |
1039 | void disable_local_APIC(void) | |
1040 | { | |
1041 | unsigned int value; | |
1042 | ||
4a13ad0b | 1043 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 1044 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
1045 | return; |
1046 | ||
0e078e2f TG |
1047 | clear_local_APIC(); |
1048 | ||
1049 | /* | |
1050 | * Disable APIC (implies clearing of registers | |
1051 | * for 82489DX!). | |
1052 | */ | |
1053 | value = apic_read(APIC_SPIV); | |
1054 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1055 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1056 | |
1057 | #ifdef CONFIG_X86_32 | |
1058 | /* | |
1059 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1060 | * restore the disabled state. | |
1061 | */ | |
1062 | if (enabled_via_apicbase) { | |
1063 | unsigned int l, h; | |
1064 | ||
1065 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1066 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1067 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1068 | } | |
1069 | #endif | |
0e078e2f TG |
1070 | } |
1071 | ||
fe4024dc CG |
1072 | /* |
1073 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1074 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1075 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1076 | * for the case where Linux didn't enable the LAPIC. | |
1077 | */ | |
0e078e2f TG |
1078 | void lapic_shutdown(void) |
1079 | { | |
1080 | unsigned long flags; | |
1081 | ||
8312136f | 1082 | if (!cpu_has_apic && !apic_from_smp_config()) |
0e078e2f TG |
1083 | return; |
1084 | ||
1085 | local_irq_save(flags); | |
1086 | ||
fe4024dc CG |
1087 | #ifdef CONFIG_X86_32 |
1088 | if (!enabled_via_apicbase) | |
1089 | clear_local_APIC(); | |
1090 | else | |
1091 | #endif | |
1092 | disable_local_APIC(); | |
1093 | ||
0e078e2f TG |
1094 | |
1095 | local_irq_restore(flags); | |
1096 | } | |
1097 | ||
0e078e2f TG |
1098 | /** |
1099 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1100 | */ | |
1da177e4 LT |
1101 | void __init sync_Arb_IDs(void) |
1102 | { | |
296cb951 CG |
1103 | /* |
1104 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1105 | * needed on AMD. | |
1106 | */ | |
1107 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1108 | return; |
1109 | ||
1110 | /* | |
1111 | * Wait for idle. | |
1112 | */ | |
1113 | apic_wait_icr_idle(); | |
1114 | ||
1115 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1116 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1117 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1118 | } |
1119 | ||
1da177e4 LT |
1120 | /* |
1121 | * An initial setup of the virtual wire mode. | |
1122 | */ | |
1123 | void __init init_bsp_APIC(void) | |
1124 | { | |
11a8e778 | 1125 | unsigned int value; |
1da177e4 LT |
1126 | |
1127 | /* | |
1128 | * Don't do the setup now if we have a SMP BIOS as the | |
1129 | * through-I/O-APIC virtual wire mode might be active. | |
1130 | */ | |
1131 | if (smp_found_config || !cpu_has_apic) | |
1132 | return; | |
1133 | ||
1da177e4 LT |
1134 | /* |
1135 | * Do not trust the local APIC being empty at bootup. | |
1136 | */ | |
1137 | clear_local_APIC(); | |
1138 | ||
1139 | /* | |
1140 | * Enable APIC. | |
1141 | */ | |
1142 | value = apic_read(APIC_SPIV); | |
1143 | value &= ~APIC_VECTOR_MASK; | |
1144 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1145 | |
1146 | #ifdef CONFIG_X86_32 | |
1147 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1148 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1149 | (boot_cpu_data.x86 == 15)) | |
1150 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1151 | else | |
1152 | #endif | |
1153 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1154 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1155 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1156 | |
1157 | /* | |
1158 | * Set up the virtual wire mode. | |
1159 | */ | |
11a8e778 | 1160 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1161 | value = APIC_DM_NMI; |
638c0411 CG |
1162 | if (!lapic_is_integrated()) /* 82489DX */ |
1163 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1164 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1165 | } |
1166 | ||
148f9bb8 | 1167 | static void lapic_setup_esr(void) |
c43da2f5 | 1168 | { |
9df08f10 CG |
1169 | unsigned int oldvalue, value, maxlvt; |
1170 | ||
1171 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1172 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1173 | return; |
1174 | } | |
c43da2f5 | 1175 | |
08125d3e | 1176 | if (apic->disable_esr) { |
c43da2f5 | 1177 | /* |
9df08f10 CG |
1178 | * Something untraceable is creating bad interrupts on |
1179 | * secondary quads ... for the moment, just leave the | |
1180 | * ESR disabled - we can't do anything useful with the | |
1181 | * errors anyway - mbligh | |
c43da2f5 | 1182 | */ |
ba21ebb6 | 1183 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1184 | return; |
c43da2f5 | 1185 | } |
9df08f10 CG |
1186 | |
1187 | maxlvt = lapic_get_maxlvt(); | |
1188 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1189 | apic_write(APIC_ESR, 0); | |
1190 | oldvalue = apic_read(APIC_ESR); | |
1191 | ||
1192 | /* enables sending errors */ | |
1193 | value = ERROR_APIC_VECTOR; | |
1194 | apic_write(APIC_LVTERR, value); | |
1195 | ||
1196 | /* | |
1197 | * spec says clear errors after enabling vector. | |
1198 | */ | |
1199 | if (maxlvt > 3) | |
1200 | apic_write(APIC_ESR, 0); | |
1201 | value = apic_read(APIC_ESR); | |
1202 | if (value != oldvalue) | |
1203 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1204 | "vector: 0x%08x after: 0x%08x\n", | |
1205 | oldvalue, value); | |
c43da2f5 CG |
1206 | } |
1207 | ||
0e078e2f TG |
1208 | /** |
1209 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1210 | * |
1211 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1212 | * Always called with preemption disabled. | |
0e078e2f | 1213 | */ |
148f9bb8 | 1214 | void setup_local_APIC(void) |
1da177e4 | 1215 | { |
0aa002fe | 1216 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1217 | unsigned int value, queued; |
1218 | int i, j, acked = 0; | |
1219 | unsigned long long tsc = 0, ntsc; | |
b47dcbdc | 1220 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
8c3ba8d0 KJ |
1221 | |
1222 | if (cpu_has_tsc) | |
4ea1636b | 1223 | tsc = rdtsc(); |
1da177e4 | 1224 | |
f1182638 | 1225 | if (disable_apic) { |
7167d08e | 1226 | disable_ioapic_support(); |
f1182638 JB |
1227 | return; |
1228 | } | |
1229 | ||
89c38c28 CG |
1230 | #ifdef CONFIG_X86_32 |
1231 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1232 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1233 | apic_write(APIC_ESR, 0); |
1234 | apic_write(APIC_ESR, 0); | |
1235 | apic_write(APIC_ESR, 0); | |
1236 | apic_write(APIC_ESR, 0); | |
1237 | } | |
1238 | #endif | |
cdd6c482 | 1239 | perf_events_lapic_init(); |
89c38c28 | 1240 | |
1da177e4 LT |
1241 | /* |
1242 | * Double-check whether this APIC is really registered. | |
1243 | * This is meaningless in clustered apic mode, so we skip it. | |
1244 | */ | |
c2777f98 | 1245 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1246 | |
1247 | /* | |
1248 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1249 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1250 | * document number 292116). So here it goes... | |
1251 | */ | |
a5c43296 | 1252 | apic->init_apic_ldr(); |
1da177e4 | 1253 | |
6f802c4b TH |
1254 | #ifdef CONFIG_X86_32 |
1255 | /* | |
acb8bc09 TH |
1256 | * APIC LDR is initialized. If logical_apicid mapping was |
1257 | * initialized during get_smp_config(), make sure it matches the | |
1258 | * actual value. | |
6f802c4b | 1259 | */ |
acb8bc09 TH |
1260 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1261 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1262 | /* always use the value from LDR */ | |
6f802c4b TH |
1263 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1264 | logical_smp_processor_id(); | |
1265 | #endif | |
1266 | ||
1da177e4 LT |
1267 | /* |
1268 | * Set Task Priority to 'accept all'. We never change this | |
1269 | * later on. | |
1270 | */ | |
1271 | value = apic_read(APIC_TASKPRI); | |
1272 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1273 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1274 | |
da7ed9f9 VG |
1275 | /* |
1276 | * After a crash, we no longer service the interrupts and a pending | |
1277 | * interrupt from previous kernel might still have ISR bit set. | |
1278 | * | |
1279 | * Most probably by now CPU has serviced that pending interrupt and | |
1280 | * it might not have done the ack_APIC_irq() because it thought, | |
1281 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1282 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1283 | * the interrupt. Hence a vector might get locked. It was noticed | |
1284 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1285 | */ | |
8c3ba8d0 KJ |
1286 | do { |
1287 | queued = 0; | |
1288 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1289 | queued |= apic_read(APIC_IRR + i*0x10); | |
1290 | ||
1291 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1292 | value = apic_read(APIC_ISR + i*0x10); | |
1293 | for (j = 31; j >= 0; j--) { | |
1294 | if (value & (1<<j)) { | |
1295 | ack_APIC_irq(); | |
1296 | acked++; | |
1297 | } | |
1298 | } | |
da7ed9f9 | 1299 | } |
8c3ba8d0 KJ |
1300 | if (acked > 256) { |
1301 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1302 | acked); | |
1303 | break; | |
1304 | } | |
42fa4250 | 1305 | if (queued) { |
b47dcbdc | 1306 | if (cpu_has_tsc && cpu_khz) { |
4ea1636b | 1307 | ntsc = rdtsc(); |
42fa4250 SF |
1308 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
1309 | } else | |
1310 | max_loops--; | |
1311 | } | |
8c3ba8d0 KJ |
1312 | } while (queued && max_loops > 0); |
1313 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1314 | |
1da177e4 LT |
1315 | /* |
1316 | * Now that we are all set up, enable the APIC | |
1317 | */ | |
1318 | value = apic_read(APIC_SPIV); | |
1319 | value &= ~APIC_VECTOR_MASK; | |
1320 | /* | |
1321 | * Enable APIC | |
1322 | */ | |
1323 | value |= APIC_SPIV_APIC_ENABLED; | |
1324 | ||
89c38c28 CG |
1325 | #ifdef CONFIG_X86_32 |
1326 | /* | |
1327 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1328 | * certain networking cards. If high frequency interrupts are | |
1329 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1330 | * entry is masked/unmasked at a high rate as well then sooner or | |
1331 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1332 | * from the device. If focus CPU is disabled then the hang goes | |
1333 | * away, oh well :-( | |
1334 | * | |
1335 | * [ This bug can be reproduced easily with a level-triggered | |
1336 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1337 | * BX chipset. ] | |
1338 | */ | |
1339 | /* | |
1340 | * Actually disabling the focus CPU check just makes the hang less | |
1341 | * frequent as it makes the interrupt distributon model be more | |
1342 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1343 | * See also the comment in end_level_ioapic_irq(). --macro | |
1344 | */ | |
1345 | ||
1346 | /* | |
1347 | * - enable focus processor (bit==0) | |
1348 | * - 64bit mode always use processor focus | |
1349 | * so no need to set it | |
1350 | */ | |
1351 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1352 | #endif | |
3f14c746 | 1353 | |
1da177e4 LT |
1354 | /* |
1355 | * Set spurious IRQ vector | |
1356 | */ | |
1357 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1358 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1359 | |
1360 | /* | |
1361 | * Set up LVT0, LVT1: | |
1362 | * | |
1363 | * set up through-local-APIC on the BP's LINT0. This is not | |
1364 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1365 | * we delegate interrupts to the 8259A. | |
1366 | */ | |
1367 | /* | |
1368 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1369 | */ | |
1370 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1371 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1372 | value = APIC_DM_EXTINT; |
0aa002fe | 1373 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1374 | } else { |
1375 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1376 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1377 | } |
11a8e778 | 1378 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1379 | |
1380 | /* | |
1381 | * only the BP should see the LINT1 NMI signal, obviously. | |
1382 | */ | |
0aa002fe | 1383 | if (!cpu) |
1da177e4 LT |
1384 | value = APIC_DM_NMI; |
1385 | else | |
1386 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1387 | if (!lapic_is_integrated()) /* 82489DX */ |
1388 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1389 | apic_write(APIC_LVT1, value); |
89c38c28 | 1390 | |
be71b855 AK |
1391 | #ifdef CONFIG_X86_MCE_INTEL |
1392 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1393 | if (!cpu) |
be71b855 AK |
1394 | cmci_recheck(); |
1395 | #endif | |
739f33b3 | 1396 | } |
1da177e4 | 1397 | |
05f7e46d | 1398 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1399 | { |
1400 | lapic_setup_esr(); | |
fa6b95fc CG |
1401 | |
1402 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1403 | { |
1404 | unsigned int value; | |
1405 | /* Disable the local apic timer */ | |
1406 | value = apic_read(APIC_LVTT); | |
1407 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1408 | apic_write(APIC_LVTT, value); | |
1409 | } | |
fa6b95fc CG |
1410 | #endif |
1411 | ||
0e078e2f | 1412 | apic_pm_activate(); |
2fb270f3 JB |
1413 | } |
1414 | ||
05f7e46d TG |
1415 | /* |
1416 | * APIC setup function for application processors. Called from smpboot.c | |
1417 | */ | |
1418 | void apic_ap_setup(void) | |
2fb270f3 | 1419 | { |
05f7e46d | 1420 | setup_local_APIC(); |
2fb270f3 | 1421 | end_local_APIC_setup(); |
1da177e4 | 1422 | } |
1da177e4 | 1423 | |
06cd9a7d | 1424 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1425 | int x2apic_mode; |
12e189d3 TG |
1426 | |
1427 | enum { | |
1428 | X2APIC_OFF, | |
1429 | X2APIC_ON, | |
1430 | X2APIC_DISABLED, | |
1431 | }; | |
1432 | static int x2apic_state; | |
1433 | ||
44e25ff9 TG |
1434 | static inline void __x2apic_disable(void) |
1435 | { | |
1436 | u64 msr; | |
1437 | ||
a57e456a | 1438 | if (!cpu_has_apic) |
659006bf TG |
1439 | return; |
1440 | ||
44e25ff9 TG |
1441 | rdmsrl(MSR_IA32_APICBASE, msr); |
1442 | if (!(msr & X2APIC_ENABLE)) | |
1443 | return; | |
1444 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1445 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1446 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1447 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1448 | } | |
1449 | ||
659006bf TG |
1450 | static inline void __x2apic_enable(void) |
1451 | { | |
1452 | u64 msr; | |
1453 | ||
1454 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1455 | if (msr & X2APIC_ENABLE) | |
1456 | return; | |
1457 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1458 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1459 | } | |
1460 | ||
bfb05070 TG |
1461 | static int __init setup_nox2apic(char *str) |
1462 | { | |
1463 | if (x2apic_enabled()) { | |
1464 | int apicid = native_apic_msr_read(APIC_ID); | |
1465 | ||
1466 | if (apicid >= 255) { | |
1467 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
1468 | apicid); | |
1469 | return 0; | |
1470 | } | |
44e25ff9 TG |
1471 | pr_warning("x2apic already enabled.\n"); |
1472 | __x2apic_disable(); | |
1473 | } | |
1474 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1475 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1476 | x2apic_mode = 0; |
bfb05070 TG |
1477 | return 0; |
1478 | } | |
1479 | early_param("nox2apic", setup_nox2apic); | |
1480 | ||
659006bf TG |
1481 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1482 | void x2apic_setup(void) | |
1483 | { | |
1484 | /* | |
1485 | * If x2apic is not in ON state, disable it if already enabled | |
1486 | * from BIOS. | |
1487 | */ | |
1488 | if (x2apic_state != X2APIC_ON) { | |
1489 | __x2apic_disable(); | |
1490 | return; | |
1491 | } | |
1492 | __x2apic_enable(); | |
1493 | } | |
1494 | ||
44e25ff9 | 1495 | static __init void x2apic_disable(void) |
fb209bd8 | 1496 | { |
a57e456a | 1497 | u32 x2apic_id, state = x2apic_state; |
fb209bd8 | 1498 | |
a57e456a TG |
1499 | x2apic_mode = 0; |
1500 | x2apic_state = X2APIC_DISABLED; | |
1501 | ||
1502 | if (state != X2APIC_ON) | |
1503 | return; | |
fb209bd8 | 1504 | |
6d2d49d2 TG |
1505 | x2apic_id = read_apic_id(); |
1506 | if (x2apic_id >= 255) | |
1507 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1508 | |
6d2d49d2 TG |
1509 | __x2apic_disable(); |
1510 | register_lapic_address(mp_lapic_addr); | |
fb209bd8 YL |
1511 | } |
1512 | ||
659006bf | 1513 | static __init void x2apic_enable(void) |
6e1cb38a | 1514 | { |
659006bf | 1515 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1516 | return; |
1517 | ||
659006bf | 1518 | x2apic_mode = 1; |
12e189d3 | 1519 | x2apic_state = X2APIC_ON; |
659006bf | 1520 | __x2apic_enable(); |
6e1cb38a | 1521 | } |
d524165c | 1522 | |
62e61633 | 1523 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1524 | { |
659006bf | 1525 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1526 | return; |
1527 | ||
62e61633 | 1528 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
07806c50 JL |
1529 | /* IR is required if there is APIC ID > 255 even when running |
1530 | * under KVM | |
1531 | */ | |
1532 | if (max_physical_apicid > 255 || | |
8329aa9f | 1533 | !hypervisor_x2apic_available()) { |
62e61633 | 1534 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1535 | x2apic_disable(); |
07806c50 JL |
1536 | return; |
1537 | } | |
1538 | ||
1539 | /* | |
1540 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1541 | * only in physical mode | |
1542 | */ | |
55eae7de | 1543 | x2apic_phys = 1; |
07806c50 | 1544 | } |
659006bf | 1545 | x2apic_enable(); |
55eae7de TG |
1546 | } |
1547 | ||
1548 | void __init check_x2apic(void) | |
1549 | { | |
1550 | if (x2apic_enabled()) { | |
1551 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1552 | x2apic_mode = 1; | |
12e189d3 TG |
1553 | x2apic_state = X2APIC_ON; |
1554 | } else if (!cpu_has_x2apic) { | |
1555 | x2apic_state = X2APIC_DISABLED; | |
55eae7de TG |
1556 | } |
1557 | } | |
1558 | #else /* CONFIG_X86_X2APIC */ | |
1559 | static int __init validate_x2apic(void) | |
1560 | { | |
1561 | if (!apic_is_x2apic_enabled()) | |
1562 | return 0; | |
1563 | /* | |
1564 | * Checkme: Can we simply turn off x2apic here instead of panic? | |
1565 | */ | |
1566 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); | |
1567 | } | |
1568 | early_initcall(validate_x2apic); | |
1569 | ||
62e61633 | 1570 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1571 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1572 | #endif /* !CONFIG_X86_X2APIC */ |
1573 | ||
1574 | static int __init try_to_enable_IR(void) | |
1575 | { | |
1576 | #ifdef CONFIG_X86_IO_APIC | |
1577 | if (!x2apic_enabled() && skip_ioapic_setup) { | |
1578 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); | |
1579 | return -1; | |
1580 | } | |
ce69a784 | 1581 | #endif |
55eae7de | 1582 | return irq_remapping_enable(); |
ce69a784 GN |
1583 | } |
1584 | ||
1585 | void __init enable_IR_x2apic(void) | |
1586 | { | |
1587 | unsigned long flags; | |
07806c50 | 1588 | int ret, ir_stat; |
b7f42ab2 | 1589 | |
07806c50 JL |
1590 | ir_stat = irq_remapping_prepare(); |
1591 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1592 | return; |
ce69a784 | 1593 | |
31dce14a | 1594 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1595 | if (ret) { |
ba21ebb6 | 1596 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1597 | return; |
5ffa4eb2 | 1598 | } |
6e1cb38a | 1599 | |
05c3dc2c | 1600 | local_irq_save(flags); |
b81bb373 | 1601 | legacy_pic->mask_all(); |
31dce14a | 1602 | mask_ioapic_entries(); |
05c3dc2c | 1603 | |
07806c50 JL |
1604 | /* If irq_remapping_prepare() succeded, try to enable it */ |
1605 | if (ir_stat >= 0) | |
1606 | ir_stat = try_to_enable_IR(); | |
1607 | /* ir_stat contains the remap mode or an error code */ | |
1608 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1609 | |
07806c50 | 1610 | if (ir_stat < 0) |
31dce14a | 1611 | restore_ioapic_entries(); |
b81bb373 | 1612 | legacy_pic->restore_mask(); |
6e1cb38a | 1613 | local_irq_restore(flags); |
6e1cb38a | 1614 | } |
93758238 | 1615 | |
be7a656f | 1616 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1617 | /* |
1618 | * Detect and enable local APICs on non-SMP boards. | |
1619 | * Original code written by Keir Fraser. | |
1620 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1621 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1622 | */ |
0e078e2f | 1623 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1624 | { |
1625 | if (!cpu_has_apic) { | |
ba21ebb6 | 1626 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1627 | return -1; |
1628 | } | |
1629 | ||
1630 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1631 | return 0; |
1632 | } | |
be7a656f | 1633 | #else |
5a7ae78f | 1634 | |
25874a29 | 1635 | static int __init apic_verify(void) |
5a7ae78f TG |
1636 | { |
1637 | u32 features, h, l; | |
1638 | ||
1639 | /* | |
1640 | * The APIC feature bit should now be enabled | |
1641 | * in `cpuid' | |
1642 | */ | |
1643 | features = cpuid_edx(1); | |
1644 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1645 | pr_warning("Could not enable APIC!\n"); | |
1646 | return -1; | |
1647 | } | |
1648 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1649 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1650 | ||
1651 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1652 | if (boot_cpu_data.x86 >= 6) { |
1653 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1654 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1655 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1656 | } | |
5a7ae78f TG |
1657 | |
1658 | pr_info("Found and enabled local APIC!\n"); | |
1659 | return 0; | |
1660 | } | |
1661 | ||
25874a29 | 1662 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1663 | { |
1664 | u32 h, l; | |
1665 | ||
1666 | if (disable_apic) | |
1667 | return -1; | |
1668 | ||
1669 | /* | |
1670 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1671 | * MSR. This can only be done in software for Intel P6 or later | |
1672 | * and AMD K7 (Model > 1) or later. | |
1673 | */ | |
cbf2829b BD |
1674 | if (boot_cpu_data.x86 >= 6) { |
1675 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1676 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1677 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1678 | l &= ~MSR_IA32_APICBASE_BASE; | |
1679 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1680 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1681 | enabled_via_apicbase = 1; | |
1682 | } | |
5a7ae78f TG |
1683 | } |
1684 | return apic_verify(); | |
1685 | } | |
1686 | ||
be7a656f YL |
1687 | /* |
1688 | * Detect and initialize APIC | |
1689 | */ | |
1690 | static int __init detect_init_APIC(void) | |
1691 | { | |
be7a656f YL |
1692 | /* Disabled by kernel option? */ |
1693 | if (disable_apic) | |
1694 | return -1; | |
1695 | ||
1696 | switch (boot_cpu_data.x86_vendor) { | |
1697 | case X86_VENDOR_AMD: | |
1698 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1699 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1700 | break; |
1701 | goto no_apic; | |
1702 | case X86_VENDOR_INTEL: | |
1703 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1704 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1705 | break; | |
1706 | goto no_apic; | |
1707 | default: | |
1708 | goto no_apic; | |
1709 | } | |
1710 | ||
1711 | if (!cpu_has_apic) { | |
1712 | /* | |
1713 | * Over-ride BIOS and try to enable the local APIC only if | |
1714 | * "lapic" specified. | |
1715 | */ | |
1716 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1717 | pr_info("Local APIC disabled by BIOS -- " |
1718 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1719 | return -1; |
1720 | } | |
a906fdaa | 1721 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1722 | return -1; |
1723 | } else { | |
1724 | if (apic_verify()) | |
1725 | return -1; | |
be7a656f | 1726 | } |
be7a656f YL |
1727 | |
1728 | apic_pm_activate(); | |
1729 | ||
1730 | return 0; | |
1731 | ||
1732 | no_apic: | |
ba21ebb6 | 1733 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1734 | return -1; |
1735 | } | |
1736 | #endif | |
1da177e4 | 1737 | |
0e078e2f TG |
1738 | /** |
1739 | * init_apic_mappings - initialize APIC mappings | |
1740 | */ | |
1da177e4 LT |
1741 | void __init init_apic_mappings(void) |
1742 | { | |
4401da61 YL |
1743 | unsigned int new_apicid; |
1744 | ||
fc1edaf9 | 1745 | if (x2apic_mode) { |
4c9961d5 | 1746 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1747 | return; |
1748 | } | |
1749 | ||
4797f6b0 | 1750 | /* If no local APIC can be found return early */ |
1da177e4 | 1751 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1752 | /* lets NOP'ify apic operations */ |
1753 | pr_info("APIC: disable apic facility\n"); | |
1754 | apic_disable(); | |
1755 | } else { | |
1da177e4 LT |
1756 | apic_phys = mp_lapic_addr; |
1757 | ||
4797f6b0 YL |
1758 | /* |
1759 | * acpi lapic path already maps that address in | |
1760 | * acpi_register_lapic_address() | |
1761 | */ | |
5989cd6a | 1762 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1763 | register_lapic_address(apic_phys); |
cec6be6d | 1764 | } |
1da177e4 LT |
1765 | |
1766 | /* | |
1767 | * Fetch the APIC ID of the BSP in case we have a | |
1768 | * default configuration (or the MP table is broken). | |
1769 | */ | |
4401da61 YL |
1770 | new_apicid = read_apic_id(); |
1771 | if (boot_cpu_physical_apicid != new_apicid) { | |
1772 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1773 | /* |
1774 | * yeah -- we lie about apic_version | |
1775 | * in case if apic was disabled via boot option | |
1776 | * but it's not a problem for SMP compiled kernel | |
1777 | * since smp_sanity_check is prepared for such a case | |
1778 | * and disable smp mode | |
1779 | */ | |
4401da61 YL |
1780 | apic_version[new_apicid] = |
1781 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1782 | } |
1da177e4 LT |
1783 | } |
1784 | ||
c0104d38 YL |
1785 | void __init register_lapic_address(unsigned long address) |
1786 | { | |
1787 | mp_lapic_addr = address; | |
1788 | ||
0450193b YL |
1789 | if (!x2apic_mode) { |
1790 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1791 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1792 | APIC_BASE, mp_lapic_addr); | |
1793 | } | |
c0104d38 YL |
1794 | if (boot_cpu_physical_apicid == -1U) { |
1795 | boot_cpu_physical_apicid = read_apic_id(); | |
1796 | apic_version[boot_cpu_physical_apicid] = | |
1797 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1798 | } | |
1799 | } | |
1800 | ||
56d91f13 | 1801 | int apic_version[MAX_LOCAL_APIC]; |
1b313f4a | 1802 | |
1da177e4 | 1803 | /* |
0e078e2f | 1804 | * Local APIC interrupts |
1da177e4 LT |
1805 | */ |
1806 | ||
0e078e2f TG |
1807 | /* |
1808 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1809 | */ | |
2414e021 | 1810 | static inline void __smp_spurious_interrupt(u8 vector) |
1da177e4 | 1811 | { |
dc1528dd YL |
1812 | u32 v; |
1813 | ||
1da177e4 | 1814 | /* |
0e078e2f TG |
1815 | * Check if this really is a spurious interrupt and ACK it |
1816 | * if it is a vectored one. Just in case... | |
1817 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1818 | */ |
2414e021 JB |
1819 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
1820 | if (v & (1 << (vector & 0x1f))) | |
0e078e2f | 1821 | ack_APIC_irq(); |
c4d58cbd | 1822 | |
915b0d01 HS |
1823 | inc_irq_stat(irq_spurious_count); |
1824 | ||
dc1528dd | 1825 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
2414e021 JB |
1826 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
1827 | "should never happen.\n", vector, smp_processor_id()); | |
eddc0e92 SA |
1828 | } |
1829 | ||
1d9090e2 | 1830 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1831 | { |
1832 | entering_irq(); | |
2414e021 | 1833 | __smp_spurious_interrupt(~regs->orig_ax); |
eddc0e92 | 1834 | exiting_irq(); |
0e078e2f | 1835 | } |
1da177e4 | 1836 | |
1d9090e2 | 1837 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
cf910e83 | 1838 | { |
2414e021 JB |
1839 | u8 vector = ~regs->orig_ax; |
1840 | ||
cf910e83 | 1841 | entering_irq(); |
2414e021 JB |
1842 | trace_spurious_apic_entry(vector); |
1843 | __smp_spurious_interrupt(vector); | |
1844 | trace_spurious_apic_exit(vector); | |
cf910e83 | 1845 | exiting_irq(); |
0e078e2f | 1846 | } |
1da177e4 | 1847 | |
0e078e2f TG |
1848 | /* |
1849 | * This interrupt should never happen with our APIC/SMP architecture | |
1850 | */ | |
eddc0e92 | 1851 | static inline void __smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1852 | { |
60283df7 | 1853 | u32 v; |
2b398bd9 YS |
1854 | u32 i = 0; |
1855 | static const char * const error_interrupt_reason[] = { | |
1856 | "Send CS error", /* APIC Error Bit 0 */ | |
1857 | "Receive CS error", /* APIC Error Bit 1 */ | |
1858 | "Send accept error", /* APIC Error Bit 2 */ | |
1859 | "Receive accept error", /* APIC Error Bit 3 */ | |
1860 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1861 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1862 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1863 | "Illegal register address", /* APIC Error Bit 7 */ | |
1864 | }; | |
1da177e4 | 1865 | |
0e078e2f | 1866 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
1867 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
1868 | apic_write(APIC_ESR, 0); | |
60283df7 | 1869 | v = apic_read(APIC_ESR); |
0e078e2f TG |
1870 | ack_APIC_irq(); |
1871 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1872 | |
60283df7 RW |
1873 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
1874 | smp_processor_id(), v); | |
2b398bd9 | 1875 | |
60283df7 RW |
1876 | v &= 0xff; |
1877 | while (v) { | |
1878 | if (v & 0x1) | |
2b398bd9 YS |
1879 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
1880 | i++; | |
60283df7 | 1881 | v >>= 1; |
4b8073e4 | 1882 | } |
2b398bd9 YS |
1883 | |
1884 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
1885 | ||
eddc0e92 SA |
1886 | } |
1887 | ||
1d9090e2 | 1888 | __visible void smp_error_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1889 | { |
1890 | entering_irq(); | |
1891 | __smp_error_interrupt(regs); | |
1892 | exiting_irq(); | |
1da177e4 LT |
1893 | } |
1894 | ||
1d9090e2 | 1895 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
cf910e83 SA |
1896 | { |
1897 | entering_irq(); | |
1898 | trace_error_apic_entry(ERROR_APIC_VECTOR); | |
1899 | __smp_error_interrupt(regs); | |
1900 | trace_error_apic_exit(ERROR_APIC_VECTOR); | |
1901 | exiting_irq(); | |
1da177e4 LT |
1902 | } |
1903 | ||
b5841765 | 1904 | /** |
36c9d674 CG |
1905 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1906 | */ | |
05f7e46d | 1907 | static void __init connect_bsp_APIC(void) |
b5841765 | 1908 | { |
36c9d674 CG |
1909 | #ifdef CONFIG_X86_32 |
1910 | if (pic_mode) { | |
1911 | /* | |
1912 | * Do not trust the local APIC being empty at bootup. | |
1913 | */ | |
1914 | clear_local_APIC(); | |
1915 | /* | |
1916 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1917 | * local APIC to INT and NMI lines. | |
1918 | */ | |
1919 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1920 | "enabling APIC mode.\n"); | |
c0eaa453 | 1921 | imcr_pic_to_apic(); |
36c9d674 CG |
1922 | } |
1923 | #endif | |
b5841765 GC |
1924 | } |
1925 | ||
274cfe59 CG |
1926 | /** |
1927 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1928 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1929 | * | |
1930 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1931 | * APIC is disabled. | |
1932 | */ | |
0e078e2f | 1933 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1934 | { |
1b4ee4e4 CG |
1935 | unsigned int value; |
1936 | ||
c177b0bc CG |
1937 | #ifdef CONFIG_X86_32 |
1938 | if (pic_mode) { | |
1939 | /* | |
1940 | * Put the board back into PIC mode (has an effect only on | |
1941 | * certain older boards). Note that APIC interrupts, including | |
1942 | * IPIs, won't work beyond this point! The only exception are | |
1943 | * INIT IPIs. | |
1944 | */ | |
1945 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1946 | "entering PIC mode.\n"); | |
c0eaa453 | 1947 | imcr_apic_to_pic(); |
c177b0bc CG |
1948 | return; |
1949 | } | |
1950 | #endif | |
1951 | ||
0e078e2f | 1952 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1953 | |
0e078e2f TG |
1954 | /* For the spurious interrupt use vector F, and enable it */ |
1955 | value = apic_read(APIC_SPIV); | |
1956 | value &= ~APIC_VECTOR_MASK; | |
1957 | value |= APIC_SPIV_APIC_ENABLED; | |
1958 | value |= 0xf; | |
1959 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1960 | |
0e078e2f TG |
1961 | if (!virt_wire_setup) { |
1962 | /* | |
1963 | * For LVT0 make it edge triggered, active high, | |
1964 | * external and enabled | |
1965 | */ | |
1966 | value = apic_read(APIC_LVT0); | |
1967 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1968 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1969 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1970 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1971 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1972 | apic_write(APIC_LVT0, value); | |
1973 | } else { | |
1974 | /* Disable LVT0 */ | |
1975 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1976 | } | |
b8ce3359 | 1977 | |
c177b0bc CG |
1978 | /* |
1979 | * For LVT1 make it edge triggered, active high, | |
1980 | * nmi and enabled | |
1981 | */ | |
0e078e2f TG |
1982 | value = apic_read(APIC_LVT1); |
1983 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1984 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1985 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1986 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1987 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1988 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1989 | } |
1990 | ||
7e1f85f9 | 1991 | int generic_processor_info(int apicid, int version) |
be8a5685 | 1992 | { |
14cb6dcf VG |
1993 | int cpu, max = nr_cpu_ids; |
1994 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
1995 | phys_cpu_present_map); | |
1996 | ||
151e0c7d HD |
1997 | /* |
1998 | * boot_cpu_physical_apicid is designed to have the apicid | |
1999 | * returned by read_apic_id(), i.e, the apicid of the | |
2000 | * currently booting-up processor. However, on some platforms, | |
5b4d1dbc | 2001 | * it is temporarily modified by the apicid reported as BSP |
151e0c7d HD |
2002 | * through MP table. Concretely: |
2003 | * | |
2004 | * - arch/x86/kernel/mpparse.c: MP_processor_info() | |
2005 | * - arch/x86/mm/amdtopology.c: amd_numa_init() | |
151e0c7d HD |
2006 | * |
2007 | * This function is executed with the modified | |
2008 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel | |
2009 | * parameter doesn't work to disable APs on kdump 2nd kernel. | |
2010 | * | |
2011 | * Since fixing handling of boot_cpu_physical_apicid requires | |
2012 | * another discussion and tests on each platform, we leave it | |
2013 | * for now and here we use read_apic_id() directly in this | |
2014 | * function, generic_processor_info(). | |
2015 | */ | |
2016 | if (disabled_cpu_apicid != BAD_APICID && | |
2017 | disabled_cpu_apicid != read_apic_id() && | |
2018 | disabled_cpu_apicid == apicid) { | |
2019 | int thiscpu = num_processors + disabled_cpus; | |
2020 | ||
5b4d1dbc | 2021 | pr_warning("APIC: Disabling requested cpu." |
151e0c7d HD |
2022 | " Processor %d/0x%x ignored.\n", |
2023 | thiscpu, apicid); | |
2024 | ||
2025 | disabled_cpus++; | |
2026 | return -ENODEV; | |
2027 | } | |
2028 | ||
14cb6dcf VG |
2029 | /* |
2030 | * If boot cpu has not been detected yet, then only allow upto | |
2031 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2032 | */ | |
2033 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2034 | apicid != boot_cpu_physical_apicid) { | |
2035 | int thiscpu = max + disabled_cpus - 1; | |
2036 | ||
2037 | pr_warning( | |
2038 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" | |
2039 | " reached. Keeping one slot for boot cpu." | |
2040 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2041 | ||
2042 | disabled_cpus++; | |
7e1f85f9 | 2043 | return -ENODEV; |
14cb6dcf | 2044 | } |
be8a5685 | 2045 | |
3b11ce7f | 2046 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2047 | int thiscpu = max + disabled_cpus; |
2048 | ||
2049 | pr_warning( | |
2050 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
2051 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2052 | ||
2053 | disabled_cpus++; | |
7e1f85f9 | 2054 | return -EINVAL; |
be8a5685 AS |
2055 | } |
2056 | ||
2057 | num_processors++; | |
be8a5685 AS |
2058 | if (apicid == boot_cpu_physical_apicid) { |
2059 | /* | |
2060 | * x86_bios_cpu_apicid is required to have processors listed | |
2061 | * in same order as logical cpu numbers. Hence the first | |
2062 | * entry is BSP, and so on. | |
e5fea868 YL |
2063 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2064 | * for BSP. | |
be8a5685 AS |
2065 | */ |
2066 | cpu = 0; | |
e5fea868 YL |
2067 | } else |
2068 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2069 | ||
2070 | /* | |
2071 | * Validate version | |
2072 | */ | |
2073 | if (version == 0x0) { | |
2074 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2075 | cpu, apicid); | |
2076 | version = 0x10; | |
be8a5685 | 2077 | } |
e5fea868 YL |
2078 | apic_version[apicid] = version; |
2079 | ||
2080 | if (version != apic_version[boot_cpu_physical_apicid]) { | |
2081 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", | |
2082 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
2083 | } | |
2084 | ||
2085 | physid_set(apicid, phys_cpu_present_map); | |
e0da3364 YL |
2086 | if (apicid > max_physical_apicid) |
2087 | max_physical_apicid = apicid; | |
2088 | ||
3e5095d1 | 2089 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2090 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2091 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2092 | #endif |
acb8bc09 TH |
2093 | #ifdef CONFIG_X86_32 |
2094 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2095 | apic->x86_32_early_logical_apicid(cpu); | |
2096 | #endif | |
1de88cd4 MT |
2097 | set_cpu_possible(cpu, true); |
2098 | set_cpu_present(cpu, true); | |
7e1f85f9 JL |
2099 | |
2100 | return cpu; | |
be8a5685 AS |
2101 | } |
2102 | ||
0c81c746 SS |
2103 | int hard_smp_processor_id(void) |
2104 | { | |
2105 | return read_apic_id(); | |
2106 | } | |
1dcdd3d1 IM |
2107 | |
2108 | void default_init_apic_ldr(void) | |
2109 | { | |
2110 | unsigned long val; | |
2111 | ||
2112 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2113 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2114 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2115 | apic_write(APIC_LDR, val); | |
2116 | } | |
2117 | ||
ff164324 AG |
2118 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
2119 | const struct cpumask *andmask, | |
2120 | unsigned int *apicid) | |
6398268d | 2121 | { |
ea3807ea | 2122 | unsigned int cpu; |
6398268d AG |
2123 | |
2124 | for_each_cpu_and(cpu, cpumask, andmask) { | |
2125 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
2126 | break; | |
2127 | } | |
ff164324 | 2128 | |
ea3807ea | 2129 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
2130 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
2131 | return 0; | |
a5a39156 | 2132 | } |
ea3807ea AG |
2133 | |
2134 | return -EINVAL; | |
6398268d AG |
2135 | } |
2136 | ||
1551df64 MT |
2137 | /* |
2138 | * Override the generic EOI implementation with an optimized version. | |
2139 | * Only called during early boot when only one CPU is active and with | |
2140 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2141 | * use. | |
2142 | */ | |
2143 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2144 | { | |
2145 | struct apic **drv; | |
2146 | ||
2147 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2148 | /* Should happen once for each apic */ | |
2149 | WARN_ON((*drv)->eoi_write == eoi_write); | |
2150 | (*drv)->eoi_write = eoi_write; | |
2151 | } | |
2152 | } | |
2153 | ||
374aab33 | 2154 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2155 | { |
374aab33 TG |
2156 | #ifdef CONFIG_X86_64 |
2157 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
2158 | #else | |
05f7e46d | 2159 | /* |
374aab33 TG |
2160 | * Hack: In case of kdump, after a crash, kernel might be booting |
2161 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
2162 | * might be zero if read from MP tables. Get it from LAPIC. | |
05f7e46d | 2163 | */ |
374aab33 TG |
2164 | # ifdef CONFIG_CRASH_DUMP |
2165 | boot_cpu_physical_apicid = read_apic_id(); | |
2166 | # endif | |
2167 | #endif | |
2168 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
05f7e46d TG |
2169 | } |
2170 | ||
2171 | /** | |
2172 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2173 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d TG |
2174 | * |
2175 | * Returns: | |
2176 | * apic_id of BSP APIC | |
2177 | */ | |
374aab33 | 2178 | int __init apic_bsp_setup(bool upmode) |
05f7e46d TG |
2179 | { |
2180 | int id; | |
2181 | ||
2182 | connect_bsp_APIC(); | |
374aab33 TG |
2183 | if (upmode) |
2184 | apic_bsp_up_setup(); | |
05f7e46d TG |
2185 | setup_local_APIC(); |
2186 | ||
2187 | if (x2apic_mode) | |
2188 | id = apic_read(APIC_LDR); | |
2189 | else | |
2190 | id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
2191 | ||
2192 | enable_IO_APIC(); | |
374aab33 TG |
2193 | end_local_APIC_setup(); |
2194 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2195 | setup_IO_APIC(); |
9c4d9c73 TG |
2196 | /* Setup local timer */ |
2197 | x86_init.timers.setup_percpu_clockev(); | |
05f7e46d TG |
2198 | return id; |
2199 | } | |
2200 | ||
e714a91f TG |
2201 | /* |
2202 | * This initializes the IO-APIC and APIC hardware if this is | |
2203 | * a UP kernel. | |
2204 | */ | |
2205 | int __init APIC_init_uniprocessor(void) | |
2206 | { | |
2207 | if (disable_apic) { | |
2208 | pr_info("Apic disabled\n"); | |
2209 | return -1; | |
2210 | } | |
2211 | #ifdef CONFIG_X86_64 | |
2212 | if (!cpu_has_apic) { | |
2213 | disable_apic = 1; | |
2214 | pr_info("Apic disabled by BIOS\n"); | |
2215 | return -1; | |
2216 | } | |
2217 | #else | |
2218 | if (!smp_found_config && !cpu_has_apic) | |
2219 | return -1; | |
2220 | ||
2221 | /* | |
2222 | * Complain if the BIOS pretends there is one. | |
2223 | */ | |
2224 | if (!cpu_has_apic && | |
2225 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
2226 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", | |
2227 | boot_cpu_physical_apicid); | |
2228 | return -1; | |
2229 | } | |
2230 | #endif | |
2231 | ||
374aab33 TG |
2232 | if (!smp_found_config) |
2233 | disable_ioapic_support(); | |
e714a91f | 2234 | |
374aab33 | 2235 | default_setup_apic_routing(); |
374aab33 | 2236 | apic_bsp_setup(true); |
e714a91f TG |
2237 | return 0; |
2238 | } | |
2239 | ||
30b8b006 TG |
2240 | #ifdef CONFIG_UP_LATE_INIT |
2241 | void __init up_late_init(void) | |
2242 | { | |
2243 | APIC_init_uniprocessor(); | |
2244 | } | |
2245 | #endif | |
2246 | ||
89039b37 | 2247 | /* |
0e078e2f | 2248 | * Power management |
89039b37 | 2249 | */ |
0e078e2f TG |
2250 | #ifdef CONFIG_PM |
2251 | ||
2252 | static struct { | |
274cfe59 CG |
2253 | /* |
2254 | * 'active' is true if the local APIC was enabled by us and | |
2255 | * not the BIOS; this signifies that we are also responsible | |
2256 | * for disabling it before entering apm/acpi suspend | |
2257 | */ | |
0e078e2f TG |
2258 | int active; |
2259 | /* r/w apic fields */ | |
2260 | unsigned int apic_id; | |
2261 | unsigned int apic_taskpri; | |
2262 | unsigned int apic_ldr; | |
2263 | unsigned int apic_dfr; | |
2264 | unsigned int apic_spiv; | |
2265 | unsigned int apic_lvtt; | |
2266 | unsigned int apic_lvtpc; | |
2267 | unsigned int apic_lvt0; | |
2268 | unsigned int apic_lvt1; | |
2269 | unsigned int apic_lvterr; | |
2270 | unsigned int apic_tmict; | |
2271 | unsigned int apic_tdcr; | |
2272 | unsigned int apic_thmr; | |
2273 | } apic_pm_state; | |
2274 | ||
f3c6ea1b | 2275 | static int lapic_suspend(void) |
0e078e2f TG |
2276 | { |
2277 | unsigned long flags; | |
2278 | int maxlvt; | |
89039b37 | 2279 | |
0e078e2f TG |
2280 | if (!apic_pm_state.active) |
2281 | return 0; | |
89039b37 | 2282 | |
0e078e2f | 2283 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2284 | |
2d7a66d0 | 2285 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2286 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2287 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2288 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2289 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2290 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2291 | if (maxlvt >= 4) | |
2292 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2293 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2294 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2295 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2296 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2297 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2298 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2299 | if (maxlvt >= 5) |
2300 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2301 | #endif | |
24968cfd | 2302 | |
0e078e2f TG |
2303 | local_irq_save(flags); |
2304 | disable_local_APIC(); | |
fc1edaf9 | 2305 | |
70733e0c | 2306 | irq_remapping_disable(); |
fc1edaf9 | 2307 | |
0e078e2f TG |
2308 | local_irq_restore(flags); |
2309 | return 0; | |
1da177e4 LT |
2310 | } |
2311 | ||
f3c6ea1b | 2312 | static void lapic_resume(void) |
1da177e4 | 2313 | { |
0e078e2f TG |
2314 | unsigned int l, h; |
2315 | unsigned long flags; | |
31dce14a | 2316 | int maxlvt; |
b24696bc | 2317 | |
0e078e2f | 2318 | if (!apic_pm_state.active) |
f3c6ea1b | 2319 | return; |
89b831ef | 2320 | |
0e078e2f | 2321 | local_irq_save(flags); |
336224ba JR |
2322 | |
2323 | /* | |
2324 | * IO-APIC and PIC have their own resume routines. | |
2325 | * We just mask them here to make sure the interrupt | |
2326 | * subsystem is completely quiet while we enable x2apic | |
2327 | * and interrupt-remapping. | |
2328 | */ | |
2329 | mask_ioapic_entries(); | |
2330 | legacy_pic->mask_all(); | |
92206c90 | 2331 | |
659006bf TG |
2332 | if (x2apic_mode) { |
2333 | __x2apic_enable(); | |
2334 | } else { | |
92206c90 CG |
2335 | /* |
2336 | * Make sure the APICBASE points to the right address | |
2337 | * | |
2338 | * FIXME! This will be wrong if we ever support suspend on | |
2339 | * SMP! We'll need to do this as part of the CPU restore! | |
2340 | */ | |
cbf2829b BD |
2341 | if (boot_cpu_data.x86 >= 6) { |
2342 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2343 | l &= ~MSR_IA32_APICBASE_BASE; | |
2344 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2345 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2346 | } | |
d5e629a6 | 2347 | } |
6e1cb38a | 2348 | |
b24696bc | 2349 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2350 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2351 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2352 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2353 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2354 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2355 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2356 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2357 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
71c69f7f | 2358 | #if defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2359 | if (maxlvt >= 5) |
2360 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2361 | #endif | |
2362 | if (maxlvt >= 4) | |
2363 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2364 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2365 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2366 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2367 | apic_write(APIC_ESR, 0); | |
2368 | apic_read(APIC_ESR); | |
2369 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2370 | apic_write(APIC_ESR, 0); | |
2371 | apic_read(APIC_ESR); | |
92206c90 | 2372 | |
70733e0c | 2373 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2374 | |
0e078e2f | 2375 | local_irq_restore(flags); |
0e078e2f | 2376 | } |
b8ce3359 | 2377 | |
274cfe59 CG |
2378 | /* |
2379 | * This device has no shutdown method - fully functioning local APICs | |
2380 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2381 | */ | |
2382 | ||
f3c6ea1b | 2383 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2384 | .resume = lapic_resume, |
2385 | .suspend = lapic_suspend, | |
2386 | }; | |
b8ce3359 | 2387 | |
148f9bb8 | 2388 | static void apic_pm_activate(void) |
0e078e2f TG |
2389 | { |
2390 | apic_pm_state.active = 1; | |
1da177e4 LT |
2391 | } |
2392 | ||
0e078e2f | 2393 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2394 | { |
0e078e2f | 2395 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
f3c6ea1b RW |
2396 | if (cpu_has_apic) |
2397 | register_syscore_ops(&lapic_syscore_ops); | |
e83a5fdc | 2398 | |
f3c6ea1b | 2399 | return 0; |
1da177e4 | 2400 | } |
b24696bc FY |
2401 | |
2402 | /* local apic needs to resume before other devices access its registers. */ | |
2403 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2404 | |
2405 | #else /* CONFIG_PM */ | |
2406 | ||
2407 | static void apic_pm_activate(void) { } | |
2408 | ||
2409 | #endif /* CONFIG_PM */ | |
1da177e4 | 2410 | |
f28c0ae2 | 2411 | #ifdef CONFIG_X86_64 |
e0e42142 | 2412 | |
148f9bb8 PG |
2413 | static int multi_checked; |
2414 | static int multi; | |
e0e42142 | 2415 | |
148f9bb8 | 2416 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2417 | { |
2418 | if (multi) | |
2419 | return 0; | |
6f0aced6 | 2420 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2421 | multi = 1; |
2422 | return 0; | |
2423 | } | |
2424 | ||
148f9bb8 | 2425 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2426 | { |
2427 | .callback = set_multi, | |
2428 | .ident = "IBM System Summit2", | |
2429 | .matches = { | |
2430 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2431 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2432 | }, | |
2433 | }, | |
2434 | {} | |
2435 | }; | |
2436 | ||
148f9bb8 | 2437 | static void dmi_check_multi(void) |
e0e42142 YL |
2438 | { |
2439 | if (multi_checked) | |
2440 | return; | |
2441 | ||
2442 | dmi_check_system(multi_dmi_table); | |
2443 | multi_checked = 1; | |
2444 | } | |
2445 | ||
2446 | /* | |
2447 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2448 | * | |
2449 | * Thus far, the major user of this is IBM's Summit2 series: | |
2450 | * Clustered boxes may have unsynced TSC problems if they are | |
2451 | * multi-chassis. | |
2452 | * Use DMI to check them | |
2453 | */ | |
148f9bb8 | 2454 | int apic_is_clustered_box(void) |
e0e42142 YL |
2455 | { |
2456 | dmi_check_multi(); | |
411cf9ee | 2457 | return multi; |
1da177e4 | 2458 | } |
f28c0ae2 | 2459 | #endif |
1da177e4 LT |
2460 | |
2461 | /* | |
0e078e2f | 2462 | * APIC command line parameters |
1da177e4 | 2463 | */ |
789fa735 | 2464 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2465 | { |
1da177e4 | 2466 | disable_apic = 1; |
9175fc06 | 2467 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2468 | return 0; |
2469 | } | |
2470 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2471 | |
2c8c0e6b | 2472 | /* same as disableapic, for compatibility */ |
789fa735 | 2473 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2474 | { |
789fa735 | 2475 | return setup_disableapic(arg); |
6935d1f9 | 2476 | } |
2c8c0e6b | 2477 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2478 | |
2e7c2838 LT |
2479 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2480 | { | |
2481 | local_apic_timer_c2_ok = 1; | |
2482 | return 0; | |
2483 | } | |
2484 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2485 | ||
36fef094 | 2486 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2487 | { |
1da177e4 | 2488 | disable_apic_timer = 1; |
36fef094 | 2489 | return 0; |
6935d1f9 | 2490 | } |
36fef094 CG |
2491 | early_param("noapictimer", parse_disable_apic_timer); |
2492 | ||
2493 | static int __init parse_nolapic_timer(char *arg) | |
2494 | { | |
2495 | disable_apic_timer = 1; | |
2496 | return 0; | |
6935d1f9 | 2497 | } |
36fef094 | 2498 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2499 | |
79af9bec CG |
2500 | static int __init apic_set_verbosity(char *arg) |
2501 | { | |
2502 | if (!arg) { | |
2503 | #ifdef CONFIG_X86_64 | |
2504 | skip_ioapic_setup = 0; | |
79af9bec CG |
2505 | return 0; |
2506 | #endif | |
2507 | return -EINVAL; | |
2508 | } | |
2509 | ||
2510 | if (strcmp("debug", arg) == 0) | |
2511 | apic_verbosity = APIC_DEBUG; | |
2512 | else if (strcmp("verbose", arg) == 0) | |
2513 | apic_verbosity = APIC_VERBOSE; | |
2514 | else { | |
ba21ebb6 | 2515 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2516 | " use apic=verbose or apic=debug\n", arg); |
2517 | return -EINVAL; | |
2518 | } | |
2519 | ||
2520 | return 0; | |
2521 | } | |
2522 | early_param("apic", apic_set_verbosity); | |
2523 | ||
1e934dda YL |
2524 | static int __init lapic_insert_resource(void) |
2525 | { | |
2526 | if (!apic_phys) | |
2527 | return -1; | |
2528 | ||
2529 | /* Put local APIC into the resource map. */ | |
2530 | lapic_resource.start = apic_phys; | |
2531 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2532 | insert_resource(&iomem_resource, &lapic_resource); | |
2533 | ||
2534 | return 0; | |
2535 | } | |
2536 | ||
2537 | /* | |
2538 | * need call insert after e820_reserve_resources() | |
2539 | * that is using request_resource | |
2540 | */ | |
2541 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2542 | |
2543 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2544 | { | |
2545 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2546 | return -EINVAL; | |
2547 | ||
2548 | return 0; | |
2549 | } | |
2550 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); |