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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
e83a5fdc | 26 | #include <linux/module.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
cdd6c482 | 38 | #include <asm/perf_event.h> |
736decac | 39 | #include <asm/x86_init.h> |
1da177e4 | 40 | #include <asm/pgalloc.h> |
60063497 | 41 | #include <linux/atomic.h> |
1da177e4 | 42 | #include <asm/mpspec.h> |
d1de36f5 | 43 | #include <asm/i8259.h> |
73dea47f | 44 | #include <asm/proto.h> |
2c8c0e6b | 45 | #include <asm/apic.h> |
7167d08e | 46 | #include <asm/io_apic.h> |
d1de36f5 IM |
47 | #include <asm/desc.h> |
48 | #include <asm/hpet.h> | |
49 | #include <asm/idle.h> | |
50 | #include <asm/mtrr.h> | |
16f871bc | 51 | #include <asm/time.h> |
2bc13797 | 52 | #include <asm/smp.h> |
be71b855 | 53 | #include <asm/mce.h> |
8c3ba8d0 | 54 | #include <asm/tsc.h> |
2904ed8d | 55 | #include <asm/hypervisor.h> |
1da177e4 | 56 | |
ec70de8b | 57 | unsigned int num_processors; |
fdbecd9f | 58 | |
ec70de8b | 59 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 60 | |
ec70de8b BG |
61 | /* Processor that is doing the boot up */ |
62 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 63 | |
80e5609c | 64 | /* |
fdbecd9f | 65 | * The highest APIC ID seen during enumeration. |
80e5609c | 66 | */ |
ec70de8b | 67 | unsigned int max_physical_apicid; |
5af5573e | 68 | |
80e5609c | 69 | /* |
fdbecd9f | 70 | * Bitmask of physically existing CPUs: |
80e5609c | 71 | */ |
ec70de8b BG |
72 | physid_mask_t phys_cpu_present_map; |
73 | ||
74 | /* | |
75 | * Map cpu index to physical APIC ID | |
76 | */ | |
77 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
78 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
79 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 81 | |
b3c51170 | 82 | #ifdef CONFIG_X86_32 |
4c321ff8 | 83 | |
4c321ff8 TH |
84 | /* |
85 | * On x86_32, the mapping between cpu and logical apicid may vary | |
86 | * depending on apic in use. The following early percpu variable is | |
87 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
88 | * actually diverge. Let's keep it ugly for now. | |
89 | */ | |
90 | DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); | |
4c321ff8 | 91 | |
b3c51170 YL |
92 | /* |
93 | * Knob to control our willingness to enable the local APIC. | |
94 | * | |
95 | * +1=force-enable | |
96 | */ | |
25874a29 | 97 | static int force_enable_local_apic __initdata; |
b3c51170 YL |
98 | /* |
99 | * APIC command line parameters | |
100 | */ | |
101 | static int __init parse_lapic(char *arg) | |
102 | { | |
103 | force_enable_local_apic = 1; | |
104 | return 0; | |
105 | } | |
106 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
107 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
108 | static int enabled_via_apicbase; | |
109 | ||
c0eaa453 CG |
110 | /* |
111 | * Handle interrupt mode configuration register (IMCR). | |
112 | * This register controls whether the interrupt signals | |
113 | * that reach the BSP come from the master PIC or from the | |
114 | * local APIC. Before entering Symmetric I/O Mode, either | |
115 | * the BIOS or the operating system must switch out of | |
116 | * PIC Mode by changing the IMCR. | |
117 | */ | |
5cda395f | 118 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
119 | { |
120 | /* select IMCR register */ | |
121 | outb(0x70, 0x22); | |
122 | /* NMI and 8259 INTR go through APIC */ | |
123 | outb(0x01, 0x23); | |
124 | } | |
125 | ||
5cda395f | 126 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
127 | { |
128 | /* select IMCR register */ | |
129 | outb(0x70, 0x22); | |
130 | /* NMI and 8259 INTR go directly to BSP */ | |
131 | outb(0x00, 0x23); | |
132 | } | |
b3c51170 YL |
133 | #endif |
134 | ||
135 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 136 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
137 | static __init int setup_apicpmtimer(char *s) |
138 | { | |
139 | apic_calibrate_pmtmr = 1; | |
140 | notsc_setup(NULL); | |
141 | return 0; | |
142 | } | |
143 | __setup("apicpmtimer", setup_apicpmtimer); | |
144 | #endif | |
145 | ||
fc1edaf9 | 146 | int x2apic_mode; |
06cd9a7d | 147 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a | 148 | /* x2apic enabled before OS handover */ |
fb209bd8 YL |
149 | int x2apic_preenabled; |
150 | static int x2apic_disabled; | |
49899eac YL |
151 | static __init int setup_nox2apic(char *str) |
152 | { | |
39d83a5d SS |
153 | if (x2apic_enabled()) { |
154 | pr_warning("Bios already enabled x2apic, " | |
155 | "can't enforce nox2apic"); | |
156 | return 0; | |
157 | } | |
158 | ||
49899eac YL |
159 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
160 | return 0; | |
161 | } | |
162 | early_param("nox2apic", setup_nox2apic); | |
163 | #endif | |
1da177e4 | 164 | |
b3c51170 YL |
165 | unsigned long mp_lapic_addr; |
166 | int disable_apic; | |
167 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 168 | static int disable_apic_timer __initdata; |
e83a5fdc | 169 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
170 | int local_apic_timer_c2_ok; |
171 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
172 | ||
efa2559f YL |
173 | int first_system_vector = 0xfe; |
174 | ||
e83a5fdc HS |
175 | /* |
176 | * Debug level, exported for io_apic.c | |
177 | */ | |
baa13188 | 178 | unsigned int apic_verbosity; |
e83a5fdc | 179 | |
89c38c28 CG |
180 | int pic_mode; |
181 | ||
bab4b27c AS |
182 | /* Have we found an MP table */ |
183 | int smp_found_config; | |
184 | ||
39928722 AD |
185 | static struct resource lapic_resource = { |
186 | .name = "Local APIC", | |
187 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
188 | }; | |
189 | ||
1ade93ef | 190 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 191 | |
0e078e2f | 192 | static void apic_pm_activate(void); |
ba7eda4c | 193 | |
d3432896 AK |
194 | static unsigned long apic_phys; |
195 | ||
0e078e2f TG |
196 | /* |
197 | * Get the LAPIC version | |
198 | */ | |
199 | static inline int lapic_get_version(void) | |
ba7eda4c | 200 | { |
0e078e2f | 201 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
202 | } |
203 | ||
0e078e2f | 204 | /* |
9c803869 | 205 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
206 | */ |
207 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 208 | { |
9c803869 | 209 | #ifdef CONFIG_X86_64 |
0e078e2f | 210 | return 1; |
9c803869 CG |
211 | #else |
212 | return APIC_INTEGRATED(lapic_get_version()); | |
213 | #endif | |
ba7eda4c TG |
214 | } |
215 | ||
216 | /* | |
0e078e2f | 217 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 218 | */ |
0e078e2f | 219 | static int modern_apic(void) |
ba7eda4c | 220 | { |
0e078e2f TG |
221 | /* AMD systems use old APIC versions, so check the CPU */ |
222 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
223 | boot_cpu_data.x86 >= 0xf) | |
224 | return 1; | |
225 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
226 | } |
227 | ||
08306ce6 | 228 | /* |
a933c618 CG |
229 | * right after this call apic become NOOP driven |
230 | * so apic->write/read doesn't do anything | |
08306ce6 | 231 | */ |
25874a29 | 232 | static void __init apic_disable(void) |
08306ce6 | 233 | { |
f88f2b4f | 234 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 235 | apic = &apic_noop; |
08306ce6 CG |
236 | } |
237 | ||
c1eeb2de | 238 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
239 | { |
240 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
241 | cpu_relax(); | |
242 | } | |
243 | ||
c1eeb2de | 244 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 245 | { |
3c6bb07a | 246 | u32 send_status; |
8339e9fb FLV |
247 | int timeout; |
248 | ||
249 | timeout = 0; | |
250 | do { | |
251 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
252 | if (!send_status) | |
253 | break; | |
b49d7d87 | 254 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
255 | udelay(100); |
256 | } while (timeout++ < 1000); | |
257 | ||
258 | return send_status; | |
259 | } | |
260 | ||
c1eeb2de | 261 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 262 | { |
ed4e5ec1 | 263 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
264 | apic_write(APIC_ICR, low); |
265 | } | |
266 | ||
c1eeb2de | 267 | u64 native_apic_icr_read(void) |
1b374e4d SS |
268 | { |
269 | u32 icr1, icr2; | |
270 | ||
271 | icr2 = apic_read(APIC_ICR2); | |
272 | icr1 = apic_read(APIC_ICR); | |
273 | ||
cf9768d7 | 274 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
275 | } |
276 | ||
7c37e48b CG |
277 | #ifdef CONFIG_X86_32 |
278 | /** | |
279 | * get_physical_broadcast - Get number of physical broadcast IDs | |
280 | */ | |
281 | int get_physical_broadcast(void) | |
282 | { | |
283 | return modern_apic() ? 0xff : 0xf; | |
284 | } | |
285 | #endif | |
286 | ||
0e078e2f TG |
287 | /** |
288 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
289 | */ | |
37e650c7 | 290 | int lapic_get_maxlvt(void) |
1da177e4 | 291 | { |
36a028de | 292 | unsigned int v; |
1da177e4 LT |
293 | |
294 | v = apic_read(APIC_LVR); | |
36a028de CG |
295 | /* |
296 | * - we always have APIC integrated on 64bit mode | |
297 | * - 82489DXs do not report # of LVT entries | |
298 | */ | |
299 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
300 | } |
301 | ||
274cfe59 CG |
302 | /* |
303 | * Local APIC timer | |
304 | */ | |
305 | ||
c40aaec6 | 306 | /* Clock divisor */ |
c40aaec6 | 307 | #define APIC_DIVISOR 16 |
f07f4f90 | 308 | |
0e078e2f TG |
309 | /* |
310 | * This function sets up the local APIC timer, with a timeout of | |
311 | * 'clocks' APIC bus clock. During calibration we actually call | |
312 | * this function twice on the boot CPU, once with a bogus timeout | |
313 | * value, second time for real. The other (noncalibrating) CPUs | |
314 | * call this function only once, with the real, calibrated value. | |
315 | * | |
316 | * We do reads before writes even if unnecessary, to get around the | |
317 | * P5 APIC double write bug. | |
318 | */ | |
0e078e2f | 319 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 320 | { |
0e078e2f | 321 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 322 | |
0e078e2f TG |
323 | lvtt_value = LOCAL_TIMER_VECTOR; |
324 | if (!oneshot) | |
325 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
326 | if (!lapic_is_integrated()) |
327 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
328 | ||
0e078e2f TG |
329 | if (!irqen) |
330 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 331 | |
0e078e2f | 332 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
333 | |
334 | /* | |
0e078e2f | 335 | * Divide PICLK by 16 |
1da177e4 | 336 | */ |
0e078e2f | 337 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
338 | apic_write(APIC_TDCR, |
339 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
340 | APIC_TDR_DIV_16); | |
0e078e2f TG |
341 | |
342 | if (!oneshot) | |
f07f4f90 | 343 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
344 | } |
345 | ||
0e078e2f | 346 | /* |
a68c439b | 347 | * Setup extended LVT, AMD specific |
7b83dae7 | 348 | * |
a68c439b RR |
349 | * Software should use the LVT offsets the BIOS provides. The offsets |
350 | * are determined by the subsystems using it like those for MCE | |
351 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
352 | * are supported. Beginning with family 10h at least 4 offsets are | |
353 | * available. | |
286f5718 | 354 | * |
a68c439b RR |
355 | * Since the offsets must be consistent for all cores, we keep track |
356 | * of the LVT offsets in software and reserve the offset for the same | |
357 | * vector also to be used on other cores. An offset is freed by | |
358 | * setting the entry to APIC_EILVT_MASKED. | |
359 | * | |
360 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
361 | * "[Firmware Bug]: ..." error message is generated. However, if | |
362 | * software does not properly determines the offsets, it is not | |
363 | * necessarily a BIOS bug. | |
0e078e2f | 364 | */ |
7b83dae7 | 365 | |
a68c439b RR |
366 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
367 | ||
368 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
369 | { | |
370 | return (old & APIC_EILVT_MASKED) | |
371 | || (new == APIC_EILVT_MASKED) | |
372 | || ((new & ~APIC_EILVT_MASKED) == old); | |
373 | } | |
374 | ||
375 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
376 | { | |
377 | unsigned int rsvd; /* 0: uninitialized */ | |
378 | ||
379 | if (offset >= APIC_EILVT_NR_MAX) | |
380 | return ~0; | |
381 | ||
382 | rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; | |
383 | do { | |
384 | if (rsvd && | |
385 | !eilvt_entry_is_changeable(rsvd, new)) | |
386 | /* may not change if vectors are different */ | |
387 | return rsvd; | |
388 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
389 | } while (rsvd != new); | |
390 | ||
391 | return new; | |
392 | } | |
393 | ||
394 | /* | |
395 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
396 | * enables the vector. See also the BKDGs. Must be called with |
397 | * preemption disabled. | |
a68c439b RR |
398 | */ |
399 | ||
27afdf20 | 400 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 401 | { |
a68c439b RR |
402 | unsigned long reg = APIC_EILVTn(offset); |
403 | unsigned int new, old, reserved; | |
404 | ||
405 | new = (mask << 16) | (msg_type << 8) | vector; | |
406 | old = apic_read(reg); | |
407 | reserved = reserve_eilvt_offset(offset, new); | |
408 | ||
409 | if (reserved != new) { | |
eb48c9cb RR |
410 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
411 | "vector 0x%x, but the register is already in use for " | |
412 | "vector 0x%x on another cpu\n", | |
413 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
414 | return -EINVAL; |
415 | } | |
416 | ||
417 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
418 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
419 | "vector 0x%x, but the register is already in use for " | |
420 | "vector 0x%x on this cpu\n", | |
421 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
422 | return -EBUSY; |
423 | } | |
424 | ||
425 | apic_write(reg, new); | |
a8fcf1a2 | 426 | |
a68c439b | 427 | return 0; |
1da177e4 | 428 | } |
27afdf20 | 429 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 430 | |
0e078e2f TG |
431 | /* |
432 | * Program the next event, relative to now | |
433 | */ | |
434 | static int lapic_next_event(unsigned long delta, | |
435 | struct clock_event_device *evt) | |
1da177e4 | 436 | { |
0e078e2f TG |
437 | apic_write(APIC_TMICT, delta); |
438 | return 0; | |
1da177e4 LT |
439 | } |
440 | ||
0e078e2f TG |
441 | /* |
442 | * Setup the lapic timer in periodic or oneshot mode | |
443 | */ | |
444 | static void lapic_timer_setup(enum clock_event_mode mode, | |
445 | struct clock_event_device *evt) | |
9b7711f0 HS |
446 | { |
447 | unsigned long flags; | |
0e078e2f | 448 | unsigned int v; |
9b7711f0 | 449 | |
0e078e2f TG |
450 | /* Lapic used as dummy for broadcast ? */ |
451 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
452 | return; |
453 | ||
454 | local_irq_save(flags); | |
455 | ||
0e078e2f TG |
456 | switch (mode) { |
457 | case CLOCK_EVT_MODE_PERIODIC: | |
458 | case CLOCK_EVT_MODE_ONESHOT: | |
1ade93ef | 459 | __setup_APIC_LVTT(lapic_timer_frequency, |
0e078e2f TG |
460 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
461 | break; | |
462 | case CLOCK_EVT_MODE_UNUSED: | |
463 | case CLOCK_EVT_MODE_SHUTDOWN: | |
464 | v = apic_read(APIC_LVTT); | |
465 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
466 | apic_write(APIC_LVTT, v); | |
6f9b4100 | 467 | apic_write(APIC_TMICT, 0); |
0e078e2f TG |
468 | break; |
469 | case CLOCK_EVT_MODE_RESUME: | |
470 | /* Nothing to do here */ | |
471 | break; | |
472 | } | |
9b7711f0 HS |
473 | |
474 | local_irq_restore(flags); | |
475 | } | |
476 | ||
1da177e4 | 477 | /* |
0e078e2f | 478 | * Local APIC timer broadcast function |
1da177e4 | 479 | */ |
9628937d | 480 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 481 | { |
0e078e2f | 482 | #ifdef CONFIG_SMP |
dac5f412 | 483 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
484 | #endif |
485 | } | |
1da177e4 | 486 | |
25874a29 HK |
487 | |
488 | /* | |
489 | * The local apic timer can be used for any function which is CPU local. | |
490 | */ | |
491 | static struct clock_event_device lapic_clockevent = { | |
492 | .name = "lapic", | |
493 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
494 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
495 | .shift = 32, | |
496 | .set_mode = lapic_timer_setup, | |
497 | .set_next_event = lapic_next_event, | |
498 | .broadcast = lapic_timer_broadcast, | |
499 | .rating = 100, | |
500 | .irq = -1, | |
501 | }; | |
502 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
503 | ||
0e078e2f | 504 | /* |
421f91d2 | 505 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
506 | * of the boot CPU and register the clock event in the framework. |
507 | */ | |
db4b5525 | 508 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
509 | { |
510 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 511 | |
349c004e | 512 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
513 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
514 | /* Make LAPIC timer preferrable over percpu HPET */ | |
515 | lapic_clockevent.rating = 150; | |
516 | } | |
517 | ||
0e078e2f | 518 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 519 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 520 | |
0e078e2f TG |
521 | clockevents_register_device(levt); |
522 | } | |
1da177e4 | 523 | |
2f04fa88 YL |
524 | /* |
525 | * In this functions we calibrate APIC bus clocks to the external timer. | |
526 | * | |
527 | * We want to do the calibration only once since we want to have local timer | |
528 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
529 | * frequency. | |
530 | * | |
531 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
532 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
533 | * readout is broken, so it never gets out of the wait loop again. This was | |
534 | * also reported by others. | |
535 | * | |
536 | * Monitoring the jiffies value is inaccurate and the clockevents | |
537 | * infrastructure allows us to do a simple substitution of the interrupt | |
538 | * handler. | |
539 | * | |
540 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
541 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
542 | * back to normal later in the boot process). | |
543 | */ | |
544 | ||
545 | #define LAPIC_CAL_LOOPS (HZ/10) | |
546 | ||
547 | static __initdata int lapic_cal_loops = -1; | |
548 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
549 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
550 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
551 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
552 | ||
553 | /* | |
554 | * Temporary interrupt handler. | |
555 | */ | |
556 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
557 | { | |
558 | unsigned long long tsc = 0; | |
559 | long tapic = apic_read(APIC_TMCCT); | |
560 | unsigned long pm = acpi_pm_read_early(); | |
561 | ||
562 | if (cpu_has_tsc) | |
563 | rdtscll(tsc); | |
564 | ||
565 | switch (lapic_cal_loops++) { | |
566 | case 0: | |
567 | lapic_cal_t1 = tapic; | |
568 | lapic_cal_tsc1 = tsc; | |
569 | lapic_cal_pm1 = pm; | |
570 | lapic_cal_j1 = jiffies; | |
571 | break; | |
572 | ||
573 | case LAPIC_CAL_LOOPS: | |
574 | lapic_cal_t2 = tapic; | |
575 | lapic_cal_tsc2 = tsc; | |
576 | if (pm < lapic_cal_pm1) | |
577 | pm += ACPI_PM_OVRRUN; | |
578 | lapic_cal_pm2 = pm; | |
579 | lapic_cal_j2 = jiffies; | |
580 | break; | |
581 | } | |
582 | } | |
583 | ||
754ef0cd YI |
584 | static int __init |
585 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
586 | { |
587 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
588 | const long pm_thresh = pm_100ms / 100; | |
589 | unsigned long mult; | |
590 | u64 res; | |
591 | ||
592 | #ifndef CONFIG_X86_PM_TIMER | |
593 | return -1; | |
594 | #endif | |
595 | ||
39ba5d43 | 596 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
597 | |
598 | /* Check, if the PM timer is available */ | |
599 | if (!deltapm) | |
600 | return -1; | |
601 | ||
602 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
603 | ||
604 | if (deltapm > (pm_100ms - pm_thresh) && | |
605 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 606 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
607 | return 0; |
608 | } | |
609 | ||
610 | res = (((u64)deltapm) * mult) >> 22; | |
611 | do_div(res, 1000000); | |
612 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 613 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
614 | |
615 | /* Correct the lapic counter value */ | |
616 | res = (((u64)(*delta)) * pm_100ms); | |
617 | do_div(res, deltapm); | |
618 | pr_info("APIC delta adjusted to PM-Timer: " | |
619 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
620 | *delta = (long)res; | |
621 | ||
622 | /* Correct the tsc counter value */ | |
623 | if (cpu_has_tsc) { | |
624 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 625 | do_div(res, deltapm); |
754ef0cd | 626 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 627 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
628 | (unsigned long)res, *deltatsc); |
629 | *deltatsc = (long)res; | |
b189892d CG |
630 | } |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
2f04fa88 YL |
635 | static int __init calibrate_APIC_clock(void) |
636 | { | |
637 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
638 | void (*real_handler)(struct clock_event_device *dev); |
639 | unsigned long deltaj; | |
754ef0cd | 640 | long delta, deltatsc; |
2f04fa88 YL |
641 | int pm_referenced = 0; |
642 | ||
1ade93ef JP |
643 | /** |
644 | * check if lapic timer has already been calibrated by platform | |
645 | * specific routine, such as tsc calibration code. if so, we just fill | |
646 | * in the clockevent structure and return. | |
647 | */ | |
648 | ||
649 | if (lapic_timer_frequency) { | |
650 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", | |
651 | lapic_timer_frequency); | |
652 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
653 | TICK_NSEC, lapic_clockevent.shift); | |
654 | lapic_clockevent.max_delta_ns = | |
655 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
656 | lapic_clockevent.min_delta_ns = | |
657 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
658 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
659 | return 0; | |
660 | } | |
661 | ||
2f04fa88 YL |
662 | local_irq_disable(); |
663 | ||
664 | /* Replace the global interrupt handler */ | |
665 | real_handler = global_clock_event->event_handler; | |
666 | global_clock_event->event_handler = lapic_cal_handler; | |
667 | ||
668 | /* | |
81608f3c | 669 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
670 | * can underflow in the 100ms detection time frame |
671 | */ | |
81608f3c | 672 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
673 | |
674 | /* Let the interrupts run */ | |
675 | local_irq_enable(); | |
676 | ||
677 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
678 | cpu_relax(); | |
679 | ||
680 | local_irq_disable(); | |
681 | ||
682 | /* Restore the real event handler */ | |
683 | global_clock_event->event_handler = real_handler; | |
684 | ||
685 | /* Build delta t1-t2 as apic timer counts down */ | |
686 | delta = lapic_cal_t1 - lapic_cal_t2; | |
687 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
688 | ||
754ef0cd YI |
689 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
690 | ||
b189892d CG |
691 | /* we trust the PM based calibration if possible */ |
692 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 693 | &delta, &deltatsc); |
2f04fa88 YL |
694 | |
695 | /* Calculate the scaled math multiplication factor */ | |
696 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
697 | lapic_clockevent.shift); | |
698 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 699 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
700 | lapic_clockevent.min_delta_ns = |
701 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
702 | ||
1ade93ef | 703 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
704 | |
705 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 706 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 707 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 708 | lapic_timer_frequency); |
2f04fa88 YL |
709 | |
710 | if (cpu_has_tsc) { | |
2f04fa88 YL |
711 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
712 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
713 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
714 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
715 | } |
716 | ||
717 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
718 | "%u.%04u MHz.\n", | |
1ade93ef JP |
719 | lapic_timer_frequency / (1000000 / HZ), |
720 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
721 | |
722 | /* | |
723 | * Do a sanity check on the APIC calibration result | |
724 | */ | |
1ade93ef | 725 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 726 | local_irq_enable(); |
ba21ebb6 | 727 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
728 | return -1; |
729 | } | |
730 | ||
731 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
732 | ||
b189892d CG |
733 | /* |
734 | * PM timer calibration failed or not turned on | |
735 | * so lets try APIC timer based calibration | |
736 | */ | |
2f04fa88 YL |
737 | if (!pm_referenced) { |
738 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
739 | ||
740 | /* | |
741 | * Setup the apic timer manually | |
742 | */ | |
743 | levt->event_handler = lapic_cal_handler; | |
744 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
745 | lapic_cal_loops = -1; | |
746 | ||
747 | /* Let the interrupts run */ | |
748 | local_irq_enable(); | |
749 | ||
750 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
751 | cpu_relax(); | |
752 | ||
2f04fa88 YL |
753 | /* Stop the lapic timer */ |
754 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
755 | ||
2f04fa88 YL |
756 | /* Jiffies delta */ |
757 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
758 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
759 | ||
760 | /* Check, if the jiffies result is consistent */ | |
761 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
762 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
763 | else | |
764 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
765 | } else | |
766 | local_irq_enable(); | |
767 | ||
768 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 769 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
770 | return -1; |
771 | } | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
e83a5fdc HS |
776 | /* |
777 | * Setup the boot APIC | |
778 | * | |
779 | * Calibrate and verify the result. | |
780 | */ | |
0e078e2f TG |
781 | void __init setup_boot_APIC_clock(void) |
782 | { | |
783 | /* | |
274cfe59 CG |
784 | * The local apic timer can be disabled via the kernel |
785 | * commandline or from the CPU detection code. Register the lapic | |
786 | * timer as a dummy clock event source on SMP systems, so the | |
787 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
788 | */ |
789 | if (disable_apic_timer) { | |
ba21ebb6 | 790 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 791 | /* No broadcast on UP ! */ |
9d09951d TG |
792 | if (num_possible_cpus() > 1) { |
793 | lapic_clockevent.mult = 1; | |
0e078e2f | 794 | setup_APIC_timer(); |
9d09951d | 795 | } |
0e078e2f TG |
796 | return; |
797 | } | |
798 | ||
274cfe59 CG |
799 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
800 | "calibrating APIC timer ...\n"); | |
801 | ||
89b3b1f4 | 802 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
803 | /* No broadcast on UP ! */ |
804 | if (num_possible_cpus() > 1) | |
805 | setup_APIC_timer(); | |
806 | return; | |
807 | } | |
808 | ||
0e078e2f TG |
809 | /* |
810 | * If nmi_watchdog is set to IO_APIC, we need the | |
811 | * PIT/HPET going. Otherwise register lapic as a dummy | |
812 | * device. | |
813 | */ | |
072b198a | 814 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 815 | |
274cfe59 | 816 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
817 | setup_APIC_timer(); |
818 | } | |
819 | ||
0e078e2f TG |
820 | void __cpuinit setup_secondary_APIC_clock(void) |
821 | { | |
0e078e2f TG |
822 | setup_APIC_timer(); |
823 | } | |
824 | ||
825 | /* | |
826 | * The guts of the apic timer interrupt | |
827 | */ | |
828 | static void local_apic_timer_interrupt(void) | |
829 | { | |
830 | int cpu = smp_processor_id(); | |
831 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
832 | ||
833 | /* | |
834 | * Normally we should not be here till LAPIC has been initialized but | |
835 | * in some cases like kdump, its possible that there is a pending LAPIC | |
836 | * timer interrupt from previous kernel's context and is delivered in | |
837 | * new kernel the moment interrupts are enabled. | |
838 | * | |
839 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
840 | * its possible that when we get here evt->event_handler is NULL. | |
841 | * Check for event_handler being NULL and discard the interrupt as | |
842 | * spurious. | |
843 | */ | |
844 | if (!evt->event_handler) { | |
ba21ebb6 | 845 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
846 | /* Switch it off */ |
847 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
848 | return; | |
849 | } | |
850 | ||
851 | /* | |
852 | * the NMI deadlock-detector uses this. | |
853 | */ | |
915b0d01 | 854 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
855 | |
856 | evt->event_handler(evt); | |
857 | } | |
858 | ||
859 | /* | |
860 | * Local APIC timer interrupt. This is the most natural way for doing | |
861 | * local interrupts, but local timer interrupts can be emulated by | |
862 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
863 | * | |
864 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
865 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
866 | */ | |
bcbc4f20 | 867 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
868 | { |
869 | struct pt_regs *old_regs = set_irq_regs(regs); | |
870 | ||
871 | /* | |
872 | * NOTE! We'd better ACK the irq immediately, | |
873 | * because timer handling can be slow. | |
874 | */ | |
875 | ack_APIC_irq(); | |
876 | /* | |
877 | * update_process_times() expects us to have done irq_enter(). | |
878 | * Besides, if we don't timer interrupts ignore the global | |
879 | * interrupt lock, which is the WrongThing (tm) to do. | |
880 | */ | |
881 | exit_idle(); | |
882 | irq_enter(); | |
883 | local_apic_timer_interrupt(); | |
884 | irq_exit(); | |
274cfe59 | 885 | |
0e078e2f TG |
886 | set_irq_regs(old_regs); |
887 | } | |
888 | ||
889 | int setup_profiling_timer(unsigned int multiplier) | |
890 | { | |
891 | return -EINVAL; | |
892 | } | |
893 | ||
0e078e2f TG |
894 | /* |
895 | * Local APIC start and shutdown | |
896 | */ | |
897 | ||
898 | /** | |
899 | * clear_local_APIC - shutdown the local APIC | |
900 | * | |
901 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
902 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
903 | * leftovers during boot. | |
904 | */ | |
905 | void clear_local_APIC(void) | |
906 | { | |
2584a82d | 907 | int maxlvt; |
0e078e2f TG |
908 | u32 v; |
909 | ||
d3432896 | 910 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 911 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
912 | return; |
913 | ||
914 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
915 | /* |
916 | * Masking an LVT entry can trigger a local APIC error | |
917 | * if the vector is zero. Mask LVTERR first to prevent this. | |
918 | */ | |
919 | if (maxlvt >= 3) { | |
920 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
921 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
922 | } | |
923 | /* | |
924 | * Careful: we have to set masks only first to deassert | |
925 | * any level-triggered sources. | |
926 | */ | |
927 | v = apic_read(APIC_LVTT); | |
928 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
929 | v = apic_read(APIC_LVT0); | |
930 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
931 | v = apic_read(APIC_LVT1); | |
932 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
933 | if (maxlvt >= 4) { | |
934 | v = apic_read(APIC_LVTPC); | |
935 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
936 | } | |
937 | ||
6764014b | 938 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 939 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
940 | if (maxlvt >= 5) { |
941 | v = apic_read(APIC_LVTTHMR); | |
942 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
943 | } | |
944 | #endif | |
5ca8681c AK |
945 | #ifdef CONFIG_X86_MCE_INTEL |
946 | if (maxlvt >= 6) { | |
947 | v = apic_read(APIC_LVTCMCI); | |
948 | if (!(v & APIC_LVT_MASKED)) | |
949 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
950 | } | |
951 | #endif | |
952 | ||
0e078e2f TG |
953 | /* |
954 | * Clean APIC state for other OSs: | |
955 | */ | |
956 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
957 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
958 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
959 | if (maxlvt >= 3) | |
960 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
961 | if (maxlvt >= 4) | |
962 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
963 | |
964 | /* Integrated APIC (!82489DX) ? */ | |
965 | if (lapic_is_integrated()) { | |
966 | if (maxlvt > 3) | |
967 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
968 | apic_write(APIC_ESR, 0); | |
969 | apic_read(APIC_ESR); | |
970 | } | |
0e078e2f TG |
971 | } |
972 | ||
973 | /** | |
974 | * disable_local_APIC - clear and disable the local APIC | |
975 | */ | |
976 | void disable_local_APIC(void) | |
977 | { | |
978 | unsigned int value; | |
979 | ||
4a13ad0b | 980 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 981 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
982 | return; |
983 | ||
0e078e2f TG |
984 | clear_local_APIC(); |
985 | ||
986 | /* | |
987 | * Disable APIC (implies clearing of registers | |
988 | * for 82489DX!). | |
989 | */ | |
990 | value = apic_read(APIC_SPIV); | |
991 | value &= ~APIC_SPIV_APIC_ENABLED; | |
992 | apic_write(APIC_SPIV, value); | |
990b183e CG |
993 | |
994 | #ifdef CONFIG_X86_32 | |
995 | /* | |
996 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
997 | * restore the disabled state. | |
998 | */ | |
999 | if (enabled_via_apicbase) { | |
1000 | unsigned int l, h; | |
1001 | ||
1002 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1003 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1004 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1005 | } | |
1006 | #endif | |
0e078e2f TG |
1007 | } |
1008 | ||
fe4024dc CG |
1009 | /* |
1010 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1011 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1012 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1013 | * for the case where Linux didn't enable the LAPIC. | |
1014 | */ | |
0e078e2f TG |
1015 | void lapic_shutdown(void) |
1016 | { | |
1017 | unsigned long flags; | |
1018 | ||
8312136f | 1019 | if (!cpu_has_apic && !apic_from_smp_config()) |
0e078e2f TG |
1020 | return; |
1021 | ||
1022 | local_irq_save(flags); | |
1023 | ||
fe4024dc CG |
1024 | #ifdef CONFIG_X86_32 |
1025 | if (!enabled_via_apicbase) | |
1026 | clear_local_APIC(); | |
1027 | else | |
1028 | #endif | |
1029 | disable_local_APIC(); | |
1030 | ||
0e078e2f TG |
1031 | |
1032 | local_irq_restore(flags); | |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * This is to verify that we're looking at a real local APIC. | |
1037 | * Check these against your board if the CPUs aren't getting | |
1038 | * started for no apparent reason. | |
1039 | */ | |
1040 | int __init verify_local_APIC(void) | |
1041 | { | |
1042 | unsigned int reg0, reg1; | |
1043 | ||
1044 | /* | |
1045 | * The version register is read-only in a real APIC. | |
1046 | */ | |
1047 | reg0 = apic_read(APIC_LVR); | |
1048 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
1049 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
1050 | reg1 = apic_read(APIC_LVR); | |
1051 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
1052 | ||
1053 | /* | |
1054 | * The two version reads above should print the same | |
1055 | * numbers. If the second one is different, then we | |
1056 | * poke at a non-APIC. | |
1057 | */ | |
1058 | if (reg1 != reg0) | |
1059 | return 0; | |
1060 | ||
1061 | /* | |
1062 | * Check if the version looks reasonably. | |
1063 | */ | |
1064 | reg1 = GET_APIC_VERSION(reg0); | |
1065 | if (reg1 == 0x00 || reg1 == 0xff) | |
1066 | return 0; | |
1067 | reg1 = lapic_get_maxlvt(); | |
1068 | if (reg1 < 0x02 || reg1 == 0xff) | |
1069 | return 0; | |
1070 | ||
1071 | /* | |
1072 | * The ID register is read/write in a real APIC. | |
1073 | */ | |
2d7a66d0 | 1074 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1075 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1076 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1077 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1078 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1079 | apic_write(APIC_ID, reg0); | |
5b812727 | 1080 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1081 | return 0; |
1082 | ||
1083 | /* | |
1da177e4 LT |
1084 | * The next two are just to see if we have sane values. |
1085 | * They're only really relevant if we're in Virtual Wire | |
1086 | * compatibility mode, but most boxes are anymore. | |
1087 | */ | |
1088 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1089 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1090 | reg1 = apic_read(APIC_LVT1); |
1091 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1092 | ||
1093 | return 1; | |
1094 | } | |
1095 | ||
0e078e2f TG |
1096 | /** |
1097 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1098 | */ | |
1da177e4 LT |
1099 | void __init sync_Arb_IDs(void) |
1100 | { | |
296cb951 CG |
1101 | /* |
1102 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1103 | * needed on AMD. | |
1104 | */ | |
1105 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1106 | return; |
1107 | ||
1108 | /* | |
1109 | * Wait for idle. | |
1110 | */ | |
1111 | apic_wait_icr_idle(); | |
1112 | ||
1113 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1114 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1115 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1116 | } |
1117 | ||
1da177e4 LT |
1118 | /* |
1119 | * An initial setup of the virtual wire mode. | |
1120 | */ | |
1121 | void __init init_bsp_APIC(void) | |
1122 | { | |
11a8e778 | 1123 | unsigned int value; |
1da177e4 LT |
1124 | |
1125 | /* | |
1126 | * Don't do the setup now if we have a SMP BIOS as the | |
1127 | * through-I/O-APIC virtual wire mode might be active. | |
1128 | */ | |
1129 | if (smp_found_config || !cpu_has_apic) | |
1130 | return; | |
1131 | ||
1da177e4 LT |
1132 | /* |
1133 | * Do not trust the local APIC being empty at bootup. | |
1134 | */ | |
1135 | clear_local_APIC(); | |
1136 | ||
1137 | /* | |
1138 | * Enable APIC. | |
1139 | */ | |
1140 | value = apic_read(APIC_SPIV); | |
1141 | value &= ~APIC_VECTOR_MASK; | |
1142 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1143 | |
1144 | #ifdef CONFIG_X86_32 | |
1145 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1146 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1147 | (boot_cpu_data.x86 == 15)) | |
1148 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1149 | else | |
1150 | #endif | |
1151 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1152 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1153 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1154 | |
1155 | /* | |
1156 | * Set up the virtual wire mode. | |
1157 | */ | |
11a8e778 | 1158 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1159 | value = APIC_DM_NMI; |
638c0411 CG |
1160 | if (!lapic_is_integrated()) /* 82489DX */ |
1161 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1162 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1163 | } |
1164 | ||
c43da2f5 CG |
1165 | static void __cpuinit lapic_setup_esr(void) |
1166 | { | |
9df08f10 CG |
1167 | unsigned int oldvalue, value, maxlvt; |
1168 | ||
1169 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1170 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1171 | return; |
1172 | } | |
c43da2f5 | 1173 | |
08125d3e | 1174 | if (apic->disable_esr) { |
c43da2f5 | 1175 | /* |
9df08f10 CG |
1176 | * Something untraceable is creating bad interrupts on |
1177 | * secondary quads ... for the moment, just leave the | |
1178 | * ESR disabled - we can't do anything useful with the | |
1179 | * errors anyway - mbligh | |
c43da2f5 | 1180 | */ |
ba21ebb6 | 1181 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1182 | return; |
c43da2f5 | 1183 | } |
9df08f10 CG |
1184 | |
1185 | maxlvt = lapic_get_maxlvt(); | |
1186 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1187 | apic_write(APIC_ESR, 0); | |
1188 | oldvalue = apic_read(APIC_ESR); | |
1189 | ||
1190 | /* enables sending errors */ | |
1191 | value = ERROR_APIC_VECTOR; | |
1192 | apic_write(APIC_LVTERR, value); | |
1193 | ||
1194 | /* | |
1195 | * spec says clear errors after enabling vector. | |
1196 | */ | |
1197 | if (maxlvt > 3) | |
1198 | apic_write(APIC_ESR, 0); | |
1199 | value = apic_read(APIC_ESR); | |
1200 | if (value != oldvalue) | |
1201 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1202 | "vector: 0x%08x after: 0x%08x\n", | |
1203 | oldvalue, value); | |
c43da2f5 CG |
1204 | } |
1205 | ||
0e078e2f TG |
1206 | /** |
1207 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1208 | * |
1209 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1210 | * Always called with preemption disabled. | |
0e078e2f TG |
1211 | */ |
1212 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1213 | { |
0aa002fe | 1214 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1215 | unsigned int value, queued; |
1216 | int i, j, acked = 0; | |
1217 | unsigned long long tsc = 0, ntsc; | |
1218 | long long max_loops = cpu_khz; | |
1219 | ||
1220 | if (cpu_has_tsc) | |
1221 | rdtscll(tsc); | |
1da177e4 | 1222 | |
f1182638 | 1223 | if (disable_apic) { |
7167d08e | 1224 | disable_ioapic_support(); |
f1182638 JB |
1225 | return; |
1226 | } | |
1227 | ||
89c38c28 CG |
1228 | #ifdef CONFIG_X86_32 |
1229 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1230 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1231 | apic_write(APIC_ESR, 0); |
1232 | apic_write(APIC_ESR, 0); | |
1233 | apic_write(APIC_ESR, 0); | |
1234 | apic_write(APIC_ESR, 0); | |
1235 | } | |
1236 | #endif | |
cdd6c482 | 1237 | perf_events_lapic_init(); |
89c38c28 | 1238 | |
1da177e4 LT |
1239 | /* |
1240 | * Double-check whether this APIC is really registered. | |
1241 | * This is meaningless in clustered apic mode, so we skip it. | |
1242 | */ | |
c2777f98 | 1243 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1244 | |
1245 | /* | |
1246 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1247 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1248 | * document number 292116). So here it goes... | |
1249 | */ | |
a5c43296 | 1250 | apic->init_apic_ldr(); |
1da177e4 | 1251 | |
6f802c4b TH |
1252 | #ifdef CONFIG_X86_32 |
1253 | /* | |
acb8bc09 TH |
1254 | * APIC LDR is initialized. If logical_apicid mapping was |
1255 | * initialized during get_smp_config(), make sure it matches the | |
1256 | * actual value. | |
6f802c4b | 1257 | */ |
acb8bc09 TH |
1258 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1259 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1260 | /* always use the value from LDR */ | |
6f802c4b TH |
1261 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1262 | logical_smp_processor_id(); | |
c4b90c11 TH |
1263 | |
1264 | /* | |
1265 | * Some NUMA implementations (NUMAQ) don't initialize apicid to | |
1266 | * node mapping during NUMA init. Now that logical apicid is | |
1267 | * guaranteed to be known, give it another chance. This is already | |
1268 | * a bit too late - percpu allocation has already happened without | |
1269 | * proper NUMA affinity. | |
1270 | */ | |
84914ed0 TH |
1271 | if (apic->x86_32_numa_cpu_node) |
1272 | set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), | |
1273 | apic->x86_32_numa_cpu_node(cpu)); | |
6f802c4b TH |
1274 | #endif |
1275 | ||
1da177e4 LT |
1276 | /* |
1277 | * Set Task Priority to 'accept all'. We never change this | |
1278 | * later on. | |
1279 | */ | |
1280 | value = apic_read(APIC_TASKPRI); | |
1281 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1282 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1283 | |
da7ed9f9 VG |
1284 | /* |
1285 | * After a crash, we no longer service the interrupts and a pending | |
1286 | * interrupt from previous kernel might still have ISR bit set. | |
1287 | * | |
1288 | * Most probably by now CPU has serviced that pending interrupt and | |
1289 | * it might not have done the ack_APIC_irq() because it thought, | |
1290 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1291 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1292 | * the interrupt. Hence a vector might get locked. It was noticed | |
1293 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1294 | */ | |
8c3ba8d0 KJ |
1295 | do { |
1296 | queued = 0; | |
1297 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1298 | queued |= apic_read(APIC_IRR + i*0x10); | |
1299 | ||
1300 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1301 | value = apic_read(APIC_ISR + i*0x10); | |
1302 | for (j = 31; j >= 0; j--) { | |
1303 | if (value & (1<<j)) { | |
1304 | ack_APIC_irq(); | |
1305 | acked++; | |
1306 | } | |
1307 | } | |
da7ed9f9 | 1308 | } |
8c3ba8d0 KJ |
1309 | if (acked > 256) { |
1310 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1311 | acked); | |
1312 | break; | |
1313 | } | |
1314 | if (cpu_has_tsc) { | |
1315 | rdtscll(ntsc); | |
1316 | max_loops = (cpu_khz << 10) - (ntsc - tsc); | |
1317 | } else | |
1318 | max_loops--; | |
1319 | } while (queued && max_loops > 0); | |
1320 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1321 | |
1da177e4 LT |
1322 | /* |
1323 | * Now that we are all set up, enable the APIC | |
1324 | */ | |
1325 | value = apic_read(APIC_SPIV); | |
1326 | value &= ~APIC_VECTOR_MASK; | |
1327 | /* | |
1328 | * Enable APIC | |
1329 | */ | |
1330 | value |= APIC_SPIV_APIC_ENABLED; | |
1331 | ||
89c38c28 CG |
1332 | #ifdef CONFIG_X86_32 |
1333 | /* | |
1334 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1335 | * certain networking cards. If high frequency interrupts are | |
1336 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1337 | * entry is masked/unmasked at a high rate as well then sooner or | |
1338 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1339 | * from the device. If focus CPU is disabled then the hang goes | |
1340 | * away, oh well :-( | |
1341 | * | |
1342 | * [ This bug can be reproduced easily with a level-triggered | |
1343 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1344 | * BX chipset. ] | |
1345 | */ | |
1346 | /* | |
1347 | * Actually disabling the focus CPU check just makes the hang less | |
1348 | * frequent as it makes the interrupt distributon model be more | |
1349 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1350 | * See also the comment in end_level_ioapic_irq(). --macro | |
1351 | */ | |
1352 | ||
1353 | /* | |
1354 | * - enable focus processor (bit==0) | |
1355 | * - 64bit mode always use processor focus | |
1356 | * so no need to set it | |
1357 | */ | |
1358 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1359 | #endif | |
3f14c746 | 1360 | |
1da177e4 LT |
1361 | /* |
1362 | * Set spurious IRQ vector | |
1363 | */ | |
1364 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1365 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1366 | |
1367 | /* | |
1368 | * Set up LVT0, LVT1: | |
1369 | * | |
1370 | * set up through-local-APIC on the BP's LINT0. This is not | |
1371 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1372 | * we delegate interrupts to the 8259A. | |
1373 | */ | |
1374 | /* | |
1375 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1376 | */ | |
1377 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1378 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1379 | value = APIC_DM_EXTINT; |
0aa002fe | 1380 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1381 | } else { |
1382 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1383 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1384 | } |
11a8e778 | 1385 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1386 | |
1387 | /* | |
1388 | * only the BP should see the LINT1 NMI signal, obviously. | |
1389 | */ | |
0aa002fe | 1390 | if (!cpu) |
1da177e4 LT |
1391 | value = APIC_DM_NMI; |
1392 | else | |
1393 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1394 | if (!lapic_is_integrated()) /* 82489DX */ |
1395 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1396 | apic_write(APIC_LVT1, value); |
89c38c28 | 1397 | |
be71b855 AK |
1398 | #ifdef CONFIG_X86_MCE_INTEL |
1399 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1400 | if (!cpu) |
be71b855 AK |
1401 | cmci_recheck(); |
1402 | #endif | |
739f33b3 | 1403 | } |
1da177e4 | 1404 | |
739f33b3 AK |
1405 | void __cpuinit end_local_APIC_setup(void) |
1406 | { | |
1407 | lapic_setup_esr(); | |
fa6b95fc CG |
1408 | |
1409 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1410 | { |
1411 | unsigned int value; | |
1412 | /* Disable the local apic timer */ | |
1413 | value = apic_read(APIC_LVTT); | |
1414 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1415 | apic_write(APIC_LVTT, value); | |
1416 | } | |
fa6b95fc CG |
1417 | #endif |
1418 | ||
0e078e2f | 1419 | apic_pm_activate(); |
2fb270f3 JB |
1420 | } |
1421 | ||
1422 | void __init bsp_end_local_APIC_setup(void) | |
1423 | { | |
1424 | end_local_APIC_setup(); | |
7f7fbf45 KK |
1425 | |
1426 | /* | |
1427 | * Now that local APIC setup is completed for BP, configure the fault | |
1428 | * handling for interrupt remapping. | |
1429 | */ | |
2fb270f3 | 1430 | if (intr_remapping_enabled) |
7f7fbf45 KK |
1431 | enable_drhd_fault_handling(); |
1432 | ||
1da177e4 | 1433 | } |
1da177e4 | 1434 | |
06cd9a7d | 1435 | #ifdef CONFIG_X86_X2APIC |
fb209bd8 YL |
1436 | /* |
1437 | * Need to disable xapic and x2apic at the same time and then enable xapic mode | |
1438 | */ | |
1439 | static inline void __disable_x2apic(u64 msr) | |
1440 | { | |
1441 | wrmsrl(MSR_IA32_APICBASE, | |
1442 | msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1443 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1444 | } | |
1445 | ||
1446 | static void disable_x2apic(void) | |
1447 | { | |
1448 | u64 msr; | |
1449 | ||
1450 | if (!cpu_has_x2apic) | |
1451 | return; | |
1452 | ||
1453 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1454 | if (msr & X2APIC_ENABLE) { | |
1455 | u32 x2apic_id = read_apic_id(); | |
1456 | ||
1457 | if (x2apic_id >= 255) | |
1458 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
1459 | ||
1460 | pr_info("Disabling x2apic\n"); | |
1461 | __disable_x2apic(msr); | |
1462 | ||
1463 | x2apic_disabled = 1; | |
1464 | x2apic_mode = 0; | |
1465 | ||
1466 | register_lapic_address(mp_lapic_addr); | |
1467 | } | |
1468 | } | |
1469 | ||
6e1cb38a SS |
1470 | void check_x2apic(void) |
1471 | { | |
ef1f87aa | 1472 | if (x2apic_enabled()) { |
ba21ebb6 | 1473 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
fc1edaf9 | 1474 | x2apic_preenabled = x2apic_mode = 1; |
6e1cb38a SS |
1475 | } |
1476 | } | |
1477 | ||
1478 | void enable_x2apic(void) | |
1479 | { | |
fb209bd8 YL |
1480 | u64 msr; |
1481 | ||
1482 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1483 | if (x2apic_disabled) { | |
1484 | __disable_x2apic(msr); | |
1485 | return; | |
1486 | } | |
6e1cb38a | 1487 | |
fc1edaf9 | 1488 | if (!x2apic_mode) |
06cd9a7d YL |
1489 | return; |
1490 | ||
6e1cb38a | 1491 | if (!(msr & X2APIC_ENABLE)) { |
450b1e8d | 1492 | printk_once(KERN_INFO "Enabling x2apic\n"); |
fb209bd8 | 1493 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); |
6e1cb38a SS |
1494 | } |
1495 | } | |
93758238 | 1496 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1497 | |
ce69a784 | 1498 | int __init enable_IR(void) |
6e1cb38a | 1499 | { |
d3f13810 | 1500 | #ifdef CONFIG_IRQ_REMAP |
93758238 WH |
1501 | if (!intr_remapping_supported()) { |
1502 | pr_debug("intr-remapping not supported\n"); | |
41750d31 | 1503 | return -1; |
6e1cb38a SS |
1504 | } |
1505 | ||
93758238 WH |
1506 | if (!x2apic_preenabled && skip_ioapic_setup) { |
1507 | pr_info("Skipped enabling intr-remap because of skipping " | |
1508 | "io-apic setup\n"); | |
41750d31 | 1509 | return -1; |
6e1cb38a SS |
1510 | } |
1511 | ||
41750d31 | 1512 | return enable_intr_remapping(); |
ce69a784 | 1513 | #endif |
41750d31 | 1514 | return -1; |
ce69a784 GN |
1515 | } |
1516 | ||
1517 | void __init enable_IR_x2apic(void) | |
1518 | { | |
1519 | unsigned long flags; | |
ce69a784 | 1520 | int ret, x2apic_enabled = 0; |
e670761f | 1521 | int dmar_table_init_ret; |
b7f42ab2 | 1522 | |
b7f42ab2 | 1523 | dmar_table_init_ret = dmar_table_init(); |
e670761f YL |
1524 | if (dmar_table_init_ret && !x2apic_supported()) |
1525 | return; | |
ce69a784 | 1526 | |
31dce14a | 1527 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1528 | if (ret) { |
ba21ebb6 | 1529 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1530 | return; |
5ffa4eb2 | 1531 | } |
6e1cb38a | 1532 | |
05c3dc2c | 1533 | local_irq_save(flags); |
b81bb373 | 1534 | legacy_pic->mask_all(); |
31dce14a | 1535 | mask_ioapic_entries(); |
05c3dc2c | 1536 | |
b7f42ab2 | 1537 | if (dmar_table_init_ret) |
41750d31 | 1538 | ret = -1; |
b7f42ab2 YL |
1539 | else |
1540 | ret = enable_IR(); | |
1541 | ||
fb209bd8 YL |
1542 | if (!x2apic_supported()) |
1543 | goto nox2apic; | |
1544 | ||
41750d31 | 1545 | if (ret < 0) { |
ce69a784 GN |
1546 | /* IR is required if there is APIC ID > 255 even when running |
1547 | * under KVM | |
1548 | */ | |
2904ed8d | 1549 | if (max_physical_apicid > 255 || |
fb209bd8 YL |
1550 | !hypervisor_x2apic_available()) { |
1551 | if (x2apic_preenabled) | |
1552 | disable_x2apic(); | |
ce69a784 | 1553 | goto nox2apic; |
fb209bd8 | 1554 | } |
ce69a784 GN |
1555 | /* |
1556 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1557 | * only in physical mode | |
1558 | */ | |
1559 | x2apic_force_phys(); | |
1560 | } | |
6e1cb38a | 1561 | |
fb209bd8 YL |
1562 | if (ret == IRQ_REMAP_XAPIC_MODE) { |
1563 | pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); | |
41750d31 | 1564 | goto nox2apic; |
fb209bd8 | 1565 | } |
41750d31 | 1566 | |
ce69a784 | 1567 | x2apic_enabled = 1; |
93758238 | 1568 | |
fc1edaf9 SS |
1569 | if (x2apic_supported() && !x2apic_mode) { |
1570 | x2apic_mode = 1; | |
6e1cb38a | 1571 | enable_x2apic(); |
93758238 | 1572 | pr_info("Enabled x2apic\n"); |
6e1cb38a | 1573 | } |
5ffa4eb2 | 1574 | |
ce69a784 | 1575 | nox2apic: |
41750d31 | 1576 | if (ret < 0) /* IR enabling failed */ |
31dce14a | 1577 | restore_ioapic_entries(); |
b81bb373 | 1578 | legacy_pic->restore_mask(); |
6e1cb38a | 1579 | local_irq_restore(flags); |
6e1cb38a | 1580 | } |
93758238 | 1581 | |
be7a656f | 1582 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1583 | /* |
1584 | * Detect and enable local APICs on non-SMP boards. | |
1585 | * Original code written by Keir Fraser. | |
1586 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1587 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1588 | */ |
0e078e2f | 1589 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1590 | { |
1591 | if (!cpu_has_apic) { | |
ba21ebb6 | 1592 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1593 | return -1; |
1594 | } | |
1595 | ||
1596 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1597 | return 0; |
1598 | } | |
be7a656f | 1599 | #else |
5a7ae78f | 1600 | |
25874a29 | 1601 | static int __init apic_verify(void) |
5a7ae78f TG |
1602 | { |
1603 | u32 features, h, l; | |
1604 | ||
1605 | /* | |
1606 | * The APIC feature bit should now be enabled | |
1607 | * in `cpuid' | |
1608 | */ | |
1609 | features = cpuid_edx(1); | |
1610 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1611 | pr_warning("Could not enable APIC!\n"); | |
1612 | return -1; | |
1613 | } | |
1614 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1615 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1616 | ||
1617 | /* The BIOS may have set up the APIC at some other address */ | |
1618 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1619 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1620 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1621 | ||
1622 | pr_info("Found and enabled local APIC!\n"); | |
1623 | return 0; | |
1624 | } | |
1625 | ||
25874a29 | 1626 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1627 | { |
1628 | u32 h, l; | |
1629 | ||
1630 | if (disable_apic) | |
1631 | return -1; | |
1632 | ||
1633 | /* | |
1634 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1635 | * MSR. This can only be done in software for Intel P6 or later | |
1636 | * and AMD K7 (Model > 1) or later. | |
1637 | */ | |
1638 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1639 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1640 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1641 | l &= ~MSR_IA32_APICBASE_BASE; | |
a906fdaa | 1642 | l |= MSR_IA32_APICBASE_ENABLE | addr; |
5a7ae78f TG |
1643 | wrmsr(MSR_IA32_APICBASE, l, h); |
1644 | enabled_via_apicbase = 1; | |
1645 | } | |
1646 | return apic_verify(); | |
1647 | } | |
1648 | ||
be7a656f YL |
1649 | /* |
1650 | * Detect and initialize APIC | |
1651 | */ | |
1652 | static int __init detect_init_APIC(void) | |
1653 | { | |
be7a656f YL |
1654 | /* Disabled by kernel option? */ |
1655 | if (disable_apic) | |
1656 | return -1; | |
1657 | ||
1658 | switch (boot_cpu_data.x86_vendor) { | |
1659 | case X86_VENDOR_AMD: | |
1660 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1661 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1662 | break; |
1663 | goto no_apic; | |
1664 | case X86_VENDOR_INTEL: | |
1665 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1666 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1667 | break; | |
1668 | goto no_apic; | |
1669 | default: | |
1670 | goto no_apic; | |
1671 | } | |
1672 | ||
1673 | if (!cpu_has_apic) { | |
1674 | /* | |
1675 | * Over-ride BIOS and try to enable the local APIC only if | |
1676 | * "lapic" specified. | |
1677 | */ | |
1678 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1679 | pr_info("Local APIC disabled by BIOS -- " |
1680 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1681 | return -1; |
1682 | } | |
a906fdaa | 1683 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1684 | return -1; |
1685 | } else { | |
1686 | if (apic_verify()) | |
1687 | return -1; | |
be7a656f | 1688 | } |
be7a656f YL |
1689 | |
1690 | apic_pm_activate(); | |
1691 | ||
1692 | return 0; | |
1693 | ||
1694 | no_apic: | |
ba21ebb6 | 1695 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1696 | return -1; |
1697 | } | |
1698 | #endif | |
1da177e4 | 1699 | |
0e078e2f TG |
1700 | /** |
1701 | * init_apic_mappings - initialize APIC mappings | |
1702 | */ | |
1da177e4 LT |
1703 | void __init init_apic_mappings(void) |
1704 | { | |
4401da61 YL |
1705 | unsigned int new_apicid; |
1706 | ||
fc1edaf9 | 1707 | if (x2apic_mode) { |
4c9961d5 | 1708 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1709 | return; |
1710 | } | |
1711 | ||
4797f6b0 | 1712 | /* If no local APIC can be found return early */ |
1da177e4 | 1713 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1714 | /* lets NOP'ify apic operations */ |
1715 | pr_info("APIC: disable apic facility\n"); | |
1716 | apic_disable(); | |
1717 | } else { | |
1da177e4 LT |
1718 | apic_phys = mp_lapic_addr; |
1719 | ||
4797f6b0 YL |
1720 | /* |
1721 | * acpi lapic path already maps that address in | |
1722 | * acpi_register_lapic_address() | |
1723 | */ | |
5989cd6a | 1724 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1725 | register_lapic_address(apic_phys); |
cec6be6d | 1726 | } |
1da177e4 LT |
1727 | |
1728 | /* | |
1729 | * Fetch the APIC ID of the BSP in case we have a | |
1730 | * default configuration (or the MP table is broken). | |
1731 | */ | |
4401da61 YL |
1732 | new_apicid = read_apic_id(); |
1733 | if (boot_cpu_physical_apicid != new_apicid) { | |
1734 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1735 | /* |
1736 | * yeah -- we lie about apic_version | |
1737 | * in case if apic was disabled via boot option | |
1738 | * but it's not a problem for SMP compiled kernel | |
1739 | * since smp_sanity_check is prepared for such a case | |
1740 | * and disable smp mode | |
1741 | */ | |
4401da61 YL |
1742 | apic_version[new_apicid] = |
1743 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1744 | } |
1da177e4 LT |
1745 | } |
1746 | ||
c0104d38 YL |
1747 | void __init register_lapic_address(unsigned long address) |
1748 | { | |
1749 | mp_lapic_addr = address; | |
1750 | ||
0450193b YL |
1751 | if (!x2apic_mode) { |
1752 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1753 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1754 | APIC_BASE, mp_lapic_addr); | |
1755 | } | |
c0104d38 YL |
1756 | if (boot_cpu_physical_apicid == -1U) { |
1757 | boot_cpu_physical_apicid = read_apic_id(); | |
1758 | apic_version[boot_cpu_physical_apicid] = | |
1759 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1760 | } | |
1761 | } | |
1762 | ||
1da177e4 | 1763 | /* |
0e078e2f TG |
1764 | * This initializes the IO-APIC and APIC hardware if this is |
1765 | * a UP kernel. | |
1da177e4 | 1766 | */ |
56d91f13 | 1767 | int apic_version[MAX_LOCAL_APIC]; |
1b313f4a | 1768 | |
0e078e2f | 1769 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1770 | { |
0e078e2f | 1771 | if (disable_apic) { |
ba21ebb6 | 1772 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1773 | return -1; |
1774 | } | |
f1182638 | 1775 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1776 | if (!cpu_has_apic) { |
1777 | disable_apic = 1; | |
ba21ebb6 | 1778 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1779 | return -1; |
1780 | } | |
fa2bd35a YL |
1781 | #else |
1782 | if (!smp_found_config && !cpu_has_apic) | |
1783 | return -1; | |
1784 | ||
1785 | /* | |
1786 | * Complain if the BIOS pretends there is one. | |
1787 | */ | |
1788 | if (!cpu_has_apic && | |
1789 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1790 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1791 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1792 | return -1; |
1793 | } | |
1794 | #endif | |
1795 | ||
72ce0165 | 1796 | default_setup_apic_routing(); |
6e1cb38a | 1797 | |
0e078e2f | 1798 | verify_local_APIC(); |
b5841765 GC |
1799 | connect_bsp_APIC(); |
1800 | ||
fa2bd35a | 1801 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1802 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1803 | #else |
1804 | /* | |
1805 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1806 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1807 | * might be zero if read from MP tables. Get it from LAPIC. | |
1808 | */ | |
1809 | # ifdef CONFIG_CRASH_DUMP | |
1810 | boot_cpu_physical_apicid = read_apic_id(); | |
1811 | # endif | |
1812 | #endif | |
1813 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1814 | setup_local_APIC(); |
1da177e4 | 1815 | |
88d0f550 | 1816 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1817 | /* |
1818 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1819 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1820 | */ |
1821 | if (!skip_ioapic_setup && nr_ioapics) | |
1822 | enable_IO_APIC(); | |
fa2bd35a | 1823 | #endif |
739f33b3 | 1824 | |
2fb270f3 | 1825 | bsp_end_local_APIC_setup(); |
739f33b3 | 1826 | |
fa2bd35a | 1827 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1828 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1829 | setup_IO_APIC(); | |
98c061b6 | 1830 | else { |
0e078e2f | 1831 | nr_ioapics = 0; |
98c061b6 | 1832 | } |
fa2bd35a YL |
1833 | #endif |
1834 | ||
736decac | 1835 | x86_init.timers.setup_percpu_clockev(); |
0e078e2f | 1836 | return 0; |
1da177e4 LT |
1837 | } |
1838 | ||
1839 | /* | |
0e078e2f | 1840 | * Local APIC interrupts |
1da177e4 LT |
1841 | */ |
1842 | ||
0e078e2f TG |
1843 | /* |
1844 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1845 | */ | |
dc1528dd | 1846 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1847 | { |
dc1528dd YL |
1848 | u32 v; |
1849 | ||
0e078e2f TG |
1850 | exit_idle(); |
1851 | irq_enter(); | |
1da177e4 | 1852 | /* |
0e078e2f TG |
1853 | * Check if this really is a spurious interrupt and ACK it |
1854 | * if it is a vectored one. Just in case... | |
1855 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1856 | */ |
0e078e2f TG |
1857 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1858 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1859 | ack_APIC_irq(); | |
c4d58cbd | 1860 | |
915b0d01 HS |
1861 | inc_irq_stat(irq_spurious_count); |
1862 | ||
dc1528dd | 1863 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1864 | pr_info("spurious APIC interrupt on CPU#%d, " |
1865 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1866 | irq_exit(); |
1867 | } | |
1da177e4 | 1868 | |
0e078e2f TG |
1869 | /* |
1870 | * This interrupt should never happen with our APIC/SMP architecture | |
1871 | */ | |
dc1528dd | 1872 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1873 | { |
2b398bd9 YS |
1874 | u32 v0, v1; |
1875 | u32 i = 0; | |
1876 | static const char * const error_interrupt_reason[] = { | |
1877 | "Send CS error", /* APIC Error Bit 0 */ | |
1878 | "Receive CS error", /* APIC Error Bit 1 */ | |
1879 | "Send accept error", /* APIC Error Bit 2 */ | |
1880 | "Receive accept error", /* APIC Error Bit 3 */ | |
1881 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1882 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1883 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1884 | "Illegal register address", /* APIC Error Bit 7 */ | |
1885 | }; | |
1da177e4 | 1886 | |
0e078e2f TG |
1887 | exit_idle(); |
1888 | irq_enter(); | |
1889 | /* First tickle the hardware, only then report what went on. -- REW */ | |
2b398bd9 | 1890 | v0 = apic_read(APIC_ESR); |
0e078e2f TG |
1891 | apic_write(APIC_ESR, 0); |
1892 | v1 = apic_read(APIC_ESR); | |
1893 | ack_APIC_irq(); | |
1894 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1895 | |
2b398bd9 YS |
1896 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", |
1897 | smp_processor_id(), v0 , v1); | |
1898 | ||
1899 | v1 = v1 & 0xff; | |
1900 | while (v1) { | |
1901 | if (v1 & 0x1) | |
1902 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); | |
1903 | i++; | |
1904 | v1 >>= 1; | |
1905 | }; | |
1906 | ||
1907 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
1908 | ||
0e078e2f | 1909 | irq_exit(); |
1da177e4 LT |
1910 | } |
1911 | ||
b5841765 | 1912 | /** |
36c9d674 CG |
1913 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1914 | */ | |
b5841765 GC |
1915 | void __init connect_bsp_APIC(void) |
1916 | { | |
36c9d674 CG |
1917 | #ifdef CONFIG_X86_32 |
1918 | if (pic_mode) { | |
1919 | /* | |
1920 | * Do not trust the local APIC being empty at bootup. | |
1921 | */ | |
1922 | clear_local_APIC(); | |
1923 | /* | |
1924 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1925 | * local APIC to INT and NMI lines. | |
1926 | */ | |
1927 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1928 | "enabling APIC mode.\n"); | |
c0eaa453 | 1929 | imcr_pic_to_apic(); |
36c9d674 CG |
1930 | } |
1931 | #endif | |
49040333 IM |
1932 | if (apic->enable_apic_mode) |
1933 | apic->enable_apic_mode(); | |
b5841765 GC |
1934 | } |
1935 | ||
274cfe59 CG |
1936 | /** |
1937 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1938 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1939 | * | |
1940 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1941 | * APIC is disabled. | |
1942 | */ | |
0e078e2f | 1943 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1944 | { |
1b4ee4e4 CG |
1945 | unsigned int value; |
1946 | ||
c177b0bc CG |
1947 | #ifdef CONFIG_X86_32 |
1948 | if (pic_mode) { | |
1949 | /* | |
1950 | * Put the board back into PIC mode (has an effect only on | |
1951 | * certain older boards). Note that APIC interrupts, including | |
1952 | * IPIs, won't work beyond this point! The only exception are | |
1953 | * INIT IPIs. | |
1954 | */ | |
1955 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1956 | "entering PIC mode.\n"); | |
c0eaa453 | 1957 | imcr_apic_to_pic(); |
c177b0bc CG |
1958 | return; |
1959 | } | |
1960 | #endif | |
1961 | ||
0e078e2f | 1962 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1963 | |
0e078e2f TG |
1964 | /* For the spurious interrupt use vector F, and enable it */ |
1965 | value = apic_read(APIC_SPIV); | |
1966 | value &= ~APIC_VECTOR_MASK; | |
1967 | value |= APIC_SPIV_APIC_ENABLED; | |
1968 | value |= 0xf; | |
1969 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1970 | |
0e078e2f TG |
1971 | if (!virt_wire_setup) { |
1972 | /* | |
1973 | * For LVT0 make it edge triggered, active high, | |
1974 | * external and enabled | |
1975 | */ | |
1976 | value = apic_read(APIC_LVT0); | |
1977 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1978 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1979 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1980 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1981 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1982 | apic_write(APIC_LVT0, value); | |
1983 | } else { | |
1984 | /* Disable LVT0 */ | |
1985 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1986 | } | |
b8ce3359 | 1987 | |
c177b0bc CG |
1988 | /* |
1989 | * For LVT1 make it edge triggered, active high, | |
1990 | * nmi and enabled | |
1991 | */ | |
0e078e2f TG |
1992 | value = apic_read(APIC_LVT1); |
1993 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1994 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1995 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1996 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1997 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1998 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1999 | } |
2000 | ||
be8a5685 AS |
2001 | void __cpuinit generic_processor_info(int apicid, int version) |
2002 | { | |
14cb6dcf VG |
2003 | int cpu, max = nr_cpu_ids; |
2004 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2005 | phys_cpu_present_map); | |
2006 | ||
2007 | /* | |
2008 | * If boot cpu has not been detected yet, then only allow upto | |
2009 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2010 | */ | |
2011 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2012 | apicid != boot_cpu_physical_apicid) { | |
2013 | int thiscpu = max + disabled_cpus - 1; | |
2014 | ||
2015 | pr_warning( | |
2016 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" | |
2017 | " reached. Keeping one slot for boot cpu." | |
2018 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2019 | ||
2020 | disabled_cpus++; | |
2021 | return; | |
2022 | } | |
be8a5685 | 2023 | |
3b11ce7f | 2024 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2025 | int thiscpu = max + disabled_cpus; |
2026 | ||
2027 | pr_warning( | |
2028 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
2029 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2030 | ||
2031 | disabled_cpus++; | |
be8a5685 AS |
2032 | return; |
2033 | } | |
2034 | ||
2035 | num_processors++; | |
be8a5685 AS |
2036 | if (apicid == boot_cpu_physical_apicid) { |
2037 | /* | |
2038 | * x86_bios_cpu_apicid is required to have processors listed | |
2039 | * in same order as logical cpu numbers. Hence the first | |
2040 | * entry is BSP, and so on. | |
e5fea868 YL |
2041 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2042 | * for BSP. | |
be8a5685 AS |
2043 | */ |
2044 | cpu = 0; | |
e5fea868 YL |
2045 | } else |
2046 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2047 | ||
2048 | /* | |
2049 | * Validate version | |
2050 | */ | |
2051 | if (version == 0x0) { | |
2052 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2053 | cpu, apicid); | |
2054 | version = 0x10; | |
be8a5685 | 2055 | } |
e5fea868 YL |
2056 | apic_version[apicid] = version; |
2057 | ||
2058 | if (version != apic_version[boot_cpu_physical_apicid]) { | |
2059 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", | |
2060 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
2061 | } | |
2062 | ||
2063 | physid_set(apicid, phys_cpu_present_map); | |
e0da3364 YL |
2064 | if (apicid > max_physical_apicid) |
2065 | max_physical_apicid = apicid; | |
2066 | ||
3e5095d1 | 2067 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2068 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2069 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2070 | #endif |
acb8bc09 TH |
2071 | #ifdef CONFIG_X86_32 |
2072 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2073 | apic->x86_32_early_logical_apicid(cpu); | |
2074 | #endif | |
1de88cd4 MT |
2075 | set_cpu_possible(cpu, true); |
2076 | set_cpu_present(cpu, true); | |
be8a5685 AS |
2077 | } |
2078 | ||
0c81c746 SS |
2079 | int hard_smp_processor_id(void) |
2080 | { | |
2081 | return read_apic_id(); | |
2082 | } | |
1dcdd3d1 IM |
2083 | |
2084 | void default_init_apic_ldr(void) | |
2085 | { | |
2086 | unsigned long val; | |
2087 | ||
2088 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2089 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2090 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2091 | apic_write(APIC_LDR, val); | |
2092 | } | |
2093 | ||
89039b37 | 2094 | /* |
0e078e2f | 2095 | * Power management |
89039b37 | 2096 | */ |
0e078e2f TG |
2097 | #ifdef CONFIG_PM |
2098 | ||
2099 | static struct { | |
274cfe59 CG |
2100 | /* |
2101 | * 'active' is true if the local APIC was enabled by us and | |
2102 | * not the BIOS; this signifies that we are also responsible | |
2103 | * for disabling it before entering apm/acpi suspend | |
2104 | */ | |
0e078e2f TG |
2105 | int active; |
2106 | /* r/w apic fields */ | |
2107 | unsigned int apic_id; | |
2108 | unsigned int apic_taskpri; | |
2109 | unsigned int apic_ldr; | |
2110 | unsigned int apic_dfr; | |
2111 | unsigned int apic_spiv; | |
2112 | unsigned int apic_lvtt; | |
2113 | unsigned int apic_lvtpc; | |
2114 | unsigned int apic_lvt0; | |
2115 | unsigned int apic_lvt1; | |
2116 | unsigned int apic_lvterr; | |
2117 | unsigned int apic_tmict; | |
2118 | unsigned int apic_tdcr; | |
2119 | unsigned int apic_thmr; | |
2120 | } apic_pm_state; | |
2121 | ||
f3c6ea1b | 2122 | static int lapic_suspend(void) |
0e078e2f TG |
2123 | { |
2124 | unsigned long flags; | |
2125 | int maxlvt; | |
89039b37 | 2126 | |
0e078e2f TG |
2127 | if (!apic_pm_state.active) |
2128 | return 0; | |
89039b37 | 2129 | |
0e078e2f | 2130 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2131 | |
2d7a66d0 | 2132 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2133 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2134 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2135 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2136 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2137 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2138 | if (maxlvt >= 4) | |
2139 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2140 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2141 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2142 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2143 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2144 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2145 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2146 | if (maxlvt >= 5) |
2147 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2148 | #endif | |
24968cfd | 2149 | |
0e078e2f TG |
2150 | local_irq_save(flags); |
2151 | disable_local_APIC(); | |
fc1edaf9 | 2152 | |
b24696bc FY |
2153 | if (intr_remapping_enabled) |
2154 | disable_intr_remapping(); | |
fc1edaf9 | 2155 | |
0e078e2f TG |
2156 | local_irq_restore(flags); |
2157 | return 0; | |
1da177e4 LT |
2158 | } |
2159 | ||
f3c6ea1b | 2160 | static void lapic_resume(void) |
1da177e4 | 2161 | { |
0e078e2f TG |
2162 | unsigned int l, h; |
2163 | unsigned long flags; | |
31dce14a | 2164 | int maxlvt; |
b24696bc | 2165 | |
0e078e2f | 2166 | if (!apic_pm_state.active) |
f3c6ea1b | 2167 | return; |
89b831ef | 2168 | |
0e078e2f | 2169 | local_irq_save(flags); |
9a2755c3 | 2170 | if (intr_remapping_enabled) { |
31dce14a SS |
2171 | /* |
2172 | * IO-APIC and PIC have their own resume routines. | |
2173 | * We just mask them here to make sure the interrupt | |
2174 | * subsystem is completely quiet while we enable x2apic | |
2175 | * and interrupt-remapping. | |
2176 | */ | |
2177 | mask_ioapic_entries(); | |
b81bb373 | 2178 | legacy_pic->mask_all(); |
b24696bc | 2179 | } |
92206c90 | 2180 | |
fc1edaf9 | 2181 | if (x2apic_mode) |
92206c90 | 2182 | enable_x2apic(); |
cf6567fe | 2183 | else { |
92206c90 CG |
2184 | /* |
2185 | * Make sure the APICBASE points to the right address | |
2186 | * | |
2187 | * FIXME! This will be wrong if we ever support suspend on | |
2188 | * SMP! We'll need to do this as part of the CPU restore! | |
2189 | */ | |
6e1cb38a SS |
2190 | rdmsr(MSR_IA32_APICBASE, l, h); |
2191 | l &= ~MSR_IA32_APICBASE_BASE; | |
2192 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2193 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2194 | } |
6e1cb38a | 2195 | |
b24696bc | 2196 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2197 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2198 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2199 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2200 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2201 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2202 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2203 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2204 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2205 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2206 | if (maxlvt >= 5) |
2207 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2208 | #endif | |
2209 | if (maxlvt >= 4) | |
2210 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2211 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2212 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2213 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2214 | apic_write(APIC_ESR, 0); | |
2215 | apic_read(APIC_ESR); | |
2216 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2217 | apic_write(APIC_ESR, 0); | |
2218 | apic_read(APIC_ESR); | |
92206c90 | 2219 | |
31dce14a | 2220 | if (intr_remapping_enabled) |
fc1edaf9 | 2221 | reenable_intr_remapping(x2apic_mode); |
31dce14a | 2222 | |
0e078e2f | 2223 | local_irq_restore(flags); |
0e078e2f | 2224 | } |
b8ce3359 | 2225 | |
274cfe59 CG |
2226 | /* |
2227 | * This device has no shutdown method - fully functioning local APICs | |
2228 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2229 | */ | |
2230 | ||
f3c6ea1b | 2231 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2232 | .resume = lapic_resume, |
2233 | .suspend = lapic_suspend, | |
2234 | }; | |
b8ce3359 | 2235 | |
0e078e2f TG |
2236 | static void __cpuinit apic_pm_activate(void) |
2237 | { | |
2238 | apic_pm_state.active = 1; | |
1da177e4 LT |
2239 | } |
2240 | ||
0e078e2f | 2241 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2242 | { |
0e078e2f | 2243 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
f3c6ea1b RW |
2244 | if (cpu_has_apic) |
2245 | register_syscore_ops(&lapic_syscore_ops); | |
e83a5fdc | 2246 | |
f3c6ea1b | 2247 | return 0; |
1da177e4 | 2248 | } |
b24696bc FY |
2249 | |
2250 | /* local apic needs to resume before other devices access its registers. */ | |
2251 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2252 | |
2253 | #else /* CONFIG_PM */ | |
2254 | ||
2255 | static void apic_pm_activate(void) { } | |
2256 | ||
2257 | #endif /* CONFIG_PM */ | |
1da177e4 | 2258 | |
f28c0ae2 | 2259 | #ifdef CONFIG_X86_64 |
e0e42142 YL |
2260 | |
2261 | static int __cpuinit apic_cluster_num(void) | |
1da177e4 LT |
2262 | { |
2263 | int i, clusters, zeros; | |
2264 | unsigned id; | |
322850af | 2265 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2266 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2267 | ||
23ca4bba | 2268 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2269 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2270 | |
168ef543 | 2271 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2272 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2273 | if (bios_cpu_apicid) { |
2274 | id = bios_cpu_apicid[i]; | |
e423e33e | 2275 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2276 | if (cpu_present(i)) |
2277 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2278 | else | |
2279 | continue; | |
e423e33e | 2280 | } else |
e8c10ef9 | 2281 | break; |
2282 | ||
1da177e4 LT |
2283 | if (id != BAD_APICID) |
2284 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2285 | } | |
2286 | ||
2287 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2288 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2289 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2290 | * Since clusters are allocated sequentially, count zeros only if | |
2291 | * they are bounded by ones. | |
1da177e4 LT |
2292 | */ |
2293 | clusters = 0; | |
2294 | zeros = 0; | |
2295 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2296 | if (test_bit(i, clustermap)) { | |
2297 | clusters += 1 + zeros; | |
2298 | zeros = 0; | |
2299 | } else | |
2300 | ++zeros; | |
2301 | } | |
2302 | ||
e0e42142 YL |
2303 | return clusters; |
2304 | } | |
2305 | ||
2306 | static int __cpuinitdata multi_checked; | |
2307 | static int __cpuinitdata multi; | |
2308 | ||
2309 | static int __cpuinit set_multi(const struct dmi_system_id *d) | |
2310 | { | |
2311 | if (multi) | |
2312 | return 0; | |
6f0aced6 | 2313 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2314 | multi = 1; |
2315 | return 0; | |
2316 | } | |
2317 | ||
2318 | static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { | |
2319 | { | |
2320 | .callback = set_multi, | |
2321 | .ident = "IBM System Summit2", | |
2322 | .matches = { | |
2323 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2324 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2325 | }, | |
2326 | }, | |
2327 | {} | |
2328 | }; | |
2329 | ||
2330 | static void __cpuinit dmi_check_multi(void) | |
2331 | { | |
2332 | if (multi_checked) | |
2333 | return; | |
2334 | ||
2335 | dmi_check_system(multi_dmi_table); | |
2336 | multi_checked = 1; | |
2337 | } | |
2338 | ||
2339 | /* | |
2340 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2341 | * | |
2342 | * Thus far, the major user of this is IBM's Summit2 series: | |
2343 | * Clustered boxes may have unsynced TSC problems if they are | |
2344 | * multi-chassis. | |
2345 | * Use DMI to check them | |
2346 | */ | |
2347 | __cpuinit int apic_is_clustered_box(void) | |
2348 | { | |
2349 | dmi_check_multi(); | |
2350 | if (multi) | |
1cb68487 RT |
2351 | return 1; |
2352 | ||
e0e42142 YL |
2353 | if (!is_vsmp_box()) |
2354 | return 0; | |
2355 | ||
1da177e4 | 2356 | /* |
e0e42142 YL |
2357 | * ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2358 | * not guaranteed to be synced between boards | |
1da177e4 | 2359 | */ |
e0e42142 YL |
2360 | if (apic_cluster_num() > 1) |
2361 | return 1; | |
2362 | ||
2363 | return 0; | |
1da177e4 | 2364 | } |
f28c0ae2 | 2365 | #endif |
1da177e4 LT |
2366 | |
2367 | /* | |
0e078e2f | 2368 | * APIC command line parameters |
1da177e4 | 2369 | */ |
789fa735 | 2370 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2371 | { |
1da177e4 | 2372 | disable_apic = 1; |
9175fc06 | 2373 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2374 | return 0; |
2375 | } | |
2376 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2377 | |
2c8c0e6b | 2378 | /* same as disableapic, for compatibility */ |
789fa735 | 2379 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2380 | { |
789fa735 | 2381 | return setup_disableapic(arg); |
6935d1f9 | 2382 | } |
2c8c0e6b | 2383 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2384 | |
2e7c2838 LT |
2385 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2386 | { | |
2387 | local_apic_timer_c2_ok = 1; | |
2388 | return 0; | |
2389 | } | |
2390 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2391 | ||
36fef094 | 2392 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2393 | { |
1da177e4 | 2394 | disable_apic_timer = 1; |
36fef094 | 2395 | return 0; |
6935d1f9 | 2396 | } |
36fef094 CG |
2397 | early_param("noapictimer", parse_disable_apic_timer); |
2398 | ||
2399 | static int __init parse_nolapic_timer(char *arg) | |
2400 | { | |
2401 | disable_apic_timer = 1; | |
2402 | return 0; | |
6935d1f9 | 2403 | } |
36fef094 | 2404 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2405 | |
79af9bec CG |
2406 | static int __init apic_set_verbosity(char *arg) |
2407 | { | |
2408 | if (!arg) { | |
2409 | #ifdef CONFIG_X86_64 | |
2410 | skip_ioapic_setup = 0; | |
79af9bec CG |
2411 | return 0; |
2412 | #endif | |
2413 | return -EINVAL; | |
2414 | } | |
2415 | ||
2416 | if (strcmp("debug", arg) == 0) | |
2417 | apic_verbosity = APIC_DEBUG; | |
2418 | else if (strcmp("verbose", arg) == 0) | |
2419 | apic_verbosity = APIC_VERBOSE; | |
2420 | else { | |
ba21ebb6 | 2421 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2422 | " use apic=verbose or apic=debug\n", arg); |
2423 | return -EINVAL; | |
2424 | } | |
2425 | ||
2426 | return 0; | |
2427 | } | |
2428 | early_param("apic", apic_set_verbosity); | |
2429 | ||
1e934dda YL |
2430 | static int __init lapic_insert_resource(void) |
2431 | { | |
2432 | if (!apic_phys) | |
2433 | return -1; | |
2434 | ||
2435 | /* Put local APIC into the resource map. */ | |
2436 | lapic_resource.start = apic_phys; | |
2437 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2438 | insert_resource(&iomem_resource, &lapic_resource); | |
2439 | ||
2440 | return 0; | |
2441 | } | |
2442 | ||
2443 | /* | |
2444 | * need call insert after e820_reserve_resources() | |
2445 | * that is using request_resource | |
2446 | */ | |
2447 | late_initcall(lapic_insert_resource); |