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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 TG |
76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
77 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 78 | |
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
2a4ab640 FT |
88 | /* IO APIC gsi routing info */ |
89 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
90 | ||
a4384df3 EB |
91 | /* The one past the highest gsi number used */ |
92 | u32 gsi_top; | |
5777372a | 93 | |
584f734d | 94 | /* MP IRQ source entries */ |
c2c21745 | 95 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
96 | |
97 | /* # of MP IRQ source entries */ | |
98 | int mp_irq_entries; | |
99 | ||
bc07844a TG |
100 | /* GSI interrupts */ |
101 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
102 | ||
8732fc4b AS |
103 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
104 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
105 | #endif | |
106 | ||
107 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
108 | ||
efa2559f YL |
109 | int skip_ioapic_setup; |
110 | ||
7167d08e HK |
111 | /** |
112 | * disable_ioapic_support() - disables ioapic support at runtime | |
113 | */ | |
114 | void disable_ioapic_support(void) | |
65a4e574 IM |
115 | { |
116 | #ifdef CONFIG_PCI | |
117 | noioapicquirk = 1; | |
118 | noioapicreroute = -1; | |
119 | #endif | |
120 | skip_ioapic_setup = 1; | |
121 | } | |
122 | ||
54168ed7 | 123 | static int __init parse_noapic(char *str) |
efa2559f YL |
124 | { |
125 | /* disable IO-APIC */ | |
7167d08e | 126 | disable_ioapic_support(); |
efa2559f YL |
127 | return 0; |
128 | } | |
129 | early_param("noapic", parse_noapic); | |
66759a01 | 130 | |
710dcda6 TG |
131 | static int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
132 | struct io_apic_irq_attr *attr); | |
133 | ||
2d8009ba FT |
134 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
135 | void mp_save_irq(struct mpc_intsrc *m) | |
136 | { | |
137 | int i; | |
138 | ||
139 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
140 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
141 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
142 | m->srcbusirq, m->dstapic, m->dstirq); | |
143 | ||
144 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 145 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
146 | return; |
147 | } | |
148 | ||
0e3fa13f | 149 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
150 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
151 | panic("Max # of irq sources exceeded!!\n"); | |
152 | } | |
153 | ||
0b8f1efa YL |
154 | struct irq_pin_list { |
155 | int apic, pin; | |
156 | struct irq_pin_list *next; | |
157 | }; | |
158 | ||
7e495529 | 159 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 160 | { |
2ee39065 | 161 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
162 | } |
163 | ||
2d8009ba | 164 | |
a1420f39 | 165 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 166 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 167 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 168 | #else |
97943390 | 169 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 170 | #endif |
a1420f39 | 171 | |
13a0c3c2 | 172 | int __init arch_early_irq_init(void) |
8f09cd20 | 173 | { |
0b8f1efa | 174 | struct irq_cfg *cfg; |
60c69948 | 175 | int count, node, i; |
d6c88a50 | 176 | |
1f91233c JP |
177 | if (!legacy_pic->nr_legacy_irqs) { |
178 | nr_irqs_gsi = 0; | |
179 | io_apic_irqs = ~0UL; | |
180 | } | |
181 | ||
0b8f1efa YL |
182 | cfg = irq_cfgx; |
183 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 184 | node = cpu_to_node(0); |
8f09cd20 | 185 | |
fbc6bff0 TG |
186 | /* Make sure the legacy interrupts are marked in the bitmap */ |
187 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
188 | ||
0b8f1efa | 189 | for (i = 0; i < count; i++) { |
2c778651 | 190 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
191 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
192 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
193 | /* |
194 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
195 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
196 | */ | |
54b56170 | 197 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
198 | cfg[i].vector = IRQ0_VECTOR + i; |
199 | cpumask_set_cpu(0, cfg[i].domain); | |
200 | } | |
0b8f1efa | 201 | } |
13a0c3c2 YL |
202 | |
203 | return 0; | |
0b8f1efa | 204 | } |
8f09cd20 | 205 | |
0b8f1efa | 206 | #ifdef CONFIG_SPARSE_IRQ |
48b26501 | 207 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 208 | { |
2c778651 | 209 | return irq_get_chip_data(irq); |
8f09cd20 | 210 | } |
d6c88a50 | 211 | |
f981a3dc | 212 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 213 | { |
0b8f1efa | 214 | struct irq_cfg *cfg; |
0f978f45 | 215 | |
2ee39065 | 216 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
217 | if (!cfg) |
218 | return NULL; | |
2ee39065 | 219 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 220 | goto out_cfg; |
2ee39065 | 221 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 222 | goto out_domain; |
0b8f1efa | 223 | return cfg; |
6e2fff50 TG |
224 | out_domain: |
225 | free_cpumask_var(cfg->domain); | |
226 | out_cfg: | |
227 | kfree(cfg); | |
228 | return NULL; | |
8f09cd20 YL |
229 | } |
230 | ||
f981a3dc | 231 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 232 | { |
fbc6bff0 TG |
233 | if (!cfg) |
234 | return; | |
2c778651 | 235 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
236 | free_cpumask_var(cfg->domain); |
237 | free_cpumask_var(cfg->old_domain); | |
238 | kfree(cfg); | |
239 | } | |
240 | ||
0b8f1efa | 241 | #else |
08c33db6 | 242 | |
9338ad6f | 243 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
244 | { |
245 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 246 | } |
1da177e4 | 247 | |
f981a3dc | 248 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
08c33db6 TG |
249 | { |
250 | return irq_cfgx + irq; | |
251 | } | |
252 | ||
f981a3dc | 253 | static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } |
08c33db6 | 254 | |
0b8f1efa YL |
255 | #endif |
256 | ||
08c33db6 TG |
257 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
258 | { | |
259 | int res = irq_alloc_desc_at(at, node); | |
260 | struct irq_cfg *cfg; | |
261 | ||
262 | if (res < 0) { | |
263 | if (res != -EEXIST) | |
264 | return NULL; | |
2c778651 | 265 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
266 | if (cfg) |
267 | return cfg; | |
268 | } | |
269 | ||
f981a3dc | 270 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 271 | if (cfg) |
2c778651 | 272 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
273 | else |
274 | irq_free_desc(at); | |
275 | return cfg; | |
276 | } | |
277 | ||
278 | static int alloc_irq_from(unsigned int from, int node) | |
279 | { | |
280 | return irq_alloc_desc_from(from, node); | |
281 | } | |
282 | ||
283 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
284 | { | |
f981a3dc | 285 | free_irq_cfg(at, cfg); |
08c33db6 TG |
286 | irq_free_desc(at); |
287 | } | |
288 | ||
130fe05d LT |
289 | struct io_apic { |
290 | unsigned int index; | |
291 | unsigned int unused[3]; | |
292 | unsigned int data; | |
0280f7c4 SS |
293 | unsigned int unused2[11]; |
294 | unsigned int eoi; | |
130fe05d LT |
295 | }; |
296 | ||
297 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
298 | { | |
299 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 300 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
301 | } |
302 | ||
0280f7c4 SS |
303 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
304 | { | |
305 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
306 | writel(vector, &io_apic->eoi); | |
307 | } | |
308 | ||
130fe05d LT |
309 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
310 | { | |
311 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
312 | writel(reg, &io_apic->index); | |
313 | return readl(&io_apic->data); | |
314 | } | |
315 | ||
316 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
317 | { | |
318 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
319 | writel(reg, &io_apic->index); | |
320 | writel(value, &io_apic->data); | |
321 | } | |
322 | ||
323 | /* | |
324 | * Re-write a value: to be used for read-modify-write | |
325 | * cycles where the read already set up the index register. | |
326 | * | |
327 | * Older SiS APIC requires we rewrite the index register | |
328 | */ | |
329 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
330 | { | |
54168ed7 | 331 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
332 | |
333 | if (sis_apic_bug) | |
334 | writel(reg, &io_apic->index); | |
130fe05d LT |
335 | writel(value, &io_apic->data); |
336 | } | |
337 | ||
3145e941 | 338 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
339 | { |
340 | struct irq_pin_list *entry; | |
341 | unsigned long flags; | |
047c8fdb | 342 | |
dade7716 | 343 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 344 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
345 | unsigned int reg; |
346 | int pin; | |
347 | ||
047c8fdb YL |
348 | pin = entry->pin; |
349 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
350 | /* Is the remote IRR bit set? */ | |
351 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 352 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
353 | return true; |
354 | } | |
047c8fdb | 355 | } |
dade7716 | 356 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
357 | |
358 | return false; | |
359 | } | |
047c8fdb | 360 | |
cf4c6a2f AK |
361 | union entry_union { |
362 | struct { u32 w1, w2; }; | |
363 | struct IO_APIC_route_entry entry; | |
364 | }; | |
365 | ||
366 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
367 | { | |
368 | union entry_union eu; | |
369 | unsigned long flags; | |
dade7716 | 370 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
371 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
372 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 373 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
374 | return eu.entry; |
375 | } | |
376 | ||
f9dadfa7 LT |
377 | /* |
378 | * When we write a new IO APIC routing entry, we need to write the high | |
379 | * word first! If the mask bit in the low word is clear, we will enable | |
380 | * the interrupt, and we need to make sure the entry is fully populated | |
381 | * before that happens. | |
382 | */ | |
d15512f4 AK |
383 | static void |
384 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 385 | { |
50a8d4d2 F |
386 | union entry_union eu = {{0, 0}}; |
387 | ||
cf4c6a2f | 388 | eu.entry = e; |
f9dadfa7 LT |
389 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
390 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
391 | } |
392 | ||
1a8ce7ff | 393 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
394 | { |
395 | unsigned long flags; | |
dade7716 | 396 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 397 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 398 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
399 | } |
400 | ||
401 | /* | |
402 | * When we mask an IO APIC routing entry, we need to write the low | |
403 | * word first, in order to set the mask bit before we change the | |
404 | * high bits! | |
405 | */ | |
406 | static void ioapic_mask_entry(int apic, int pin) | |
407 | { | |
408 | unsigned long flags; | |
409 | union entry_union eu = { .entry.mask = 1 }; | |
410 | ||
dade7716 | 411 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
412 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
413 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 414 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
415 | } |
416 | ||
1da177e4 LT |
417 | /* |
418 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
419 | * shared ISA-space IRQs, so we have to support them. We are super | |
420 | * fast in the common case, and fast for shared ISA-space IRQs. | |
421 | */ | |
f3d1915a | 422 | static int |
7e495529 | 423 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 424 | { |
2977fb3f | 425 | struct irq_pin_list **last, *entry; |
0f978f45 | 426 | |
2977fb3f CG |
427 | /* don't allow duplicates */ |
428 | last = &cfg->irq_2_pin; | |
429 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 430 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 431 | return 0; |
2977fb3f | 432 | last = &entry->next; |
1da177e4 | 433 | } |
0f978f45 | 434 | |
7e495529 | 435 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 436 | if (!entry) { |
f3d1915a CG |
437 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
438 | node, apic, pin); | |
439 | return -ENOMEM; | |
a7428cd2 | 440 | } |
1da177e4 LT |
441 | entry->apic = apic; |
442 | entry->pin = pin; | |
875e68ec | 443 | |
2977fb3f | 444 | *last = entry; |
f3d1915a CG |
445 | return 0; |
446 | } | |
447 | ||
448 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
449 | { | |
7e495529 | 450 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 451 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
452 | } |
453 | ||
454 | /* | |
455 | * Reroute an IRQ to a different pin. | |
456 | */ | |
85ac16d0 | 457 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
458 | int oldapic, int oldpin, |
459 | int newapic, int newpin) | |
1da177e4 | 460 | { |
535b6429 | 461 | struct irq_pin_list *entry; |
1da177e4 | 462 | |
2977fb3f | 463 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
464 | if (entry->apic == oldapic && entry->pin == oldpin) { |
465 | entry->apic = newapic; | |
466 | entry->pin = newpin; | |
0f978f45 | 467 | /* every one is different, right? */ |
4eea6fff | 468 | return; |
0f978f45 | 469 | } |
1da177e4 | 470 | } |
0f978f45 | 471 | |
4eea6fff JF |
472 | /* old apic/pin didn't exist, so just add new ones */ |
473 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
474 | } |
475 | ||
c29d9db3 SS |
476 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
477 | int mask_and, int mask_or, | |
478 | void (*final)(struct irq_pin_list *entry)) | |
479 | { | |
480 | unsigned int reg, pin; | |
481 | ||
482 | pin = entry->pin; | |
483 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
484 | reg &= mask_and; | |
485 | reg |= mask_or; | |
486 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
487 | if (final) | |
488 | final(entry); | |
489 | } | |
490 | ||
2f210deb JF |
491 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
492 | int mask_and, int mask_or, | |
493 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 494 | { |
87783be4 | 495 | struct irq_pin_list *entry; |
047c8fdb | 496 | |
c29d9db3 SS |
497 | for_each_irq_pin(entry, cfg->irq_2_pin) |
498 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
499 | } | |
500 | ||
501 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
502 | { | |
503 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
504 | IO_APIC_REDIR_MASKED, NULL); | |
505 | } | |
506 | ||
507 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
508 | { | |
509 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
510 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 511 | } |
047c8fdb | 512 | |
7f3e632f | 513 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 514 | { |
87783be4 CG |
515 | /* |
516 | * Synchronize the IO-APIC and the CPU by doing | |
517 | * a dummy read from the IO-APIC | |
518 | */ | |
519 | struct io_apic __iomem *io_apic; | |
520 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 521 | readl(&io_apic->data); |
1da177e4 LT |
522 | } |
523 | ||
dd5f15e5 | 524 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 525 | { |
dd5f15e5 TG |
526 | unsigned long flags; |
527 | ||
528 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 529 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 530 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 531 | } |
1da177e4 | 532 | |
90297c5f | 533 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 534 | { |
90297c5f | 535 | mask_ioapic(data->chip_data); |
dd5f15e5 | 536 | } |
3145e941 | 537 | |
dd5f15e5 TG |
538 | static void __unmask_ioapic(struct irq_cfg *cfg) |
539 | { | |
540 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
541 | } |
542 | ||
dd5f15e5 | 543 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
544 | { |
545 | unsigned long flags; | |
546 | ||
dade7716 | 547 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 548 | __unmask_ioapic(cfg); |
dade7716 | 549 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
550 | } |
551 | ||
90297c5f | 552 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 553 | { |
90297c5f | 554 | unmask_ioapic(data->chip_data); |
3145e941 YL |
555 | } |
556 | ||
1da177e4 LT |
557 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
558 | { | |
559 | struct IO_APIC_route_entry entry; | |
36062448 | 560 | |
1da177e4 | 561 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 562 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
563 | if (entry.delivery_mode == dest_SMI) |
564 | return; | |
1da177e4 LT |
565 | /* |
566 | * Disable it in the IO-APIC irq-routing table: | |
567 | */ | |
f9dadfa7 | 568 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
569 | } |
570 | ||
54168ed7 | 571 | static void clear_IO_APIC (void) |
1da177e4 LT |
572 | { |
573 | int apic, pin; | |
574 | ||
575 | for (apic = 0; apic < nr_ioapics; apic++) | |
576 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
577 | clear_IO_APIC_pin(apic, pin); | |
578 | } | |
579 | ||
54168ed7 | 580 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
581 | /* |
582 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
583 | * specific CPU-side IRQs. | |
584 | */ | |
585 | ||
586 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
587 | static int pirq_entries[MAX_PIRQS] = { |
588 | [0 ... MAX_PIRQS - 1] = -1 | |
589 | }; | |
1da177e4 | 590 | |
1da177e4 LT |
591 | static int __init ioapic_pirq_setup(char *str) |
592 | { | |
593 | int i, max; | |
594 | int ints[MAX_PIRQS+1]; | |
595 | ||
596 | get_options(str, ARRAY_SIZE(ints), ints); | |
597 | ||
1da177e4 LT |
598 | apic_printk(APIC_VERBOSE, KERN_INFO |
599 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
600 | max = MAX_PIRQS; | |
601 | if (ints[0] < MAX_PIRQS) | |
602 | max = ints[0]; | |
603 | ||
604 | for (i = 0; i < max; i++) { | |
605 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
606 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
607 | /* | |
608 | * PIRQs are mapped upside down, usually. | |
609 | */ | |
610 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
611 | } | |
612 | return 1; | |
613 | } | |
614 | ||
615 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
616 | #endif /* CONFIG_X86_32 */ |
617 | ||
b24696bc FY |
618 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
619 | { | |
620 | int apic; | |
621 | struct IO_APIC_route_entry **ioapic_entries; | |
622 | ||
623 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
2ee39065 | 624 | GFP_KERNEL); |
b24696bc FY |
625 | if (!ioapic_entries) |
626 | return 0; | |
627 | ||
628 | for (apic = 0; apic < nr_ioapics; apic++) { | |
629 | ioapic_entries[apic] = | |
630 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
2ee39065 | 631 | nr_ioapic_registers[apic], GFP_KERNEL); |
b24696bc FY |
632 | if (!ioapic_entries[apic]) |
633 | goto nomem; | |
634 | } | |
635 | ||
636 | return ioapic_entries; | |
637 | ||
638 | nomem: | |
639 | while (--apic >= 0) | |
640 | kfree(ioapic_entries[apic]); | |
641 | kfree(ioapic_entries); | |
642 | ||
643 | return 0; | |
644 | } | |
54168ed7 IM |
645 | |
646 | /* | |
05c3dc2c | 647 | * Saves all the IO-APIC RTE's |
54168ed7 | 648 | */ |
b24696bc | 649 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 650 | { |
54168ed7 IM |
651 | int apic, pin; |
652 | ||
b24696bc FY |
653 | if (!ioapic_entries) |
654 | return -ENOMEM; | |
54168ed7 IM |
655 | |
656 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
657 | if (!ioapic_entries[apic]) |
658 | return -ENOMEM; | |
54168ed7 | 659 | |
05c3dc2c | 660 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 661 | ioapic_entries[apic][pin] = |
54168ed7 | 662 | ioapic_read_entry(apic, pin); |
b24696bc | 663 | } |
5ffa4eb2 | 664 | |
54168ed7 IM |
665 | return 0; |
666 | } | |
667 | ||
b24696bc FY |
668 | /* |
669 | * Mask all IO APIC entries. | |
670 | */ | |
671 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
672 | { |
673 | int apic, pin; | |
674 | ||
b24696bc FY |
675 | if (!ioapic_entries) |
676 | return; | |
677 | ||
05c3dc2c | 678 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 679 | if (!ioapic_entries[apic]) |
05c3dc2c | 680 | break; |
b24696bc | 681 | |
05c3dc2c SS |
682 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
683 | struct IO_APIC_route_entry entry; | |
684 | ||
b24696bc | 685 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
686 | if (!entry.mask) { |
687 | entry.mask = 1; | |
688 | ioapic_write_entry(apic, pin, entry); | |
689 | } | |
690 | } | |
691 | } | |
692 | } | |
693 | ||
b24696bc FY |
694 | /* |
695 | * Restore IO APIC entries which was saved in ioapic_entries. | |
696 | */ | |
697 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
698 | { |
699 | int apic, pin; | |
700 | ||
b24696bc FY |
701 | if (!ioapic_entries) |
702 | return -ENOMEM; | |
703 | ||
5ffa4eb2 | 704 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
705 | if (!ioapic_entries[apic]) |
706 | return -ENOMEM; | |
707 | ||
54168ed7 IM |
708 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
709 | ioapic_write_entry(apic, pin, | |
b24696bc | 710 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 711 | } |
b24696bc | 712 | return 0; |
54168ed7 IM |
713 | } |
714 | ||
b24696bc FY |
715 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
716 | { | |
717 | int apic; | |
718 | ||
719 | for (apic = 0; apic < nr_ioapics; apic++) | |
720 | kfree(ioapic_entries[apic]); | |
721 | ||
722 | kfree(ioapic_entries); | |
54168ed7 | 723 | } |
1da177e4 LT |
724 | |
725 | /* | |
726 | * Find the IRQ entry number of a certain pin. | |
727 | */ | |
728 | static int find_irq_entry(int apic, int pin, int type) | |
729 | { | |
730 | int i; | |
731 | ||
732 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
733 | if (mp_irqs[i].irqtype == type && |
734 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
735 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
736 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
737 | return i; |
738 | ||
739 | return -1; | |
740 | } | |
741 | ||
742 | /* | |
743 | * Find the pin to which IRQ[irq] (ISA) is connected | |
744 | */ | |
fcfd636a | 745 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
746 | { |
747 | int i; | |
748 | ||
749 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 750 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 751 | |
d27e2b8e | 752 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
753 | (mp_irqs[i].irqtype == type) && |
754 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 755 | |
c2c21745 | 756 | return mp_irqs[i].dstirq; |
1da177e4 LT |
757 | } |
758 | return -1; | |
759 | } | |
760 | ||
fcfd636a EB |
761 | static int __init find_isa_irq_apic(int irq, int type) |
762 | { | |
763 | int i; | |
764 | ||
765 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 766 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 767 | |
73b2961b | 768 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
769 | (mp_irqs[i].irqtype == type) && |
770 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
771 | break; |
772 | } | |
773 | if (i < mp_irq_entries) { | |
774 | int apic; | |
54168ed7 | 775 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 776 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
777 | return apic; |
778 | } | |
779 | } | |
780 | ||
781 | return -1; | |
782 | } | |
783 | ||
c0a282c2 | 784 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
785 | /* |
786 | * EISA Edge/Level control register, ELCR | |
787 | */ | |
788 | static int EISA_ELCR(unsigned int irq) | |
789 | { | |
b81bb373 | 790 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
791 | unsigned int port = 0x4d0 + (irq >> 3); |
792 | return (inb(port) >> (irq & 7)) & 1; | |
793 | } | |
794 | apic_printk(APIC_VERBOSE, KERN_INFO | |
795 | "Broken MPtable reports ISA irq %d\n", irq); | |
796 | return 0; | |
797 | } | |
54168ed7 | 798 | |
c0a282c2 | 799 | #endif |
1da177e4 | 800 | |
6728801d AS |
801 | /* ISA interrupts are always polarity zero edge triggered, |
802 | * when listed as conforming in the MP table. */ | |
803 | ||
804 | #define default_ISA_trigger(idx) (0) | |
805 | #define default_ISA_polarity(idx) (0) | |
806 | ||
1da177e4 LT |
807 | /* EISA interrupts are always polarity zero and can be edge or level |
808 | * trigger depending on the ELCR value. If an interrupt is listed as | |
809 | * EISA conforming in the MP table, that means its trigger type must | |
810 | * be read in from the ELCR */ | |
811 | ||
c2c21745 | 812 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 813 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
814 | |
815 | /* PCI interrupts are always polarity one level triggered, | |
816 | * when listed as conforming in the MP table. */ | |
817 | ||
818 | #define default_PCI_trigger(idx) (1) | |
819 | #define default_PCI_polarity(idx) (1) | |
820 | ||
821 | /* MCA interrupts are always polarity zero level triggered, | |
822 | * when listed as conforming in the MP table. */ | |
823 | ||
824 | #define default_MCA_trigger(idx) (1) | |
6728801d | 825 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 826 | |
b77cf6a8 | 827 | static int irq_polarity(int idx) |
1da177e4 | 828 | { |
c2c21745 | 829 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
830 | int polarity; |
831 | ||
832 | /* | |
833 | * Determine IRQ line polarity (high active or low active): | |
834 | */ | |
c2c21745 | 835 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 836 | { |
54168ed7 IM |
837 | case 0: /* conforms, ie. bus-type dependent polarity */ |
838 | if (test_bit(bus, mp_bus_not_pci)) | |
839 | polarity = default_ISA_polarity(idx); | |
840 | else | |
841 | polarity = default_PCI_polarity(idx); | |
842 | break; | |
843 | case 1: /* high active */ | |
844 | { | |
845 | polarity = 0; | |
846 | break; | |
847 | } | |
848 | case 2: /* reserved */ | |
849 | { | |
850 | printk(KERN_WARNING "broken BIOS!!\n"); | |
851 | polarity = 1; | |
852 | break; | |
853 | } | |
854 | case 3: /* low active */ | |
855 | { | |
856 | polarity = 1; | |
857 | break; | |
858 | } | |
859 | default: /* invalid */ | |
860 | { | |
861 | printk(KERN_WARNING "broken BIOS!!\n"); | |
862 | polarity = 1; | |
863 | break; | |
864 | } | |
1da177e4 LT |
865 | } |
866 | return polarity; | |
867 | } | |
868 | ||
b77cf6a8 | 869 | static int irq_trigger(int idx) |
1da177e4 | 870 | { |
c2c21745 | 871 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
872 | int trigger; |
873 | ||
874 | /* | |
875 | * Determine IRQ trigger mode (edge or level sensitive): | |
876 | */ | |
c2c21745 | 877 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 878 | { |
54168ed7 IM |
879 | case 0: /* conforms, ie. bus-type dependent */ |
880 | if (test_bit(bus, mp_bus_not_pci)) | |
881 | trigger = default_ISA_trigger(idx); | |
882 | else | |
883 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 884 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
885 | switch (mp_bus_id_to_type[bus]) { |
886 | case MP_BUS_ISA: /* ISA pin */ | |
887 | { | |
888 | /* set before the switch */ | |
889 | break; | |
890 | } | |
891 | case MP_BUS_EISA: /* EISA pin */ | |
892 | { | |
893 | trigger = default_EISA_trigger(idx); | |
894 | break; | |
895 | } | |
896 | case MP_BUS_PCI: /* PCI pin */ | |
897 | { | |
898 | /* set before the switch */ | |
899 | break; | |
900 | } | |
901 | case MP_BUS_MCA: /* MCA pin */ | |
902 | { | |
903 | trigger = default_MCA_trigger(idx); | |
904 | break; | |
905 | } | |
906 | default: | |
907 | { | |
908 | printk(KERN_WARNING "broken BIOS!!\n"); | |
909 | trigger = 1; | |
910 | break; | |
911 | } | |
912 | } | |
913 | #endif | |
1da177e4 | 914 | break; |
54168ed7 | 915 | case 1: /* edge */ |
1da177e4 | 916 | { |
54168ed7 | 917 | trigger = 0; |
1da177e4 LT |
918 | break; |
919 | } | |
54168ed7 | 920 | case 2: /* reserved */ |
1da177e4 | 921 | { |
54168ed7 IM |
922 | printk(KERN_WARNING "broken BIOS!!\n"); |
923 | trigger = 1; | |
1da177e4 LT |
924 | break; |
925 | } | |
54168ed7 | 926 | case 3: /* level */ |
1da177e4 | 927 | { |
54168ed7 | 928 | trigger = 1; |
1da177e4 LT |
929 | break; |
930 | } | |
54168ed7 | 931 | default: /* invalid */ |
1da177e4 LT |
932 | { |
933 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 934 | trigger = 0; |
1da177e4 LT |
935 | break; |
936 | } | |
937 | } | |
938 | return trigger; | |
939 | } | |
940 | ||
1da177e4 LT |
941 | static int pin_2_irq(int idx, int apic, int pin) |
942 | { | |
d464207c | 943 | int irq; |
c2c21745 | 944 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
945 | |
946 | /* | |
947 | * Debugging check, we are in big trouble if this message pops up! | |
948 | */ | |
c2c21745 | 949 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
950 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
951 | ||
54168ed7 | 952 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 953 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 954 | } else { |
d464207c | 955 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
956 | |
957 | if (gsi >= NR_IRQS_LEGACY) | |
958 | irq = gsi; | |
959 | else | |
a4384df3 | 960 | irq = gsi_top + gsi; |
1da177e4 LT |
961 | } |
962 | ||
54168ed7 | 963 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
964 | /* |
965 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
966 | */ | |
967 | if ((pin >= 16) && (pin <= 23)) { | |
968 | if (pirq_entries[pin-16] != -1) { | |
969 | if (!pirq_entries[pin-16]) { | |
970 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
971 | "disabling PIRQ%d\n", pin-16); | |
972 | } else { | |
973 | irq = pirq_entries[pin-16]; | |
974 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
975 | "using PIRQ%d -> IRQ %d\n", | |
976 | pin-16, irq); | |
977 | } | |
978 | } | |
979 | } | |
54168ed7 IM |
980 | #endif |
981 | ||
1da177e4 LT |
982 | return irq; |
983 | } | |
984 | ||
e20c06fd YL |
985 | /* |
986 | * Find a specific PCI IRQ entry. | |
987 | * Not an __init, possibly needed by modules | |
988 | */ | |
989 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 990 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
991 | { |
992 | int apic, i, best_guess = -1; | |
993 | ||
994 | apic_printk(APIC_DEBUG, | |
995 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
996 | bus, slot, pin); | |
997 | if (test_bit(bus, mp_bus_not_pci)) { | |
998 | apic_printk(APIC_VERBOSE, | |
999 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1000 | return -1; | |
1001 | } | |
1002 | for (i = 0; i < mp_irq_entries; i++) { | |
1003 | int lbus = mp_irqs[i].srcbus; | |
1004 | ||
1005 | for (apic = 0; apic < nr_ioapics; apic++) | |
1006 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1007 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1008 | break; | |
1009 | ||
1010 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1011 | !mp_irqs[i].irqtype && | |
1012 | (bus == lbus) && | |
1013 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1014 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1015 | ||
1016 | if (!(apic || IO_APIC_IRQ(irq))) | |
1017 | continue; | |
1018 | ||
1019 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1020 | set_io_apic_irq_attr(irq_attr, apic, |
1021 | mp_irqs[i].dstirq, | |
1022 | irq_trigger(i), | |
1023 | irq_polarity(i)); | |
e20c06fd YL |
1024 | return irq; |
1025 | } | |
1026 | /* | |
1027 | * Use the first all-but-pin matching entry as a | |
1028 | * best-guess fuzzy result for broken mptables. | |
1029 | */ | |
1030 | if (best_guess < 0) { | |
e5198075 YL |
1031 | set_io_apic_irq_attr(irq_attr, apic, |
1032 | mp_irqs[i].dstirq, | |
1033 | irq_trigger(i), | |
1034 | irq_polarity(i)); | |
e20c06fd YL |
1035 | best_guess = irq; |
1036 | } | |
1037 | } | |
1038 | } | |
1039 | return best_guess; | |
1040 | } | |
1041 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1042 | ||
497c9a19 YL |
1043 | void lock_vector_lock(void) |
1044 | { | |
1045 | /* Used to the online set of cpus does not change | |
1046 | * during assign_irq_vector. | |
1047 | */ | |
dade7716 | 1048 | raw_spin_lock(&vector_lock); |
497c9a19 | 1049 | } |
1da177e4 | 1050 | |
497c9a19 | 1051 | void unlock_vector_lock(void) |
1da177e4 | 1052 | { |
dade7716 | 1053 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1054 | } |
1da177e4 | 1055 | |
e7986739 MT |
1056 | static int |
1057 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1058 | { |
047c8fdb YL |
1059 | /* |
1060 | * NOTE! The local APIC isn't very good at handling | |
1061 | * multiple interrupts at the same interrupt level. | |
1062 | * As the interrupt level is determined by taking the | |
1063 | * vector number and shifting that right by 4, we | |
1064 | * want to spread these out a bit so that they don't | |
1065 | * all fall in the same interrupt level. | |
1066 | * | |
1067 | * Also, we've got to be careful not to trash gate | |
1068 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1069 | */ | |
6579b474 | 1070 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1071 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1072 | unsigned int old_vector; |
22f65d31 MT |
1073 | int cpu, err; |
1074 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1075 | |
23359a88 | 1076 | if (cfg->move_in_progress) |
54168ed7 | 1077 | return -EBUSY; |
0a1ad60d | 1078 | |
22f65d31 MT |
1079 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1080 | return -ENOMEM; | |
ace80ab7 | 1081 | |
54168ed7 IM |
1082 | old_vector = cfg->vector; |
1083 | if (old_vector) { | |
22f65d31 MT |
1084 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1085 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1086 | if (!cpumask_empty(tmp_mask)) { | |
1087 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1088 | return 0; |
22f65d31 | 1089 | } |
54168ed7 | 1090 | } |
497c9a19 | 1091 | |
e7986739 | 1092 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1093 | err = -ENOSPC; |
1094 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1095 | int new_cpu; |
1096 | int vector, offset; | |
497c9a19 | 1097 | |
e2d40b18 | 1098 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1099 | |
54168ed7 IM |
1100 | vector = current_vector; |
1101 | offset = current_offset; | |
497c9a19 | 1102 | next: |
54168ed7 IM |
1103 | vector += 8; |
1104 | if (vector >= first_system_vector) { | |
e7986739 | 1105 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1106 | offset = (offset + 1) % 8; |
6579b474 | 1107 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1108 | } |
1109 | if (unlikely(current_vector == vector)) | |
1110 | continue; | |
b77b881f YL |
1111 | |
1112 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1113 | goto next; |
b77b881f | 1114 | |
22f65d31 | 1115 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1116 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1117 | goto next; | |
1118 | /* Found one! */ | |
1119 | current_vector = vector; | |
1120 | current_offset = offset; | |
1121 | if (old_vector) { | |
1122 | cfg->move_in_progress = 1; | |
22f65d31 | 1123 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1124 | } |
22f65d31 | 1125 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1126 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1127 | cfg->vector = vector; | |
22f65d31 MT |
1128 | cpumask_copy(cfg->domain, tmp_mask); |
1129 | err = 0; | |
1130 | break; | |
54168ed7 | 1131 | } |
22f65d31 MT |
1132 | free_cpumask_var(tmp_mask); |
1133 | return err; | |
497c9a19 YL |
1134 | } |
1135 | ||
9338ad6f | 1136 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1137 | { |
1138 | int err; | |
ace80ab7 | 1139 | unsigned long flags; |
ace80ab7 | 1140 | |
dade7716 | 1141 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1142 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1143 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1144 | return err; |
1145 | } | |
1146 | ||
3145e941 | 1147 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1148 | { |
497c9a19 YL |
1149 | int cpu, vector; |
1150 | ||
497c9a19 YL |
1151 | BUG_ON(!cfg->vector); |
1152 | ||
1153 | vector = cfg->vector; | |
22f65d31 | 1154 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1155 | per_cpu(vector_irq, cpu)[vector] = -1; |
1156 | ||
1157 | cfg->vector = 0; | |
22f65d31 | 1158 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1159 | |
1160 | if (likely(!cfg->move_in_progress)) | |
1161 | return; | |
22f65d31 | 1162 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1163 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1164 | vector++) { | |
1165 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1166 | continue; | |
1167 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1168 | break; | |
1169 | } | |
1170 | } | |
1171 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1172 | } |
1173 | ||
1174 | void __setup_vector_irq(int cpu) | |
1175 | { | |
1176 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1177 | int irq, vector; |
1178 | struct irq_cfg *cfg; | |
1179 | ||
9d133e5d SS |
1180 | /* |
1181 | * vector_lock will make sure that we don't run into irq vector | |
1182 | * assignments that might be happening on another cpu in parallel, | |
1183 | * while we setup our initial vector to irq mappings. | |
1184 | */ | |
dade7716 | 1185 | raw_spin_lock(&vector_lock); |
497c9a19 | 1186 | /* Mark the inuse vectors */ |
ad9f4334 | 1187 | for_each_active_irq(irq) { |
2c778651 | 1188 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1189 | if (!cfg) |
1190 | continue; | |
36e9e1ea SS |
1191 | /* |
1192 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1193 | * will be part of the irq_cfg's domain. | |
1194 | */ | |
1195 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1196 | cpumask_set_cpu(cpu, cfg->domain); | |
1197 | ||
22f65d31 | 1198 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1199 | continue; |
1200 | vector = cfg->vector; | |
497c9a19 YL |
1201 | per_cpu(vector_irq, cpu)[vector] = irq; |
1202 | } | |
1203 | /* Mark the free vectors */ | |
1204 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1205 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1206 | if (irq < 0) | |
1207 | continue; | |
1208 | ||
1209 | cfg = irq_cfg(irq); | |
22f65d31 | 1210 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1211 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1212 | } |
dade7716 | 1213 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1214 | } |
3fde6900 | 1215 | |
f5b9ed7a | 1216 | static struct irq_chip ioapic_chip; |
54168ed7 | 1217 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1218 | |
047c8fdb | 1219 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1220 | static inline int IO_APIC_irq_trigger(int irq) |
1221 | { | |
d6c88a50 | 1222 | int apic, idx, pin; |
1d025192 | 1223 | |
d6c88a50 TG |
1224 | for (apic = 0; apic < nr_ioapics; apic++) { |
1225 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1226 | idx = find_irq_entry(apic, pin, mp_INT); | |
1227 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1228 | return irq_trigger(idx); | |
1229 | } | |
1230 | } | |
1231 | /* | |
54168ed7 IM |
1232 | * nonexistent IRQs are edge default |
1233 | */ | |
d6c88a50 | 1234 | return 0; |
1d025192 | 1235 | } |
047c8fdb YL |
1236 | #else |
1237 | static inline int IO_APIC_irq_trigger(int irq) | |
1238 | { | |
54168ed7 | 1239 | return 1; |
047c8fdb YL |
1240 | } |
1241 | #endif | |
1d025192 | 1242 | |
1a0e62a4 TG |
1243 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1244 | unsigned long trigger) | |
1da177e4 | 1245 | { |
c60eaf25 TG |
1246 | struct irq_chip *chip = &ioapic_chip; |
1247 | irq_flow_handler_t hdl; | |
1248 | bool fasteoi; | |
199751d7 | 1249 | |
6ebcc00e | 1250 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1251 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1252 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1253 | fasteoi = true; |
1254 | } else { | |
60c69948 | 1255 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1256 | fasteoi = false; |
1257 | } | |
047c8fdb | 1258 | |
1a0e62a4 | 1259 | if (irq_remapped(cfg)) { |
60c69948 | 1260 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
1261 | chip = &ir_ioapic_chip; |
1262 | fasteoi = trigger != 0; | |
54168ed7 | 1263 | } |
29b61be6 | 1264 | |
c60eaf25 TG |
1265 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1266 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1267 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1268 | } |
1269 | ||
1a8ce7ff TG |
1270 | static int setup_ioapic_entry(int apic_id, int irq, |
1271 | struct IO_APIC_route_entry *entry, | |
1272 | unsigned int destination, int trigger, | |
1273 | int polarity, int vector, int pin) | |
1da177e4 | 1274 | { |
497c9a19 YL |
1275 | /* |
1276 | * add it to the IO-APIC irq-routing table: | |
1277 | */ | |
1278 | memset(entry,0,sizeof(*entry)); | |
1279 | ||
54168ed7 | 1280 | if (intr_remapping_enabled) { |
c8d46cf0 | 1281 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1282 | struct irte irte; |
1283 | struct IR_IO_APIC_route_entry *ir_entry = | |
1284 | (struct IR_IO_APIC_route_entry *) entry; | |
1285 | int index; | |
1286 | ||
1287 | if (!iommu) | |
c8d46cf0 | 1288 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1289 | |
1290 | index = alloc_irte(iommu, irq, 1); | |
1291 | if (index < 0) | |
c8d46cf0 | 1292 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1293 | |
62a92f4c | 1294 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1295 | |
f007e99c WH |
1296 | /* Set source-id of interrupt request */ |
1297 | set_ioapic_sid(&irte, apic_id); | |
1298 | ||
54168ed7 IM |
1299 | modify_irte(irq, &irte); |
1300 | ||
1301 | ir_entry->index2 = (index >> 15) & 0x1; | |
1302 | ir_entry->zero = 0; | |
1303 | ir_entry->format = 1; | |
1304 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1305 | /* |
1306 | * IO-APIC RTE will be configured with virtual vector. | |
1307 | * irq handler will do the explicit EOI to the io-apic. | |
1308 | */ | |
1309 | ir_entry->vector = pin; | |
29b61be6 | 1310 | } else { |
9b5bc8dc IM |
1311 | entry->delivery_mode = apic->irq_delivery_mode; |
1312 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1313 | entry->dest = destination; |
0280f7c4 | 1314 | entry->vector = vector; |
54168ed7 | 1315 | } |
497c9a19 | 1316 | |
54168ed7 | 1317 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1318 | entry->trigger = trigger; |
1319 | entry->polarity = polarity; | |
497c9a19 YL |
1320 | |
1321 | /* Mask level triggered irqs. | |
1322 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1323 | */ | |
1324 | if (trigger) | |
1325 | entry->mask = 1; | |
497c9a19 YL |
1326 | return 0; |
1327 | } | |
1328 | ||
60c69948 TG |
1329 | static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, |
1330 | struct irq_cfg *cfg, int trigger, int polarity) | |
497c9a19 | 1331 | { |
1da177e4 | 1332 | struct IO_APIC_route_entry entry; |
22f65d31 | 1333 | unsigned int dest; |
497c9a19 YL |
1334 | |
1335 | if (!IO_APIC_IRQ(irq)) | |
1336 | return; | |
69c89efb SS |
1337 | /* |
1338 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1339 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1340 | * the cfg->domain. | |
1341 | */ | |
28c6a0ba | 1342 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1343 | apic->vector_allocation_domain(0, cfg->domain); |
1344 | ||
fe402e1f | 1345 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1346 | return; |
1347 | ||
debccb3e | 1348 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1349 | |
1350 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1351 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1352 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1353 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1354 | irq, trigger, polarity); |
1355 | ||
1356 | ||
c8d46cf0 | 1357 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1358 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1359 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1360 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1361 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1362 | return; |
1363 | } | |
1364 | ||
1a0e62a4 | 1365 | ioapic_register_intr(irq, cfg, trigger); |
b81bb373 | 1366 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1367 | legacy_pic->mask(irq); |
497c9a19 | 1368 | |
c8d46cf0 | 1369 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1370 | } |
1371 | ||
b9c61b70 YL |
1372 | static struct { |
1373 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1374 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1375 | ||
c8d6b8fe TG |
1376 | static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) |
1377 | { | |
1378 | if (idx != -1) | |
1379 | return false; | |
1380 | ||
1381 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
1382 | mp_ioapics[apic_id].apicid, pin); | |
1383 | return true; | |
1384 | } | |
1385 | ||
ed972ccf | 1386 | static void __init __io_apic_setup_irqs(unsigned int apic_id) |
497c9a19 | 1387 | { |
ed972ccf | 1388 | int idx, node = cpu_to_node(0); |
2d57e37d | 1389 | struct io_apic_irq_attr attr; |
ed972ccf | 1390 | unsigned int pin, irq; |
1da177e4 | 1391 | |
b9c61b70 YL |
1392 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1393 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
c8d6b8fe | 1394 | if (io_apic_pin_not_connected(idx, apic_id, pin)) |
b9c61b70 | 1395 | continue; |
33a201fa | 1396 | |
b9c61b70 | 1397 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1398 | |
fad53995 EB |
1399 | if ((apic_id > 0) && (irq > 16)) |
1400 | continue; | |
1401 | ||
b9c61b70 YL |
1402 | /* |
1403 | * Skip the timer IRQ if there's a quirk handler | |
1404 | * installed and if it returns 1: | |
1405 | */ | |
1406 | if (apic->multi_timer_check && | |
2d57e37d | 1407 | apic->multi_timer_check(apic_id, irq)) |
b9c61b70 | 1408 | continue; |
36062448 | 1409 | |
2d57e37d TG |
1410 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1411 | irq_polarity(idx)); | |
fbc6bff0 | 1412 | |
2d57e37d | 1413 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1414 | } |
1da177e4 LT |
1415 | } |
1416 | ||
ed972ccf TG |
1417 | static void __init setup_IO_APIC_irqs(void) |
1418 | { | |
1419 | unsigned int apic_id; | |
1420 | ||
1421 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1422 | ||
1423 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) | |
1424 | __io_apic_setup_irqs(apic_id); | |
1425 | } | |
1426 | ||
18dce6ba YL |
1427 | /* |
1428 | * for the gsit that is not in first ioapic | |
1429 | * but could not use acpi_register_gsi() | |
1430 | * like some special sci in IBM x3330 | |
1431 | */ | |
1432 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1433 | { | |
fbc6bff0 | 1434 | int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1435 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1436 | |
1437 | /* | |
1438 | * Convert 'gsi' to 'ioapic.pin'. | |
1439 | */ | |
1440 | apic_id = mp_find_ioapic(gsi); | |
1441 | if (apic_id < 0) | |
1442 | return; | |
1443 | ||
1444 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1445 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1446 | if (idx == -1) | |
1447 | return; | |
1448 | ||
1449 | irq = pin_2_irq(idx, apic_id, pin); | |
fe6dab4e YL |
1450 | |
1451 | /* Only handle the non legacy irqs on secondary ioapics */ | |
1452 | if (apic_id == 0 || irq < NR_IRQS_LEGACY) | |
18dce6ba | 1453 | return; |
fe6dab4e | 1454 | |
da1ad9d7 TG |
1455 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1456 | irq_polarity(idx)); | |
1457 | ||
710dcda6 | 1458 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1459 | } |
1460 | ||
1da177e4 | 1461 | /* |
f7633ce5 | 1462 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1463 | */ |
c8d46cf0 | 1464 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1465 | int vector) |
1da177e4 LT |
1466 | { |
1467 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1468 | |
54168ed7 IM |
1469 | if (intr_remapping_enabled) |
1470 | return; | |
54168ed7 | 1471 | |
36062448 | 1472 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1473 | |
1474 | /* | |
1475 | * We use logical delivery to get the timer IRQ | |
1476 | * to the first CPU. | |
1477 | */ | |
9b5bc8dc | 1478 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1479 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1480 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1481 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1482 | entry.polarity = 0; |
1483 | entry.trigger = 0; | |
1484 | entry.vector = vector; | |
1485 | ||
1486 | /* | |
1487 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1488 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1489 | */ |
2c778651 TG |
1490 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1491 | "edge"); | |
1da177e4 LT |
1492 | |
1493 | /* | |
1494 | * Add it to the IO-APIC irq-routing table: | |
1495 | */ | |
c8d46cf0 | 1496 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1497 | } |
1498 | ||
32f71aff MR |
1499 | |
1500 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1501 | { |
1502 | int apic, i; | |
1503 | union IO_APIC_reg_00 reg_00; | |
1504 | union IO_APIC_reg_01 reg_01; | |
1505 | union IO_APIC_reg_02 reg_02; | |
1506 | union IO_APIC_reg_03 reg_03; | |
1507 | unsigned long flags; | |
0f978f45 | 1508 | struct irq_cfg *cfg; |
8f09cd20 | 1509 | unsigned int irq; |
1da177e4 | 1510 | |
36062448 | 1511 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1512 | for (i = 0; i < nr_ioapics; i++) |
1513 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1514 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1515 | |
1516 | /* | |
1517 | * We are a bit conservative about what we expect. We have to | |
1518 | * know about every hardware change ASAP. | |
1519 | */ | |
1520 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1521 | ||
1522 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1523 | ||
dade7716 | 1524 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1525 | reg_00.raw = io_apic_read(apic, 0); |
1526 | reg_01.raw = io_apic_read(apic, 1); | |
1527 | if (reg_01.bits.version >= 0x10) | |
1528 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1529 | if (reg_01.bits.version >= 0x20) |
1530 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1531 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1532 | |
54168ed7 | 1533 | printk("\n"); |
b5ba7e6d | 1534 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1535 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1536 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1537 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1538 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1539 | |
54168ed7 | 1540 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1541 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1542 | |
1543 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1544 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1545 | |
1546 | /* | |
1547 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1548 | * but the value of reg_02 is read as the previous read register | |
1549 | * value, so ignore it if reg_02 == reg_01. | |
1550 | */ | |
1551 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1552 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1553 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1554 | } |
1555 | ||
1556 | /* | |
1557 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1558 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1559 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1560 | */ | |
1561 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1562 | reg_03.raw != reg_01.raw) { | |
1563 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1564 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1565 | } |
1566 | ||
1567 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1568 | ||
d83e94ac | 1569 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1570 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1571 | |
1572 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1573 | struct IO_APIC_route_entry entry; | |
1574 | ||
cf4c6a2f | 1575 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1576 | |
54168ed7 IM |
1577 | printk(KERN_DEBUG " %02x %03X ", |
1578 | i, | |
1579 | entry.dest | |
1580 | ); | |
1da177e4 LT |
1581 | |
1582 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1583 | entry.mask, | |
1584 | entry.trigger, | |
1585 | entry.irr, | |
1586 | entry.polarity, | |
1587 | entry.delivery_status, | |
1588 | entry.dest_mode, | |
1589 | entry.delivery_mode, | |
1590 | entry.vector | |
1591 | ); | |
1592 | } | |
1593 | } | |
1da177e4 | 1594 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1595 | for_each_active_irq(irq) { |
0b8f1efa YL |
1596 | struct irq_pin_list *entry; |
1597 | ||
2c778651 | 1598 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1599 | if (!cfg) |
1600 | continue; | |
0b8f1efa | 1601 | entry = cfg->irq_2_pin; |
0f978f45 | 1602 | if (!entry) |
1da177e4 | 1603 | continue; |
8f09cd20 | 1604 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1605 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1606 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1607 | printk("\n"); |
1608 | } | |
1609 | ||
1610 | printk(KERN_INFO ".................................... done.\n"); | |
1611 | ||
1612 | return; | |
1613 | } | |
1614 | ||
251e1e44 | 1615 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1616 | { |
251e1e44 | 1617 | int i; |
1da177e4 | 1618 | |
251e1e44 IM |
1619 | printk(KERN_DEBUG); |
1620 | ||
1621 | for (i = 0; i < 8; i++) | |
1622 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1623 | ||
1624 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1625 | } |
1626 | ||
32f71aff | 1627 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1628 | { |
97a52714 | 1629 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1630 | u64 icr; |
1da177e4 | 1631 | |
251e1e44 | 1632 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1633 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1634 | v = apic_read(APIC_ID); |
54168ed7 | 1635 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1636 | v = apic_read(APIC_LVR); |
1637 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1638 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1639 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1640 | |
1641 | v = apic_read(APIC_TASKPRI); | |
1642 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1643 | ||
54168ed7 | 1644 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1645 | if (!APIC_XAPIC(ver)) { |
1646 | v = apic_read(APIC_ARBPRI); | |
1647 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1648 | v & APIC_ARBPRI_MASK); | |
1649 | } | |
1da177e4 LT |
1650 | v = apic_read(APIC_PROCPRI); |
1651 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1652 | } | |
1653 | ||
a11b5abe YL |
1654 | /* |
1655 | * Remote read supported only in the 82489DX and local APIC for | |
1656 | * Pentium processors. | |
1657 | */ | |
1658 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1659 | v = apic_read(APIC_RRR); | |
1660 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1661 | } | |
1662 | ||
1da177e4 LT |
1663 | v = apic_read(APIC_LDR); |
1664 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1665 | if (!x2apic_enabled()) { |
1666 | v = apic_read(APIC_DFR); | |
1667 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1668 | } | |
1da177e4 LT |
1669 | v = apic_read(APIC_SPIV); |
1670 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1671 | ||
1672 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1673 | print_APIC_field(APIC_ISR); |
1da177e4 | 1674 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1675 | print_APIC_field(APIC_TMR); |
1da177e4 | 1676 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1677 | print_APIC_field(APIC_IRR); |
1da177e4 | 1678 | |
54168ed7 IM |
1679 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1680 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1681 | apic_write(APIC_ESR, 0); |
54168ed7 | 1682 | |
1da177e4 LT |
1683 | v = apic_read(APIC_ESR); |
1684 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1685 | } | |
1686 | ||
7ab6af7a | 1687 | icr = apic_icr_read(); |
0c425cec IM |
1688 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1689 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1690 | |
1691 | v = apic_read(APIC_LVTT); | |
1692 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1693 | ||
1694 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1695 | v = apic_read(APIC_LVTPC); | |
1696 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1697 | } | |
1698 | v = apic_read(APIC_LVT0); | |
1699 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1700 | v = apic_read(APIC_LVT1); | |
1701 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1702 | ||
1703 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1704 | v = apic_read(APIC_LVTERR); | |
1705 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1706 | } | |
1707 | ||
1708 | v = apic_read(APIC_TMICT); | |
1709 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1710 | v = apic_read(APIC_TMCCT); | |
1711 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1712 | v = apic_read(APIC_TDCR); | |
1713 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1714 | |
1715 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1716 | v = apic_read(APIC_EFEAT); | |
1717 | maxlvt = (v >> 16) & 0xff; | |
1718 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1719 | v = apic_read(APIC_ECTRL); | |
1720 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1721 | for (i = 0; i < maxlvt; i++) { | |
1722 | v = apic_read(APIC_EILVTn(i)); | |
1723 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1724 | } | |
1725 | } | |
1da177e4 LT |
1726 | printk("\n"); |
1727 | } | |
1728 | ||
2626eb2b | 1729 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1730 | { |
ffd5aae7 YL |
1731 | int cpu; |
1732 | ||
2626eb2b CG |
1733 | if (!maxcpu) |
1734 | return; | |
1735 | ||
ffd5aae7 | 1736 | preempt_disable(); |
2626eb2b CG |
1737 | for_each_online_cpu(cpu) { |
1738 | if (cpu >= maxcpu) | |
1739 | break; | |
ffd5aae7 | 1740 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1741 | } |
ffd5aae7 | 1742 | preempt_enable(); |
1da177e4 LT |
1743 | } |
1744 | ||
32f71aff | 1745 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1746 | { |
1da177e4 LT |
1747 | unsigned int v; |
1748 | unsigned long flags; | |
1749 | ||
b81bb373 | 1750 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1751 | return; |
1752 | ||
1753 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1754 | ||
5619c280 | 1755 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1756 | |
1757 | v = inb(0xa1) << 8 | inb(0x21); | |
1758 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1759 | ||
1760 | v = inb(0xa0) << 8 | inb(0x20); | |
1761 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1762 | ||
54168ed7 IM |
1763 | outb(0x0b,0xa0); |
1764 | outb(0x0b,0x20); | |
1da177e4 | 1765 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1766 | outb(0x0a,0xa0); |
1767 | outb(0x0a,0x20); | |
1da177e4 | 1768 | |
5619c280 | 1769 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1770 | |
1771 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1772 | ||
1773 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1774 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1775 | } | |
1776 | ||
2626eb2b CG |
1777 | static int __initdata show_lapic = 1; |
1778 | static __init int setup_show_lapic(char *arg) | |
1779 | { | |
1780 | int num = -1; | |
1781 | ||
1782 | if (strcmp(arg, "all") == 0) { | |
1783 | show_lapic = CONFIG_NR_CPUS; | |
1784 | } else { | |
1785 | get_option(&arg, &num); | |
1786 | if (num >= 0) | |
1787 | show_lapic = num; | |
1788 | } | |
1789 | ||
1790 | return 1; | |
1791 | } | |
1792 | __setup("show_lapic=", setup_show_lapic); | |
1793 | ||
1794 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1795 | { |
2626eb2b CG |
1796 | if (apic_verbosity == APIC_QUIET) |
1797 | return 0; | |
1798 | ||
32f71aff | 1799 | print_PIC(); |
4797f6b0 YL |
1800 | |
1801 | /* don't print out if apic is not there */ | |
8312136f | 1802 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1803 | return 0; |
1804 | ||
2626eb2b | 1805 | print_local_APICs(show_lapic); |
32f71aff MR |
1806 | print_IO_APIC(); |
1807 | ||
1808 | return 0; | |
1809 | } | |
1810 | ||
2626eb2b | 1811 | fs_initcall(print_ICs); |
32f71aff | 1812 | |
1da177e4 | 1813 | |
efa2559f YL |
1814 | /* Where if anywhere is the i8259 connect in external int mode */ |
1815 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1816 | ||
54168ed7 | 1817 | void __init enable_IO_APIC(void) |
1da177e4 | 1818 | { |
fcfd636a | 1819 | int i8259_apic, i8259_pin; |
54168ed7 | 1820 | int apic; |
bc07844a | 1821 | |
b81bb373 | 1822 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1823 | return; |
1824 | ||
54168ed7 | 1825 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1826 | int pin; |
1827 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1828 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1829 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1830 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1831 | |
fcfd636a EB |
1832 | /* If the interrupt line is enabled and in ExtInt mode |
1833 | * I have found the pin where the i8259 is connected. | |
1834 | */ | |
1835 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1836 | ioapic_i8259.apic = apic; | |
1837 | ioapic_i8259.pin = pin; | |
1838 | goto found_i8259; | |
1839 | } | |
1840 | } | |
1841 | } | |
1842 | found_i8259: | |
1843 | /* Look to see what if the MP table has reported the ExtINT */ | |
1844 | /* If we could not find the appropriate pin by looking at the ioapic | |
1845 | * the i8259 probably is not connected the ioapic but give the | |
1846 | * mptable a chance anyway. | |
1847 | */ | |
1848 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1849 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1850 | /* Trust the MP table if nothing is setup in the hardware */ | |
1851 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1852 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1853 | ioapic_i8259.pin = i8259_pin; | |
1854 | ioapic_i8259.apic = i8259_apic; | |
1855 | } | |
1856 | /* Complain if the MP table and the hardware disagree */ | |
1857 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1858 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1859 | { | |
1860 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1861 | } |
1862 | ||
1863 | /* | |
1864 | * Do not trust the IO-APIC being empty at bootup | |
1865 | */ | |
1866 | clear_IO_APIC(); | |
1867 | } | |
1868 | ||
1869 | /* | |
1870 | * Not an __init, needed by the reboot code | |
1871 | */ | |
1872 | void disable_IO_APIC(void) | |
1873 | { | |
1874 | /* | |
1875 | * Clear the IO-APIC before rebooting: | |
1876 | */ | |
1877 | clear_IO_APIC(); | |
1878 | ||
b81bb373 | 1879 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1880 | return; |
1881 | ||
650927ef | 1882 | /* |
0b968d23 | 1883 | * If the i8259 is routed through an IOAPIC |
650927ef | 1884 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1885 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1886 | * |
1887 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1888 | * as virtual wire B is little complex (need to configure both | |
0d2eb44f | 1889 | * IOAPIC RTE as well as interrupt-remapping table entry). |
7c6d9f97 | 1890 | * As this gets called during crash dump, keep this simple for now. |
650927ef | 1891 | */ |
7c6d9f97 | 1892 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1893 | struct IO_APIC_route_entry entry; |
650927ef EB |
1894 | |
1895 | memset(&entry, 0, sizeof(entry)); | |
1896 | entry.mask = 0; /* Enabled */ | |
1897 | entry.trigger = 0; /* Edge */ | |
1898 | entry.irr = 0; | |
1899 | entry.polarity = 0; /* High */ | |
1900 | entry.delivery_status = 0; | |
1901 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1902 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1903 | entry.vector = 0; |
54168ed7 | 1904 | entry.dest = read_apic_id(); |
650927ef EB |
1905 | |
1906 | /* | |
1907 | * Add it to the IO-APIC irq-routing table: | |
1908 | */ | |
cf4c6a2f | 1909 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1910 | } |
54168ed7 | 1911 | |
7c6d9f97 SS |
1912 | /* |
1913 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1914 | */ | |
8312136f | 1915 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1916 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1917 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1918 | } |
1919 | ||
54168ed7 | 1920 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1921 | /* |
1922 | * function to set the IO-APIC physical IDs based on the | |
1923 | * values stored in the MPC table. | |
1924 | * | |
1925 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1926 | */ | |
a38c5380 | 1927 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1928 | { |
1929 | union IO_APIC_reg_00 reg_00; | |
1930 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1931 | int apic_id; |
1da177e4 LT |
1932 | int i; |
1933 | unsigned char old_id; | |
1934 | unsigned long flags; | |
1935 | ||
1936 | /* | |
1937 | * This is broken; anything with a real cpu count has to | |
1938 | * circumvent this idiocy regardless. | |
1939 | */ | |
7abc0753 | 1940 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1941 | |
1942 | /* | |
1943 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1944 | */ | |
c8d46cf0 | 1945 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
1946 | |
1947 | /* Read the register 0 value */ | |
dade7716 | 1948 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1949 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1950 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1951 | |
c8d46cf0 | 1952 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 1953 | |
c8d46cf0 | 1954 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 1955 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 1956 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1957 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1958 | reg_00.bits.ID); | |
c8d46cf0 | 1959 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
1960 | } |
1961 | ||
1da177e4 LT |
1962 | /* |
1963 | * Sanity check, is the ID really free? Every APIC in a | |
1964 | * system must have a unique ID or we get lots of nice | |
1965 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1966 | */ | |
7abc0753 | 1967 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 1968 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 1969 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 1970 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1971 | for (i = 0; i < get_physical_broadcast(); i++) |
1972 | if (!physid_isset(i, phys_id_present_map)) | |
1973 | break; | |
1974 | if (i >= get_physical_broadcast()) | |
1975 | panic("Max APIC ID exceeded!\n"); | |
1976 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1977 | i); | |
1978 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 1979 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
1980 | } else { |
1981 | physid_mask_t tmp; | |
7abc0753 | 1982 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
1983 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1984 | "phys_id_present_map\n", | |
c8d46cf0 | 1985 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1986 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1987 | } | |
1988 | ||
1da177e4 LT |
1989 | /* |
1990 | * We need to adjust the IRQ routing table | |
1991 | * if the ID changed. | |
1992 | */ | |
c8d46cf0 | 1993 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 1994 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1995 | if (mp_irqs[i].dstapic == old_id) |
1996 | mp_irqs[i].dstapic | |
c8d46cf0 | 1997 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
1998 | |
1999 | /* | |
60d79fd9 YL |
2000 | * Update the ID register according to the right value |
2001 | * from the MPC table if they are different. | |
36062448 | 2002 | */ |
60d79fd9 YL |
2003 | if (mp_ioapics[apic_id].apicid == reg_00.bits.ID) |
2004 | continue; | |
2005 | ||
1da177e4 LT |
2006 | apic_printk(APIC_VERBOSE, KERN_INFO |
2007 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2008 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2009 | |
c8d46cf0 | 2010 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2011 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2012 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2013 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2014 | |
2015 | /* | |
2016 | * Sanity check | |
2017 | */ | |
dade7716 | 2018 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2019 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2020 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2021 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2022 | printk("could not set ID!\n"); |
2023 | else | |
2024 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2025 | } | |
2026 | } | |
a38c5380 SAS |
2027 | |
2028 | void __init setup_ioapic_ids_from_mpc(void) | |
2029 | { | |
2030 | ||
2031 | if (acpi_ioapic) | |
2032 | return; | |
2033 | /* | |
2034 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2035 | * no meaning without the serial APIC bus. | |
2036 | */ | |
2037 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2038 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2039 | return; | |
2040 | setup_ioapic_ids_from_mpc_nocheck(); | |
2041 | } | |
54168ed7 | 2042 | #endif |
1da177e4 | 2043 | |
7ce0bcfd | 2044 | int no_timer_check __initdata; |
8542b200 ZA |
2045 | |
2046 | static int __init notimercheck(char *s) | |
2047 | { | |
2048 | no_timer_check = 1; | |
2049 | return 1; | |
2050 | } | |
2051 | __setup("no_timer_check", notimercheck); | |
2052 | ||
1da177e4 LT |
2053 | /* |
2054 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2055 | * about the timer IRQ. We do the following to work around the situation: | |
2056 | * | |
2057 | * - timer IRQ defaults to IO-APIC IRQ | |
2058 | * - if this function detects that timer IRQs are defunct, then we fall | |
2059 | * back to ISA timer IRQs | |
2060 | */ | |
f0a7a5c9 | 2061 | static int __init timer_irq_works(void) |
1da177e4 LT |
2062 | { |
2063 | unsigned long t1 = jiffies; | |
4aae0702 | 2064 | unsigned long flags; |
1da177e4 | 2065 | |
8542b200 ZA |
2066 | if (no_timer_check) |
2067 | return 1; | |
2068 | ||
4aae0702 | 2069 | local_save_flags(flags); |
1da177e4 LT |
2070 | local_irq_enable(); |
2071 | /* Let ten ticks pass... */ | |
2072 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2073 | local_irq_restore(flags); |
1da177e4 LT |
2074 | |
2075 | /* | |
2076 | * Expect a few ticks at least, to be sure some possible | |
2077 | * glue logic does not lock up after one or two first | |
2078 | * ticks in a non-ExtINT mode. Also the local APIC | |
2079 | * might have cached one ExtINT interrupt. Finally, at | |
2080 | * least one tick may be lost due to delays. | |
2081 | */ | |
54168ed7 IM |
2082 | |
2083 | /* jiffies wrap? */ | |
1d16b53e | 2084 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2085 | return 1; |
1da177e4 LT |
2086 | return 0; |
2087 | } | |
2088 | ||
2089 | /* | |
2090 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2091 | * number of pending IRQ events unhandled. These cases are very rare, | |
2092 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2093 | * better to do it this way as thus we do not have to be aware of | |
2094 | * 'pending' interrupts in the IRQ path, except at this point. | |
2095 | */ | |
2096 | /* | |
2097 | * Edge triggered needs to resend any interrupt | |
2098 | * that was delayed but this is now handled in the device | |
2099 | * independent code. | |
2100 | */ | |
2101 | ||
2102 | /* | |
2103 | * Starting up a edge-triggered IO-APIC interrupt is | |
2104 | * nasty - we need to make sure that we get the edge. | |
2105 | * If it is already asserted for some reason, we need | |
2106 | * return 1 to indicate that is was pending. | |
2107 | * | |
2108 | * This is not complete - we should be able to fake | |
2109 | * an edge even if it isn't on the 8259A... | |
2110 | */ | |
54168ed7 | 2111 | |
61a38ce3 | 2112 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2113 | { |
61a38ce3 | 2114 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2115 | unsigned long flags; |
2116 | ||
dade7716 | 2117 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2118 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2119 | legacy_pic->mask(irq); |
b81bb373 | 2120 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2121 | was_pending = 1; |
2122 | } | |
61a38ce3 | 2123 | __unmask_ioapic(data->chip_data); |
dade7716 | 2124 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2125 | |
2126 | return was_pending; | |
2127 | } | |
2128 | ||
90297c5f | 2129 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2130 | { |
90297c5f | 2131 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2132 | unsigned long flags; |
2133 | ||
dade7716 | 2134 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2135 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2136 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2137 | |
2138 | return 1; | |
2139 | } | |
497c9a19 | 2140 | |
54168ed7 IM |
2141 | /* |
2142 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2143 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2144 | * handled with the level-triggered descriptor, but that one has slightly | |
2145 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2146 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2147 | * races. | |
2148 | */ | |
497c9a19 | 2149 | |
54168ed7 | 2150 | #ifdef CONFIG_SMP |
9338ad6f | 2151 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2152 | { |
2153 | cpumask_var_t cleanup_mask; | |
2154 | ||
2155 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2156 | unsigned int i; | |
e85abf8f GH |
2157 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2158 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2159 | } else { | |
2160 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2161 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2162 | free_cpumask_var(cleanup_mask); | |
2163 | } | |
2164 | cfg->move_in_progress = 0; | |
2165 | } | |
2166 | ||
4420471f | 2167 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2168 | { |
2169 | int apic, pin; | |
2170 | struct irq_pin_list *entry; | |
2171 | u8 vector = cfg->vector; | |
2172 | ||
2977fb3f | 2173 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2174 | unsigned int reg; |
2175 | ||
e85abf8f GH |
2176 | apic = entry->apic; |
2177 | pin = entry->pin; | |
2178 | /* | |
2179 | * With interrupt-remapping, destination information comes | |
2180 | * from interrupt-remapping table entry. | |
2181 | */ | |
1a0730d6 | 2182 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2183 | io_apic_write(apic, 0x11 + pin*2, dest); |
2184 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2185 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2186 | reg |= vector; | |
2187 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2188 | } |
2189 | } | |
2190 | ||
2191 | /* | |
f7e909ea | 2192 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2193 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2194 | * leaves data->affinity untouched. |
e85abf8f | 2195 | */ |
f7e909ea TG |
2196 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2197 | unsigned int *dest_id) | |
e85abf8f | 2198 | { |
f7e909ea | 2199 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2200 | |
2201 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2202 | return -1; |
e85abf8f | 2203 | |
f7e909ea | 2204 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2205 | return -1; |
e85abf8f | 2206 | |
f7e909ea | 2207 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2208 | |
f7e909ea | 2209 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2210 | return 0; |
e85abf8f GH |
2211 | } |
2212 | ||
4420471f | 2213 | static int |
f7e909ea TG |
2214 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2215 | bool force) | |
e85abf8f | 2216 | { |
f7e909ea | 2217 | unsigned int dest, irq = data->irq; |
e85abf8f | 2218 | unsigned long flags; |
f7e909ea | 2219 | int ret; |
e85abf8f | 2220 | |
dade7716 | 2221 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2222 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2223 | if (!ret) { |
e85abf8f GH |
2224 | /* Only the high 8 bits are valid. */ |
2225 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2226 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2227 | } |
dade7716 | 2228 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2229 | return ret; |
e85abf8f GH |
2230 | } |
2231 | ||
54168ed7 | 2232 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2233 | |
54168ed7 IM |
2234 | /* |
2235 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2236 | * | |
0280f7c4 SS |
2237 | * For both level and edge triggered, irq migration is a simple atomic |
2238 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2239 | * |
0280f7c4 SS |
2240 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2241 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2242 | * Real vector that is used for interrupting cpu will be coming from | |
2243 | * the interrupt-remapping table entry. | |
54168ed7 | 2244 | */ |
d5dedd45 | 2245 | static int |
f19f5ecc TG |
2246 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2247 | bool force) | |
497c9a19 | 2248 | { |
f19f5ecc TG |
2249 | struct irq_cfg *cfg = data->chip_data; |
2250 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2251 | struct irte irte; |
497c9a19 | 2252 | |
22f65d31 | 2253 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2254 | return -EINVAL; |
497c9a19 | 2255 | |
54168ed7 | 2256 | if (get_irte(irq, &irte)) |
f19f5ecc | 2257 | return -EBUSY; |
497c9a19 | 2258 | |
3145e941 | 2259 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2260 | return -EBUSY; |
54168ed7 | 2261 | |
debccb3e | 2262 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2263 | |
54168ed7 IM |
2264 | irte.vector = cfg->vector; |
2265 | irte.dest_id = IRTE_DEST(dest); | |
2266 | ||
2267 | /* | |
2268 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2269 | */ | |
2270 | modify_irte(irq, &irte); | |
2271 | ||
22f65d31 MT |
2272 | if (cfg->move_in_progress) |
2273 | send_cleanup_vector(cfg); | |
54168ed7 | 2274 | |
f19f5ecc | 2275 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2276 | return 0; |
54168ed7 IM |
2277 | } |
2278 | ||
29b61be6 | 2279 | #else |
f19f5ecc TG |
2280 | static inline int |
2281 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2282 | bool force) | |
29b61be6 | 2283 | { |
d5dedd45 | 2284 | return 0; |
29b61be6 | 2285 | } |
54168ed7 IM |
2286 | #endif |
2287 | ||
2288 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2289 | { | |
2290 | unsigned vector, me; | |
8f2466f4 | 2291 | |
54168ed7 | 2292 | ack_APIC_irq(); |
54168ed7 | 2293 | exit_idle(); |
54168ed7 IM |
2294 | irq_enter(); |
2295 | ||
2296 | me = smp_processor_id(); | |
2297 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2298 | unsigned int irq; | |
68a8ca59 | 2299 | unsigned int irr; |
54168ed7 IM |
2300 | struct irq_desc *desc; |
2301 | struct irq_cfg *cfg; | |
0a3aee0d | 2302 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2303 | |
0b8f1efa YL |
2304 | if (irq == -1) |
2305 | continue; | |
2306 | ||
54168ed7 IM |
2307 | desc = irq_to_desc(irq); |
2308 | if (!desc) | |
2309 | continue; | |
2310 | ||
2311 | cfg = irq_cfg(irq); | |
239007b8 | 2312 | raw_spin_lock(&desc->lock); |
54168ed7 | 2313 | |
7f41c2e1 SS |
2314 | /* |
2315 | * Check if the irq migration is in progress. If so, we | |
2316 | * haven't received the cleanup request yet for this irq. | |
2317 | */ | |
2318 | if (cfg->move_in_progress) | |
2319 | goto unlock; | |
2320 | ||
22f65d31 | 2321 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2322 | goto unlock; |
2323 | ||
68a8ca59 SS |
2324 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2325 | /* | |
2326 | * Check if the vector that needs to be cleanedup is | |
2327 | * registered at the cpu's IRR. If so, then this is not | |
2328 | * the best time to clean it up. Lets clean it up in the | |
2329 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2330 | * to myself. | |
2331 | */ | |
2332 | if (irr & (1 << (vector % 32))) { | |
2333 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2334 | goto unlock; | |
2335 | } | |
0a3aee0d | 2336 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2337 | unlock: |
239007b8 | 2338 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2339 | } |
2340 | ||
2341 | irq_exit(); | |
2342 | } | |
2343 | ||
dd5f15e5 | 2344 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2345 | { |
a5e74b84 | 2346 | unsigned me; |
54168ed7 | 2347 | |
fcef5911 | 2348 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2349 | return; |
2350 | ||
54168ed7 | 2351 | me = smp_processor_id(); |
10b888d6 | 2352 | |
fcef5911 | 2353 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2354 | send_cleanup_vector(cfg); |
497c9a19 | 2355 | } |
a5e74b84 | 2356 | |
dd5f15e5 | 2357 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2358 | { |
dd5f15e5 | 2359 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2360 | } |
2361 | ||
2362 | void irq_force_complete_move(int irq) | |
2363 | { | |
2c778651 | 2364 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2365 | |
bbd391a1 PB |
2366 | if (!cfg) |
2367 | return; | |
2368 | ||
dd5f15e5 | 2369 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2370 | } |
497c9a19 | 2371 | #else |
dd5f15e5 | 2372 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2373 | #endif |
3145e941 | 2374 | |
90297c5f | 2375 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2376 | { |
90297c5f | 2377 | irq_complete_move(data->chip_data); |
08221110 | 2378 | irq_move_irq(data); |
1d025192 YL |
2379 | ack_APIC_irq(); |
2380 | } | |
2381 | ||
3eb2cce8 | 2382 | atomic_t irq_mis_count; |
3eb2cce8 | 2383 | |
c29d9db3 SS |
2384 | /* |
2385 | * IO-APIC versions below 0x20 don't support EOI register. | |
2386 | * For the record, here is the information about various versions: | |
2387 | * 0Xh 82489DX | |
2388 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2389 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2390 | * 30h-FFh Reserved | |
2391 | * | |
2392 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2393 | * version as 0x2. This is an error with documentation and these ICH chips | |
2394 | * use io-apic's of version 0x20. | |
2395 | * | |
2396 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2397 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2398 | * mode to edge and then back to level, with RTE being masked during this. | |
2399 | */ | |
dd5f15e5 | 2400 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2401 | { |
2402 | struct irq_pin_list *entry; | |
dd5f15e5 | 2403 | unsigned long flags; |
b3ec0a37 | 2404 | |
dd5f15e5 | 2405 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2406 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2407 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2408 | /* | |
2409 | * Intr-remapping uses pin number as the virtual vector | |
2410 | * in the RTE. Actual vector is programmed in | |
2411 | * intr-remapping table entry. Hence for the io-apic | |
2412 | * EOI we use the pin number. | |
2413 | */ | |
1a0730d6 | 2414 | if (irq_remapped(cfg)) |
c29d9db3 SS |
2415 | io_apic_eoi(entry->apic, entry->pin); |
2416 | else | |
2417 | io_apic_eoi(entry->apic, cfg->vector); | |
2418 | } else { | |
2419 | __mask_and_edge_IO_APIC_irq(entry); | |
2420 | __unmask_and_level_IO_APIC_irq(entry); | |
2421 | } | |
b3ec0a37 | 2422 | } |
dade7716 | 2423 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2424 | } |
2425 | ||
90297c5f | 2426 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2427 | { |
90297c5f TG |
2428 | struct irq_cfg *cfg = data->chip_data; |
2429 | int i, do_unmask_irq = 0, irq = data->irq; | |
3eb2cce8 | 2430 | unsigned long v; |
047c8fdb | 2431 | |
dd5f15e5 | 2432 | irq_complete_move(cfg); |
047c8fdb | 2433 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2434 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2435 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
54168ed7 | 2436 | do_unmask_irq = 1; |
dd5f15e5 | 2437 | mask_ioapic(cfg); |
54168ed7 | 2438 | } |
047c8fdb YL |
2439 | #endif |
2440 | ||
3eb2cce8 | 2441 | /* |
916a0fe7 JF |
2442 | * It appears there is an erratum which affects at least version 0x11 |
2443 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2444 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2445 | * erroneously delivered as edge-triggered one but the respective IRR | |
2446 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2447 | * message but it will never arrive and further interrupts are blocked | |
2448 | * from the source. The exact reason is so far unknown, but the | |
2449 | * phenomenon was observed when two consecutive interrupt requests | |
2450 | * from a given source get delivered to the same CPU and the source is | |
2451 | * temporarily disabled in between. | |
2452 | * | |
2453 | * A workaround is to simulate an EOI message manually. We achieve it | |
2454 | * by setting the trigger mode to edge and then to level when the edge | |
2455 | * trigger mode gets detected in the TMR of a local APIC for a | |
2456 | * level-triggered interrupt. We mask the source for the time of the | |
2457 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2458 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2459 | * |
2460 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2461 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2462 | * destination that is handling the corresponding interrupt. This | |
2463 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2464 | * level-triggered io-apic interrupt will be seen as an edge | |
2465 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2466 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2467 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2468 | * supporting EOI register, we do an explicit EOI to clear the | |
2469 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2470 | * we use the above logic (mask+edge followed by unmask+level) from | |
2471 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2472 | */ |
3145e941 | 2473 | i = cfg->vector; |
3eb2cce8 | 2474 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2475 | |
54168ed7 IM |
2476 | /* |
2477 | * We must acknowledge the irq before we move it or the acknowledge will | |
2478 | * not propagate properly. | |
2479 | */ | |
2480 | ack_APIC_irq(); | |
2481 | ||
1c83995b SS |
2482 | /* |
2483 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2484 | * message via io-apic EOI register write or simulating it using | |
2485 | * mask+edge followed by unnask+level logic) manually when the | |
2486 | * level triggered interrupt is seen as the edge triggered interrupt | |
2487 | * at the cpu. | |
2488 | */ | |
ca64c47c MR |
2489 | if (!(v & (1 << (i & 0x1f)))) { |
2490 | atomic_inc(&irq_mis_count); | |
2491 | ||
dd5f15e5 | 2492 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2493 | } |
2494 | ||
54168ed7 IM |
2495 | /* Now we can move and renable the irq */ |
2496 | if (unlikely(do_unmask_irq)) { | |
2497 | /* Only migrate the irq if the ack has been received. | |
2498 | * | |
2499 | * On rare occasions the broadcast level triggered ack gets | |
2500 | * delayed going to ioapics, and if we reprogram the | |
2501 | * vector while Remote IRR is still set the irq will never | |
2502 | * fire again. | |
2503 | * | |
2504 | * To prevent this scenario we read the Remote IRR bit | |
2505 | * of the ioapic. This has two effects. | |
2506 | * - On any sane system the read of the ioapic will | |
2507 | * flush writes (and acks) going to the ioapic from | |
2508 | * this cpu. | |
2509 | * - We get to see if the ACK has actually been delivered. | |
2510 | * | |
2511 | * Based on failed experiments of reprogramming the | |
2512 | * ioapic entry from outside of irq context starting | |
2513 | * with masking the ioapic entry and then polling until | |
2514 | * Remote IRR was clear before reprogramming the | |
2515 | * ioapic I don't trust the Remote IRR bit to be | |
2516 | * completey accurate. | |
2517 | * | |
2518 | * However there appears to be no other way to plug | |
2519 | * this race, so if the Remote IRR bit is not | |
2520 | * accurate and is causing problems then it is a hardware bug | |
2521 | * and you can go talk to the chipset vendor about it. | |
2522 | */ | |
3145e941 | 2523 | if (!io_apic_level_ack_pending(cfg)) |
08221110 | 2524 | irq_move_masked_irq(data); |
dd5f15e5 | 2525 | unmask_ioapic(cfg); |
54168ed7 | 2526 | } |
3eb2cce8 | 2527 | } |
1d025192 | 2528 | |
d0b03bd1 | 2529 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2530 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2531 | { |
5d0ae2db | 2532 | ack_APIC_irq(); |
d0b03bd1 HW |
2533 | } |
2534 | ||
90297c5f | 2535 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2536 | { |
5d0ae2db | 2537 | ack_APIC_irq(); |
90297c5f | 2538 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2539 | } |
2540 | #endif /* CONFIG_INTR_REMAP */ | |
2541 | ||
f5b9ed7a | 2542 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2543 | .name = "IO-APIC", |
2544 | .irq_startup = startup_ioapic_irq, | |
2545 | .irq_mask = mask_ioapic_irq, | |
2546 | .irq_unmask = unmask_ioapic_irq, | |
2547 | .irq_ack = ack_apic_edge, | |
2548 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2549 | #ifdef CONFIG_SMP |
f7e909ea | 2550 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2551 | #endif |
f7e909ea | 2552 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2553 | }; |
2554 | ||
54168ed7 | 2555 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
f19f5ecc TG |
2556 | .name = "IR-IO-APIC", |
2557 | .irq_startup = startup_ioapic_irq, | |
2558 | .irq_mask = mask_ioapic_irq, | |
2559 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2560 | #ifdef CONFIG_INTR_REMAP |
f19f5ecc TG |
2561 | .irq_ack = ir_ack_apic_edge, |
2562 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2563 | #ifdef CONFIG_SMP |
f19f5ecc | 2564 | .irq_set_affinity = ir_ioapic_set_affinity, |
a1e38ca5 | 2565 | #endif |
54168ed7 | 2566 | #endif |
f19f5ecc | 2567 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2568 | }; |
1da177e4 LT |
2569 | |
2570 | static inline void init_IO_APIC_traps(void) | |
2571 | { | |
da51a821 | 2572 | struct irq_cfg *cfg; |
ad9f4334 | 2573 | unsigned int irq; |
1da177e4 LT |
2574 | |
2575 | /* | |
2576 | * NOTE! The local APIC isn't very good at handling | |
2577 | * multiple interrupts at the same interrupt level. | |
2578 | * As the interrupt level is determined by taking the | |
2579 | * vector number and shifting that right by 4, we | |
2580 | * want to spread these out a bit so that they don't | |
2581 | * all fall in the same interrupt level. | |
2582 | * | |
2583 | * Also, we've got to be careful not to trash gate | |
2584 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2585 | */ | |
ad9f4334 | 2586 | for_each_active_irq(irq) { |
2c778651 | 2587 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2588 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2589 | /* |
2590 | * Hmm.. We don't have an entry for this, | |
2591 | * so default to an old-fashioned 8259 | |
2592 | * interrupt if we can.. | |
2593 | */ | |
b81bb373 JP |
2594 | if (irq < legacy_pic->nr_legacy_irqs) |
2595 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2596 | else |
1da177e4 | 2597 | /* Strange. Oh, well.. */ |
2c778651 | 2598 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2599 | } |
2600 | } | |
2601 | } | |
2602 | ||
f5b9ed7a IM |
2603 | /* |
2604 | * The local APIC irq-chip implementation: | |
2605 | */ | |
1da177e4 | 2606 | |
90297c5f | 2607 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2608 | { |
2609 | unsigned long v; | |
2610 | ||
2611 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2612 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2613 | } |
2614 | ||
90297c5f | 2615 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2616 | { |
f5b9ed7a | 2617 | unsigned long v; |
1da177e4 | 2618 | |
f5b9ed7a | 2619 | v = apic_read(APIC_LVT0); |
593f4a78 | 2620 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2621 | } |
1da177e4 | 2622 | |
90297c5f | 2623 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2624 | { |
2625 | ack_APIC_irq(); | |
2626 | } | |
2627 | ||
f5b9ed7a | 2628 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2629 | .name = "local-APIC", |
90297c5f TG |
2630 | .irq_mask = mask_lapic_irq, |
2631 | .irq_unmask = unmask_lapic_irq, | |
2632 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2633 | }; |
2634 | ||
60c69948 | 2635 | static void lapic_register_intr(int irq) |
c88ac1df | 2636 | { |
60c69948 | 2637 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2638 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2639 | "edge"); |
c88ac1df MR |
2640 | } |
2641 | ||
1da177e4 LT |
2642 | /* |
2643 | * This looks a bit hackish but it's about the only one way of sending | |
2644 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2645 | * not support the ExtINT mode, unfortunately. We need to send these | |
2646 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2647 | * 8259A interrupt line asserted until INTA. --macro | |
2648 | */ | |
28acf285 | 2649 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2650 | { |
fcfd636a | 2651 | int apic, pin, i; |
1da177e4 LT |
2652 | struct IO_APIC_route_entry entry0, entry1; |
2653 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2654 | |
fcfd636a | 2655 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2656 | if (pin == -1) { |
2657 | WARN_ON_ONCE(1); | |
2658 | return; | |
2659 | } | |
fcfd636a | 2660 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2661 | if (apic == -1) { |
2662 | WARN_ON_ONCE(1); | |
1da177e4 | 2663 | return; |
956fb531 | 2664 | } |
1da177e4 | 2665 | |
cf4c6a2f | 2666 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2667 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2668 | |
2669 | memset(&entry1, 0, sizeof(entry1)); | |
2670 | ||
2671 | entry1.dest_mode = 0; /* physical delivery */ | |
2672 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2673 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2674 | entry1.delivery_mode = dest_ExtINT; |
2675 | entry1.polarity = entry0.polarity; | |
2676 | entry1.trigger = 0; | |
2677 | entry1.vector = 0; | |
2678 | ||
cf4c6a2f | 2679 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2680 | |
2681 | save_control = CMOS_READ(RTC_CONTROL); | |
2682 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2683 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2684 | RTC_FREQ_SELECT); | |
2685 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2686 | ||
2687 | i = 100; | |
2688 | while (i-- > 0) { | |
2689 | mdelay(10); | |
2690 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2691 | i -= 10; | |
2692 | } | |
2693 | ||
2694 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2695 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2696 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2697 | |
cf4c6a2f | 2698 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2699 | } |
2700 | ||
efa2559f | 2701 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2702 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2703 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2704 | { |
2705 | disable_timer_pin_1 = 1; | |
2706 | return 0; | |
2707 | } | |
54168ed7 | 2708 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2709 | |
2710 | int timer_through_8259 __initdata; | |
2711 | ||
1da177e4 LT |
2712 | /* |
2713 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2714 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2715 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2716 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2717 | * |
2718 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2719 | */ |
8542b200 | 2720 | static inline void __init check_timer(void) |
1da177e4 | 2721 | { |
2c778651 | 2722 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2723 | int node = cpu_to_node(0); |
fcfd636a | 2724 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2725 | unsigned long flags; |
047c8fdb | 2726 | int no_pin1 = 0; |
4aae0702 IM |
2727 | |
2728 | local_irq_save(flags); | |
d4d25dec | 2729 | |
1da177e4 LT |
2730 | /* |
2731 | * get/set the timer IRQ vector: | |
2732 | */ | |
4305df94 | 2733 | legacy_pic->mask(0); |
fe402e1f | 2734 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2735 | |
2736 | /* | |
d11d5794 MR |
2737 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2738 | * wire has to be disabled in the local APIC. Also | |
2739 | * timer interrupts need to be acknowledged manually in | |
2740 | * the 8259A for the i82489DX when using the NMI | |
2741 | * watchdog as that APIC treats NMIs as level-triggered. | |
2742 | * The AEOI mode will finish them in the 8259A | |
2743 | * automatically. | |
1da177e4 | 2744 | */ |
593f4a78 | 2745 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2746 | legacy_pic->init(1); |
1da177e4 | 2747 | |
fcfd636a EB |
2748 | pin1 = find_isa_irq_pin(0, mp_INT); |
2749 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2750 | pin2 = ioapic_i8259.pin; | |
2751 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2752 | |
49a66a0b MR |
2753 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2754 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2755 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2756 | |
691874fa MR |
2757 | /* |
2758 | * Some BIOS writers are clueless and report the ExtINTA | |
2759 | * I/O APIC input from the cascaded 8259A as the timer | |
2760 | * interrupt input. So just in case, if only one pin | |
2761 | * was found above, try it both directly and through the | |
2762 | * 8259A. | |
2763 | */ | |
2764 | if (pin1 == -1) { | |
54168ed7 IM |
2765 | if (intr_remapping_enabled) |
2766 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2767 | pin1 = pin2; |
2768 | apic1 = apic2; | |
2769 | no_pin1 = 1; | |
2770 | } else if (pin2 == -1) { | |
2771 | pin2 = pin1; | |
2772 | apic2 = apic1; | |
2773 | } | |
2774 | ||
1da177e4 LT |
2775 | if (pin1 != -1) { |
2776 | /* | |
2777 | * Ok, does IRQ0 through the IOAPIC work? | |
2778 | */ | |
691874fa | 2779 | if (no_pin1) { |
85ac16d0 | 2780 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2781 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2782 | } else { |
60c69948 | 2783 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2784 | * leave it unmasked. |
2785 | * so only need to unmask if it is level-trigger | |
2786 | * do we really have level trigger timer? | |
2787 | */ | |
2788 | int idx; | |
2789 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2790 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2791 | unmask_ioapic(cfg); |
691874fa | 2792 | } |
1da177e4 | 2793 | if (timer_irq_works()) { |
66759a01 CE |
2794 | if (disable_timer_pin_1 > 0) |
2795 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2796 | goto out; |
1da177e4 | 2797 | } |
54168ed7 IM |
2798 | if (intr_remapping_enabled) |
2799 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2800 | local_irq_disable(); |
fcfd636a | 2801 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2802 | if (!no_pin1) |
49a66a0b MR |
2803 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2804 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2805 | |
49a66a0b MR |
2806 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2807 | "(IRQ0) through the 8259A ...\n"); | |
2808 | apic_printk(APIC_QUIET, KERN_INFO | |
2809 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2810 | /* |
2811 | * legacy devices should be connected to IO APIC #0 | |
2812 | */ | |
85ac16d0 | 2813 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2814 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2815 | legacy_pic->unmask(0); |
1da177e4 | 2816 | if (timer_irq_works()) { |
49a66a0b | 2817 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2818 | timer_through_8259 = 1; |
4aae0702 | 2819 | goto out; |
1da177e4 LT |
2820 | } |
2821 | /* | |
2822 | * Cleanup, just in case ... | |
2823 | */ | |
f72dccac | 2824 | local_irq_disable(); |
4305df94 | 2825 | legacy_pic->mask(0); |
fcfd636a | 2826 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2827 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2828 | } |
1da177e4 | 2829 | |
49a66a0b MR |
2830 | apic_printk(APIC_QUIET, KERN_INFO |
2831 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2832 | |
60c69948 | 2833 | lapic_register_intr(0); |
497c9a19 | 2834 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2835 | legacy_pic->unmask(0); |
1da177e4 LT |
2836 | |
2837 | if (timer_irq_works()) { | |
49a66a0b | 2838 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2839 | goto out; |
1da177e4 | 2840 | } |
f72dccac | 2841 | local_irq_disable(); |
4305df94 | 2842 | legacy_pic->mask(0); |
497c9a19 | 2843 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2844 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2845 | |
49a66a0b MR |
2846 | apic_printk(APIC_QUIET, KERN_INFO |
2847 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2848 | |
b81bb373 JP |
2849 | legacy_pic->init(0); |
2850 | legacy_pic->make_irq(0); | |
593f4a78 | 2851 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2852 | |
2853 | unlock_ExtINT_logic(); | |
2854 | ||
2855 | if (timer_irq_works()) { | |
49a66a0b | 2856 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2857 | goto out; |
1da177e4 | 2858 | } |
f72dccac | 2859 | local_irq_disable(); |
49a66a0b | 2860 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2861 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2862 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2863 | out: |
2864 | local_irq_restore(flags); | |
1da177e4 LT |
2865 | } |
2866 | ||
2867 | /* | |
af174783 MR |
2868 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2869 | * to devices. However there may be an I/O APIC pin available for | |
2870 | * this interrupt regardless. The pin may be left unconnected, but | |
2871 | * typically it will be reused as an ExtINT cascade interrupt for | |
2872 | * the master 8259A. In the MPS case such a pin will normally be | |
2873 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2874 | * there is no provision for ExtINT interrupts, and in the absence | |
2875 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2876 | * interrupt, that is edge-triggered and unmasked by default. We | |
2877 | * used to do this, but it caused problems on some systems because | |
2878 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2879 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2880 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2881 | * the I/O APIC in all cases now. No actual device should request | |
2882 | * it anyway. --macro | |
1da177e4 | 2883 | */ |
bc07844a | 2884 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2885 | |
2886 | void __init setup_IO_APIC(void) | |
2887 | { | |
54168ed7 | 2888 | |
54168ed7 IM |
2889 | /* |
2890 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2891 | */ | |
b81bb373 | 2892 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2893 | |
54168ed7 | 2894 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2895 | /* |
54168ed7 IM |
2896 | * Set up IO-APIC IRQ routing. |
2897 | */ | |
de934103 TG |
2898 | x86_init.mpparse.setup_ioapic_ids(); |
2899 | ||
1da177e4 LT |
2900 | sync_Arb_IDs(); |
2901 | setup_IO_APIC_irqs(); | |
2902 | init_IO_APIC_traps(); | |
b81bb373 | 2903 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2904 | check_timer(); |
1da177e4 LT |
2905 | } |
2906 | ||
2907 | /* | |
0d2eb44f | 2908 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2909 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2910 | */ |
36062448 | 2911 | |
1da177e4 LT |
2912 | static int __init io_apic_bug_finalize(void) |
2913 | { | |
d6c88a50 TG |
2914 | if (sis_apic_bug == -1) |
2915 | sis_apic_bug = 0; | |
2916 | return 0; | |
1da177e4 LT |
2917 | } |
2918 | ||
2919 | late_initcall(io_apic_bug_finalize); | |
2920 | ||
2921 | struct sysfs_ioapic_data { | |
2922 | struct sys_device dev; | |
2923 | struct IO_APIC_route_entry entry[0]; | |
2924 | }; | |
54168ed7 | 2925 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2926 | |
438510f6 | 2927 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2928 | { |
2929 | struct IO_APIC_route_entry *entry; | |
2930 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2931 | int i; |
36062448 | 2932 | |
1da177e4 LT |
2933 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2934 | entry = data->entry; | |
54168ed7 IM |
2935 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2936 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2937 | |
2938 | return 0; | |
2939 | } | |
2940 | ||
2941 | static int ioapic_resume(struct sys_device *dev) | |
2942 | { | |
2943 | struct IO_APIC_route_entry *entry; | |
2944 | struct sysfs_ioapic_data *data; | |
2945 | unsigned long flags; | |
2946 | union IO_APIC_reg_00 reg_00; | |
2947 | int i; | |
36062448 | 2948 | |
1da177e4 LT |
2949 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2950 | entry = data->entry; | |
2951 | ||
dade7716 | 2952 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2953 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
2954 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
2955 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
2956 | io_apic_write(dev->id, 0, reg_00.raw); |
2957 | } | |
dade7716 | 2958 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2959 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2960 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2961 | |
2962 | return 0; | |
2963 | } | |
2964 | ||
2965 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2966 | .name = "ioapic", |
1da177e4 LT |
2967 | .suspend = ioapic_suspend, |
2968 | .resume = ioapic_resume, | |
2969 | }; | |
2970 | ||
2971 | static int __init ioapic_init_sysfs(void) | |
2972 | { | |
54168ed7 IM |
2973 | struct sys_device * dev; |
2974 | int i, size, error; | |
1da177e4 LT |
2975 | |
2976 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2977 | if (error) | |
2978 | return error; | |
2979 | ||
54168ed7 | 2980 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 2981 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 2982 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2983 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2984 | if (!mp_ioapic_data[i]) { |
2985 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2986 | continue; | |
2987 | } | |
1da177e4 | 2988 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2989 | dev->id = i; |
1da177e4 LT |
2990 | dev->cls = &ioapic_sysdev_class; |
2991 | error = sysdev_register(dev); | |
2992 | if (error) { | |
2993 | kfree(mp_ioapic_data[i]); | |
2994 | mp_ioapic_data[i] = NULL; | |
2995 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2996 | continue; | |
2997 | } | |
2998 | } | |
2999 | ||
3000 | return 0; | |
3001 | } | |
3002 | ||
3003 | device_initcall(ioapic_init_sysfs); | |
3004 | ||
3fc471ed | 3005 | /* |
95d77884 | 3006 | * Dynamic irq allocate and deallocation |
3fc471ed | 3007 | */ |
fbc6bff0 | 3008 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 3009 | { |
fbc6bff0 | 3010 | struct irq_cfg *cfg; |
3fc471ed | 3011 | unsigned long flags; |
fbc6bff0 TG |
3012 | unsigned int ret = 0; |
3013 | int irq; | |
d047f53a | 3014 | |
fbc6bff0 TG |
3015 | if (from < nr_irqs_gsi) |
3016 | from = nr_irqs_gsi; | |
d047f53a | 3017 | |
fbc6bff0 TG |
3018 | irq = alloc_irq_from(from, node); |
3019 | if (irq < 0) | |
3020 | return 0; | |
3021 | cfg = alloc_irq_cfg(irq, node); | |
3022 | if (!cfg) { | |
3023 | free_irq_at(irq, NULL); | |
3024 | return 0; | |
ace80ab7 | 3025 | } |
3fc471ed | 3026 | |
fbc6bff0 TG |
3027 | raw_spin_lock_irqsave(&vector_lock, flags); |
3028 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
3029 | ret = irq; | |
3030 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3031 | |
fbc6bff0 | 3032 | if (ret) { |
2c778651 | 3033 | irq_set_chip_data(irq, cfg); |
fbc6bff0 TG |
3034 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
3035 | } else { | |
3036 | free_irq_at(irq, cfg); | |
3037 | } | |
3038 | return ret; | |
3fc471ed EB |
3039 | } |
3040 | ||
199751d7 YL |
3041 | int create_irq(void) |
3042 | { | |
f6e9456c | 3043 | int node = cpu_to_node(0); |
be5d5350 | 3044 | unsigned int irq_want; |
54168ed7 IM |
3045 | int irq; |
3046 | ||
be5d5350 | 3047 | irq_want = nr_irqs_gsi; |
d047f53a | 3048 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3049 | |
3050 | if (irq == 0) | |
3051 | irq = -1; | |
3052 | ||
3053 | return irq; | |
199751d7 YL |
3054 | } |
3055 | ||
3fc471ed EB |
3056 | void destroy_irq(unsigned int irq) |
3057 | { | |
2c778651 | 3058 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 3059 | unsigned long flags; |
3fc471ed | 3060 | |
fbc6bff0 | 3061 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3062 | |
7b79462a | 3063 | if (irq_remapped(cfg)) |
9717967c | 3064 | free_irte(irq); |
dade7716 | 3065 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3066 | __clear_irq_vector(irq, cfg); |
dade7716 | 3067 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3068 | free_irq_at(irq, cfg); |
3fc471ed | 3069 | } |
3fc471ed | 3070 | |
2d3fcc1c | 3071 | /* |
27b46d76 | 3072 | * MSI message composition |
2d3fcc1c EB |
3073 | */ |
3074 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3075 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3076 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3077 | { |
497c9a19 YL |
3078 | struct irq_cfg *cfg; |
3079 | int err; | |
2d3fcc1c EB |
3080 | unsigned dest; |
3081 | ||
f1182638 JB |
3082 | if (disable_apic) |
3083 | return -ENXIO; | |
3084 | ||
3145e941 | 3085 | cfg = irq_cfg(irq); |
fe402e1f | 3086 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3087 | if (err) |
3088 | return err; | |
2d3fcc1c | 3089 | |
debccb3e | 3090 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3091 | |
1a0e62a4 | 3092 | if (irq_remapped(cfg)) { |
54168ed7 IM |
3093 | struct irte irte; |
3094 | int ir_index; | |
3095 | u16 sub_handle; | |
3096 | ||
3097 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3098 | BUG_ON(ir_index == -1); | |
3099 | ||
62a92f4c | 3100 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3101 | |
f007e99c | 3102 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3103 | if (pdev) |
3104 | set_msi_sid(&irte, pdev); | |
3105 | else | |
3106 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3107 | |
54168ed7 IM |
3108 | modify_irte(irq, &irte); |
3109 | ||
3110 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3111 | msg->data = sub_handle; | |
3112 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3113 | MSI_ADDR_IR_SHV | | |
3114 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3115 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3116 | } else { |
9d783ba0 SS |
3117 | if (x2apic_enabled()) |
3118 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3119 | MSI_ADDR_EXT_DEST_ID(dest); | |
3120 | else | |
3121 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3122 | ||
54168ed7 IM |
3123 | msg->address_lo = |
3124 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3125 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3126 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3127 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3128 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3129 | MSI_ADDR_REDIRECTION_CPU: |
3130 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3131 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3132 | |
54168ed7 IM |
3133 | msg->data = |
3134 | MSI_DATA_TRIGGER_EDGE | | |
3135 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3136 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3137 | MSI_DATA_DELIVERY_FIXED: |
3138 | MSI_DATA_DELIVERY_LOWPRI) | | |
3139 | MSI_DATA_VECTOR(cfg->vector); | |
3140 | } | |
497c9a19 | 3141 | return err; |
2d3fcc1c EB |
3142 | } |
3143 | ||
3b7d1921 | 3144 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3145 | static int |
3146 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3147 | { |
5346b2a7 | 3148 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3149 | struct msi_msg msg; |
3150 | unsigned int dest; | |
3b7d1921 | 3151 | |
5346b2a7 | 3152 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3153 | return -1; |
2d3fcc1c | 3154 | |
5346b2a7 | 3155 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3156 | |
3157 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3158 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3159 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3160 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3161 | ||
5346b2a7 | 3162 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3163 | |
3164 | return 0; | |
2d3fcc1c | 3165 | } |
54168ed7 IM |
3166 | #ifdef CONFIG_INTR_REMAP |
3167 | /* | |
3168 | * Migrate the MSI irq to another cpumask. This migration is | |
3169 | * done in the process context using interrupt-remapping hardware. | |
3170 | */ | |
d5dedd45 | 3171 | static int |
b5d1c465 TG |
3172 | ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3173 | bool force) | |
54168ed7 | 3174 | { |
b5d1c465 TG |
3175 | struct irq_cfg *cfg = data->chip_data; |
3176 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3177 | struct irte irte; |
54168ed7 IM |
3178 | |
3179 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3180 | return -1; |
54168ed7 | 3181 | |
b5d1c465 | 3182 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3183 | return -1; |
54168ed7 | 3184 | |
54168ed7 IM |
3185 | irte.vector = cfg->vector; |
3186 | irte.dest_id = IRTE_DEST(dest); | |
3187 | ||
3188 | /* | |
3189 | * atomically update the IRTE with the new destination and vector. | |
3190 | */ | |
3191 | modify_irte(irq, &irte); | |
3192 | ||
3193 | /* | |
3194 | * After this point, all the interrupts will start arriving | |
3195 | * at the new destination. So, time to cleanup the previous | |
3196 | * vector allocation. | |
3197 | */ | |
22f65d31 MT |
3198 | if (cfg->move_in_progress) |
3199 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3200 | |
3201 | return 0; | |
54168ed7 | 3202 | } |
3145e941 | 3203 | |
54168ed7 | 3204 | #endif |
3b7d1921 | 3205 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3206 | |
3b7d1921 EB |
3207 | /* |
3208 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3209 | * which implement the MSI or MSI-X Capability Structure. | |
3210 | */ | |
3211 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3212 | .name = "PCI-MSI", |
3213 | .irq_unmask = unmask_msi_irq, | |
3214 | .irq_mask = mask_msi_irq, | |
3215 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3216 | #ifdef CONFIG_SMP |
5346b2a7 | 3217 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3218 | #endif |
5346b2a7 | 3219 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3220 | }; |
3221 | ||
54168ed7 | 3222 | static struct irq_chip msi_ir_chip = { |
b5d1c465 TG |
3223 | .name = "IR-PCI-MSI", |
3224 | .irq_unmask = unmask_msi_irq, | |
3225 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3226 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3227 | .irq_ack = ir_ack_apic_edge, |
54168ed7 | 3228 | #ifdef CONFIG_SMP |
b5d1c465 | 3229 | .irq_set_affinity = ir_msi_set_affinity, |
a1e38ca5 | 3230 | #endif |
54168ed7 | 3231 | #endif |
b5d1c465 | 3232 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3233 | }; |
3234 | ||
3235 | /* | |
3236 | * Map the PCI dev to the corresponding remapping hardware unit | |
3237 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3238 | * in it. | |
3239 | */ | |
3240 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3241 | { | |
3242 | struct intel_iommu *iommu; | |
3243 | int index; | |
3244 | ||
3245 | iommu = map_dev_to_ir(dev); | |
3246 | if (!iommu) { | |
3247 | printk(KERN_ERR | |
3248 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3249 | return -ENOENT; | |
3250 | } | |
3251 | ||
3252 | index = alloc_irte(iommu, irq, nvec); | |
3253 | if (index < 0) { | |
3254 | printk(KERN_ERR | |
3255 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3256 | pci_name(dev)); |
54168ed7 IM |
3257 | return -ENOSPC; |
3258 | } | |
3259 | return index; | |
3260 | } | |
1d025192 | 3261 | |
3145e941 | 3262 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3263 | { |
c60eaf25 | 3264 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3265 | struct msi_msg msg; |
60c69948 | 3266 | int ret; |
1d025192 | 3267 | |
c8bc6f3c | 3268 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3269 | if (ret < 0) |
3270 | return ret; | |
3271 | ||
2c778651 | 3272 | irq_set_msi_desc(irq, msidesc); |
1d025192 YL |
3273 | write_msi_msg(irq, &msg); |
3274 | ||
2c778651 | 3275 | if (irq_remapped(irq_get_chip_data(irq))) { |
60c69948 | 3276 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
3277 | chip = &msi_ir_chip; |
3278 | } | |
3279 | ||
3280 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3281 | |
c81bba49 YL |
3282 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3283 | ||
1d025192 YL |
3284 | return 0; |
3285 | } | |
3286 | ||
294ee6f8 | 3287 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3288 | { |
60c69948 TG |
3289 | int node, ret, sub_handle, index = 0; |
3290 | unsigned int irq, irq_want; | |
0b8f1efa | 3291 | struct msi_desc *msidesc; |
1cc18521 | 3292 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3293 | |
1c8d7b0a MW |
3294 | /* x86 doesn't support multiple MSI yet */ |
3295 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3296 | return 1; | |
3297 | ||
d047f53a | 3298 | node = dev_to_node(&dev->dev); |
be5d5350 | 3299 | irq_want = nr_irqs_gsi; |
54168ed7 | 3300 | sub_handle = 0; |
0b8f1efa | 3301 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3302 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3303 | if (irq == 0) |
3304 | return -1; | |
f1ee5548 | 3305 | irq_want = irq + 1; |
54168ed7 IM |
3306 | if (!intr_remapping_enabled) |
3307 | goto no_ir; | |
3308 | ||
3309 | if (!sub_handle) { | |
3310 | /* | |
3311 | * allocate the consecutive block of IRTE's | |
3312 | * for 'nvec' | |
3313 | */ | |
3314 | index = msi_alloc_irte(dev, irq, nvec); | |
3315 | if (index < 0) { | |
3316 | ret = index; | |
3317 | goto error; | |
3318 | } | |
3319 | } else { | |
3320 | iommu = map_dev_to_ir(dev); | |
3321 | if (!iommu) { | |
3322 | ret = -ENOENT; | |
3323 | goto error; | |
3324 | } | |
3325 | /* | |
3326 | * setup the mapping between the irq and the IRTE | |
3327 | * base index, the sub_handle pointing to the | |
3328 | * appropriate interrupt remap table entry. | |
3329 | */ | |
3330 | set_irte_irq(irq, iommu, index, sub_handle); | |
3331 | } | |
3332 | no_ir: | |
0b8f1efa | 3333 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3334 | if (ret < 0) |
3335 | goto error; | |
3336 | sub_handle++; | |
3337 | } | |
3338 | return 0; | |
047c8fdb YL |
3339 | |
3340 | error: | |
54168ed7 IM |
3341 | destroy_irq(irq); |
3342 | return ret; | |
047c8fdb YL |
3343 | } |
3344 | ||
294ee6f8 | 3345 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3346 | { |
f7feaca7 | 3347 | destroy_irq(irq); |
3b7d1921 EB |
3348 | } |
3349 | ||
9d783ba0 | 3350 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3351 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3352 | static int |
3353 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3354 | bool force) | |
54168ed7 | 3355 | { |
fe52b2d2 TG |
3356 | struct irq_cfg *cfg = data->chip_data; |
3357 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3358 | struct msi_msg msg; |
54168ed7 | 3359 | |
fe52b2d2 | 3360 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3361 | return -1; |
54168ed7 | 3362 | |
54168ed7 IM |
3363 | dmar_msi_read(irq, &msg); |
3364 | ||
3365 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3366 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3367 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3368 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3369 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3370 | |
3371 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3372 | |
3373 | return 0; | |
54168ed7 | 3374 | } |
3145e941 | 3375 | |
54168ed7 IM |
3376 | #endif /* CONFIG_SMP */ |
3377 | ||
8f7007aa | 3378 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3379 | .name = "DMAR_MSI", |
3380 | .irq_unmask = dmar_msi_unmask, | |
3381 | .irq_mask = dmar_msi_mask, | |
3382 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3383 | #ifdef CONFIG_SMP |
fe52b2d2 | 3384 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3385 | #endif |
fe52b2d2 | 3386 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3387 | }; |
3388 | ||
3389 | int arch_setup_dmar_msi(unsigned int irq) | |
3390 | { | |
3391 | int ret; | |
3392 | struct msi_msg msg; | |
2d3fcc1c | 3393 | |
c8bc6f3c | 3394 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3395 | if (ret < 0) |
3396 | return ret; | |
3397 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3398 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3399 | "edge"); | |
54168ed7 IM |
3400 | return 0; |
3401 | } | |
3402 | #endif | |
3403 | ||
58ac1e76 | 3404 | #ifdef CONFIG_HPET_TIMER |
3405 | ||
3406 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3407 | static int hpet_msi_set_affinity(struct irq_data *data, |
3408 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3409 | { |
d0fbca8f | 3410 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3411 | struct msi_msg msg; |
3412 | unsigned int dest; | |
58ac1e76 | 3413 | |
0e09ddf2 | 3414 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3415 | return -1; |
58ac1e76 | 3416 | |
d0fbca8f | 3417 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3418 | |
3419 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3420 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3421 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3422 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3423 | ||
d0fbca8f | 3424 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3425 | |
3426 | return 0; | |
58ac1e76 | 3427 | } |
3145e941 | 3428 | |
58ac1e76 | 3429 | #endif /* CONFIG_SMP */ |
3430 | ||
c8bc6f3c | 3431 | static struct irq_chip ir_hpet_msi_type = { |
b5d1c465 TG |
3432 | .name = "IR-HPET_MSI", |
3433 | .irq_unmask = hpet_msi_unmask, | |
3434 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3435 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3436 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c | 3437 | #ifdef CONFIG_SMP |
b5d1c465 | 3438 | .irq_set_affinity = ir_msi_set_affinity, |
c8bc6f3c SS |
3439 | #endif |
3440 | #endif | |
b5d1c465 | 3441 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3442 | }; |
3443 | ||
1cc18521 | 3444 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3445 | .name = "HPET_MSI", |
d0fbca8f TG |
3446 | .irq_unmask = hpet_msi_unmask, |
3447 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3448 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3449 | #ifdef CONFIG_SMP |
d0fbca8f | 3450 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3451 | #endif |
90297c5f | 3452 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3453 | }; |
3454 | ||
c8bc6f3c | 3455 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3456 | { |
c60eaf25 | 3457 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3458 | struct msi_msg msg; |
d0fbca8f | 3459 | int ret; |
58ac1e76 | 3460 | |
c8bc6f3c SS |
3461 | if (intr_remapping_enabled) { |
3462 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3463 | int index; | |
3464 | ||
3465 | if (!iommu) | |
3466 | return -1; | |
3467 | ||
3468 | index = alloc_irte(iommu, irq, 1); | |
3469 | if (index < 0) | |
3470 | return -1; | |
3471 | } | |
3472 | ||
3473 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3474 | if (ret < 0) |
3475 | return ret; | |
3476 | ||
2c778651 | 3477 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3478 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2c778651 | 3479 | if (irq_remapped(irq_get_chip_data(irq))) |
c60eaf25 | 3480 | chip = &ir_hpet_msi_type; |
c81bba49 | 3481 | |
c60eaf25 | 3482 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3483 | return 0; |
3484 | } | |
3485 | #endif | |
3486 | ||
54168ed7 | 3487 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3488 | /* |
3489 | * Hypertransport interrupt support | |
3490 | */ | |
3491 | #ifdef CONFIG_HT_IRQ | |
3492 | ||
3493 | #ifdef CONFIG_SMP | |
3494 | ||
497c9a19 | 3495 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3496 | { |
ec68307c EB |
3497 | struct ht_irq_msg msg; |
3498 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3499 | |
497c9a19 | 3500 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3501 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3502 | |
497c9a19 | 3503 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3504 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3505 | |
ec68307c | 3506 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3507 | } |
3508 | ||
be5b7bf7 TG |
3509 | static int |
3510 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3511 | { |
be5b7bf7 | 3512 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3513 | unsigned int dest; |
8b955b0d | 3514 | |
be5b7bf7 | 3515 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3516 | return -1; |
8b955b0d | 3517 | |
be5b7bf7 | 3518 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3519 | return 0; |
8b955b0d | 3520 | } |
3145e941 | 3521 | |
8b955b0d EB |
3522 | #endif |
3523 | ||
c37e108d | 3524 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3525 | .name = "PCI-HT", |
3526 | .irq_mask = mask_ht_irq, | |
3527 | .irq_unmask = unmask_ht_irq, | |
3528 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3529 | #ifdef CONFIG_SMP |
be5b7bf7 | 3530 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3531 | #endif |
be5b7bf7 | 3532 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3533 | }; |
3534 | ||
3535 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3536 | { | |
497c9a19 YL |
3537 | struct irq_cfg *cfg; |
3538 | int err; | |
8b955b0d | 3539 | |
f1182638 JB |
3540 | if (disable_apic) |
3541 | return -ENXIO; | |
3542 | ||
3145e941 | 3543 | cfg = irq_cfg(irq); |
fe402e1f | 3544 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3545 | if (!err) { |
ec68307c | 3546 | struct ht_irq_msg msg; |
8b955b0d | 3547 | unsigned dest; |
8b955b0d | 3548 | |
debccb3e IM |
3549 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3550 | apic->target_cpus()); | |
8b955b0d | 3551 | |
ec68307c | 3552 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3553 | |
ec68307c EB |
3554 | msg.address_lo = |
3555 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3556 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3557 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3558 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3559 | HT_IRQ_LOW_DM_PHYSICAL : |
3560 | HT_IRQ_LOW_DM_LOGICAL) | | |
3561 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3562 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3563 | HT_IRQ_LOW_MT_FIXED : |
3564 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3565 | HT_IRQ_LOW_IRQ_MASKED; | |
3566 | ||
ec68307c | 3567 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3568 | |
2c778651 | 3569 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
a460e745 | 3570 | handle_edge_irq, "edge"); |
c81bba49 YL |
3571 | |
3572 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3573 | } |
497c9a19 | 3574 | return err; |
8b955b0d EB |
3575 | } |
3576 | #endif /* CONFIG_HT_IRQ */ | |
3577 | ||
ff973d04 TG |
3578 | int |
3579 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) | |
3580 | { | |
3581 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3582 | int ret; | |
3583 | ||
3584 | if (!cfg) | |
3585 | return -EINVAL; | |
3586 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3587 | if (!ret) | |
3588 | setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, | |
3589 | attr->trigger, attr->polarity); | |
3590 | return ret; | |
3591 | } | |
3592 | ||
710dcda6 TG |
3593 | static int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3594 | struct io_apic_irq_attr *attr) | |
3595 | { | |
3596 | unsigned int id = attr->ioapic, pin = attr->ioapic_pin; | |
3597 | int ret; | |
3598 | ||
3599 | /* Avoid redundant programming */ | |
3600 | if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) { | |
3601 | pr_debug("Pin %d-%d already programmed\n", | |
3602 | mp_ioapics[id].apicid, pin); | |
3603 | return 0; | |
3604 | } | |
3605 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3606 | if (!ret) | |
3607 | set_bit(pin, mp_ioapic_routing[id].pin_programmed); | |
3608 | return ret; | |
3609 | } | |
3610 | ||
41098ffe | 3611 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3612 | { |
3613 | union IO_APIC_reg_01 reg_01; | |
3614 | unsigned long flags; | |
3615 | ||
dade7716 | 3616 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3617 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3618 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3619 | |
4b6b19a1 EB |
3620 | /* The register returns the maximum index redir index |
3621 | * supported, which is one less than the total number of redir | |
3622 | * entries. | |
3623 | */ | |
3624 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3625 | } |
3626 | ||
23f9b267 | 3627 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3628 | { |
4afc51a8 | 3629 | int nr; |
be5d5350 | 3630 | |
a4384df3 | 3631 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3632 | if (nr > nr_irqs_gsi) |
be5d5350 | 3633 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3634 | |
3635 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3636 | } |
3637 | ||
7b586d71 JF |
3638 | int get_nr_irqs_gsi(void) |
3639 | { | |
3640 | return nr_irqs_gsi; | |
3641 | } | |
3642 | ||
4a046d17 YL |
3643 | #ifdef CONFIG_SPARSE_IRQ |
3644 | int __init arch_probe_nr_irqs(void) | |
3645 | { | |
3646 | int nr; | |
3647 | ||
f1ee5548 YL |
3648 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3649 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3650 | |
f1ee5548 YL |
3651 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3652 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3653 | /* | |
3654 | * for MSI and HT dyn irq | |
3655 | */ | |
3656 | nr += nr_irqs_gsi * 16; | |
3657 | #endif | |
3658 | if (nr < nr_irqs) | |
4a046d17 YL |
3659 | nr_irqs = nr; |
3660 | ||
b683de2b | 3661 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3662 | } |
3663 | #endif | |
3664 | ||
710dcda6 TG |
3665 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3666 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3667 | { |
5ef21837 YL |
3668 | int node; |
3669 | ||
3670 | if (!IO_APIC_IRQ(irq)) { | |
3671 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3672 | irq_attr->ioapic); |
5ef21837 YL |
3673 | return -EINVAL; |
3674 | } | |
3675 | ||
e0799c04 | 3676 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3677 | |
710dcda6 | 3678 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3679 | } |
3680 | ||
54168ed7 | 3681 | #ifdef CONFIG_X86_32 |
41098ffe | 3682 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3683 | { |
3684 | union IO_APIC_reg_00 reg_00; | |
3685 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3686 | physid_mask_t tmp; | |
3687 | unsigned long flags; | |
3688 | int i = 0; | |
3689 | ||
3690 | /* | |
36062448 PC |
3691 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3692 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3693 | * supports up to 16 on one shared APIC bus. |
36062448 | 3694 | * |
1da177e4 LT |
3695 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3696 | * advantage of new APIC bus architecture. | |
3697 | */ | |
3698 | ||
3699 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3700 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3701 | |
dade7716 | 3702 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3703 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3704 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3705 | |
3706 | if (apic_id >= get_physical_broadcast()) { | |
3707 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3708 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3709 | apic_id = reg_00.bits.ID; | |
3710 | } | |
3711 | ||
3712 | /* | |
36062448 | 3713 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3714 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3715 | */ | |
7abc0753 | 3716 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3717 | |
3718 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3719 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3720 | break; |
3721 | } | |
3722 | ||
3723 | if (i == get_physical_broadcast()) | |
3724 | panic("Max apic_id exceeded!\n"); | |
3725 | ||
3726 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3727 | "trying %d\n", ioapic, apic_id, i); | |
3728 | ||
3729 | apic_id = i; | |
36062448 | 3730 | } |
1da177e4 | 3731 | |
7abc0753 | 3732 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3733 | physids_or(apic_id_map, apic_id_map, tmp); |
3734 | ||
3735 | if (reg_00.bits.ID != apic_id) { | |
3736 | reg_00.bits.ID = apic_id; | |
3737 | ||
dade7716 | 3738 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3739 | io_apic_write(ioapic, 0, reg_00.raw); |
3740 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3741 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3742 | |
3743 | /* Sanity check */ | |
6070f9ec AD |
3744 | if (reg_00.bits.ID != apic_id) { |
3745 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3746 | return -1; | |
3747 | } | |
1da177e4 LT |
3748 | } |
3749 | ||
3750 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3751 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3752 | ||
3753 | return apic_id; | |
3754 | } | |
41098ffe TG |
3755 | |
3756 | static u8 __init io_apic_unique_id(u8 id) | |
3757 | { | |
3758 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3759 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3760 | return io_apic_get_unique_id(nr_ioapics, id); | |
3761 | else | |
3762 | return id; | |
3763 | } | |
3764 | #else | |
3765 | static u8 __init io_apic_unique_id(u8 id) | |
3766 | { | |
3767 | int i; | |
3768 | DECLARE_BITMAP(used, 256); | |
3769 | ||
3770 | bitmap_zero(used, 256); | |
3771 | for (i = 0; i < nr_ioapics; i++) { | |
3772 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3773 | __set_bit(ia->apicid, used); | |
3774 | } | |
3775 | if (!test_bit(id, used)) | |
3776 | return id; | |
3777 | return find_first_zero_bit(used, 256); | |
3778 | } | |
58f892e0 | 3779 | #endif |
1da177e4 | 3780 | |
41098ffe | 3781 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3782 | { |
3783 | union IO_APIC_reg_01 reg_01; | |
3784 | unsigned long flags; | |
3785 | ||
dade7716 | 3786 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3787 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3788 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3789 | |
3790 | return reg_01.bits.version; | |
3791 | } | |
3792 | ||
9a0a91bb | 3793 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3794 | { |
9a0a91bb | 3795 | int ioapic, pin, idx; |
61fd47e0 SL |
3796 | |
3797 | if (skip_ioapic_setup) | |
3798 | return -1; | |
3799 | ||
9a0a91bb EB |
3800 | ioapic = mp_find_ioapic(gsi); |
3801 | if (ioapic < 0) | |
61fd47e0 SL |
3802 | return -1; |
3803 | ||
9a0a91bb EB |
3804 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3805 | if (pin < 0) | |
3806 | return -1; | |
3807 | ||
3808 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3809 | if (idx < 0) | |
61fd47e0 SL |
3810 | return -1; |
3811 | ||
9a0a91bb EB |
3812 | *trigger = irq_trigger(idx); |
3813 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3814 | return 0; |
3815 | } | |
3816 | ||
497c9a19 YL |
3817 | /* |
3818 | * This function currently is only a helper for the i386 smp boot process where | |
3819 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3820 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3821 | */ |
3822 | #ifdef CONFIG_SMP | |
3823 | void __init setup_ioapic_dest(void) | |
3824 | { | |
fad53995 | 3825 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3826 | const struct cpumask *mask; |
5451ddc5 | 3827 | struct irq_data *idata; |
497c9a19 YL |
3828 | |
3829 | if (skip_ioapic_setup == 1) | |
3830 | return; | |
3831 | ||
fad53995 | 3832 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
3833 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
3834 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3835 | if (irq_entry == -1) | |
3836 | continue; | |
3837 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3838 | |
fad53995 EB |
3839 | if ((ioapic > 0) && (irq > 16)) |
3840 | continue; | |
3841 | ||
5451ddc5 | 3842 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3843 | |
b9c61b70 YL |
3844 | /* |
3845 | * Honour affinities which have been set in early boot | |
3846 | */ | |
5451ddc5 TG |
3847 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3848 | mask = idata->affinity; | |
b9c61b70 YL |
3849 | else |
3850 | mask = apic->target_cpus(); | |
497c9a19 | 3851 | |
b9c61b70 | 3852 | if (intr_remapping_enabled) |
5451ddc5 | 3853 | ir_ioapic_set_affinity(idata, mask, false); |
b9c61b70 | 3854 | else |
5451ddc5 | 3855 | ioapic_set_affinity(idata, mask, false); |
497c9a19 | 3856 | } |
b9c61b70 | 3857 | |
497c9a19 YL |
3858 | } |
3859 | #endif | |
3860 | ||
54168ed7 IM |
3861 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3862 | ||
3863 | static struct resource *ioapic_resources; | |
3864 | ||
ffc43836 | 3865 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3866 | { |
3867 | unsigned long n; | |
3868 | struct resource *res; | |
3869 | char *mem; | |
3870 | int i; | |
3871 | ||
3872 | if (nr_ioapics <= 0) | |
3873 | return NULL; | |
3874 | ||
3875 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3876 | n *= nr_ioapics; | |
3877 | ||
3878 | mem = alloc_bootmem(n); | |
3879 | res = (void *)mem; | |
3880 | ||
ffc43836 | 3881 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3882 | |
ffc43836 CG |
3883 | for (i = 0; i < nr_ioapics; i++) { |
3884 | res[i].name = mem; | |
3885 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3886 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3887 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3888 | } |
3889 | ||
3890 | ioapic_resources = res; | |
3891 | ||
3892 | return res; | |
3893 | } | |
54168ed7 | 3894 | |
23f9b267 | 3895 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3896 | { |
3897 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3898 | struct resource *ioapic_res; |
d6c88a50 | 3899 | int i; |
f3294a33 | 3900 | |
ffc43836 | 3901 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3902 | for (i = 0; i < nr_ioapics; i++) { |
3903 | if (smp_found_config) { | |
b5ba7e6d | 3904 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 3905 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3906 | if (!ioapic_phys) { |
3907 | printk(KERN_ERR | |
3908 | "WARNING: bogus zero IO-APIC " | |
3909 | "address found in MPTABLE, " | |
3910 | "disabling IO/APIC support!\n"); | |
3911 | smp_found_config = 0; | |
3912 | skip_ioapic_setup = 1; | |
3913 | goto fake_ioapic_page; | |
3914 | } | |
54168ed7 | 3915 | #endif |
f3294a33 | 3916 | } else { |
54168ed7 | 3917 | #ifdef CONFIG_X86_32 |
f3294a33 | 3918 | fake_ioapic_page: |
54168ed7 | 3919 | #endif |
e79c65a9 | 3920 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3921 | ioapic_phys = __pa(ioapic_phys); |
3922 | } | |
3923 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3924 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3925 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3926 | ioapic_phys); | |
f3294a33 | 3927 | idx++; |
54168ed7 | 3928 | |
ffc43836 | 3929 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3930 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3931 | ioapic_res++; |
f3294a33 | 3932 | } |
23f9b267 TG |
3933 | |
3934 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3935 | } |
3936 | ||
857fdc53 | 3937 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3938 | { |
3939 | int i; | |
3940 | struct resource *r = ioapic_resources; | |
3941 | ||
3942 | if (!r) { | |
857fdc53 | 3943 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3944 | printk(KERN_ERR |
3945 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3946 | return; |
54168ed7 IM |
3947 | } |
3948 | ||
3949 | for (i = 0; i < nr_ioapics; i++) { | |
3950 | insert_resource(&iomem_resource, r); | |
3951 | r++; | |
3952 | } | |
54168ed7 | 3953 | } |
2a4ab640 | 3954 | |
eddb0c55 | 3955 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3956 | { |
3957 | int i = 0; | |
3958 | ||
678301ec PB |
3959 | if (nr_ioapics == 0) |
3960 | return -1; | |
3961 | ||
2a4ab640 FT |
3962 | /* Find the IOAPIC that manages this GSI. */ |
3963 | for (i = 0; i < nr_ioapics; i++) { | |
3964 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
3965 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
3966 | return i; | |
3967 | } | |
54168ed7 | 3968 | |
2a4ab640 FT |
3969 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3970 | return -1; | |
3971 | } | |
3972 | ||
eddb0c55 | 3973 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
3974 | { |
3975 | if (WARN_ON(ioapic == -1)) | |
3976 | return -1; | |
3977 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
3978 | return -1; | |
3979 | ||
3980 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
3981 | } | |
3982 | ||
41098ffe | 3983 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3984 | { |
3985 | if (nr_ioapics >= MAX_IO_APICS) { | |
3986 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
3987 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
3988 | return 1; | |
3989 | } | |
3990 | if (!address) { | |
3991 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
3992 | " found in table, skipping!\n"); | |
3993 | return 1; | |
3994 | } | |
54168ed7 IM |
3995 | return 0; |
3996 | } | |
3997 | ||
2a4ab640 FT |
3998 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3999 | { | |
4000 | int idx = 0; | |
7716a5c4 | 4001 | int entries; |
2a4ab640 FT |
4002 | |
4003 | if (bad_ioapic(address)) | |
4004 | return; | |
4005 | ||
4006 | idx = nr_ioapics; | |
4007 | ||
4008 | mp_ioapics[idx].type = MP_IOAPIC; | |
4009 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4010 | mp_ioapics[idx].apicaddr = address; | |
4011 | ||
4012 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4013 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4014 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4015 | ||
4016 | /* | |
4017 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4018 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4019 | */ | |
7716a5c4 | 4020 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4021 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4022 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4023 | ||
4024 | /* | |
4025 | * The number of IO-APIC IRQ registers (== #pins): | |
4026 | */ | |
4027 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4028 | |
a4384df3 EB |
4029 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4030 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4031 | |
4032 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4033 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4034 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4035 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4036 | ||
4037 | nr_ioapics++; | |
4038 | } | |
05ddafb1 JP |
4039 | |
4040 | /* Enable IOAPIC early just for system timer */ | |
4041 | void __init pre_init_apic_IRQ0(void) | |
4042 | { | |
f880ec78 | 4043 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
4044 | |
4045 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4046 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
4047 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
4048 | &phys_cpu_present_map); | |
05ddafb1 | 4049 | #endif |
05ddafb1 JP |
4050 | setup_local_APIC(); |
4051 | ||
f880ec78 | 4052 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
4053 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
4054 | "edge"); | |
05ddafb1 | 4055 | } |