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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
d7f3d478 | 34 | #include <linux/irqdomain.h> |
7dfb7103 | 35 | #include <linux/freezer.h> |
f26d6a2b | 36 | #include <linux/kthread.h> |
54168ed7 | 37 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 38 | #include <linux/slab.h> |
d4057bdb | 39 | #include <linux/bootmem.h> |
54d5d424 | 40 | |
d4057bdb | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
6d652ea1 | 44 | #include <asm/cpu.h> |
1da177e4 | 45 | #include <asm/desc.h> |
d4057bdb YL |
46 | #include <asm/proto.h> |
47 | #include <asm/acpi.h> | |
48 | #include <asm/dma.h> | |
1da177e4 | 49 | #include <asm/timer.h> |
306e440d | 50 | #include <asm/i8259.h> |
a4dbc34d | 51 | #include <asm/setup.h> |
8a8f422d | 52 | #include <asm/irq_remapping.h> |
2c1b284e | 53 | #include <asm/hw_irq.h> |
1da177e4 | 54 | |
7b6aa335 | 55 | #include <asm/apic.h> |
1da177e4 | 56 | |
f44d1692 JL |
57 | #define for_each_ioapic(idx) \ |
58 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
59 | #define for_each_ioapic_reverse(idx) \ | |
60 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
61 | #define for_each_pin(idx, pin) \ | |
62 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
63 | #define for_each_ioapic_pin(idx, pin) \ | |
64 | for_each_ioapic((idx)) \ | |
65 | for_each_pin((idx), (pin)) | |
66 | ||
2977fb3f | 67 | #define for_each_irq_pin(entry, head) \ |
a178b87b | 68 | list_for_each_entry(entry, &head, list) |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 | 76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
d7f3d478 | 77 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 78 | static unsigned int ioapic_dynirq_base; |
b81975ea | 79 | static int ioapic_initialized; |
efa2559f | 80 | |
49c7e600 JL |
81 | struct mp_chip_data { |
82 | struct IO_APIC_route_entry entry; | |
83 | int trigger; | |
84 | int polarity; | |
85 | bool isa_irq; | |
86 | }; | |
87 | ||
15a3c7cc JL |
88 | struct mp_pin_info { |
89 | int trigger; | |
90 | int polarity; | |
91 | int node; | |
92 | int set; | |
93 | u32 count; | |
94 | }; | |
95 | ||
b69c6c3b SS |
96 | static struct ioapic { |
97 | /* | |
98 | * # of IRQ routing registers | |
99 | */ | |
100 | int nr_registers; | |
57a6f740 SS |
101 | /* |
102 | * Saved state during suspend/resume, or while enabling intr-remap. | |
103 | */ | |
104 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
105 | /* I/O APIC config */ |
106 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
107 | /* IO APIC gsi routing info */ |
108 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
109 | struct ioapic_domain_cfg irqdomain_cfg; |
110 | struct irq_domain *irqdomain; | |
15a3c7cc | 111 | struct mp_pin_info *pin_info; |
15516a3b | 112 | struct resource *iomem_res; |
b69c6c3b | 113 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 114 | |
6f50d45f | 115 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 116 | |
6f50d45f | 117 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 118 | { |
6f50d45f | 119 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
120 | } |
121 | ||
6f50d45f | 122 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 123 | { |
6f50d45f | 124 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
125 | } |
126 | ||
6f50d45f | 127 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 128 | { |
6f50d45f | 129 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 130 | } |
9f640ccb | 131 | |
18e48551 JL |
132 | static inline int mp_ioapic_pin_count(int ioapic) |
133 | { | |
134 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
135 | ||
136 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
137 | } | |
138 | ||
139 | u32 mp_pin_to_gsi(int ioapic, int pin) | |
140 | { | |
141 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
142 | } | |
143 | ||
95d76acc JL |
144 | /* |
145 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
146 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
147 | * may rely on non-legacy pins on the first IOAPIC. | |
148 | */ | |
18e48551 JL |
149 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
150 | { | |
95d76acc JL |
151 | if (!nr_legacy_irqs()) |
152 | return 0; | |
153 | ||
154 | return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs()); | |
18e48551 JL |
155 | } |
156 | ||
15a3c7cc JL |
157 | static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin) |
158 | { | |
159 | return ioapics[ioapic_idx].pin_info + pin; | |
160 | } | |
161 | ||
d7f3d478 JL |
162 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
163 | { | |
164 | return ioapics[ioapic].irqdomain; | |
165 | } | |
166 | ||
c040aaeb | 167 | int nr_ioapics; |
2a4ab640 | 168 | |
a4384df3 EB |
169 | /* The one past the highest gsi number used */ |
170 | u32 gsi_top; | |
5777372a | 171 | |
584f734d | 172 | /* MP IRQ source entries */ |
c2c21745 | 173 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
174 | |
175 | /* # of MP IRQ source entries */ | |
176 | int mp_irq_entries; | |
177 | ||
bb8187d3 | 178 | #ifdef CONFIG_EISA |
8732fc4b AS |
179 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
180 | #endif | |
181 | ||
182 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
183 | ||
efa2559f YL |
184 | int skip_ioapic_setup; |
185 | ||
7167d08e HK |
186 | /** |
187 | * disable_ioapic_support() - disables ioapic support at runtime | |
188 | */ | |
189 | void disable_ioapic_support(void) | |
65a4e574 IM |
190 | { |
191 | #ifdef CONFIG_PCI | |
192 | noioapicquirk = 1; | |
193 | noioapicreroute = -1; | |
194 | #endif | |
195 | skip_ioapic_setup = 1; | |
196 | } | |
197 | ||
54168ed7 | 198 | static int __init parse_noapic(char *str) |
efa2559f YL |
199 | { |
200 | /* disable IO-APIC */ | |
7167d08e | 201 | disable_ioapic_support(); |
efa2559f YL |
202 | return 0; |
203 | } | |
204 | early_param("noapic", parse_noapic); | |
66759a01 | 205 | |
2d8009ba FT |
206 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
207 | void mp_save_irq(struct mpc_intsrc *m) | |
208 | { | |
209 | int i; | |
210 | ||
211 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
212 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
213 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
214 | m->srcbusirq, m->dstapic, m->dstirq); | |
215 | ||
216 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 217 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
218 | return; |
219 | } | |
220 | ||
0e3fa13f | 221 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
222 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
223 | panic("Max # of irq sources exceeded!!\n"); | |
224 | } | |
225 | ||
0b8f1efa | 226 | struct irq_pin_list { |
a178b87b | 227 | struct list_head list; |
0b8f1efa | 228 | int apic, pin; |
0b8f1efa YL |
229 | }; |
230 | ||
7e495529 | 231 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 232 | { |
2ee39065 | 233 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
234 | } |
235 | ||
7e899419 YL |
236 | static void alloc_ioapic_saved_registers(int idx) |
237 | { | |
238 | size_t size; | |
239 | ||
240 | if (ioapics[idx].saved_registers) | |
241 | return; | |
242 | ||
243 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; | |
244 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); | |
245 | if (!ioapics[idx].saved_registers) | |
246 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); | |
247 | } | |
248 | ||
15516a3b JL |
249 | static void free_ioapic_saved_registers(int idx) |
250 | { | |
251 | kfree(ioapics[idx].saved_registers); | |
252 | ioapics[idx].saved_registers = NULL; | |
253 | } | |
254 | ||
11d686e9 | 255 | int __init arch_early_ioapic_init(void) |
8f09cd20 | 256 | { |
13315320 | 257 | int i; |
d6c88a50 | 258 | |
95d76acc | 259 | if (!nr_legacy_irqs()) |
1f91233c | 260 | io_apic_irqs = ~0UL; |
1f91233c | 261 | |
7e899419 YL |
262 | for_each_ioapic(i) |
263 | alloc_ioapic_saved_registers(i); | |
4c79185c | 264 | |
13a0c3c2 | 265 | return 0; |
0b8f1efa | 266 | } |
8f09cd20 | 267 | |
130fe05d LT |
268 | struct io_apic { |
269 | unsigned int index; | |
270 | unsigned int unused[3]; | |
271 | unsigned int data; | |
0280f7c4 SS |
272 | unsigned int unused2[11]; |
273 | unsigned int eoi; | |
130fe05d LT |
274 | }; |
275 | ||
276 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
277 | { | |
278 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 279 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
280 | } |
281 | ||
da165322 | 282 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
283 | { |
284 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
285 | writel(vector, &io_apic->eoi); | |
286 | } | |
287 | ||
4a8e2a31 | 288 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
289 | { |
290 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
291 | writel(reg, &io_apic->index); | |
292 | return readl(&io_apic->data); | |
293 | } | |
294 | ||
4a8e2a31 | 295 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
296 | { |
297 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 298 | |
130fe05d LT |
299 | writel(reg, &io_apic->index); |
300 | writel(value, &io_apic->data); | |
301 | } | |
302 | ||
303 | /* | |
304 | * Re-write a value: to be used for read-modify-write | |
305 | * cycles where the read already set up the index register. | |
306 | * | |
307 | * Older SiS APIC requires we rewrite the index register | |
308 | */ | |
4a8e2a31 | 309 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 310 | { |
54168ed7 | 311 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
312 | |
313 | if (sis_apic_bug) | |
314 | writel(reg, &io_apic->index); | |
130fe05d LT |
315 | writel(value, &io_apic->data); |
316 | } | |
317 | ||
cf4c6a2f AK |
318 | union entry_union { |
319 | struct { u32 w1, w2; }; | |
320 | struct IO_APIC_route_entry entry; | |
321 | }; | |
322 | ||
e57253a8 SS |
323 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
324 | { | |
325 | union entry_union eu; | |
326 | ||
327 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
328 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 329 | |
e57253a8 SS |
330 | return eu.entry; |
331 | } | |
332 | ||
cf4c6a2f AK |
333 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
334 | { | |
335 | union entry_union eu; | |
336 | unsigned long flags; | |
136d249e | 337 | |
dade7716 | 338 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 339 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 340 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 341 | |
cf4c6a2f AK |
342 | return eu.entry; |
343 | } | |
344 | ||
f9dadfa7 LT |
345 | /* |
346 | * When we write a new IO APIC routing entry, we need to write the high | |
347 | * word first! If the mask bit in the low word is clear, we will enable | |
348 | * the interrupt, and we need to make sure the entry is fully populated | |
349 | * before that happens. | |
350 | */ | |
136d249e | 351 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 352 | { |
50a8d4d2 F |
353 | union entry_union eu = {{0, 0}}; |
354 | ||
cf4c6a2f | 355 | eu.entry = e; |
f9dadfa7 LT |
356 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
357 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
358 | } |
359 | ||
1a8ce7ff | 360 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
361 | { |
362 | unsigned long flags; | |
136d249e | 363 | |
dade7716 | 364 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 365 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 366 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
367 | } |
368 | ||
369 | /* | |
370 | * When we mask an IO APIC routing entry, we need to write the low | |
371 | * word first, in order to set the mask bit before we change the | |
372 | * high bits! | |
373 | */ | |
374 | static void ioapic_mask_entry(int apic, int pin) | |
375 | { | |
376 | unsigned long flags; | |
377 | union entry_union eu = { .entry.mask = 1 }; | |
378 | ||
dade7716 | 379 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
380 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
381 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 382 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
383 | } |
384 | ||
1da177e4 LT |
385 | /* |
386 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
387 | * shared ISA-space IRQs, so we have to support them. We are super | |
388 | * fast in the common case, and fast for shared ISA-space IRQs. | |
389 | */ | |
136d249e | 390 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 391 | { |
a178b87b | 392 | struct irq_pin_list *entry; |
0f978f45 | 393 | |
2977fb3f | 394 | /* don't allow duplicates */ |
a178b87b | 395 | for_each_irq_pin(entry, cfg->irq_2_pin) |
0f978f45 | 396 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 397 | return 0; |
0f978f45 | 398 | |
7e495529 | 399 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 400 | if (!entry) { |
c767a54b JP |
401 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
402 | node, apic, pin); | |
f3d1915a | 403 | return -ENOMEM; |
a7428cd2 | 404 | } |
1da177e4 LT |
405 | entry->apic = apic; |
406 | entry->pin = pin; | |
875e68ec | 407 | |
a178b87b | 408 | list_add_tail(&entry->list, &cfg->irq_2_pin); |
f3d1915a CG |
409 | return 0; |
410 | } | |
411 | ||
df334bea JL |
412 | static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin) |
413 | { | |
a178b87b | 414 | struct irq_pin_list *tmp, *entry; |
df334bea | 415 | |
a178b87b | 416 | list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list) |
df334bea | 417 | if (entry->apic == apic && entry->pin == pin) { |
a178b87b | 418 | list_del(&entry->list); |
df334bea JL |
419 | kfree(entry); |
420 | return; | |
df334bea JL |
421 | } |
422 | } | |
423 | ||
f3d1915a CG |
424 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
425 | { | |
7e495529 | 426 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 427 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
428 | } |
429 | ||
430 | /* | |
431 | * Reroute an IRQ to a different pin. | |
432 | */ | |
85ac16d0 | 433 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
434 | int oldapic, int oldpin, |
435 | int newapic, int newpin) | |
1da177e4 | 436 | { |
535b6429 | 437 | struct irq_pin_list *entry; |
1da177e4 | 438 | |
2977fb3f | 439 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
440 | if (entry->apic == oldapic && entry->pin == oldpin) { |
441 | entry->apic = newapic; | |
442 | entry->pin = newpin; | |
0f978f45 | 443 | /* every one is different, right? */ |
4eea6fff | 444 | return; |
0f978f45 | 445 | } |
1da177e4 | 446 | } |
0f978f45 | 447 | |
4eea6fff JF |
448 | /* old apic/pin didn't exist, so just add new ones */ |
449 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
450 | } |
451 | ||
c29d9db3 SS |
452 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
453 | int mask_and, int mask_or, | |
454 | void (*final)(struct irq_pin_list *entry)) | |
455 | { | |
456 | unsigned int reg, pin; | |
457 | ||
458 | pin = entry->pin; | |
459 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
460 | reg &= mask_and; | |
461 | reg |= mask_or; | |
462 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
463 | if (final) | |
464 | final(entry); | |
465 | } | |
466 | ||
2f210deb JF |
467 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
468 | int mask_and, int mask_or, | |
469 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 470 | { |
87783be4 | 471 | struct irq_pin_list *entry; |
047c8fdb | 472 | |
c29d9db3 SS |
473 | for_each_irq_pin(entry, cfg->irq_2_pin) |
474 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
475 | } | |
476 | ||
7f3e632f | 477 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 478 | { |
87783be4 CG |
479 | /* |
480 | * Synchronize the IO-APIC and the CPU by doing | |
481 | * a dummy read from the IO-APIC | |
482 | */ | |
483 | struct io_apic __iomem *io_apic; | |
136d249e | 484 | |
87783be4 | 485 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 486 | readl(&io_apic->data); |
1da177e4 LT |
487 | } |
488 | ||
dd5f15e5 | 489 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 490 | { |
dd5f15e5 TG |
491 | unsigned long flags; |
492 | ||
493 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 494 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 495 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 496 | } |
1da177e4 | 497 | |
90297c5f | 498 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 499 | { |
a9786091 | 500 | mask_ioapic(irqd_cfg(data)); |
dd5f15e5 | 501 | } |
3145e941 | 502 | |
dd5f15e5 TG |
503 | static void __unmask_ioapic(struct irq_cfg *cfg) |
504 | { | |
505 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
506 | } |
507 | ||
dd5f15e5 | 508 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
509 | { |
510 | unsigned long flags; | |
511 | ||
dade7716 | 512 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 513 | __unmask_ioapic(cfg); |
dade7716 | 514 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
515 | } |
516 | ||
90297c5f | 517 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 518 | { |
a9786091 | 519 | unmask_ioapic(irqd_cfg(data)); |
3145e941 YL |
520 | } |
521 | ||
c0205701 SS |
522 | /* |
523 | * IO-APIC versions below 0x20 don't support EOI register. | |
524 | * For the record, here is the information about various versions: | |
525 | * 0Xh 82489DX | |
526 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
527 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
528 | * 30h-FFh Reserved | |
529 | * | |
530 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
531 | * version as 0x2. This is an error with documentation and these ICH chips | |
532 | * use io-apic's of version 0x20. | |
533 | * | |
534 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
535 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
536 | * mode to edge and then back to level, with RTE being masked during this. | |
537 | */ | |
da165322 | 538 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
539 | { |
540 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 541 | io_apic_eoi(apic, vector); |
c0205701 SS |
542 | } else { |
543 | struct IO_APIC_route_entry entry, entry1; | |
544 | ||
545 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
546 | ||
547 | /* | |
548 | * Mask the entry and change the trigger mode to edge. | |
549 | */ | |
550 | entry1.mask = 1; | |
551 | entry1.trigger = IOAPIC_EDGE; | |
552 | ||
553 | __ioapic_write_entry(apic, pin, entry1); | |
554 | ||
555 | /* | |
556 | * Restore the previous level triggered entry. | |
557 | */ | |
558 | __ioapic_write_entry(apic, pin, entry); | |
559 | } | |
560 | } | |
561 | ||
9b1b0e42 | 562 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
c0205701 SS |
563 | { |
564 | struct irq_pin_list *entry; | |
565 | unsigned long flags; | |
566 | ||
567 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
568 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
da165322 JR |
569 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
570 | cfg->vector); | |
c0205701 SS |
571 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
572 | } | |
573 | ||
1da177e4 LT |
574 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
575 | { | |
576 | struct IO_APIC_route_entry entry; | |
36062448 | 577 | |
1da177e4 | 578 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 579 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
580 | if (entry.delivery_mode == dest_SMI) |
581 | return; | |
1e75b31d | 582 | |
1da177e4 | 583 | /* |
1e75b31d SS |
584 | * Make sure the entry is masked and re-read the contents to check |
585 | * if it is a level triggered pin and if the remote-IRR is set. | |
586 | */ | |
587 | if (!entry.mask) { | |
588 | entry.mask = 1; | |
589 | ioapic_write_entry(apic, pin, entry); | |
590 | entry = ioapic_read_entry(apic, pin); | |
591 | } | |
592 | ||
593 | if (entry.irr) { | |
c0205701 SS |
594 | unsigned long flags; |
595 | ||
1e75b31d SS |
596 | /* |
597 | * Make sure the trigger mode is set to level. Explicit EOI | |
598 | * doesn't clear the remote-IRR if the trigger mode is not | |
599 | * set to level. | |
600 | */ | |
601 | if (!entry.trigger) { | |
602 | entry.trigger = IOAPIC_LEVEL; | |
603 | ioapic_write_entry(apic, pin, entry); | |
604 | } | |
605 | ||
c0205701 | 606 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
da165322 | 607 | x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 608 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
609 | } |
610 | ||
611 | /* | |
612 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
613 | * bit. | |
1da177e4 | 614 | */ |
f9dadfa7 | 615 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
616 | entry = ioapic_read_entry(apic, pin); |
617 | if (entry.irr) | |
c767a54b | 618 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 619 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
620 | } |
621 | ||
54168ed7 | 622 | static void clear_IO_APIC (void) |
1da177e4 LT |
623 | { |
624 | int apic, pin; | |
625 | ||
f44d1692 JL |
626 | for_each_ioapic_pin(apic, pin) |
627 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
628 | } |
629 | ||
54168ed7 | 630 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
631 | /* |
632 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
633 | * specific CPU-side IRQs. | |
634 | */ | |
635 | ||
636 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
637 | static int pirq_entries[MAX_PIRQS] = { |
638 | [0 ... MAX_PIRQS - 1] = -1 | |
639 | }; | |
1da177e4 | 640 | |
1da177e4 LT |
641 | static int __init ioapic_pirq_setup(char *str) |
642 | { | |
643 | int i, max; | |
644 | int ints[MAX_PIRQS+1]; | |
645 | ||
646 | get_options(str, ARRAY_SIZE(ints), ints); | |
647 | ||
1da177e4 LT |
648 | apic_printk(APIC_VERBOSE, KERN_INFO |
649 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
650 | max = MAX_PIRQS; | |
651 | if (ints[0] < MAX_PIRQS) | |
652 | max = ints[0]; | |
653 | ||
654 | for (i = 0; i < max; i++) { | |
655 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
656 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
657 | /* | |
658 | * PIRQs are mapped upside down, usually. | |
659 | */ | |
660 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
661 | } | |
662 | return 1; | |
663 | } | |
664 | ||
665 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
666 | #endif /* CONFIG_X86_32 */ |
667 | ||
54168ed7 | 668 | /* |
05c3dc2c | 669 | * Saves all the IO-APIC RTE's |
54168ed7 | 670 | */ |
31dce14a | 671 | int save_ioapic_entries(void) |
54168ed7 | 672 | { |
54168ed7 | 673 | int apic, pin; |
31dce14a | 674 | int err = 0; |
54168ed7 | 675 | |
f44d1692 | 676 | for_each_ioapic(apic) { |
57a6f740 | 677 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
678 | err = -ENOMEM; |
679 | continue; | |
680 | } | |
54168ed7 | 681 | |
f44d1692 | 682 | for_each_pin(apic, pin) |
57a6f740 | 683 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 684 | ioapic_read_entry(apic, pin); |
b24696bc | 685 | } |
5ffa4eb2 | 686 | |
31dce14a | 687 | return err; |
54168ed7 IM |
688 | } |
689 | ||
b24696bc FY |
690 | /* |
691 | * Mask all IO APIC entries. | |
692 | */ | |
31dce14a | 693 | void mask_ioapic_entries(void) |
05c3dc2c SS |
694 | { |
695 | int apic, pin; | |
696 | ||
f44d1692 | 697 | for_each_ioapic(apic) { |
2f344d2e | 698 | if (!ioapics[apic].saved_registers) |
31dce14a | 699 | continue; |
b24696bc | 700 | |
f44d1692 | 701 | for_each_pin(apic, pin) { |
05c3dc2c SS |
702 | struct IO_APIC_route_entry entry; |
703 | ||
57a6f740 | 704 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
705 | if (!entry.mask) { |
706 | entry.mask = 1; | |
707 | ioapic_write_entry(apic, pin, entry); | |
708 | } | |
709 | } | |
710 | } | |
711 | } | |
712 | ||
b24696bc | 713 | /* |
57a6f740 | 714 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 715 | */ |
31dce14a | 716 | int restore_ioapic_entries(void) |
54168ed7 IM |
717 | { |
718 | int apic, pin; | |
719 | ||
f44d1692 | 720 | for_each_ioapic(apic) { |
2f344d2e | 721 | if (!ioapics[apic].saved_registers) |
31dce14a | 722 | continue; |
b24696bc | 723 | |
f44d1692 | 724 | for_each_pin(apic, pin) |
54168ed7 | 725 | ioapic_write_entry(apic, pin, |
57a6f740 | 726 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 727 | } |
b24696bc | 728 | return 0; |
54168ed7 IM |
729 | } |
730 | ||
1da177e4 LT |
731 | /* |
732 | * Find the IRQ entry number of a certain pin. | |
733 | */ | |
6f50d45f | 734 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
735 | { |
736 | int i; | |
737 | ||
738 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 739 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 740 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
741 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
742 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
743 | return i; |
744 | ||
745 | return -1; | |
746 | } | |
747 | ||
748 | /* | |
749 | * Find the pin to which IRQ[irq] (ISA) is connected | |
750 | */ | |
fcfd636a | 751 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
752 | { |
753 | int i; | |
754 | ||
755 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 756 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 757 | |
d27e2b8e | 758 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
759 | (mp_irqs[i].irqtype == type) && |
760 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 761 | |
c2c21745 | 762 | return mp_irqs[i].dstirq; |
1da177e4 LT |
763 | } |
764 | return -1; | |
765 | } | |
766 | ||
fcfd636a EB |
767 | static int __init find_isa_irq_apic(int irq, int type) |
768 | { | |
769 | int i; | |
770 | ||
771 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 772 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 773 | |
73b2961b | 774 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
775 | (mp_irqs[i].irqtype == type) && |
776 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
777 | break; |
778 | } | |
6f50d45f | 779 | |
fcfd636a | 780 | if (i < mp_irq_entries) { |
6f50d45f YL |
781 | int ioapic_idx; |
782 | ||
f44d1692 | 783 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
784 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
785 | return ioapic_idx; | |
fcfd636a EB |
786 | } |
787 | ||
788 | return -1; | |
789 | } | |
790 | ||
bb8187d3 | 791 | #ifdef CONFIG_EISA |
1da177e4 LT |
792 | /* |
793 | * EISA Edge/Level control register, ELCR | |
794 | */ | |
795 | static int EISA_ELCR(unsigned int irq) | |
796 | { | |
95d76acc | 797 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
798 | unsigned int port = 0x4d0 + (irq >> 3); |
799 | return (inb(port) >> (irq & 7)) & 1; | |
800 | } | |
801 | apic_printk(APIC_VERBOSE, KERN_INFO | |
802 | "Broken MPtable reports ISA irq %d\n", irq); | |
803 | return 0; | |
804 | } | |
54168ed7 | 805 | |
c0a282c2 | 806 | #endif |
1da177e4 | 807 | |
6728801d AS |
808 | /* ISA interrupts are always polarity zero edge triggered, |
809 | * when listed as conforming in the MP table. */ | |
810 | ||
811 | #define default_ISA_trigger(idx) (0) | |
812 | #define default_ISA_polarity(idx) (0) | |
813 | ||
1da177e4 LT |
814 | /* EISA interrupts are always polarity zero and can be edge or level |
815 | * trigger depending on the ELCR value. If an interrupt is listed as | |
816 | * EISA conforming in the MP table, that means its trigger type must | |
817 | * be read in from the ELCR */ | |
818 | ||
c2c21745 | 819 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 820 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
821 | |
822 | /* PCI interrupts are always polarity one level triggered, | |
823 | * when listed as conforming in the MP table. */ | |
824 | ||
825 | #define default_PCI_trigger(idx) (1) | |
826 | #define default_PCI_polarity(idx) (1) | |
827 | ||
b77cf6a8 | 828 | static int irq_polarity(int idx) |
1da177e4 | 829 | { |
c2c21745 | 830 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
831 | int polarity; |
832 | ||
833 | /* | |
834 | * Determine IRQ line polarity (high active or low active): | |
835 | */ | |
c2c21745 | 836 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 837 | { |
54168ed7 IM |
838 | case 0: /* conforms, ie. bus-type dependent polarity */ |
839 | if (test_bit(bus, mp_bus_not_pci)) | |
840 | polarity = default_ISA_polarity(idx); | |
841 | else | |
842 | polarity = default_PCI_polarity(idx); | |
843 | break; | |
844 | case 1: /* high active */ | |
845 | { | |
846 | polarity = 0; | |
847 | break; | |
848 | } | |
849 | case 2: /* reserved */ | |
850 | { | |
c767a54b | 851 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
852 | polarity = 1; |
853 | break; | |
854 | } | |
855 | case 3: /* low active */ | |
856 | { | |
857 | polarity = 1; | |
858 | break; | |
859 | } | |
860 | default: /* invalid */ | |
861 | { | |
c767a54b | 862 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
863 | polarity = 1; |
864 | break; | |
865 | } | |
1da177e4 LT |
866 | } |
867 | return polarity; | |
868 | } | |
869 | ||
b77cf6a8 | 870 | static int irq_trigger(int idx) |
1da177e4 | 871 | { |
c2c21745 | 872 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
873 | int trigger; |
874 | ||
875 | /* | |
876 | * Determine IRQ trigger mode (edge or level sensitive): | |
877 | */ | |
c2c21745 | 878 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 879 | { |
54168ed7 IM |
880 | case 0: /* conforms, ie. bus-type dependent */ |
881 | if (test_bit(bus, mp_bus_not_pci)) | |
882 | trigger = default_ISA_trigger(idx); | |
883 | else | |
884 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 885 | #ifdef CONFIG_EISA |
54168ed7 IM |
886 | switch (mp_bus_id_to_type[bus]) { |
887 | case MP_BUS_ISA: /* ISA pin */ | |
888 | { | |
889 | /* set before the switch */ | |
890 | break; | |
891 | } | |
892 | case MP_BUS_EISA: /* EISA pin */ | |
893 | { | |
894 | trigger = default_EISA_trigger(idx); | |
895 | break; | |
896 | } | |
897 | case MP_BUS_PCI: /* PCI pin */ | |
898 | { | |
899 | /* set before the switch */ | |
900 | break; | |
901 | } | |
54168ed7 IM |
902 | default: |
903 | { | |
c767a54b | 904 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
905 | trigger = 1; |
906 | break; | |
907 | } | |
908 | } | |
909 | #endif | |
1da177e4 | 910 | break; |
54168ed7 | 911 | case 1: /* edge */ |
1da177e4 | 912 | { |
54168ed7 | 913 | trigger = 0; |
1da177e4 LT |
914 | break; |
915 | } | |
54168ed7 | 916 | case 2: /* reserved */ |
1da177e4 | 917 | { |
c767a54b | 918 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 919 | trigger = 1; |
1da177e4 LT |
920 | break; |
921 | } | |
54168ed7 | 922 | case 3: /* level */ |
1da177e4 | 923 | { |
54168ed7 | 924 | trigger = 1; |
1da177e4 LT |
925 | break; |
926 | } | |
54168ed7 | 927 | default: /* invalid */ |
1da177e4 | 928 | { |
c767a54b | 929 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 930 | trigger = 0; |
1da177e4 LT |
931 | break; |
932 | } | |
933 | } | |
934 | return trigger; | |
935 | } | |
936 | ||
c4d05a2c JL |
937 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
938 | int trigger, int polarity) | |
939 | { | |
940 | init_irq_alloc_info(info, NULL); | |
941 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
942 | info->ioapic_node = node; | |
943 | info->ioapic_trigger = trigger; | |
944 | info->ioapic_polarity = polarity; | |
945 | info->ioapic_valid = 1; | |
946 | } | |
947 | ||
49c7e600 JL |
948 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
949 | { | |
950 | irq_flow_handler_t hdl; | |
951 | bool fasteoi; | |
952 | ||
953 | if (trigger) { | |
954 | irq_set_status_flags(irq, IRQ_LEVEL); | |
955 | fasteoi = true; | |
956 | } else { | |
957 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
958 | fasteoi = false; | |
959 | } | |
960 | ||
961 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; | |
962 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); | |
963 | } | |
964 | ||
c4d05a2c JL |
965 | static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin, |
966 | struct irq_alloc_info *info) | |
6b9fb708 | 967 | { |
d7f3d478 | 968 | int irq = -1; |
49c7e600 | 969 | int ioapic = mp_irqdomain_ioapic_idx(domain); |
d7f3d478 JL |
970 | int type = ioapics[ioapic].irqdomain_cfg.type; |
971 | ||
972 | switch (type) { | |
973 | case IOAPIC_DOMAIN_LEGACY: | |
974 | /* | |
975 | * Dynamically allocate IRQ number for non-ISA IRQs in the first 16 | |
976 | * GSIs on some weird platforms. | |
977 | */ | |
978 | if (gsi < nr_legacy_irqs()) | |
979 | irq = irq_create_mapping(domain, pin); | |
980 | else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0) | |
981 | irq = gsi; | |
982 | break; | |
983 | case IOAPIC_DOMAIN_STRICT: | |
984 | if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0) | |
985 | irq = gsi; | |
986 | break; | |
987 | case IOAPIC_DOMAIN_DYNAMIC: | |
988 | irq = irq_create_mapping(domain, pin); | |
989 | break; | |
990 | default: | |
991 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
992 | break; | |
993 | } | |
994 | ||
995 | return irq > 0 ? irq : -1; | |
996 | } | |
997 | ||
998 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
c4d05a2c | 999 | unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1000 | { |
1001 | int irq; | |
1002 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); | |
c4d05a2c | 1003 | struct mp_pin_info *pinfo = mp_pin_info(ioapic, pin); |
d7f3d478 | 1004 | |
b81975ea JL |
1005 | if (!domain) |
1006 | return -1; | |
16ee7b3d JL |
1007 | |
1008 | mutex_lock(&ioapic_mutex); | |
1009 | ||
6b9fb708 | 1010 | /* |
d7f3d478 JL |
1011 | * Don't use irqdomain to manage ISA IRQs because there may be |
1012 | * multiple IOAPIC pins sharing the same ISA IRQ number and | |
1013 | * irqdomain only supports 1:1 mapping between IOAPIC pin and | |
1014 | * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used | |
1015 | * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
1016 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are | |
1017 | * available, and some BIOSes may use MP Interrupt Source records | |
1018 | * to override IRQ numbers for PIRQs instead of reprogramming | |
1019 | * the interrupt routing logic. Thus there may be multiple pins | |
1020 | * sharing the same legacy IRQ number when ACPI is disabled. | |
6b9fb708 | 1021 | */ |
16ee7b3d JL |
1022 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1023 | irq = mp_irqs[idx].srcbusirq; | |
1024 | if (flags & IOAPIC_MAP_ALLOC) { | |
c4d05a2c | 1025 | if (pinfo->count == 0 && |
16ee7b3d JL |
1026 | mp_irqdomain_map(domain, irq, pin) != 0) |
1027 | irq = -1; | |
1028 | ||
1029 | /* special handling for timer IRQ0 */ | |
1030 | if (irq == 0) | |
c4d05a2c | 1031 | pinfo->count++; |
16ee7b3d JL |
1032 | } |
1033 | } else { | |
1034 | irq = irq_find_mapping(domain, pin); | |
1035 | if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC)) | |
c4d05a2c | 1036 | irq = alloc_irq_from_domain(domain, gsi, pin, info); |
d7f3d478 JL |
1037 | } |
1038 | ||
15a3c7cc | 1039 | if (flags & IOAPIC_MAP_ALLOC) { |
f395dcae | 1040 | /* special handling for legacy IRQs */ |
c4d05a2c | 1041 | if (irq < nr_legacy_irqs() && pinfo->count == 1 && |
f395dcae JL |
1042 | mp_irqdomain_map(domain, irq, pin) != 0) |
1043 | irq = -1; | |
1044 | ||
15a3c7cc | 1045 | if (irq > 0) |
c4d05a2c JL |
1046 | pinfo->count++; |
1047 | else if (pinfo->count == 0) | |
1048 | pinfo->set = 0; | |
15a3c7cc | 1049 | } |
16ee7b3d | 1050 | |
d7f3d478 JL |
1051 | mutex_unlock(&ioapic_mutex); |
1052 | ||
1053 | return irq > 0 ? irq : -1; | |
6b9fb708 JL |
1054 | } |
1055 | ||
d7f3d478 | 1056 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1057 | { |
d7f3d478 | 1058 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1059 | |
1060 | /* | |
1061 | * Debugging check, we are in big trouble if this message pops up! | |
1062 | */ | |
c2c21745 | 1063 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1064 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1065 | |
54168ed7 | 1066 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1067 | /* |
1068 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1069 | */ | |
1070 | if ((pin >= 16) && (pin <= 23)) { | |
1071 | if (pirq_entries[pin-16] != -1) { | |
1072 | if (!pirq_entries[pin-16]) { | |
1073 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1074 | "disabling PIRQ%d\n", pin-16); | |
1075 | } else { | |
d7f3d478 | 1076 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1077 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1078 | "using PIRQ%d -> IRQ %d\n", | |
1079 | pin-16, irq); | |
6b9fb708 | 1080 | return irq; |
1da177e4 LT |
1081 | } |
1082 | } | |
1083 | } | |
54168ed7 IM |
1084 | #endif |
1085 | ||
c4d05a2c | 1086 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
d7f3d478 | 1087 | } |
6b9fb708 | 1088 | |
c4d05a2c JL |
1089 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
1090 | struct irq_alloc_info *info) | |
d7f3d478 JL |
1091 | { |
1092 | int ioapic, pin, idx; | |
1093 | ||
1094 | ioapic = mp_find_ioapic(gsi); | |
1095 | if (ioapic < 0) | |
1096 | return -1; | |
1097 | ||
1098 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1099 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1100 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
1101 | return -1; | |
1102 | ||
c4d05a2c | 1103 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
1da177e4 LT |
1104 | } |
1105 | ||
df334bea JL |
1106 | void mp_unmap_irq(int irq) |
1107 | { | |
1108 | struct irq_data *data = irq_get_irq_data(irq); | |
1109 | struct mp_pin_info *info; | |
1110 | int ioapic, pin; | |
1111 | ||
1112 | if (!data || !data->domain) | |
1113 | return; | |
1114 | ||
1115 | ioapic = (int)(long)data->domain->host_data; | |
1116 | pin = (int)data->hwirq; | |
1117 | info = mp_pin_info(ioapic, pin); | |
1118 | ||
1119 | mutex_lock(&ioapic_mutex); | |
1120 | if (--info->count == 0) { | |
1121 | info->set = 0; | |
1122 | if (irq < nr_legacy_irqs() && | |
1123 | ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY) | |
1124 | mp_irqdomain_unmap(data->domain, irq); | |
1125 | else | |
1126 | irq_dispose_mapping(irq); | |
1127 | } | |
1128 | mutex_unlock(&ioapic_mutex); | |
1129 | } | |
1130 | ||
e20c06fd YL |
1131 | /* |
1132 | * Find a specific PCI IRQ entry. | |
1133 | * Not an __init, possibly needed by modules | |
1134 | */ | |
25d0d35e | 1135 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
e20c06fd | 1136 | { |
d7f3d478 | 1137 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1138 | |
1139 | apic_printk(APIC_DEBUG, | |
1140 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1141 | bus, slot, pin); | |
1142 | if (test_bit(bus, mp_bus_not_pci)) { | |
1143 | apic_printk(APIC_VERBOSE, | |
1144 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1145 | return -1; | |
1146 | } | |
79598505 | 1147 | |
e20c06fd YL |
1148 | for (i = 0; i < mp_irq_entries; i++) { |
1149 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1150 | int ioapic_idx, found = 0; |
1151 | ||
1152 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1153 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1154 | continue; | |
e20c06fd | 1155 | |
f44d1692 | 1156 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1157 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1158 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1159 | found = 1; | |
e20c06fd | 1160 | break; |
e20c06fd | 1161 | } |
79598505 JL |
1162 | if (!found) |
1163 | continue; | |
1164 | ||
1165 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1166 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1167 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1168 | continue; |
1169 | ||
1170 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1171 | best_idx = i; |
1172 | best_ioapic = ioapic_idx; | |
1173 | goto out; | |
79598505 | 1174 | } |
d7f3d478 | 1175 | |
79598505 JL |
1176 | /* |
1177 | * Use the first all-but-pin matching entry as a | |
1178 | * best-guess fuzzy result for broken mptables. | |
1179 | */ | |
d7f3d478 JL |
1180 | if (best_idx < 0) { |
1181 | best_idx = i; | |
1182 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1183 | } |
1184 | } | |
d7f3d478 JL |
1185 | if (best_idx < 0) |
1186 | return -1; | |
1187 | ||
1188 | out: | |
25d0d35e JL |
1189 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
1190 | IOAPIC_MAP_ALLOC); | |
e20c06fd YL |
1191 | } |
1192 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1193 | ||
f5b9ed7a | 1194 | static struct irq_chip ioapic_chip; |
1da177e4 | 1195 | |
047c8fdb | 1196 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1197 | static inline int IO_APIC_irq_trigger(int irq) |
1198 | { | |
d6c88a50 | 1199 | int apic, idx, pin; |
1d025192 | 1200 | |
f44d1692 JL |
1201 | for_each_ioapic_pin(apic, pin) { |
1202 | idx = find_irq_entry(apic, pin, mp_INT); | |
d7f3d478 | 1203 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
f44d1692 | 1204 | return irq_trigger(idx); |
d6c88a50 TG |
1205 | } |
1206 | /* | |
54168ed7 IM |
1207 | * nonexistent IRQs are edge default |
1208 | */ | |
d6c88a50 | 1209 | return 0; |
1d025192 | 1210 | } |
047c8fdb YL |
1211 | #else |
1212 | static inline int IO_APIC_irq_trigger(int irq) | |
1213 | { | |
54168ed7 | 1214 | return 1; |
047c8fdb YL |
1215 | } |
1216 | #endif | |
1d025192 | 1217 | |
1a0e62a4 TG |
1218 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1219 | unsigned long trigger) | |
1da177e4 | 1220 | { |
c60eaf25 TG |
1221 | struct irq_chip *chip = &ioapic_chip; |
1222 | irq_flow_handler_t hdl; | |
1223 | bool fasteoi; | |
199751d7 | 1224 | |
6ebcc00e | 1225 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1226 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1227 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1228 | fasteoi = true; |
1229 | } else { | |
60c69948 | 1230 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1231 | fasteoi = false; |
1232 | } | |
047c8fdb | 1233 | |
2976fd84 | 1234 | if (setup_remapped_irq(irq, cfg, chip)) |
c60eaf25 | 1235 | fasteoi = trigger != 0; |
29b61be6 | 1236 | |
c60eaf25 TG |
1237 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1238 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1239 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1240 | } |
1241 | ||
a6a25dd3 JR |
1242 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1243 | unsigned int destination, int vector, | |
1244 | struct io_apic_irq_attr *attr) | |
c5b4712c | 1245 | { |
c5b4712c YL |
1246 | memset(entry, 0, sizeof(*entry)); |
1247 | ||
1248 | entry->delivery_mode = apic->irq_delivery_mode; | |
1249 | entry->dest_mode = apic->irq_dest_mode; | |
1250 | entry->dest = destination; | |
1251 | entry->vector = vector; | |
1252 | entry->mask = 0; /* enable IRQ */ | |
1253 | entry->trigger = attr->trigger; | |
1254 | entry->polarity = attr->polarity; | |
1255 | ||
1256 | /* | |
1257 | * Mask level triggered irqs. | |
497c9a19 YL |
1258 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1259 | */ | |
c5b4712c | 1260 | if (attr->trigger) |
497c9a19 | 1261 | entry->mask = 1; |
c5b4712c | 1262 | |
497c9a19 YL |
1263 | return 0; |
1264 | } | |
1265 | ||
e4aff811 YL |
1266 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1267 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1268 | { |
1da177e4 | 1269 | struct IO_APIC_route_entry entry; |
22f65d31 | 1270 | unsigned int dest; |
497c9a19 YL |
1271 | |
1272 | if (!IO_APIC_IRQ(irq)) | |
1273 | return; | |
f1c63001 | 1274 | |
fe402e1f | 1275 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1276 | return; |
1277 | ||
ff164324 AG |
1278 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1279 | &dest)) { | |
1280 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1281 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
b794ef26 | 1282 | clear_irq_vector(irq, cfg); |
ff164324 AG |
1283 | |
1284 | return; | |
1285 | } | |
497c9a19 YL |
1286 | |
1287 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1288 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1289 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1290 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1291 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1292 | |
a6a25dd3 JR |
1293 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
1294 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
c5b4712c | 1295 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
b794ef26 | 1296 | clear_irq_vector(irq, cfg); |
c5b4712c | 1297 | |
497c9a19 YL |
1298 | return; |
1299 | } | |
1300 | ||
e4aff811 | 1301 | ioapic_register_intr(irq, cfg, attr->trigger); |
95d76acc | 1302 | if (irq < nr_legacy_irqs()) |
4305df94 | 1303 | legacy_pic->mask(irq); |
497c9a19 | 1304 | |
e4aff811 | 1305 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1306 | } |
1307 | ||
ed972ccf TG |
1308 | static void __init setup_IO_APIC_irqs(void) |
1309 | { | |
16ee7b3d JL |
1310 | unsigned int ioapic, pin; |
1311 | int idx; | |
ed972ccf TG |
1312 | |
1313 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1314 | ||
16ee7b3d JL |
1315 | for_each_ioapic_pin(ioapic, pin) { |
1316 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1317 | if (idx < 0) | |
1318 | apic_printk(APIC_VERBOSE, | |
1319 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1320 | mpc_ioapic_id(ioapic), pin); | |
1321 | else | |
1322 | pin_2_irq(idx, ioapic, pin, | |
1323 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1324 | } | |
ed972ccf TG |
1325 | } |
1326 | ||
1da177e4 | 1327 | /* |
f7633ce5 | 1328 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1329 | */ |
6f50d45f | 1330 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1331 | unsigned int pin, int vector) |
1da177e4 LT |
1332 | { |
1333 | struct IO_APIC_route_entry entry; | |
ff164324 | 1334 | unsigned int dest; |
1da177e4 | 1335 | |
36062448 | 1336 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1337 | |
1338 | /* | |
1339 | * We use logical delivery to get the timer IRQ | |
1340 | * to the first CPU. | |
1341 | */ | |
a5a39156 AG |
1342 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1343 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1344 | dest = BAD_APICID; |
1345 | ||
9b5bc8dc | 1346 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1347 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1348 | entry.dest = dest; |
9b5bc8dc | 1349 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1350 | entry.polarity = 0; |
1351 | entry.trigger = 0; | |
1352 | entry.vector = vector; | |
1353 | ||
1354 | /* | |
1355 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1356 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1357 | */ |
2c778651 TG |
1358 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1359 | "edge"); | |
1da177e4 LT |
1360 | |
1361 | /* | |
1362 | * Add it to the IO-APIC irq-routing table: | |
1363 | */ | |
6f50d45f | 1364 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1365 | } |
1366 | ||
afcc8a40 JR |
1367 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1368 | { | |
1369 | int i; | |
1370 | ||
1371 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); | |
1372 | ||
1373 | for (i = 0; i <= nr_entries; i++) { | |
1374 | struct IO_APIC_route_entry entry; | |
1375 | ||
1376 | entry = ioapic_read_entry(apic, i); | |
1377 | ||
1378 | pr_debug(" %02x %02X ", i, entry.dest); | |
1379 | pr_cont("%1d %1d %1d %1d %1d " | |
1380 | "%1d %1d %02X\n", | |
1381 | entry.mask, | |
1382 | entry.trigger, | |
1383 | entry.irr, | |
1384 | entry.polarity, | |
1385 | entry.delivery_status, | |
1386 | entry.dest_mode, | |
1387 | entry.delivery_mode, | |
1388 | entry.vector); | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | void intel_ir_io_apic_print_entries(unsigned int apic, | |
1393 | unsigned int nr_entries) | |
1da177e4 | 1394 | { |
cda417dd | 1395 | int i; |
afcc8a40 JR |
1396 | |
1397 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); | |
1398 | ||
1399 | for (i = 0; i <= nr_entries; i++) { | |
1400 | struct IR_IO_APIC_route_entry *ir_entry; | |
1401 | struct IO_APIC_route_entry entry; | |
1402 | ||
1403 | entry = ioapic_read_entry(apic, i); | |
1404 | ||
1405 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; | |
1406 | ||
1407 | pr_debug(" %02x %04X ", i, ir_entry->index); | |
1408 | pr_cont("%1d %1d %1d %1d %1d " | |
1409 | "%1d %1d %X %02X\n", | |
1410 | ir_entry->format, | |
1411 | ir_entry->mask, | |
1412 | ir_entry->trigger, | |
1413 | ir_entry->irr, | |
1414 | ir_entry->polarity, | |
1415 | ir_entry->delivery_status, | |
1416 | ir_entry->index2, | |
1417 | ir_entry->zero, | |
1418 | ir_entry->vector); | |
1419 | } | |
1420 | } | |
1421 | ||
17405453 YY |
1422 | void ioapic_zap_locks(void) |
1423 | { | |
1424 | raw_spin_lock_init(&ioapic_lock); | |
1425 | } | |
1426 | ||
74afab7a | 1427 | static void __init print_IO_APIC(int ioapic_idx) |
afcc8a40 | 1428 | { |
1da177e4 LT |
1429 | union IO_APIC_reg_00 reg_00; |
1430 | union IO_APIC_reg_01 reg_01; | |
1431 | union IO_APIC_reg_02 reg_02; | |
1432 | union IO_APIC_reg_03 reg_03; | |
1433 | unsigned long flags; | |
1da177e4 | 1434 | |
dade7716 | 1435 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1436 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1437 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1438 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1439 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1440 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1441 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1442 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1443 | |
6f50d45f | 1444 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1445 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1446 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1447 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1448 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1449 | |
54168ed7 | 1450 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1451 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1452 | reg_01.bits.entries); | |
1da177e4 LT |
1453 | |
1454 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1455 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1456 | reg_01.bits.version); | |
1da177e4 LT |
1457 | |
1458 | /* | |
1459 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1460 | * but the value of reg_02 is read as the previous read register | |
1461 | * value, so ignore it if reg_02 == reg_01. | |
1462 | */ | |
1463 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1464 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1465 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1466 | } |
1467 | ||
1468 | /* | |
1469 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1470 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1471 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1472 | */ | |
1473 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1474 | reg_03.raw != reg_01.raw) { | |
1475 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1476 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1477 | } |
1478 | ||
1479 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1480 | ||
afcc8a40 | 1481 | x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1482 | } |
1483 | ||
74afab7a | 1484 | void __init print_IO_APICs(void) |
cda417dd | 1485 | { |
6f50d45f | 1486 | int ioapic_idx; |
cda417dd YL |
1487 | struct irq_cfg *cfg; |
1488 | unsigned int irq; | |
6fd36ba0 | 1489 | struct irq_chip *chip; |
cda417dd YL |
1490 | |
1491 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1492 | for_each_ioapic(ioapic_idx) |
cda417dd | 1493 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1494 | mpc_ioapic_id(ioapic_idx), |
1495 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1496 | |
1497 | /* | |
1498 | * We are a bit conservative about what we expect. We have to | |
1499 | * know about every hardware change ASAP. | |
1500 | */ | |
1501 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1502 | ||
f44d1692 | 1503 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1504 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1505 | |
1da177e4 | 1506 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1507 | for_each_active_irq(irq) { |
0b8f1efa YL |
1508 | struct irq_pin_list *entry; |
1509 | ||
6fd36ba0 MN |
1510 | chip = irq_get_chip(irq); |
1511 | if (chip != &ioapic_chip) | |
1512 | continue; | |
1513 | ||
32f5ef5d | 1514 | cfg = irq_cfg(irq); |
05e40760 DK |
1515 | if (!cfg) |
1516 | continue; | |
a178b87b | 1517 | if (list_empty(&cfg->irq_2_pin)) |
1da177e4 | 1518 | continue; |
8f09cd20 | 1519 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1520 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1521 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1522 | pr_cont("\n"); | |
1da177e4 LT |
1523 | } |
1524 | ||
1525 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1526 | } |
1527 | ||
efa2559f YL |
1528 | /* Where if anywhere is the i8259 connect in external int mode */ |
1529 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1530 | ||
54168ed7 | 1531 | void __init enable_IO_APIC(void) |
1da177e4 | 1532 | { |
fcfd636a | 1533 | int i8259_apic, i8259_pin; |
f44d1692 | 1534 | int apic, pin; |
bc07844a | 1535 | |
a46f5c89 TG |
1536 | if (skip_ioapic_setup) |
1537 | nr_ioapics = 0; | |
1538 | ||
1539 | if (!nr_legacy_irqs() || !nr_ioapics) | |
bc07844a TG |
1540 | return; |
1541 | ||
f44d1692 | 1542 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1543 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1544 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1545 | |
f44d1692 JL |
1546 | /* If the interrupt line is enabled and in ExtInt mode |
1547 | * I have found the pin where the i8259 is connected. | |
1548 | */ | |
1549 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1550 | ioapic_i8259.apic = apic; | |
1551 | ioapic_i8259.pin = pin; | |
1552 | goto found_i8259; | |
fcfd636a EB |
1553 | } |
1554 | } | |
1555 | found_i8259: | |
1556 | /* Look to see what if the MP table has reported the ExtINT */ | |
1557 | /* If we could not find the appropriate pin by looking at the ioapic | |
1558 | * the i8259 probably is not connected the ioapic but give the | |
1559 | * mptable a chance anyway. | |
1560 | */ | |
1561 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1562 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1563 | /* Trust the MP table if nothing is setup in the hardware */ | |
1564 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1565 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1566 | ioapic_i8259.pin = i8259_pin; | |
1567 | ioapic_i8259.apic = i8259_apic; | |
1568 | } | |
1569 | /* Complain if the MP table and the hardware disagree */ | |
1570 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1571 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1572 | { | |
1573 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1574 | } |
1575 | ||
1576 | /* | |
1577 | * Do not trust the IO-APIC being empty at bootup | |
1578 | */ | |
1579 | clear_IO_APIC(); | |
1580 | } | |
1581 | ||
1c4248ca | 1582 | void native_disable_io_apic(void) |
1da177e4 | 1583 | { |
650927ef | 1584 | /* |
0b968d23 | 1585 | * If the i8259 is routed through an IOAPIC |
650927ef | 1586 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1587 | * so legacy interrupts can be delivered. |
650927ef | 1588 | */ |
1c4248ca | 1589 | if (ioapic_i8259.pin != -1) { |
650927ef | 1590 | struct IO_APIC_route_entry entry; |
650927ef EB |
1591 | |
1592 | memset(&entry, 0, sizeof(entry)); | |
1593 | entry.mask = 0; /* Enabled */ | |
1594 | entry.trigger = 0; /* Edge */ | |
1595 | entry.irr = 0; | |
1596 | entry.polarity = 0; /* High */ | |
1597 | entry.delivery_status = 0; | |
1598 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1599 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1600 | entry.vector = 0; |
54168ed7 | 1601 | entry.dest = read_apic_id(); |
650927ef EB |
1602 | |
1603 | /* | |
1604 | * Add it to the IO-APIC irq-routing table: | |
1605 | */ | |
cf4c6a2f | 1606 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1607 | } |
54168ed7 | 1608 | |
1c4248ca JR |
1609 | if (cpu_has_apic || apic_from_smp_config()) |
1610 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1611 | ||
1612 | } | |
1613 | ||
1614 | /* | |
1615 | * Not an __init, needed by the reboot code | |
1616 | */ | |
1617 | void disable_IO_APIC(void) | |
1618 | { | |
7c6d9f97 | 1619 | /* |
1c4248ca | 1620 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1621 | */ |
1c4248ca JR |
1622 | clear_IO_APIC(); |
1623 | ||
95d76acc | 1624 | if (!nr_legacy_irqs()) |
1c4248ca JR |
1625 | return; |
1626 | ||
1627 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1628 | } |
1629 | ||
54168ed7 | 1630 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1631 | /* |
1632 | * function to set the IO-APIC physical IDs based on the | |
1633 | * values stored in the MPC table. | |
1634 | * | |
1635 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1636 | */ | |
a38c5380 | 1637 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1638 | { |
1639 | union IO_APIC_reg_00 reg_00; | |
1640 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1641 | int ioapic_idx; |
1da177e4 LT |
1642 | int i; |
1643 | unsigned char old_id; | |
1644 | unsigned long flags; | |
1645 | ||
1646 | /* | |
1647 | * This is broken; anything with a real cpu count has to | |
1648 | * circumvent this idiocy regardless. | |
1649 | */ | |
7abc0753 | 1650 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1651 | |
1652 | /* | |
1653 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1654 | */ | |
f44d1692 | 1655 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1656 | /* Read the register 0 value */ |
dade7716 | 1657 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1658 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1659 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1660 | |
6f50d45f | 1661 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1662 | |
6f50d45f | 1663 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1664 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1665 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1666 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1667 | reg_00.bits.ID); | |
6f50d45f | 1668 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1669 | } |
1670 | ||
1da177e4 LT |
1671 | /* |
1672 | * Sanity check, is the ID really free? Every APIC in a | |
1673 | * system must have a unique ID or we get lots of nice | |
1674 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1675 | */ | |
7abc0753 | 1676 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1677 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1678 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1679 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1680 | for (i = 0; i < get_physical_broadcast(); i++) |
1681 | if (!physid_isset(i, phys_id_present_map)) | |
1682 | break; | |
1683 | if (i >= get_physical_broadcast()) | |
1684 | panic("Max APIC ID exceeded!\n"); | |
1685 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1686 | i); | |
1687 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1688 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1689 | } else { |
1690 | physid_mask_t tmp; | |
6f50d45f | 1691 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1692 | &tmp); |
1da177e4 LT |
1693 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1694 | "phys_id_present_map\n", | |
6f50d45f | 1695 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1696 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1697 | } | |
1698 | ||
1da177e4 LT |
1699 | /* |
1700 | * We need to adjust the IRQ routing table | |
1701 | * if the ID changed. | |
1702 | */ | |
6f50d45f | 1703 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 1704 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1705 | if (mp_irqs[i].dstapic == old_id) |
1706 | mp_irqs[i].dstapic | |
6f50d45f | 1707 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
1708 | |
1709 | /* | |
60d79fd9 YL |
1710 | * Update the ID register according to the right value |
1711 | * from the MPC table if they are different. | |
36062448 | 1712 | */ |
6f50d45f | 1713 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
1714 | continue; |
1715 | ||
1da177e4 LT |
1716 | apic_printk(APIC_VERBOSE, KERN_INFO |
1717 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 1718 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 1719 | |
6f50d45f | 1720 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 1721 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1722 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 1723 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1724 | |
1725 | /* | |
1726 | * Sanity check | |
1727 | */ | |
dade7716 | 1728 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1729 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1730 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 1731 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 1732 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
1733 | else |
1734 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1735 | } | |
1736 | } | |
a38c5380 SAS |
1737 | |
1738 | void __init setup_ioapic_ids_from_mpc(void) | |
1739 | { | |
1740 | ||
1741 | if (acpi_ioapic) | |
1742 | return; | |
1743 | /* | |
1744 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1745 | * no meaning without the serial APIC bus. | |
1746 | */ | |
1747 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
1748 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
1749 | return; | |
1750 | setup_ioapic_ids_from_mpc_nocheck(); | |
1751 | } | |
54168ed7 | 1752 | #endif |
1da177e4 | 1753 | |
7ce0bcfd | 1754 | int no_timer_check __initdata; |
8542b200 ZA |
1755 | |
1756 | static int __init notimercheck(char *s) | |
1757 | { | |
1758 | no_timer_check = 1; | |
1759 | return 1; | |
1760 | } | |
1761 | __setup("no_timer_check", notimercheck); | |
1762 | ||
1da177e4 LT |
1763 | /* |
1764 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1765 | * about the timer IRQ. We do the following to work around the situation: | |
1766 | * | |
1767 | * - timer IRQ defaults to IO-APIC IRQ | |
1768 | * - if this function detects that timer IRQs are defunct, then we fall | |
1769 | * back to ISA timer IRQs | |
1770 | */ | |
f0a7a5c9 | 1771 | static int __init timer_irq_works(void) |
1da177e4 LT |
1772 | { |
1773 | unsigned long t1 = jiffies; | |
4aae0702 | 1774 | unsigned long flags; |
1da177e4 | 1775 | |
8542b200 ZA |
1776 | if (no_timer_check) |
1777 | return 1; | |
1778 | ||
4aae0702 | 1779 | local_save_flags(flags); |
1da177e4 LT |
1780 | local_irq_enable(); |
1781 | /* Let ten ticks pass... */ | |
1782 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1783 | local_irq_restore(flags); |
1da177e4 LT |
1784 | |
1785 | /* | |
1786 | * Expect a few ticks at least, to be sure some possible | |
1787 | * glue logic does not lock up after one or two first | |
1788 | * ticks in a non-ExtINT mode. Also the local APIC | |
1789 | * might have cached one ExtINT interrupt. Finally, at | |
1790 | * least one tick may be lost due to delays. | |
1791 | */ | |
54168ed7 IM |
1792 | |
1793 | /* jiffies wrap? */ | |
1d16b53e | 1794 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 1795 | return 1; |
1da177e4 LT |
1796 | return 0; |
1797 | } | |
1798 | ||
1799 | /* | |
1800 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1801 | * number of pending IRQ events unhandled. These cases are very rare, | |
1802 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1803 | * better to do it this way as thus we do not have to be aware of | |
1804 | * 'pending' interrupts in the IRQ path, except at this point. | |
1805 | */ | |
1806 | /* | |
1807 | * Edge triggered needs to resend any interrupt | |
1808 | * that was delayed but this is now handled in the device | |
1809 | * independent code. | |
1810 | */ | |
1811 | ||
1812 | /* | |
1813 | * Starting up a edge-triggered IO-APIC interrupt is | |
1814 | * nasty - we need to make sure that we get the edge. | |
1815 | * If it is already asserted for some reason, we need | |
1816 | * return 1 to indicate that is was pending. | |
1817 | * | |
1818 | * This is not complete - we should be able to fake | |
1819 | * an edge even if it isn't on the 8259A... | |
1820 | */ | |
54168ed7 | 1821 | |
61a38ce3 | 1822 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 1823 | { |
61a38ce3 | 1824 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
1825 | unsigned long flags; |
1826 | ||
dade7716 | 1827 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 1828 | if (irq < nr_legacy_irqs()) { |
4305df94 | 1829 | legacy_pic->mask(irq); |
b81bb373 | 1830 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
1831 | was_pending = 1; |
1832 | } | |
a9786091 | 1833 | __unmask_ioapic(irqd_cfg(data)); |
dade7716 | 1834 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1835 | |
1836 | return was_pending; | |
1837 | } | |
1838 | ||
54168ed7 IM |
1839 | /* |
1840 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1841 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1842 | * handled with the level-triggered descriptor, but that one has slightly | |
1843 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1844 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1845 | * races. | |
1846 | */ | |
497c9a19 | 1847 | |
7eb9ae07 SS |
1848 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
1849 | { | |
1850 | int apic, pin; | |
1851 | struct irq_pin_list *entry; | |
1852 | u8 vector = cfg->vector; | |
1853 | ||
1854 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
1855 | unsigned int reg; | |
1856 | ||
1857 | apic = entry->apic; | |
1858 | pin = entry->pin; | |
9f9d39e4 JR |
1859 | |
1860 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
1861 | reg = io_apic_read(apic, 0x10 + pin*2); |
1862 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
1863 | reg |= vector; | |
1864 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
1865 | } | |
1866 | } | |
1867 | ||
373dd7a2 JR |
1868 | int native_ioapic_set_affinity(struct irq_data *data, |
1869 | const struct cpumask *mask, | |
1870 | bool force) | |
7eb9ae07 SS |
1871 | { |
1872 | unsigned int dest, irq = data->irq; | |
1873 | unsigned long flags; | |
1874 | int ret; | |
1875 | ||
1876 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 1877 | return -EPERM; |
7eb9ae07 SS |
1878 | |
1879 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
cb39288c | 1880 | ret = apic_set_affinity(data, mask, &dest); |
7eb9ae07 SS |
1881 | if (!ret) { |
1882 | /* Only the high 8 bits are valid. */ | |
1883 | dest = SET_APIC_LOGICAL_ID(dest); | |
a9786091 | 1884 | __target_IO_APIC_irq(irq, dest, irqd_cfg(data)); |
7eb9ae07 SS |
1885 | ret = IRQ_SET_MASK_OK_NOCOPY; |
1886 | } | |
1887 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1888 | return ret; | |
1889 | } | |
1890 | ||
3eb2cce8 | 1891 | atomic_t irq_mis_count; |
3eb2cce8 | 1892 | |
047c8fdb | 1893 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
1894 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
1895 | { | |
1896 | struct irq_pin_list *entry; | |
1897 | unsigned long flags; | |
1898 | ||
1899 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
1900 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
1901 | unsigned int reg; | |
1902 | int pin; | |
1903 | ||
1904 | pin = entry->pin; | |
1905 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
1906 | /* Is the remote IRR bit set? */ | |
1907 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
1908 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1909 | return true; | |
1910 | } | |
1911 | } | |
1912 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1913 | ||
1914 | return false; | |
1915 | } | |
1916 | ||
4da7072a AG |
1917 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
1918 | { | |
54168ed7 | 1919 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 1920 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 1921 | mask_ioapic(cfg); |
4da7072a | 1922 | return true; |
54168ed7 | 1923 | } |
4da7072a AG |
1924 | return false; |
1925 | } | |
1926 | ||
1927 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
1928 | struct irq_cfg *cfg, bool masked) | |
1929 | { | |
1930 | if (unlikely(masked)) { | |
1931 | /* Only migrate the irq if the ack has been received. | |
1932 | * | |
1933 | * On rare occasions the broadcast level triggered ack gets | |
1934 | * delayed going to ioapics, and if we reprogram the | |
1935 | * vector while Remote IRR is still set the irq will never | |
1936 | * fire again. | |
1937 | * | |
1938 | * To prevent this scenario we read the Remote IRR bit | |
1939 | * of the ioapic. This has two effects. | |
1940 | * - On any sane system the read of the ioapic will | |
1941 | * flush writes (and acks) going to the ioapic from | |
1942 | * this cpu. | |
1943 | * - We get to see if the ACK has actually been delivered. | |
1944 | * | |
1945 | * Based on failed experiments of reprogramming the | |
1946 | * ioapic entry from outside of irq context starting | |
1947 | * with masking the ioapic entry and then polling until | |
1948 | * Remote IRR was clear before reprogramming the | |
1949 | * ioapic I don't trust the Remote IRR bit to be | |
1950 | * completey accurate. | |
1951 | * | |
1952 | * However there appears to be no other way to plug | |
1953 | * this race, so if the Remote IRR bit is not | |
1954 | * accurate and is causing problems then it is a hardware bug | |
1955 | * and you can go talk to the chipset vendor about it. | |
1956 | */ | |
1957 | if (!io_apic_level_ack_pending(cfg)) | |
1958 | irq_move_masked_irq(data); | |
1959 | unmask_ioapic(cfg); | |
1960 | } | |
1961 | } | |
1962 | #else | |
1963 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
1964 | { | |
1965 | return false; | |
1966 | } | |
1967 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
1968 | struct irq_cfg *cfg, bool masked) | |
1969 | { | |
1970 | } | |
047c8fdb YL |
1971 | #endif |
1972 | ||
cb39288c | 1973 | static void ack_ioapic_level(struct irq_data *data) |
4da7072a | 1974 | { |
a9786091 | 1975 | struct irq_cfg *cfg = irqd_cfg(data); |
4da7072a AG |
1976 | int i, irq = data->irq; |
1977 | unsigned long v; | |
1978 | bool masked; | |
1979 | ||
1980 | irq_complete_move(cfg); | |
1981 | masked = ioapic_irqd_mask(data, cfg); | |
1982 | ||
3eb2cce8 | 1983 | /* |
916a0fe7 JF |
1984 | * It appears there is an erratum which affects at least version 0x11 |
1985 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1986 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1987 | * erroneously delivered as edge-triggered one but the respective IRR | |
1988 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1989 | * message but it will never arrive and further interrupts are blocked | |
1990 | * from the source. The exact reason is so far unknown, but the | |
1991 | * phenomenon was observed when two consecutive interrupt requests | |
1992 | * from a given source get delivered to the same CPU and the source is | |
1993 | * temporarily disabled in between. | |
1994 | * | |
1995 | * A workaround is to simulate an EOI message manually. We achieve it | |
1996 | * by setting the trigger mode to edge and then to level when the edge | |
1997 | * trigger mode gets detected in the TMR of a local APIC for a | |
1998 | * level-triggered interrupt. We mask the source for the time of the | |
1999 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2000 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2001 | * |
2002 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2003 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2004 | * destination that is handling the corresponding interrupt. This | |
2005 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2006 | * level-triggered io-apic interrupt will be seen as an edge | |
2007 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2008 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2009 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2010 | * supporting EOI register, we do an explicit EOI to clear the | |
2011 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2012 | * we use the above logic (mask+edge followed by unmask+level) from | |
2013 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2014 | */ |
3145e941 | 2015 | i = cfg->vector; |
3eb2cce8 | 2016 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2017 | |
54168ed7 IM |
2018 | /* |
2019 | * We must acknowledge the irq before we move it or the acknowledge will | |
2020 | * not propagate properly. | |
2021 | */ | |
2022 | ack_APIC_irq(); | |
2023 | ||
1c83995b SS |
2024 | /* |
2025 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2026 | * message via io-apic EOI register write or simulating it using | |
2027 | * mask+edge followed by unnask+level logic) manually when the | |
2028 | * level triggered interrupt is seen as the edge triggered interrupt | |
2029 | * at the cpu. | |
2030 | */ | |
ca64c47c MR |
2031 | if (!(v & (1 << (i & 0x1f)))) { |
2032 | atomic_inc(&irq_mis_count); | |
2033 | ||
dd5f15e5 | 2034 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2035 | } |
2036 | ||
4da7072a | 2037 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2038 | } |
1d025192 | 2039 | |
f5b9ed7a | 2040 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2041 | .name = "IO-APIC", |
2042 | .irq_startup = startup_ioapic_irq, | |
2043 | .irq_mask = mask_ioapic_irq, | |
2044 | .irq_unmask = unmask_ioapic_irq, | |
cb39288c JL |
2045 | .irq_ack = apic_ack_edge, |
2046 | .irq_eoi = ack_ioapic_level, | |
373dd7a2 | 2047 | .irq_set_affinity = native_ioapic_set_affinity, |
cb39288c | 2048 | .irq_retrigger = apic_retrigger_irq, |
5613570b | 2049 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
2050 | }; |
2051 | ||
1da177e4 LT |
2052 | static inline void init_IO_APIC_traps(void) |
2053 | { | |
da51a821 | 2054 | struct irq_cfg *cfg; |
ad9f4334 | 2055 | unsigned int irq; |
1da177e4 | 2056 | |
ad9f4334 | 2057 | for_each_active_irq(irq) { |
32f5ef5d | 2058 | cfg = irq_cfg(irq); |
0b8f1efa | 2059 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2060 | /* |
2061 | * Hmm.. We don't have an entry for this, | |
2062 | * so default to an old-fashioned 8259 | |
2063 | * interrupt if we can.. | |
2064 | */ | |
95d76acc | 2065 | if (irq < nr_legacy_irqs()) |
b81bb373 | 2066 | legacy_pic->make_irq(irq); |
0b8f1efa | 2067 | else |
1da177e4 | 2068 | /* Strange. Oh, well.. */ |
2c778651 | 2069 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2070 | } |
2071 | } | |
2072 | } | |
2073 | ||
f5b9ed7a IM |
2074 | /* |
2075 | * The local APIC irq-chip implementation: | |
2076 | */ | |
1da177e4 | 2077 | |
90297c5f | 2078 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2079 | { |
2080 | unsigned long v; | |
2081 | ||
2082 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2083 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2084 | } |
2085 | ||
90297c5f | 2086 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2087 | { |
f5b9ed7a | 2088 | unsigned long v; |
1da177e4 | 2089 | |
f5b9ed7a | 2090 | v = apic_read(APIC_LVT0); |
593f4a78 | 2091 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2092 | } |
1da177e4 | 2093 | |
90297c5f | 2094 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2095 | { |
2096 | ack_APIC_irq(); | |
2097 | } | |
2098 | ||
f5b9ed7a | 2099 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2100 | .name = "local-APIC", |
90297c5f TG |
2101 | .irq_mask = mask_lapic_irq, |
2102 | .irq_unmask = unmask_lapic_irq, | |
2103 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2104 | }; |
2105 | ||
60c69948 | 2106 | static void lapic_register_intr(int irq) |
c88ac1df | 2107 | { |
60c69948 | 2108 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2109 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2110 | "edge"); |
c88ac1df MR |
2111 | } |
2112 | ||
1da177e4 LT |
2113 | /* |
2114 | * This looks a bit hackish but it's about the only one way of sending | |
2115 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2116 | * not support the ExtINT mode, unfortunately. We need to send these | |
2117 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2118 | * 8259A interrupt line asserted until INTA. --macro | |
2119 | */ | |
28acf285 | 2120 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2121 | { |
fcfd636a | 2122 | int apic, pin, i; |
1da177e4 LT |
2123 | struct IO_APIC_route_entry entry0, entry1; |
2124 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2125 | |
fcfd636a | 2126 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2127 | if (pin == -1) { |
2128 | WARN_ON_ONCE(1); | |
2129 | return; | |
2130 | } | |
fcfd636a | 2131 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2132 | if (apic == -1) { |
2133 | WARN_ON_ONCE(1); | |
1da177e4 | 2134 | return; |
956fb531 | 2135 | } |
1da177e4 | 2136 | |
cf4c6a2f | 2137 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2138 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2139 | |
2140 | memset(&entry1, 0, sizeof(entry1)); | |
2141 | ||
2142 | entry1.dest_mode = 0; /* physical delivery */ | |
2143 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2144 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2145 | entry1.delivery_mode = dest_ExtINT; |
2146 | entry1.polarity = entry0.polarity; | |
2147 | entry1.trigger = 0; | |
2148 | entry1.vector = 0; | |
2149 | ||
cf4c6a2f | 2150 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2151 | |
2152 | save_control = CMOS_READ(RTC_CONTROL); | |
2153 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2154 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2155 | RTC_FREQ_SELECT); | |
2156 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2157 | ||
2158 | i = 100; | |
2159 | while (i-- > 0) { | |
2160 | mdelay(10); | |
2161 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2162 | i -= 10; | |
2163 | } | |
2164 | ||
2165 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2166 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2167 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2168 | |
cf4c6a2f | 2169 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2170 | } |
2171 | ||
efa2559f | 2172 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2173 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2174 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2175 | { |
2176 | disable_timer_pin_1 = 1; | |
2177 | return 0; | |
2178 | } | |
54168ed7 | 2179 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2180 | |
1da177e4 LT |
2181 | /* |
2182 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2183 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2184 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2185 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2186 | * |
2187 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2188 | */ |
8542b200 | 2189 | static inline void __init check_timer(void) |
1da177e4 | 2190 | { |
32f5ef5d | 2191 | struct irq_cfg *cfg = irq_cfg(0); |
f6e9456c | 2192 | int node = cpu_to_node(0); |
fcfd636a | 2193 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2194 | unsigned long flags; |
047c8fdb | 2195 | int no_pin1 = 0; |
4aae0702 IM |
2196 | |
2197 | local_irq_save(flags); | |
d4d25dec | 2198 | |
1da177e4 LT |
2199 | /* |
2200 | * get/set the timer IRQ vector: | |
2201 | */ | |
4305df94 | 2202 | legacy_pic->mask(0); |
fe402e1f | 2203 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2204 | |
2205 | /* | |
d11d5794 MR |
2206 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2207 | * wire has to be disabled in the local APIC. Also | |
2208 | * timer interrupts need to be acknowledged manually in | |
2209 | * the 8259A for the i82489DX when using the NMI | |
2210 | * watchdog as that APIC treats NMIs as level-triggered. | |
2211 | * The AEOI mode will finish them in the 8259A | |
2212 | * automatically. | |
1da177e4 | 2213 | */ |
593f4a78 | 2214 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2215 | legacy_pic->init(1); |
1da177e4 | 2216 | |
fcfd636a EB |
2217 | pin1 = find_isa_irq_pin(0, mp_INT); |
2218 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2219 | pin2 = ioapic_i8259.pin; | |
2220 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2221 | |
49a66a0b MR |
2222 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2223 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2224 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2225 | |
691874fa MR |
2226 | /* |
2227 | * Some BIOS writers are clueless and report the ExtINTA | |
2228 | * I/O APIC input from the cascaded 8259A as the timer | |
2229 | * interrupt input. So just in case, if only one pin | |
2230 | * was found above, try it both directly and through the | |
2231 | * 8259A. | |
2232 | */ | |
2233 | if (pin1 == -1) { | |
6a9f5de2 | 2234 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2235 | pin1 = pin2; |
2236 | apic1 = apic2; | |
2237 | no_pin1 = 1; | |
2238 | } else if (pin2 == -1) { | |
2239 | pin2 = pin1; | |
2240 | apic2 = apic1; | |
2241 | } | |
2242 | ||
1da177e4 LT |
2243 | if (pin1 != -1) { |
2244 | /* | |
2245 | * Ok, does IRQ0 through the IOAPIC work? | |
2246 | */ | |
691874fa | 2247 | if (no_pin1) { |
85ac16d0 | 2248 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2249 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2250 | } else { |
60c69948 | 2251 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2252 | * leave it unmasked. |
2253 | * so only need to unmask if it is level-trigger | |
2254 | * do we really have level trigger timer? | |
2255 | */ | |
2256 | int idx; | |
2257 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2258 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2259 | unmask_ioapic(cfg); |
691874fa | 2260 | } |
1da177e4 | 2261 | if (timer_irq_works()) { |
66759a01 CE |
2262 | if (disable_timer_pin_1 > 0) |
2263 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2264 | goto out; |
1da177e4 | 2265 | } |
6a9f5de2 | 2266 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2267 | local_irq_disable(); |
fcfd636a | 2268 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2269 | if (!no_pin1) |
49a66a0b MR |
2270 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2271 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2272 | |
49a66a0b MR |
2273 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2274 | "(IRQ0) through the 8259A ...\n"); | |
2275 | apic_printk(APIC_QUIET, KERN_INFO | |
2276 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2277 | /* |
2278 | * legacy devices should be connected to IO APIC #0 | |
2279 | */ | |
85ac16d0 | 2280 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2281 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2282 | legacy_pic->unmask(0); |
1da177e4 | 2283 | if (timer_irq_works()) { |
49a66a0b | 2284 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2285 | goto out; |
1da177e4 LT |
2286 | } |
2287 | /* | |
2288 | * Cleanup, just in case ... | |
2289 | */ | |
f72dccac | 2290 | local_irq_disable(); |
4305df94 | 2291 | legacy_pic->mask(0); |
fcfd636a | 2292 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2293 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2294 | } |
1da177e4 | 2295 | |
49a66a0b MR |
2296 | apic_printk(APIC_QUIET, KERN_INFO |
2297 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2298 | |
60c69948 | 2299 | lapic_register_intr(0); |
497c9a19 | 2300 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2301 | legacy_pic->unmask(0); |
1da177e4 LT |
2302 | |
2303 | if (timer_irq_works()) { | |
49a66a0b | 2304 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2305 | goto out; |
1da177e4 | 2306 | } |
f72dccac | 2307 | local_irq_disable(); |
4305df94 | 2308 | legacy_pic->mask(0); |
497c9a19 | 2309 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2310 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2311 | |
49a66a0b MR |
2312 | apic_printk(APIC_QUIET, KERN_INFO |
2313 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2314 | |
b81bb373 JP |
2315 | legacy_pic->init(0); |
2316 | legacy_pic->make_irq(0); | |
593f4a78 | 2317 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2318 | |
2319 | unlock_ExtINT_logic(); | |
2320 | ||
2321 | if (timer_irq_works()) { | |
49a66a0b | 2322 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2323 | goto out; |
1da177e4 | 2324 | } |
f72dccac | 2325 | local_irq_disable(); |
49a66a0b | 2326 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2ca5b404 | 2327 | if (apic_is_x2apic_enabled()) |
fb209bd8 YL |
2328 | apic_printk(APIC_QUIET, KERN_INFO |
2329 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2330 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2331 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2332 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2333 | out: |
2334 | local_irq_restore(flags); | |
1da177e4 LT |
2335 | } |
2336 | ||
2337 | /* | |
af174783 MR |
2338 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2339 | * to devices. However there may be an I/O APIC pin available for | |
2340 | * this interrupt regardless. The pin may be left unconnected, but | |
2341 | * typically it will be reused as an ExtINT cascade interrupt for | |
2342 | * the master 8259A. In the MPS case such a pin will normally be | |
2343 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2344 | * there is no provision for ExtINT interrupts, and in the absence | |
2345 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2346 | * interrupt, that is edge-triggered and unmasked by default. We | |
2347 | * used to do this, but it caused problems on some systems because | |
2348 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2349 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2350 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2351 | * the I/O APIC in all cases now. No actual device should request | |
2352 | * it anyway. --macro | |
1da177e4 | 2353 | */ |
bc07844a | 2354 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2355 | |
44767bfa JL |
2356 | static int mp_irqdomain_create(int ioapic) |
2357 | { | |
15a3c7cc | 2358 | size_t size; |
44767bfa JL |
2359 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2360 | struct ioapic *ip = &ioapics[ioapic]; | |
2361 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2362 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2363 | ||
15a3c7cc JL |
2364 | size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic); |
2365 | ip->pin_info = kzalloc(size, GFP_KERNEL); | |
2366 | if (!ip->pin_info) | |
2367 | return -ENOMEM; | |
2368 | ||
44767bfa JL |
2369 | if (cfg->type == IOAPIC_DOMAIN_INVALID) |
2370 | return 0; | |
2371 | ||
2372 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, | |
2373 | (void *)(long)ioapic); | |
15a3c7cc JL |
2374 | if(!ip->irqdomain) { |
2375 | kfree(ip->pin_info); | |
2376 | ip->pin_info = NULL; | |
44767bfa | 2377 | return -ENOMEM; |
15a3c7cc | 2378 | } |
44767bfa JL |
2379 | |
2380 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2381 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2382 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2383 | gsi_cfg->gsi_end + 1); | |
2384 | ||
44767bfa JL |
2385 | return 0; |
2386 | } | |
2387 | ||
15516a3b JL |
2388 | static void ioapic_destroy_irqdomain(int idx) |
2389 | { | |
2390 | if (ioapics[idx].irqdomain) { | |
2391 | irq_domain_remove(ioapics[idx].irqdomain); | |
2392 | ioapics[idx].irqdomain = NULL; | |
2393 | } | |
2394 | kfree(ioapics[idx].pin_info); | |
2395 | ioapics[idx].pin_info = NULL; | |
2396 | } | |
2397 | ||
1da177e4 LT |
2398 | void __init setup_IO_APIC(void) |
2399 | { | |
44767bfa | 2400 | int ioapic; |
54168ed7 | 2401 | |
a46f5c89 TG |
2402 | if (skip_ioapic_setup || !nr_ioapics) |
2403 | return; | |
2404 | ||
95d76acc | 2405 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2406 | |
54168ed7 | 2407 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2408 | for_each_ioapic(ioapic) |
2409 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2410 | ||
d6c88a50 | 2411 | /* |
54168ed7 IM |
2412 | * Set up IO-APIC IRQ routing. |
2413 | */ | |
de934103 TG |
2414 | x86_init.mpparse.setup_ioapic_ids(); |
2415 | ||
1da177e4 LT |
2416 | sync_Arb_IDs(); |
2417 | setup_IO_APIC_irqs(); | |
2418 | init_IO_APIC_traps(); | |
95d76acc | 2419 | if (nr_legacy_irqs()) |
bc07844a | 2420 | check_timer(); |
b81975ea JL |
2421 | |
2422 | ioapic_initialized = 1; | |
1da177e4 LT |
2423 | } |
2424 | ||
2425 | /* | |
0d2eb44f | 2426 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2427 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2428 | */ |
36062448 | 2429 | |
1da177e4 LT |
2430 | static int __init io_apic_bug_finalize(void) |
2431 | { | |
d6c88a50 TG |
2432 | if (sis_apic_bug == -1) |
2433 | sis_apic_bug = 0; | |
2434 | return 0; | |
1da177e4 LT |
2435 | } |
2436 | ||
2437 | late_initcall(io_apic_bug_finalize); | |
2438 | ||
6f50d45f | 2439 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2440 | { |
1da177e4 LT |
2441 | unsigned long flags; |
2442 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2443 | |
dade7716 | 2444 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2445 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2446 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2447 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2448 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2449 | } |
dade7716 | 2450 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2451 | } |
1da177e4 | 2452 | |
f3c6ea1b RW |
2453 | static void ioapic_resume(void) |
2454 | { | |
6f50d45f | 2455 | int ioapic_idx; |
f3c6ea1b | 2456 | |
f44d1692 | 2457 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2458 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2459 | |
2460 | restore_ioapic_entries(); | |
1da177e4 LT |
2461 | } |
2462 | ||
f3c6ea1b | 2463 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2464 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2465 | .resume = ioapic_resume, |
2466 | }; | |
2467 | ||
f3c6ea1b | 2468 | static int __init ioapic_init_ops(void) |
1da177e4 | 2469 | { |
f3c6ea1b RW |
2470 | register_syscore_ops(&ioapic_syscore_ops); |
2471 | ||
1da177e4 LT |
2472 | return 0; |
2473 | } | |
2474 | ||
f3c6ea1b | 2475 | device_initcall(ioapic_init_ops); |
1da177e4 | 2476 | |
20443598 | 2477 | static int |
ff973d04 TG |
2478 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
2479 | { | |
2480 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
2481 | int ret; | |
2482 | ||
2483 | if (!cfg) | |
2484 | return -EINVAL; | |
2485 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
2486 | if (!ret) | |
e4aff811 | 2487 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
2488 | return ret; |
2489 | } | |
2490 | ||
67dc5e70 | 2491 | static int io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
2492 | { |
2493 | union IO_APIC_reg_01 reg_01; | |
2494 | unsigned long flags; | |
2495 | ||
dade7716 | 2496 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 2497 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2498 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 2499 | |
4b6b19a1 EB |
2500 | /* The register returns the maximum index redir index |
2501 | * supported, which is one less than the total number of redir | |
2502 | * entries. | |
2503 | */ | |
2504 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
2505 | } |
2506 | ||
62a08ae2 TG |
2507 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
2508 | { | |
b81975ea JL |
2509 | /* |
2510 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
2511 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
2512 | */ | |
2513 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
2514 | } |
2515 | ||
54168ed7 | 2516 | #ifdef CONFIG_X86_32 |
67dc5e70 | 2517 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2518 | { |
2519 | union IO_APIC_reg_00 reg_00; | |
2520 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2521 | physid_mask_t tmp; | |
2522 | unsigned long flags; | |
2523 | int i = 0; | |
2524 | ||
2525 | /* | |
36062448 PC |
2526 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2527 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2528 | * supports up to 16 on one shared APIC bus. |
36062448 | 2529 | * |
1da177e4 LT |
2530 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2531 | * advantage of new APIC bus architecture. | |
2532 | */ | |
2533 | ||
2534 | if (physids_empty(apic_id_map)) | |
7abc0753 | 2535 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 2536 | |
dade7716 | 2537 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2538 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 2539 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2540 | |
2541 | if (apic_id >= get_physical_broadcast()) { | |
2542 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2543 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2544 | apic_id = reg_00.bits.ID; | |
2545 | } | |
2546 | ||
2547 | /* | |
36062448 | 2548 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2549 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2550 | */ | |
7abc0753 | 2551 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
2552 | |
2553 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 2554 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
2555 | break; |
2556 | } | |
2557 | ||
2558 | if (i == get_physical_broadcast()) | |
2559 | panic("Max apic_id exceeded!\n"); | |
2560 | ||
2561 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2562 | "trying %d\n", ioapic, apic_id, i); | |
2563 | ||
2564 | apic_id = i; | |
36062448 | 2565 | } |
1da177e4 | 2566 | |
7abc0753 | 2567 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
2568 | physids_or(apic_id_map, apic_id_map, tmp); |
2569 | ||
2570 | if (reg_00.bits.ID != apic_id) { | |
2571 | reg_00.bits.ID = apic_id; | |
2572 | ||
dade7716 | 2573 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2574 | io_apic_write(ioapic, 0, reg_00.raw); |
2575 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 2576 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2577 | |
2578 | /* Sanity check */ | |
6070f9ec | 2579 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
2580 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
2581 | ioapic); | |
6070f9ec AD |
2582 | return -1; |
2583 | } | |
1da177e4 LT |
2584 | } |
2585 | ||
2586 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2587 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2588 | ||
2589 | return apic_id; | |
2590 | } | |
41098ffe | 2591 | |
67dc5e70 | 2592 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe TG |
2593 | { |
2594 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
2595 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
5411dc4c | 2596 | return io_apic_get_unique_id(idx, id); |
41098ffe TG |
2597 | else |
2598 | return id; | |
2599 | } | |
2600 | #else | |
67dc5e70 | 2601 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe | 2602 | { |
5411dc4c | 2603 | union IO_APIC_reg_00 reg_00; |
41098ffe | 2604 | DECLARE_BITMAP(used, 256); |
5411dc4c YL |
2605 | unsigned long flags; |
2606 | u8 new_id; | |
2607 | int i; | |
41098ffe TG |
2608 | |
2609 | bitmap_zero(used, 256); | |
f44d1692 | 2610 | for_each_ioapic(i) |
d5371430 | 2611 | __set_bit(mpc_ioapic_id(i), used); |
5411dc4c YL |
2612 | |
2613 | /* Hand out the requested id if available */ | |
41098ffe TG |
2614 | if (!test_bit(id, used)) |
2615 | return id; | |
5411dc4c YL |
2616 | |
2617 | /* | |
2618 | * Read the current id from the ioapic and keep it if | |
2619 | * available. | |
2620 | */ | |
2621 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2622 | reg_00.raw = io_apic_read(idx, 0); | |
2623 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2624 | new_id = reg_00.bits.ID; | |
2625 | if (!test_bit(new_id, used)) { | |
2626 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2627 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", | |
2628 | idx, new_id, id); | |
2629 | return new_id; | |
2630 | } | |
2631 | ||
2632 | /* | |
2633 | * Get the next free id and write it to the ioapic. | |
2634 | */ | |
2635 | new_id = find_first_zero_bit(used, 256); | |
2636 | reg_00.bits.ID = new_id; | |
2637 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2638 | io_apic_write(idx, 0, reg_00.raw); | |
2639 | reg_00.raw = io_apic_read(idx, 0); | |
2640 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2641 | /* Sanity check */ | |
2642 | BUG_ON(reg_00.bits.ID != new_id); | |
2643 | ||
2644 | return new_id; | |
41098ffe | 2645 | } |
58f892e0 | 2646 | #endif |
1da177e4 | 2647 | |
67dc5e70 | 2648 | static int io_apic_get_version(int ioapic) |
1da177e4 LT |
2649 | { |
2650 | union IO_APIC_reg_01 reg_01; | |
2651 | unsigned long flags; | |
2652 | ||
dade7716 | 2653 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2654 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2655 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2656 | |
2657 | return reg_01.bits.version; | |
2658 | } | |
2659 | ||
9a0a91bb | 2660 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 2661 | { |
9a0a91bb | 2662 | int ioapic, pin, idx; |
61fd47e0 SL |
2663 | |
2664 | if (skip_ioapic_setup) | |
2665 | return -1; | |
2666 | ||
9a0a91bb EB |
2667 | ioapic = mp_find_ioapic(gsi); |
2668 | if (ioapic < 0) | |
61fd47e0 SL |
2669 | return -1; |
2670 | ||
9a0a91bb EB |
2671 | pin = mp_find_ioapic_pin(ioapic, gsi); |
2672 | if (pin < 0) | |
2673 | return -1; | |
2674 | ||
2675 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
2676 | if (idx < 0) | |
61fd47e0 SL |
2677 | return -1; |
2678 | ||
9a0a91bb EB |
2679 | *trigger = irq_trigger(idx); |
2680 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
2681 | return 0; |
2682 | } | |
2683 | ||
497c9a19 YL |
2684 | /* |
2685 | * This function currently is only a helper for the i386 smp boot process where | |
2686 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 2687 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
2688 | */ |
2689 | #ifdef CONFIG_SMP | |
2690 | void __init setup_ioapic_dest(void) | |
2691 | { | |
fad53995 | 2692 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 2693 | const struct cpumask *mask; |
5451ddc5 | 2694 | struct irq_data *idata; |
497c9a19 YL |
2695 | |
2696 | if (skip_ioapic_setup == 1) | |
2697 | return; | |
2698 | ||
f44d1692 | 2699 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
2700 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
2701 | if (irq_entry == -1) | |
2702 | continue; | |
6c2e9403 | 2703 | |
d7f3d478 JL |
2704 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
2705 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
2706 | continue; |
2707 | ||
5451ddc5 | 2708 | idata = irq_get_irq_data(irq); |
6c2e9403 | 2709 | |
b9c61b70 YL |
2710 | /* |
2711 | * Honour affinities which have been set in early boot | |
2712 | */ | |
5451ddc5 TG |
2713 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
2714 | mask = idata->affinity; | |
b9c61b70 YL |
2715 | else |
2716 | mask = apic->target_cpus(); | |
497c9a19 | 2717 | |
373dd7a2 | 2718 | x86_io_apic_ops.set_affinity(idata, mask, false); |
497c9a19 | 2719 | } |
b9c61b70 | 2720 | |
497c9a19 YL |
2721 | } |
2722 | #endif | |
2723 | ||
54168ed7 IM |
2724 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2725 | ||
2726 | static struct resource *ioapic_resources; | |
2727 | ||
f44d1692 | 2728 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
2729 | { |
2730 | unsigned long n; | |
2731 | struct resource *res; | |
2732 | char *mem; | |
f44d1692 | 2733 | int i, num = 0; |
54168ed7 | 2734 | |
f44d1692 JL |
2735 | for_each_ioapic(i) |
2736 | num++; | |
2737 | if (num == 0) | |
54168ed7 IM |
2738 | return NULL; |
2739 | ||
2740 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 2741 | n *= num; |
54168ed7 IM |
2742 | |
2743 | mem = alloc_bootmem(n); | |
2744 | res = (void *)mem; | |
2745 | ||
f44d1692 | 2746 | mem += sizeof(struct resource) * num; |
54168ed7 | 2747 | |
f44d1692 JL |
2748 | num = 0; |
2749 | for_each_ioapic(i) { | |
2750 | res[num].name = mem; | |
2751 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 2752 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 2753 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 2754 | num++; |
15516a3b | 2755 | ioapics[i].iomem_res = res; |
54168ed7 IM |
2756 | } |
2757 | ||
2758 | ioapic_resources = res; | |
2759 | ||
2760 | return res; | |
2761 | } | |
54168ed7 | 2762 | |
4a8e2a31 | 2763 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
2764 | { |
2765 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 2766 | struct resource *ioapic_res; |
d6c88a50 | 2767 | int i; |
f3294a33 | 2768 | |
f44d1692 JL |
2769 | ioapic_res = ioapic_setup_resources(); |
2770 | for_each_ioapic(i) { | |
f3294a33 | 2771 | if (smp_found_config) { |
d5371430 | 2772 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 2773 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
2774 | if (!ioapic_phys) { |
2775 | printk(KERN_ERR | |
2776 | "WARNING: bogus zero IO-APIC " | |
2777 | "address found in MPTABLE, " | |
2778 | "disabling IO/APIC support!\n"); | |
2779 | smp_found_config = 0; | |
2780 | skip_ioapic_setup = 1; | |
2781 | goto fake_ioapic_page; | |
2782 | } | |
54168ed7 | 2783 | #endif |
f3294a33 | 2784 | } else { |
54168ed7 | 2785 | #ifdef CONFIG_X86_32 |
f3294a33 | 2786 | fake_ioapic_page: |
54168ed7 | 2787 | #endif |
e79c65a9 | 2788 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
2789 | ioapic_phys = __pa(ioapic_phys); |
2790 | } | |
2791 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
2792 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
2793 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
2794 | ioapic_phys); | |
f3294a33 | 2795 | idx++; |
54168ed7 | 2796 | |
ffc43836 | 2797 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 2798 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 2799 | ioapic_res++; |
f3294a33 YL |
2800 | } |
2801 | } | |
2802 | ||
857fdc53 | 2803 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
2804 | { |
2805 | int i; | |
2806 | struct resource *r = ioapic_resources; | |
2807 | ||
2808 | if (!r) { | |
857fdc53 | 2809 | if (nr_ioapics > 0) |
04c93ce4 BZ |
2810 | printk(KERN_ERR |
2811 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 2812 | return; |
54168ed7 IM |
2813 | } |
2814 | ||
f44d1692 | 2815 | for_each_ioapic(i) { |
54168ed7 IM |
2816 | insert_resource(&iomem_resource, r); |
2817 | r++; | |
2818 | } | |
54168ed7 | 2819 | } |
2a4ab640 | 2820 | |
eddb0c55 | 2821 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 2822 | { |
f44d1692 | 2823 | int i; |
2a4ab640 | 2824 | |
678301ec PB |
2825 | if (nr_ioapics == 0) |
2826 | return -1; | |
2827 | ||
2a4ab640 | 2828 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 2829 | for_each_ioapic(i) { |
c040aaeb | 2830 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 2831 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
2832 | return i; |
2833 | } | |
54168ed7 | 2834 | |
2a4ab640 FT |
2835 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
2836 | return -1; | |
2837 | } | |
2838 | ||
eddb0c55 | 2839 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 2840 | { |
c040aaeb SS |
2841 | struct mp_ioapic_gsi *gsi_cfg; |
2842 | ||
f44d1692 | 2843 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 2844 | return -1; |
c040aaeb SS |
2845 | |
2846 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2847 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
2848 | return -1; |
2849 | ||
c040aaeb | 2850 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
2851 | } |
2852 | ||
67dc5e70 | 2853 | static int bad_ioapic_register(int idx) |
73d63d03 SS |
2854 | { |
2855 | union IO_APIC_reg_00 reg_00; | |
2856 | union IO_APIC_reg_01 reg_01; | |
2857 | union IO_APIC_reg_02 reg_02; | |
2858 | ||
2859 | reg_00.raw = io_apic_read(idx, 0); | |
2860 | reg_01.raw = io_apic_read(idx, 1); | |
2861 | reg_02.raw = io_apic_read(idx, 2); | |
2862 | ||
2863 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
2864 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
2865 | mpc_ioapic_addr(idx)); | |
2866 | return 1; | |
2867 | } | |
2868 | ||
2869 | return 0; | |
2870 | } | |
2871 | ||
35ef9c94 JL |
2872 | static int find_free_ioapic_entry(void) |
2873 | { | |
7db298cb JL |
2874 | int idx; |
2875 | ||
2876 | for (idx = 0; idx < MAX_IO_APICS; idx++) | |
2877 | if (ioapics[idx].nr_registers == 0) | |
2878 | return idx; | |
2879 | ||
2880 | return MAX_IO_APICS; | |
35ef9c94 JL |
2881 | } |
2882 | ||
2883 | /** | |
2884 | * mp_register_ioapic - Register an IOAPIC device | |
2885 | * @id: hardware IOAPIC ID | |
2886 | * @address: physical address of IOAPIC register area | |
2887 | * @gsi_base: base of GSI associated with the IOAPIC | |
2888 | * @cfg: configuration information for the IOAPIC | |
2889 | */ | |
2890 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, | |
2891 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 | 2892 | { |
7db298cb | 2893 | bool hotplug = !!ioapic_initialized; |
c040aaeb | 2894 | struct mp_ioapic_gsi *gsi_cfg; |
35ef9c94 JL |
2895 | int idx, ioapic, entries; |
2896 | u32 gsi_end; | |
2a4ab640 | 2897 | |
35ef9c94 JL |
2898 | if (!address) { |
2899 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); | |
2900 | return -EINVAL; | |
2901 | } | |
2902 | for_each_ioapic(ioapic) | |
2903 | if (ioapics[ioapic].mp_config.apicaddr == address) { | |
2904 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", | |
2905 | address, ioapic); | |
2906 | return -EEXIST; | |
2907 | } | |
2a4ab640 | 2908 | |
35ef9c94 JL |
2909 | idx = find_free_ioapic_entry(); |
2910 | if (idx >= MAX_IO_APICS) { | |
2911 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", | |
2912 | MAX_IO_APICS, idx); | |
2913 | return -ENOSPC; | |
2914 | } | |
2a4ab640 | 2915 | |
d5371430 SS |
2916 | ioapics[idx].mp_config.type = MP_IOAPIC; |
2917 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
2918 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
2919 | |
2920 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
2921 | if (bad_ioapic_register(idx)) { |
2922 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
35ef9c94 | 2923 | return -ENODEV; |
73d63d03 SS |
2924 | } |
2925 | ||
5411dc4c | 2926 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
d5371430 | 2927 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
2a4ab640 FT |
2928 | |
2929 | /* | |
2930 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
2931 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
2932 | */ | |
7716a5c4 | 2933 | entries = io_apic_get_redir_entries(idx); |
35ef9c94 JL |
2934 | gsi_end = gsi_base + entries - 1; |
2935 | for_each_ioapic(ioapic) { | |
2936 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2937 | if ((gsi_base >= gsi_cfg->gsi_base && | |
2938 | gsi_base <= gsi_cfg->gsi_end) || | |
2939 | (gsi_end >= gsi_cfg->gsi_base && | |
2940 | gsi_end <= gsi_cfg->gsi_end)) { | |
2941 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", | |
2942 | gsi_base, gsi_end, | |
2943 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2944 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2945 | return -ENOSPC; | |
2946 | } | |
2947 | } | |
c040aaeb SS |
2948 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
2949 | gsi_cfg->gsi_base = gsi_base; | |
35ef9c94 | 2950 | gsi_cfg->gsi_end = gsi_end; |
7716a5c4 | 2951 | |
35ef9c94 JL |
2952 | ioapics[idx].irqdomain = NULL; |
2953 | ioapics[idx].irqdomain_cfg = *cfg; | |
2a4ab640 | 2954 | |
7db298cb JL |
2955 | /* |
2956 | * If mp_register_ioapic() is called during early boot stage when | |
2957 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, | |
2958 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). | |
2959 | */ | |
2960 | if (hotplug) { | |
2961 | if (mp_irqdomain_create(idx)) { | |
2962 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2963 | return -ENOMEM; | |
2964 | } | |
2965 | alloc_ioapic_saved_registers(idx); | |
2966 | } | |
2967 | ||
c040aaeb SS |
2968 | if (gsi_cfg->gsi_end >= gsi_top) |
2969 | gsi_top = gsi_cfg->gsi_end + 1; | |
35ef9c94 JL |
2970 | if (nr_ioapics <= idx) |
2971 | nr_ioapics = idx + 1; | |
2972 | ||
2973 | /* Set nr_registers to mark entry present */ | |
2974 | ioapics[idx].nr_registers = entries; | |
2a4ab640 | 2975 | |
73d63d03 SS |
2976 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
2977 | idx, mpc_ioapic_id(idx), | |
2978 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
2979 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 | 2980 | |
35ef9c94 | 2981 | return 0; |
2a4ab640 | 2982 | } |
05ddafb1 | 2983 | |
15516a3b JL |
2984 | int mp_unregister_ioapic(u32 gsi_base) |
2985 | { | |
2986 | int ioapic, pin; | |
2987 | int found = 0; | |
2988 | struct mp_pin_info *pin_info; | |
2989 | ||
2990 | for_each_ioapic(ioapic) | |
2991 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { | |
2992 | found = 1; | |
2993 | break; | |
2994 | } | |
2995 | if (!found) { | |
2996 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); | |
2997 | return -ENODEV; | |
2998 | } | |
2999 | ||
3000 | for_each_pin(ioapic, pin) { | |
3001 | pin_info = mp_pin_info(ioapic, pin); | |
3002 | if (pin_info->count) { | |
3003 | pr_warn("pin%d on IOAPIC%d is still in use.\n", | |
3004 | pin, ioapic); | |
3005 | return -EBUSY; | |
3006 | } | |
3007 | } | |
3008 | ||
3009 | /* Mark entry not present */ | |
3010 | ioapics[ioapic].nr_registers = 0; | |
3011 | ioapic_destroy_irqdomain(ioapic); | |
3012 | free_ioapic_saved_registers(ioapic); | |
3013 | if (ioapics[ioapic].iomem_res) | |
3014 | release_resource(ioapics[ioapic].iomem_res); | |
3015 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); | |
3016 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); | |
3017 | ||
3018 | return 0; | |
3019 | } | |
3020 | ||
e89900c9 JL |
3021 | int mp_ioapic_registered(u32 gsi_base) |
3022 | { | |
3023 | int ioapic; | |
3024 | ||
3025 | for_each_ioapic(ioapic) | |
3026 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) | |
3027 | return 1; | |
3028 | ||
3029 | return 0; | |
3030 | } | |
3031 | ||
8643e28d JL |
3032 | static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr, |
3033 | int ioapic, int ioapic_pin, | |
3034 | int trigger, int polarity) | |
3035 | { | |
3036 | irq_attr->ioapic = ioapic; | |
3037 | irq_attr->ioapic_pin = ioapic_pin; | |
3038 | irq_attr->trigger = trigger; | |
3039 | irq_attr->polarity = polarity; | |
3040 | } | |
3041 | ||
15a3c7cc JL |
3042 | int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq, |
3043 | irq_hw_number_t hwirq) | |
3044 | { | |
49c7e600 | 3045 | int ioapic = mp_irqdomain_ioapic_idx(domain); |
15a3c7cc JL |
3046 | struct mp_pin_info *info = mp_pin_info(ioapic, hwirq); |
3047 | struct io_apic_irq_attr attr; | |
3048 | ||
15a3c7cc JL |
3049 | /* Get default attribute if not set by caller yet */ |
3050 | if (!info->set) { | |
3051 | u32 gsi = mp_pin_to_gsi(ioapic, hwirq); | |
3052 | ||
3053 | if (acpi_get_override_irq(gsi, &info->trigger, | |
3054 | &info->polarity) < 0) { | |
3055 | /* | |
3056 | * PCI interrupts are always polarity one level | |
3057 | * triggered. | |
3058 | */ | |
3059 | info->trigger = 1; | |
3060 | info->polarity = 1; | |
3061 | } | |
3062 | info->node = NUMA_NO_NODE; | |
f395dcae JL |
3063 | |
3064 | /* | |
3065 | * setup_IO_APIC_irqs() programs all legacy IRQs with default | |
3066 | * trigger and polarity attributes. Don't set the flag for that | |
3067 | * case so the first legacy IRQ user could reprogram the pin | |
3068 | * with real trigger and polarity attributes. | |
3069 | */ | |
3070 | if (virq >= nr_legacy_irqs() || info->count) | |
3071 | info->set = 1; | |
15a3c7cc JL |
3072 | } |
3073 | set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger, | |
3074 | info->polarity); | |
3075 | ||
3076 | return io_apic_setup_irq_pin(virq, info->node, &attr); | |
3077 | } | |
3078 | ||
df334bea JL |
3079 | void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq) |
3080 | { | |
3081 | struct irq_data *data = irq_get_irq_data(virq); | |
3082 | struct irq_cfg *cfg = irq_cfg(virq); | |
49c7e600 | 3083 | int ioapic = mp_irqdomain_ioapic_idx(domain); |
df334bea JL |
3084 | int pin = (int)data->hwirq; |
3085 | ||
df334bea JL |
3086 | ioapic_mask_entry(ioapic, pin); |
3087 | __remove_pin_from_irq(cfg, ioapic, pin); | |
a178b87b | 3088 | WARN_ON(!list_empty(&cfg->irq_2_pin)); |
df334bea JL |
3089 | arch_teardown_hwirq(virq); |
3090 | } | |
3091 | ||
49c7e600 JL |
3092 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
3093 | struct irq_alloc_info *info) | |
3094 | { | |
3095 | if (info && info->ioapic_valid) { | |
3096 | data->trigger = info->ioapic_trigger; | |
3097 | data->polarity = info->ioapic_polarity; | |
3098 | } else if (acpi_get_override_irq(gsi, &data->trigger, | |
3099 | &data->polarity) < 0) { | |
3100 | /* PCI interrupts are always polarity one level triggered. */ | |
3101 | data->trigger = 1; | |
3102 | data->polarity = 1; | |
3103 | } | |
3104 | } | |
3105 | ||
3106 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, | |
3107 | struct IO_APIC_route_entry *entry) | |
3108 | { | |
3109 | memset(entry, 0, sizeof(*entry)); | |
3110 | entry->delivery_mode = apic->irq_delivery_mode; | |
3111 | entry->dest_mode = apic->irq_dest_mode; | |
3112 | entry->dest = cfg->dest_apicid; | |
3113 | entry->vector = cfg->vector; | |
3114 | entry->mask = 0; /* enable IRQ */ | |
3115 | entry->trigger = data->trigger; | |
3116 | entry->polarity = data->polarity; | |
3117 | /* | |
3118 | * Mask level triggered irqs. | |
3119 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
3120 | */ | |
3121 | if (data->trigger) | |
3122 | entry->mask = 1; | |
3123 | } | |
3124 | ||
3125 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, | |
3126 | unsigned int nr_irqs, void *arg) | |
3127 | { | |
3128 | int ret, ioapic, pin; | |
3129 | struct irq_cfg *cfg; | |
3130 | struct irq_data *irq_data; | |
3131 | struct mp_chip_data *data; | |
3132 | struct irq_alloc_info *info = arg; | |
3133 | ||
3134 | if (!info || nr_irqs > 1) | |
3135 | return -EINVAL; | |
3136 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3137 | if (!irq_data) | |
3138 | return -EINVAL; | |
3139 | ||
3140 | ioapic = mp_irqdomain_ioapic_idx(domain); | |
3141 | pin = info->ioapic_pin; | |
3142 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) | |
3143 | return -EEXIST; | |
3144 | ||
3145 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3146 | if (!data) | |
3147 | return -ENOMEM; | |
3148 | ||
3149 | info->ioapic_entry = &data->entry; | |
3150 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); | |
3151 | if (ret < 0) { | |
3152 | kfree(data); | |
3153 | return ret; | |
3154 | } | |
3155 | ||
3156 | irq_data->hwirq = info->ioapic_pin; | |
3157 | irq_data->chip = &ioapic_chip; | |
3158 | irq_data->chip_data = data; | |
3159 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); | |
3160 | ||
3161 | cfg = irqd_cfg(irq_data); | |
3162 | add_pin_to_irq_node(cfg, info->ioapic_node, ioapic, pin); | |
3163 | if (info->ioapic_entry) | |
3164 | mp_setup_entry(cfg, data, info->ioapic_entry); | |
3165 | mp_register_handler(virq, data->trigger); | |
3166 | if (virq < nr_legacy_irqs()) | |
3167 | legacy_pic->mask(virq); | |
3168 | ||
3169 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
3170 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", | |
3171 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, | |
3172 | virq, data->trigger, data->polarity, cfg->dest_apicid); | |
3173 | ||
3174 | return 0; | |
3175 | } | |
3176 | ||
3177 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, | |
3178 | unsigned int nr_irqs) | |
3179 | { | |
3180 | struct irq_cfg *cfg = irq_cfg(virq); | |
3181 | struct irq_data *irq_data; | |
3182 | ||
3183 | BUG_ON(nr_irqs != 1); | |
3184 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3185 | if (irq_data && irq_data->chip_data) { | |
3186 | __remove_pin_from_irq(cfg, mp_irqdomain_ioapic_idx(domain), | |
3187 | (int)irq_data->hwirq); | |
3188 | WARN_ON(!list_empty(&cfg->irq_2_pin)); | |
3189 | kfree(irq_data->chip_data); | |
3190 | } | |
3191 | irq_domain_free_irqs_top(domain, virq, nr_irqs); | |
3192 | } | |
3193 | ||
3194 | void mp_irqdomain_activate(struct irq_domain *domain, | |
3195 | struct irq_data *irq_data) | |
3196 | { | |
3197 | unsigned long flags; | |
3198 | struct irq_pin_list *entry; | |
3199 | struct mp_chip_data *data = irq_data->chip_data; | |
3200 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
3201 | ||
3202 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3203 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
3204 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); | |
3205 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
3206 | } | |
3207 | ||
3208 | void mp_irqdomain_deactivate(struct irq_domain *domain, | |
3209 | struct irq_data *irq_data) | |
3210 | { | |
3211 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ | |
3212 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), | |
3213 | (int)irq_data->hwirq); | |
3214 | } | |
3215 | ||
15a3c7cc JL |
3216 | int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node) |
3217 | { | |
3218 | int ret = 0; | |
3219 | int ioapic, pin; | |
3220 | struct mp_pin_info *info; | |
3221 | ||
3222 | ioapic = mp_find_ioapic(gsi); | |
3223 | if (ioapic < 0) | |
3224 | return -ENODEV; | |
3225 | ||
3226 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
3227 | info = mp_pin_info(ioapic, pin); | |
3228 | trigger = trigger ? 1 : 0; | |
3229 | polarity = polarity ? 1 : 0; | |
3230 | ||
3231 | mutex_lock(&ioapic_mutex); | |
3232 | if (!info->set) { | |
3233 | info->trigger = trigger; | |
3234 | info->polarity = polarity; | |
3235 | info->node = node; | |
3236 | info->set = 1; | |
3237 | } else if (info->trigger != trigger || info->polarity != polarity) { | |
3238 | ret = -EBUSY; | |
3239 | } | |
3240 | mutex_unlock(&ioapic_mutex); | |
3241 | ||
3242 | return ret; | |
3243 | } | |
49c7e600 JL |
3244 | |
3245 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) | |
3246 | { | |
3247 | return (int)(long)domain->host_data; | |
3248 | } |