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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
b5ba7e6d | 85 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
2a4ab640 FT |
88 | /* IO APIC gsi routing info */ |
89 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
90 | ||
584f734d | 91 | /* MP IRQ source entries */ |
c2c21745 | 92 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
93 | |
94 | /* # of MP IRQ source entries */ | |
95 | int mp_irq_entries; | |
96 | ||
bc07844a TG |
97 | /* Number of legacy interrupts */ |
98 | static int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY; | |
99 | /* GSI interrupts */ | |
100 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
101 | ||
8732fc4b AS |
102 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
103 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
104 | #endif | |
105 | ||
106 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
107 | ||
efa2559f YL |
108 | int skip_ioapic_setup; |
109 | ||
65a4e574 IM |
110 | void arch_disable_smp_support(void) |
111 | { | |
112 | #ifdef CONFIG_PCI | |
113 | noioapicquirk = 1; | |
114 | noioapicreroute = -1; | |
115 | #endif | |
116 | skip_ioapic_setup = 1; | |
117 | } | |
118 | ||
54168ed7 | 119 | static int __init parse_noapic(char *str) |
efa2559f YL |
120 | { |
121 | /* disable IO-APIC */ | |
65a4e574 | 122 | arch_disable_smp_support(); |
efa2559f YL |
123 | return 0; |
124 | } | |
125 | early_param("noapic", parse_noapic); | |
66759a01 | 126 | |
0b8f1efa YL |
127 | struct irq_pin_list { |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
85ac16d0 | 132 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
133 | { |
134 | struct irq_pin_list *pin; | |
0b8f1efa YL |
135 | |
136 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
137 | |
138 | return pin; | |
139 | } | |
140 | ||
a1420f39 | 141 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
142 | #ifdef CONFIG_SPARSE_IRQ |
143 | static struct irq_cfg irq_cfgx[] = { | |
144 | #else | |
d6c88a50 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 146 | #endif |
22f65d31 MT |
147 | [0] = { .vector = IRQ0_VECTOR, }, |
148 | [1] = { .vector = IRQ1_VECTOR, }, | |
149 | [2] = { .vector = IRQ2_VECTOR, }, | |
150 | [3] = { .vector = IRQ3_VECTOR, }, | |
151 | [4] = { .vector = IRQ4_VECTOR, }, | |
152 | [5] = { .vector = IRQ5_VECTOR, }, | |
153 | [6] = { .vector = IRQ6_VECTOR, }, | |
154 | [7] = { .vector = IRQ7_VECTOR, }, | |
155 | [8] = { .vector = IRQ8_VECTOR, }, | |
156 | [9] = { .vector = IRQ9_VECTOR, }, | |
157 | [10] = { .vector = IRQ10_VECTOR, }, | |
158 | [11] = { .vector = IRQ11_VECTOR, }, | |
159 | [12] = { .vector = IRQ12_VECTOR, }, | |
160 | [13] = { .vector = IRQ13_VECTOR, }, | |
161 | [14] = { .vector = IRQ14_VECTOR, }, | |
162 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
163 | }; |
164 | ||
bc07844a TG |
165 | void __init io_apic_disable_legacy(void) |
166 | { | |
167 | nr_legacy_irqs = 0; | |
168 | nr_irqs_gsi = 0; | |
169 | } | |
170 | ||
13a0c3c2 | 171 | int __init arch_early_irq_init(void) |
8f09cd20 | 172 | { |
0b8f1efa YL |
173 | struct irq_cfg *cfg; |
174 | struct irq_desc *desc; | |
175 | int count; | |
dad213ae | 176 | int node; |
0b8f1efa | 177 | int i; |
d6c88a50 | 178 | |
0b8f1efa YL |
179 | cfg = irq_cfgx; |
180 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 181 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 182 | |
0b8f1efa YL |
183 | for (i = 0; i < count; i++) { |
184 | desc = irq_to_desc(i); | |
185 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
186 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
187 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
bc07844a | 188 | if (i < nr_legacy_irqs) |
22f65d31 | 189 | cpumask_setall(cfg[i].domain); |
0b8f1efa | 190 | } |
13a0c3c2 YL |
191 | |
192 | return 0; | |
0b8f1efa | 193 | } |
8f09cd20 | 194 | |
0b8f1efa | 195 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 196 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 197 | { |
0b8f1efa YL |
198 | struct irq_cfg *cfg = NULL; |
199 | struct irq_desc *desc; | |
1da177e4 | 200 | |
0b8f1efa YL |
201 | desc = irq_to_desc(irq); |
202 | if (desc) | |
203 | cfg = desc->chip_data; | |
0f978f45 | 204 | |
0b8f1efa | 205 | return cfg; |
8f09cd20 | 206 | } |
d6c88a50 | 207 | |
85ac16d0 | 208 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 209 | { |
0b8f1efa | 210 | struct irq_cfg *cfg; |
0f978f45 | 211 | |
0b8f1efa | 212 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 213 | if (cfg) { |
79f55997 | 214 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
215 | kfree(cfg); |
216 | cfg = NULL; | |
79f55997 | 217 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 218 | GFP_ATOMIC, node)) { |
22f65d31 MT |
219 | free_cpumask_var(cfg->domain); |
220 | kfree(cfg); | |
221 | cfg = NULL; | |
22f65d31 MT |
222 | } |
223 | } | |
0f978f45 | 224 | |
0b8f1efa | 225 | return cfg; |
8f09cd20 YL |
226 | } |
227 | ||
85ac16d0 | 228 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 229 | { |
0b8f1efa | 230 | struct irq_cfg *cfg; |
d6c88a50 | 231 | |
0b8f1efa YL |
232 | cfg = desc->chip_data; |
233 | if (!cfg) { | |
85ac16d0 | 234 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
235 | if (!desc->chip_data) { |
236 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
237 | BUG_ON(1); | |
238 | } | |
239 | } | |
1da177e4 | 240 | |
13a0c3c2 | 241 | return 0; |
0b8f1efa | 242 | } |
0f978f45 | 243 | |
fcef5911 | 244 | /* for move_irq_desc */ |
48a1b10a | 245 | static void |
85ac16d0 | 246 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 247 | { |
48a1b10a YL |
248 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
249 | ||
250 | cfg->irq_2_pin = NULL; | |
251 | old_entry = old_cfg->irq_2_pin; | |
252 | if (!old_entry) | |
253 | return; | |
0f978f45 | 254 | |
85ac16d0 | 255 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
256 | if (!entry) |
257 | return; | |
0f978f45 | 258 | |
48a1b10a YL |
259 | entry->apic = old_entry->apic; |
260 | entry->pin = old_entry->pin; | |
261 | head = entry; | |
262 | tail = entry; | |
263 | old_entry = old_entry->next; | |
264 | while (old_entry) { | |
85ac16d0 | 265 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
266 | if (!entry) { |
267 | entry = head; | |
268 | while (entry) { | |
269 | head = entry->next; | |
270 | kfree(entry); | |
271 | entry = head; | |
272 | } | |
273 | /* still use the old one */ | |
274 | return; | |
275 | } | |
276 | entry->apic = old_entry->apic; | |
277 | entry->pin = old_entry->pin; | |
278 | tail->next = entry; | |
279 | tail = entry; | |
280 | old_entry = old_entry->next; | |
281 | } | |
0f978f45 | 282 | |
48a1b10a YL |
283 | tail->next = NULL; |
284 | cfg->irq_2_pin = head; | |
0f978f45 | 285 | } |
0f978f45 | 286 | |
48a1b10a | 287 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 288 | { |
48a1b10a | 289 | struct irq_pin_list *entry, *next; |
0f978f45 | 290 | |
48a1b10a YL |
291 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
292 | return; | |
301e6190 | 293 | |
48a1b10a | 294 | entry = old_cfg->irq_2_pin; |
0f978f45 | 295 | |
48a1b10a YL |
296 | while (entry) { |
297 | next = entry->next; | |
298 | kfree(entry); | |
299 | entry = next; | |
300 | } | |
301 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 302 | } |
0f978f45 | 303 | |
48a1b10a | 304 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 305 | struct irq_desc *desc, int node) |
0f978f45 | 306 | { |
48a1b10a YL |
307 | struct irq_cfg *cfg; |
308 | struct irq_cfg *old_cfg; | |
0f978f45 | 309 | |
85ac16d0 | 310 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 311 | |
48a1b10a YL |
312 | if (!cfg) |
313 | return; | |
314 | ||
315 | desc->chip_data = cfg; | |
316 | ||
317 | old_cfg = old_desc->chip_data; | |
318 | ||
319 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
320 | ||
85ac16d0 | 321 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 322 | } |
1da177e4 | 323 | |
48a1b10a YL |
324 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
325 | { | |
326 | kfree(old_cfg); | |
327 | } | |
328 | ||
329 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
330 | { | |
331 | struct irq_cfg *old_cfg, *cfg; | |
332 | ||
333 | old_cfg = old_desc->chip_data; | |
334 | cfg = desc->chip_data; | |
335 | ||
336 | if (old_cfg == cfg) | |
337 | return; | |
338 | ||
339 | if (old_cfg) { | |
340 | free_irq_2_pin(old_cfg, cfg); | |
341 | free_irq_cfg(old_cfg); | |
342 | old_desc->chip_data = NULL; | |
343 | } | |
344 | } | |
fcef5911 | 345 | /* end for move_irq_desc */ |
48a1b10a | 346 | |
0b8f1efa | 347 | #else |
9338ad6f | 348 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
349 | { |
350 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 351 | } |
1da177e4 | 352 | |
0b8f1efa YL |
353 | #endif |
354 | ||
130fe05d LT |
355 | struct io_apic { |
356 | unsigned int index; | |
357 | unsigned int unused[3]; | |
358 | unsigned int data; | |
0280f7c4 SS |
359 | unsigned int unused2[11]; |
360 | unsigned int eoi; | |
130fe05d LT |
361 | }; |
362 | ||
363 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
364 | { | |
365 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 366 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
367 | } |
368 | ||
0280f7c4 SS |
369 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
370 | { | |
371 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
372 | writel(vector, &io_apic->eoi); | |
373 | } | |
374 | ||
130fe05d LT |
375 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
376 | { | |
377 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
378 | writel(reg, &io_apic->index); | |
379 | return readl(&io_apic->data); | |
380 | } | |
381 | ||
382 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
383 | { | |
384 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
385 | writel(reg, &io_apic->index); | |
386 | writel(value, &io_apic->data); | |
387 | } | |
388 | ||
389 | /* | |
390 | * Re-write a value: to be used for read-modify-write | |
391 | * cycles where the read already set up the index register. | |
392 | * | |
393 | * Older SiS APIC requires we rewrite the index register | |
394 | */ | |
395 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
396 | { | |
54168ed7 | 397 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
398 | |
399 | if (sis_apic_bug) | |
400 | writel(reg, &io_apic->index); | |
130fe05d LT |
401 | writel(value, &io_apic->data); |
402 | } | |
403 | ||
3145e941 | 404 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
405 | { |
406 | struct irq_pin_list *entry; | |
407 | unsigned long flags; | |
047c8fdb YL |
408 | |
409 | spin_lock_irqsave(&ioapic_lock, flags); | |
2977fb3f | 410 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
411 | unsigned int reg; |
412 | int pin; | |
413 | ||
047c8fdb YL |
414 | pin = entry->pin; |
415 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
416 | /* Is the remote IRR bit set? */ | |
417 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
418 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
419 | return true; | |
420 | } | |
047c8fdb YL |
421 | } |
422 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
423 | ||
424 | return false; | |
425 | } | |
047c8fdb | 426 | |
cf4c6a2f AK |
427 | union entry_union { |
428 | struct { u32 w1, w2; }; | |
429 | struct IO_APIC_route_entry entry; | |
430 | }; | |
431 | ||
432 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
433 | { | |
434 | union entry_union eu; | |
435 | unsigned long flags; | |
436 | spin_lock_irqsave(&ioapic_lock, flags); | |
437 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
438 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
439 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
440 | return eu.entry; | |
441 | } | |
442 | ||
f9dadfa7 LT |
443 | /* |
444 | * When we write a new IO APIC routing entry, we need to write the high | |
445 | * word first! If the mask bit in the low word is clear, we will enable | |
446 | * the interrupt, and we need to make sure the entry is fully populated | |
447 | * before that happens. | |
448 | */ | |
d15512f4 AK |
449 | static void |
450 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 451 | { |
50a8d4d2 F |
452 | union entry_union eu = {{0, 0}}; |
453 | ||
cf4c6a2f | 454 | eu.entry = e; |
f9dadfa7 LT |
455 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
456 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
457 | } |
458 | ||
ca97ab90 | 459 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
460 | { |
461 | unsigned long flags; | |
462 | spin_lock_irqsave(&ioapic_lock, flags); | |
463 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
464 | spin_unlock_irqrestore(&ioapic_lock, flags); |
465 | } | |
466 | ||
467 | /* | |
468 | * When we mask an IO APIC routing entry, we need to write the low | |
469 | * word first, in order to set the mask bit before we change the | |
470 | * high bits! | |
471 | */ | |
472 | static void ioapic_mask_entry(int apic, int pin) | |
473 | { | |
474 | unsigned long flags; | |
475 | union entry_union eu = { .entry.mask = 1 }; | |
476 | ||
cf4c6a2f AK |
477 | spin_lock_irqsave(&ioapic_lock, flags); |
478 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
479 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
480 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
481 | } | |
482 | ||
1da177e4 LT |
483 | /* |
484 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
485 | * shared ISA-space IRQs, so we have to support them. We are super | |
486 | * fast in the common case, and fast for shared ISA-space IRQs. | |
487 | */ | |
f3d1915a CG |
488 | static int |
489 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 490 | { |
2977fb3f | 491 | struct irq_pin_list **last, *entry; |
0f978f45 | 492 | |
2977fb3f CG |
493 | /* don't allow duplicates */ |
494 | last = &cfg->irq_2_pin; | |
495 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 496 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 497 | return 0; |
2977fb3f | 498 | last = &entry->next; |
1da177e4 | 499 | } |
0f978f45 | 500 | |
875e68ec | 501 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 502 | if (!entry) { |
f3d1915a CG |
503 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
504 | node, apic, pin); | |
505 | return -ENOMEM; | |
a7428cd2 | 506 | } |
1da177e4 LT |
507 | entry->apic = apic; |
508 | entry->pin = pin; | |
875e68ec | 509 | |
2977fb3f | 510 | *last = entry; |
f3d1915a CG |
511 | return 0; |
512 | } | |
513 | ||
514 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
515 | { | |
516 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
517 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
518 | } |
519 | ||
520 | /* | |
521 | * Reroute an IRQ to a different pin. | |
522 | */ | |
85ac16d0 | 523 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
524 | int oldapic, int oldpin, |
525 | int newapic, int newpin) | |
1da177e4 | 526 | { |
535b6429 | 527 | struct irq_pin_list *entry; |
1da177e4 | 528 | |
2977fb3f | 529 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
530 | if (entry->apic == oldapic && entry->pin == oldpin) { |
531 | entry->apic = newapic; | |
532 | entry->pin = newpin; | |
0f978f45 | 533 | /* every one is different, right? */ |
4eea6fff | 534 | return; |
0f978f45 | 535 | } |
1da177e4 | 536 | } |
0f978f45 | 537 | |
4eea6fff JF |
538 | /* old apic/pin didn't exist, so just add new ones */ |
539 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
540 | } |
541 | ||
c29d9db3 SS |
542 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
543 | int mask_and, int mask_or, | |
544 | void (*final)(struct irq_pin_list *entry)) | |
545 | { | |
546 | unsigned int reg, pin; | |
547 | ||
548 | pin = entry->pin; | |
549 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
550 | reg &= mask_and; | |
551 | reg |= mask_or; | |
552 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
553 | if (final) | |
554 | final(entry); | |
555 | } | |
556 | ||
2f210deb JF |
557 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
558 | int mask_and, int mask_or, | |
559 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 560 | { |
87783be4 | 561 | struct irq_pin_list *entry; |
047c8fdb | 562 | |
c29d9db3 SS |
563 | for_each_irq_pin(entry, cfg->irq_2_pin) |
564 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
565 | } | |
566 | ||
567 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
568 | { | |
569 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
570 | IO_APIC_REDIR_MASKED, NULL); | |
571 | } | |
572 | ||
573 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
574 | { | |
575 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
576 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 577 | } |
047c8fdb | 578 | |
3145e941 | 579 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 580 | { |
3145e941 | 581 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 582 | } |
047c8fdb | 583 | |
7f3e632f | 584 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 585 | { |
87783be4 CG |
586 | /* |
587 | * Synchronize the IO-APIC and the CPU by doing | |
588 | * a dummy read from the IO-APIC | |
589 | */ | |
590 | struct io_apic __iomem *io_apic; | |
591 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 592 | readl(&io_apic->data); |
1da177e4 LT |
593 | } |
594 | ||
3145e941 | 595 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 596 | { |
3145e941 | 597 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 598 | } |
1da177e4 | 599 | |
3145e941 | 600 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 601 | { |
3145e941 | 602 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
603 | unsigned long flags; |
604 | ||
3145e941 YL |
605 | BUG_ON(!cfg); |
606 | ||
1da177e4 | 607 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 608 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
609 | spin_unlock_irqrestore(&ioapic_lock, flags); |
610 | } | |
611 | ||
3145e941 | 612 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 613 | { |
3145e941 | 614 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
615 | unsigned long flags; |
616 | ||
617 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 618 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
619 | spin_unlock_irqrestore(&ioapic_lock, flags); |
620 | } | |
621 | ||
3145e941 YL |
622 | static void mask_IO_APIC_irq(unsigned int irq) |
623 | { | |
624 | struct irq_desc *desc = irq_to_desc(irq); | |
625 | ||
626 | mask_IO_APIC_irq_desc(desc); | |
627 | } | |
628 | static void unmask_IO_APIC_irq(unsigned int irq) | |
629 | { | |
630 | struct irq_desc *desc = irq_to_desc(irq); | |
631 | ||
632 | unmask_IO_APIC_irq_desc(desc); | |
633 | } | |
634 | ||
1da177e4 LT |
635 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
636 | { | |
637 | struct IO_APIC_route_entry entry; | |
36062448 | 638 | |
1da177e4 | 639 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 640 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
641 | if (entry.delivery_mode == dest_SMI) |
642 | return; | |
1da177e4 LT |
643 | /* |
644 | * Disable it in the IO-APIC irq-routing table: | |
645 | */ | |
f9dadfa7 | 646 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
647 | } |
648 | ||
54168ed7 | 649 | static void clear_IO_APIC (void) |
1da177e4 LT |
650 | { |
651 | int apic, pin; | |
652 | ||
653 | for (apic = 0; apic < nr_ioapics; apic++) | |
654 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
655 | clear_IO_APIC_pin(apic, pin); | |
656 | } | |
657 | ||
54168ed7 | 658 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
659 | /* |
660 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
661 | * specific CPU-side IRQs. | |
662 | */ | |
663 | ||
664 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
665 | static int pirq_entries[MAX_PIRQS] = { |
666 | [0 ... MAX_PIRQS - 1] = -1 | |
667 | }; | |
1da177e4 | 668 | |
1da177e4 LT |
669 | static int __init ioapic_pirq_setup(char *str) |
670 | { | |
671 | int i, max; | |
672 | int ints[MAX_PIRQS+1]; | |
673 | ||
674 | get_options(str, ARRAY_SIZE(ints), ints); | |
675 | ||
1da177e4 LT |
676 | apic_printk(APIC_VERBOSE, KERN_INFO |
677 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
678 | max = MAX_PIRQS; | |
679 | if (ints[0] < MAX_PIRQS) | |
680 | max = ints[0]; | |
681 | ||
682 | for (i = 0; i < max; i++) { | |
683 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
684 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
685 | /* | |
686 | * PIRQs are mapped upside down, usually. | |
687 | */ | |
688 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
689 | } | |
690 | return 1; | |
691 | } | |
692 | ||
693 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
694 | #endif /* CONFIG_X86_32 */ |
695 | ||
b24696bc FY |
696 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
697 | { | |
698 | int apic; | |
699 | struct IO_APIC_route_entry **ioapic_entries; | |
700 | ||
701 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
702 | GFP_ATOMIC); | |
703 | if (!ioapic_entries) | |
704 | return 0; | |
705 | ||
706 | for (apic = 0; apic < nr_ioapics; apic++) { | |
707 | ioapic_entries[apic] = | |
708 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
709 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
710 | if (!ioapic_entries[apic]) | |
711 | goto nomem; | |
712 | } | |
713 | ||
714 | return ioapic_entries; | |
715 | ||
716 | nomem: | |
717 | while (--apic >= 0) | |
718 | kfree(ioapic_entries[apic]); | |
719 | kfree(ioapic_entries); | |
720 | ||
721 | return 0; | |
722 | } | |
54168ed7 IM |
723 | |
724 | /* | |
05c3dc2c | 725 | * Saves all the IO-APIC RTE's |
54168ed7 | 726 | */ |
b24696bc | 727 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 728 | { |
54168ed7 IM |
729 | int apic, pin; |
730 | ||
b24696bc FY |
731 | if (!ioapic_entries) |
732 | return -ENOMEM; | |
54168ed7 IM |
733 | |
734 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
735 | if (!ioapic_entries[apic]) |
736 | return -ENOMEM; | |
54168ed7 | 737 | |
05c3dc2c | 738 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 739 | ioapic_entries[apic][pin] = |
54168ed7 | 740 | ioapic_read_entry(apic, pin); |
b24696bc | 741 | } |
5ffa4eb2 | 742 | |
54168ed7 IM |
743 | return 0; |
744 | } | |
745 | ||
b24696bc FY |
746 | /* |
747 | * Mask all IO APIC entries. | |
748 | */ | |
749 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
750 | { |
751 | int apic, pin; | |
752 | ||
b24696bc FY |
753 | if (!ioapic_entries) |
754 | return; | |
755 | ||
05c3dc2c | 756 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 757 | if (!ioapic_entries[apic]) |
05c3dc2c | 758 | break; |
b24696bc | 759 | |
05c3dc2c SS |
760 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
761 | struct IO_APIC_route_entry entry; | |
762 | ||
b24696bc | 763 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
764 | if (!entry.mask) { |
765 | entry.mask = 1; | |
766 | ioapic_write_entry(apic, pin, entry); | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | ||
b24696bc FY |
772 | /* |
773 | * Restore IO APIC entries which was saved in ioapic_entries. | |
774 | */ | |
775 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
776 | { |
777 | int apic, pin; | |
778 | ||
b24696bc FY |
779 | if (!ioapic_entries) |
780 | return -ENOMEM; | |
781 | ||
5ffa4eb2 | 782 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
783 | if (!ioapic_entries[apic]) |
784 | return -ENOMEM; | |
785 | ||
54168ed7 IM |
786 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
787 | ioapic_write_entry(apic, pin, | |
b24696bc | 788 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 789 | } |
b24696bc | 790 | return 0; |
54168ed7 IM |
791 | } |
792 | ||
b24696bc FY |
793 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
794 | { | |
795 | int apic; | |
796 | ||
797 | for (apic = 0; apic < nr_ioapics; apic++) | |
798 | kfree(ioapic_entries[apic]); | |
799 | ||
800 | kfree(ioapic_entries); | |
54168ed7 | 801 | } |
1da177e4 LT |
802 | |
803 | /* | |
804 | * Find the IRQ entry number of a certain pin. | |
805 | */ | |
806 | static int find_irq_entry(int apic, int pin, int type) | |
807 | { | |
808 | int i; | |
809 | ||
810 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
811 | if (mp_irqs[i].irqtype == type && |
812 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
813 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
814 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
815 | return i; |
816 | ||
817 | return -1; | |
818 | } | |
819 | ||
820 | /* | |
821 | * Find the pin to which IRQ[irq] (ISA) is connected | |
822 | */ | |
fcfd636a | 823 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
824 | { |
825 | int i; | |
826 | ||
827 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 828 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 829 | |
d27e2b8e | 830 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
831 | (mp_irqs[i].irqtype == type) && |
832 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 833 | |
c2c21745 | 834 | return mp_irqs[i].dstirq; |
1da177e4 LT |
835 | } |
836 | return -1; | |
837 | } | |
838 | ||
fcfd636a EB |
839 | static int __init find_isa_irq_apic(int irq, int type) |
840 | { | |
841 | int i; | |
842 | ||
843 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 844 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 845 | |
73b2961b | 846 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
847 | (mp_irqs[i].irqtype == type) && |
848 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
849 | break; |
850 | } | |
851 | if (i < mp_irq_entries) { | |
852 | int apic; | |
54168ed7 | 853 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 854 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
855 | return apic; |
856 | } | |
857 | } | |
858 | ||
859 | return -1; | |
860 | } | |
861 | ||
c0a282c2 | 862 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
863 | /* |
864 | * EISA Edge/Level control register, ELCR | |
865 | */ | |
866 | static int EISA_ELCR(unsigned int irq) | |
867 | { | |
bc07844a | 868 | if (irq < nr_legacy_irqs) { |
1da177e4 LT |
869 | unsigned int port = 0x4d0 + (irq >> 3); |
870 | return (inb(port) >> (irq & 7)) & 1; | |
871 | } | |
872 | apic_printk(APIC_VERBOSE, KERN_INFO | |
873 | "Broken MPtable reports ISA irq %d\n", irq); | |
874 | return 0; | |
875 | } | |
54168ed7 | 876 | |
c0a282c2 | 877 | #endif |
1da177e4 | 878 | |
6728801d AS |
879 | /* ISA interrupts are always polarity zero edge triggered, |
880 | * when listed as conforming in the MP table. */ | |
881 | ||
882 | #define default_ISA_trigger(idx) (0) | |
883 | #define default_ISA_polarity(idx) (0) | |
884 | ||
1da177e4 LT |
885 | /* EISA interrupts are always polarity zero and can be edge or level |
886 | * trigger depending on the ELCR value. If an interrupt is listed as | |
887 | * EISA conforming in the MP table, that means its trigger type must | |
888 | * be read in from the ELCR */ | |
889 | ||
c2c21745 | 890 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 891 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
892 | |
893 | /* PCI interrupts are always polarity one level triggered, | |
894 | * when listed as conforming in the MP table. */ | |
895 | ||
896 | #define default_PCI_trigger(idx) (1) | |
897 | #define default_PCI_polarity(idx) (1) | |
898 | ||
899 | /* MCA interrupts are always polarity zero level triggered, | |
900 | * when listed as conforming in the MP table. */ | |
901 | ||
902 | #define default_MCA_trigger(idx) (1) | |
6728801d | 903 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 904 | |
61fd47e0 | 905 | static int MPBIOS_polarity(int idx) |
1da177e4 | 906 | { |
c2c21745 | 907 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
908 | int polarity; |
909 | ||
910 | /* | |
911 | * Determine IRQ line polarity (high active or low active): | |
912 | */ | |
c2c21745 | 913 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 914 | { |
54168ed7 IM |
915 | case 0: /* conforms, ie. bus-type dependent polarity */ |
916 | if (test_bit(bus, mp_bus_not_pci)) | |
917 | polarity = default_ISA_polarity(idx); | |
918 | else | |
919 | polarity = default_PCI_polarity(idx); | |
920 | break; | |
921 | case 1: /* high active */ | |
922 | { | |
923 | polarity = 0; | |
924 | break; | |
925 | } | |
926 | case 2: /* reserved */ | |
927 | { | |
928 | printk(KERN_WARNING "broken BIOS!!\n"); | |
929 | polarity = 1; | |
930 | break; | |
931 | } | |
932 | case 3: /* low active */ | |
933 | { | |
934 | polarity = 1; | |
935 | break; | |
936 | } | |
937 | default: /* invalid */ | |
938 | { | |
939 | printk(KERN_WARNING "broken BIOS!!\n"); | |
940 | polarity = 1; | |
941 | break; | |
942 | } | |
1da177e4 LT |
943 | } |
944 | return polarity; | |
945 | } | |
946 | ||
947 | static int MPBIOS_trigger(int idx) | |
948 | { | |
c2c21745 | 949 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
950 | int trigger; |
951 | ||
952 | /* | |
953 | * Determine IRQ trigger mode (edge or level sensitive): | |
954 | */ | |
c2c21745 | 955 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 956 | { |
54168ed7 IM |
957 | case 0: /* conforms, ie. bus-type dependent */ |
958 | if (test_bit(bus, mp_bus_not_pci)) | |
959 | trigger = default_ISA_trigger(idx); | |
960 | else | |
961 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 962 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
963 | switch (mp_bus_id_to_type[bus]) { |
964 | case MP_BUS_ISA: /* ISA pin */ | |
965 | { | |
966 | /* set before the switch */ | |
967 | break; | |
968 | } | |
969 | case MP_BUS_EISA: /* EISA pin */ | |
970 | { | |
971 | trigger = default_EISA_trigger(idx); | |
972 | break; | |
973 | } | |
974 | case MP_BUS_PCI: /* PCI pin */ | |
975 | { | |
976 | /* set before the switch */ | |
977 | break; | |
978 | } | |
979 | case MP_BUS_MCA: /* MCA pin */ | |
980 | { | |
981 | trigger = default_MCA_trigger(idx); | |
982 | break; | |
983 | } | |
984 | default: | |
985 | { | |
986 | printk(KERN_WARNING "broken BIOS!!\n"); | |
987 | trigger = 1; | |
988 | break; | |
989 | } | |
990 | } | |
991 | #endif | |
1da177e4 | 992 | break; |
54168ed7 | 993 | case 1: /* edge */ |
1da177e4 | 994 | { |
54168ed7 | 995 | trigger = 0; |
1da177e4 LT |
996 | break; |
997 | } | |
54168ed7 | 998 | case 2: /* reserved */ |
1da177e4 | 999 | { |
54168ed7 IM |
1000 | printk(KERN_WARNING "broken BIOS!!\n"); |
1001 | trigger = 1; | |
1da177e4 LT |
1002 | break; |
1003 | } | |
54168ed7 | 1004 | case 3: /* level */ |
1da177e4 | 1005 | { |
54168ed7 | 1006 | trigger = 1; |
1da177e4 LT |
1007 | break; |
1008 | } | |
54168ed7 | 1009 | default: /* invalid */ |
1da177e4 LT |
1010 | { |
1011 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1012 | trigger = 0; |
1da177e4 LT |
1013 | break; |
1014 | } | |
1015 | } | |
1016 | return trigger; | |
1017 | } | |
1018 | ||
1019 | static inline int irq_polarity(int idx) | |
1020 | { | |
1021 | return MPBIOS_polarity(idx); | |
1022 | } | |
1023 | ||
1024 | static inline int irq_trigger(int idx) | |
1025 | { | |
1026 | return MPBIOS_trigger(idx); | |
1027 | } | |
1028 | ||
efa2559f | 1029 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1030 | static int pin_2_irq(int idx, int apic, int pin) |
1031 | { | |
1032 | int irq, i; | |
c2c21745 | 1033 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1034 | |
1035 | /* | |
1036 | * Debugging check, we are in big trouble if this message pops up! | |
1037 | */ | |
c2c21745 | 1038 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1039 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1040 | ||
54168ed7 | 1041 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1042 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1043 | } else { |
643befed AS |
1044 | /* |
1045 | * PCI IRQs are mapped in order | |
1046 | */ | |
1047 | i = irq = 0; | |
1048 | while (i < apic) | |
1049 | irq += nr_ioapic_registers[i++]; | |
1050 | irq += pin; | |
d6c88a50 | 1051 | /* |
54168ed7 IM |
1052 | * For MPS mode, so far only needed by ES7000 platform |
1053 | */ | |
d6c88a50 TG |
1054 | if (ioapic_renumber_irq) |
1055 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1056 | } |
1057 | ||
54168ed7 | 1058 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1059 | /* |
1060 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1061 | */ | |
1062 | if ((pin >= 16) && (pin <= 23)) { | |
1063 | if (pirq_entries[pin-16] != -1) { | |
1064 | if (!pirq_entries[pin-16]) { | |
1065 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1066 | "disabling PIRQ%d\n", pin-16); | |
1067 | } else { | |
1068 | irq = pirq_entries[pin-16]; | |
1069 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1070 | "using PIRQ%d -> IRQ %d\n", | |
1071 | pin-16, irq); | |
1072 | } | |
1073 | } | |
1074 | } | |
54168ed7 IM |
1075 | #endif |
1076 | ||
1da177e4 LT |
1077 | return irq; |
1078 | } | |
1079 | ||
e20c06fd YL |
1080 | /* |
1081 | * Find a specific PCI IRQ entry. | |
1082 | * Not an __init, possibly needed by modules | |
1083 | */ | |
1084 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1085 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1086 | { |
1087 | int apic, i, best_guess = -1; | |
1088 | ||
1089 | apic_printk(APIC_DEBUG, | |
1090 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1091 | bus, slot, pin); | |
1092 | if (test_bit(bus, mp_bus_not_pci)) { | |
1093 | apic_printk(APIC_VERBOSE, | |
1094 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1095 | return -1; | |
1096 | } | |
1097 | for (i = 0; i < mp_irq_entries; i++) { | |
1098 | int lbus = mp_irqs[i].srcbus; | |
1099 | ||
1100 | for (apic = 0; apic < nr_ioapics; apic++) | |
1101 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1102 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1103 | break; | |
1104 | ||
1105 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1106 | !mp_irqs[i].irqtype && | |
1107 | (bus == lbus) && | |
1108 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1109 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1110 | ||
1111 | if (!(apic || IO_APIC_IRQ(irq))) | |
1112 | continue; | |
1113 | ||
1114 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1115 | set_io_apic_irq_attr(irq_attr, apic, |
1116 | mp_irqs[i].dstirq, | |
1117 | irq_trigger(i), | |
1118 | irq_polarity(i)); | |
e20c06fd YL |
1119 | return irq; |
1120 | } | |
1121 | /* | |
1122 | * Use the first all-but-pin matching entry as a | |
1123 | * best-guess fuzzy result for broken mptables. | |
1124 | */ | |
1125 | if (best_guess < 0) { | |
e5198075 YL |
1126 | set_io_apic_irq_attr(irq_attr, apic, |
1127 | mp_irqs[i].dstirq, | |
1128 | irq_trigger(i), | |
1129 | irq_polarity(i)); | |
e20c06fd YL |
1130 | best_guess = irq; |
1131 | } | |
1132 | } | |
1133 | } | |
1134 | return best_guess; | |
1135 | } | |
1136 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1137 | ||
497c9a19 YL |
1138 | void lock_vector_lock(void) |
1139 | { | |
1140 | /* Used to the online set of cpus does not change | |
1141 | * during assign_irq_vector. | |
1142 | */ | |
1143 | spin_lock(&vector_lock); | |
1144 | } | |
1da177e4 | 1145 | |
497c9a19 | 1146 | void unlock_vector_lock(void) |
1da177e4 | 1147 | { |
497c9a19 YL |
1148 | spin_unlock(&vector_lock); |
1149 | } | |
1da177e4 | 1150 | |
e7986739 MT |
1151 | static int |
1152 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1153 | { |
047c8fdb YL |
1154 | /* |
1155 | * NOTE! The local APIC isn't very good at handling | |
1156 | * multiple interrupts at the same interrupt level. | |
1157 | * As the interrupt level is determined by taking the | |
1158 | * vector number and shifting that right by 4, we | |
1159 | * want to spread these out a bit so that they don't | |
1160 | * all fall in the same interrupt level. | |
1161 | * | |
1162 | * Also, we've got to be careful not to trash gate | |
1163 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1164 | */ | |
54168ed7 IM |
1165 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1166 | unsigned int old_vector; | |
22f65d31 MT |
1167 | int cpu, err; |
1168 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1169 | |
23359a88 | 1170 | if (cfg->move_in_progress) |
54168ed7 | 1171 | return -EBUSY; |
0a1ad60d | 1172 | |
22f65d31 MT |
1173 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1174 | return -ENOMEM; | |
ace80ab7 | 1175 | |
54168ed7 IM |
1176 | old_vector = cfg->vector; |
1177 | if (old_vector) { | |
22f65d31 MT |
1178 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1179 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1180 | if (!cpumask_empty(tmp_mask)) { | |
1181 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1182 | return 0; |
22f65d31 | 1183 | } |
54168ed7 | 1184 | } |
497c9a19 | 1185 | |
e7986739 | 1186 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1187 | err = -ENOSPC; |
1188 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1189 | int new_cpu; |
1190 | int vector, offset; | |
497c9a19 | 1191 | |
e2d40b18 | 1192 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1193 | |
54168ed7 IM |
1194 | vector = current_vector; |
1195 | offset = current_offset; | |
497c9a19 | 1196 | next: |
54168ed7 IM |
1197 | vector += 8; |
1198 | if (vector >= first_system_vector) { | |
e7986739 | 1199 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1200 | offset = (offset + 1) % 8; |
1201 | vector = FIRST_DEVICE_VECTOR + offset; | |
1202 | } | |
1203 | if (unlikely(current_vector == vector)) | |
1204 | continue; | |
b77b881f YL |
1205 | |
1206 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1207 | goto next; |
b77b881f | 1208 | |
22f65d31 | 1209 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1210 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1211 | goto next; | |
1212 | /* Found one! */ | |
1213 | current_vector = vector; | |
1214 | current_offset = offset; | |
1215 | if (old_vector) { | |
1216 | cfg->move_in_progress = 1; | |
22f65d31 | 1217 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1218 | } |
22f65d31 | 1219 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1220 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1221 | cfg->vector = vector; | |
22f65d31 MT |
1222 | cpumask_copy(cfg->domain, tmp_mask); |
1223 | err = 0; | |
1224 | break; | |
54168ed7 | 1225 | } |
22f65d31 MT |
1226 | free_cpumask_var(tmp_mask); |
1227 | return err; | |
497c9a19 YL |
1228 | } |
1229 | ||
9338ad6f | 1230 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1231 | { |
1232 | int err; | |
ace80ab7 | 1233 | unsigned long flags; |
ace80ab7 EB |
1234 | |
1235 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1236 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1237 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1238 | return err; |
1239 | } | |
1240 | ||
3145e941 | 1241 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1242 | { |
497c9a19 YL |
1243 | int cpu, vector; |
1244 | ||
497c9a19 YL |
1245 | BUG_ON(!cfg->vector); |
1246 | ||
1247 | vector = cfg->vector; | |
22f65d31 | 1248 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1249 | per_cpu(vector_irq, cpu)[vector] = -1; |
1250 | ||
1251 | cfg->vector = 0; | |
22f65d31 | 1252 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1253 | |
1254 | if (likely(!cfg->move_in_progress)) | |
1255 | return; | |
22f65d31 | 1256 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1257 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1258 | vector++) { | |
1259 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1260 | continue; | |
1261 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1262 | break; | |
1263 | } | |
1264 | } | |
1265 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1266 | } |
1267 | ||
1268 | void __setup_vector_irq(int cpu) | |
1269 | { | |
1270 | /* Initialize vector_irq on a new cpu */ | |
1271 | /* This function must be called with vector_lock held */ | |
1272 | int irq, vector; | |
1273 | struct irq_cfg *cfg; | |
0b8f1efa | 1274 | struct irq_desc *desc; |
497c9a19 YL |
1275 | |
1276 | /* Mark the inuse vectors */ | |
0b8f1efa | 1277 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1278 | cfg = desc->chip_data; |
22f65d31 | 1279 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1280 | continue; |
1281 | vector = cfg->vector; | |
497c9a19 YL |
1282 | per_cpu(vector_irq, cpu)[vector] = irq; |
1283 | } | |
1284 | /* Mark the free vectors */ | |
1285 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1286 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1287 | if (irq < 0) | |
1288 | continue; | |
1289 | ||
1290 | cfg = irq_cfg(irq); | |
22f65d31 | 1291 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1292 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1293 | } |
1da177e4 | 1294 | } |
3fde6900 | 1295 | |
f5b9ed7a | 1296 | static struct irq_chip ioapic_chip; |
54168ed7 | 1297 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1298 | |
54168ed7 IM |
1299 | #define IOAPIC_AUTO -1 |
1300 | #define IOAPIC_EDGE 0 | |
1301 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1302 | |
047c8fdb | 1303 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1304 | static inline int IO_APIC_irq_trigger(int irq) |
1305 | { | |
d6c88a50 | 1306 | int apic, idx, pin; |
1d025192 | 1307 | |
d6c88a50 TG |
1308 | for (apic = 0; apic < nr_ioapics; apic++) { |
1309 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1310 | idx = find_irq_entry(apic, pin, mp_INT); | |
1311 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1312 | return irq_trigger(idx); | |
1313 | } | |
1314 | } | |
1315 | /* | |
54168ed7 IM |
1316 | * nonexistent IRQs are edge default |
1317 | */ | |
d6c88a50 | 1318 | return 0; |
1d025192 | 1319 | } |
047c8fdb YL |
1320 | #else |
1321 | static inline int IO_APIC_irq_trigger(int irq) | |
1322 | { | |
54168ed7 | 1323 | return 1; |
047c8fdb YL |
1324 | } |
1325 | #endif | |
1d025192 | 1326 | |
3145e941 | 1327 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1328 | { |
199751d7 | 1329 | |
6ebcc00e | 1330 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1331 | trigger == IOAPIC_LEVEL) |
08678b08 | 1332 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1333 | else |
1334 | desc->status &= ~IRQ_LEVEL; | |
1335 | ||
54168ed7 IM |
1336 | if (irq_remapped(irq)) { |
1337 | desc->status |= IRQ_MOVE_PCNTXT; | |
1338 | if (trigger) | |
1339 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1340 | handle_fasteoi_irq, | |
1341 | "fasteoi"); | |
1342 | else | |
1343 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1344 | handle_edge_irq, "edge"); | |
1345 | return; | |
1346 | } | |
29b61be6 | 1347 | |
047c8fdb YL |
1348 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1349 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1350 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1351 | handle_fasteoi_irq, |
1352 | "fasteoi"); | |
047c8fdb | 1353 | else |
a460e745 | 1354 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1355 | handle_edge_irq, "edge"); |
1da177e4 LT |
1356 | } |
1357 | ||
ca97ab90 JF |
1358 | int setup_ioapic_entry(int apic_id, int irq, |
1359 | struct IO_APIC_route_entry *entry, | |
1360 | unsigned int destination, int trigger, | |
0280f7c4 | 1361 | int polarity, int vector, int pin) |
1da177e4 | 1362 | { |
497c9a19 YL |
1363 | /* |
1364 | * add it to the IO-APIC irq-routing table: | |
1365 | */ | |
1366 | memset(entry,0,sizeof(*entry)); | |
1367 | ||
54168ed7 | 1368 | if (intr_remapping_enabled) { |
c8d46cf0 | 1369 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1370 | struct irte irte; |
1371 | struct IR_IO_APIC_route_entry *ir_entry = | |
1372 | (struct IR_IO_APIC_route_entry *) entry; | |
1373 | int index; | |
1374 | ||
1375 | if (!iommu) | |
c8d46cf0 | 1376 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1377 | |
1378 | index = alloc_irte(iommu, irq, 1); | |
1379 | if (index < 0) | |
c8d46cf0 | 1380 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1381 | |
1382 | memset(&irte, 0, sizeof(irte)); | |
1383 | ||
1384 | irte.present = 1; | |
9b5bc8dc | 1385 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1386 | /* |
1387 | * Trigger mode in the IRTE will always be edge, and the | |
1388 | * actual level or edge trigger will be setup in the IO-APIC | |
1389 | * RTE. This will help simplify level triggered irq migration. | |
1390 | * For more details, see the comments above explainig IO-APIC | |
1391 | * irq migration in the presence of interrupt-remapping. | |
1392 | */ | |
1393 | irte.trigger_mode = 0; | |
9b5bc8dc | 1394 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1395 | irte.vector = vector; |
1396 | irte.dest_id = IRTE_DEST(destination); | |
1397 | ||
f007e99c WH |
1398 | /* Set source-id of interrupt request */ |
1399 | set_ioapic_sid(&irte, apic_id); | |
1400 | ||
54168ed7 IM |
1401 | modify_irte(irq, &irte); |
1402 | ||
1403 | ir_entry->index2 = (index >> 15) & 0x1; | |
1404 | ir_entry->zero = 0; | |
1405 | ir_entry->format = 1; | |
1406 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1407 | /* |
1408 | * IO-APIC RTE will be configured with virtual vector. | |
1409 | * irq handler will do the explicit EOI to the io-apic. | |
1410 | */ | |
1411 | ir_entry->vector = pin; | |
29b61be6 | 1412 | } else { |
9b5bc8dc IM |
1413 | entry->delivery_mode = apic->irq_delivery_mode; |
1414 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1415 | entry->dest = destination; |
0280f7c4 | 1416 | entry->vector = vector; |
54168ed7 | 1417 | } |
497c9a19 | 1418 | |
54168ed7 | 1419 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1420 | entry->trigger = trigger; |
1421 | entry->polarity = polarity; | |
497c9a19 YL |
1422 | |
1423 | /* Mask level triggered irqs. | |
1424 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1425 | */ | |
1426 | if (trigger) | |
1427 | entry->mask = 1; | |
497c9a19 YL |
1428 | return 0; |
1429 | } | |
1430 | ||
c8d46cf0 | 1431 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1432 | int trigger, int polarity) |
497c9a19 YL |
1433 | { |
1434 | struct irq_cfg *cfg; | |
1da177e4 | 1435 | struct IO_APIC_route_entry entry; |
22f65d31 | 1436 | unsigned int dest; |
497c9a19 YL |
1437 | |
1438 | if (!IO_APIC_IRQ(irq)) | |
1439 | return; | |
1440 | ||
3145e941 | 1441 | cfg = desc->chip_data; |
497c9a19 | 1442 | |
fe402e1f | 1443 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1444 | return; |
1445 | ||
debccb3e | 1446 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1447 | |
1448 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1449 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1450 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1451 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1452 | irq, trigger, polarity); |
1453 | ||
1454 | ||
c8d46cf0 | 1455 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1456 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1457 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1458 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1459 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1460 | return; |
1461 | } | |
1462 | ||
3145e941 | 1463 | ioapic_register_intr(irq, desc, trigger); |
bc07844a | 1464 | if (irq < nr_legacy_irqs) |
497c9a19 YL |
1465 | disable_8259A_irq(irq); |
1466 | ||
c8d46cf0 | 1467 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1468 | } |
1469 | ||
b9c61b70 YL |
1470 | static struct { |
1471 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1472 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1473 | ||
497c9a19 YL |
1474 | static void __init setup_IO_APIC_irqs(void) |
1475 | { | |
b9c61b70 | 1476 | int apic_id = 0, pin, idx, irq; |
3c2cbd24 | 1477 | int notcon = 0; |
0b8f1efa | 1478 | struct irq_desc *desc; |
3145e941 | 1479 | struct irq_cfg *cfg; |
85ac16d0 | 1480 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1481 | |
1482 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1483 | ||
b9c61b70 YL |
1484 | #ifdef CONFIG_ACPI |
1485 | if (!acpi_disabled && acpi_ioapic) { | |
1486 | apic_id = mp_find_ioapic(0); | |
1487 | if (apic_id < 0) | |
1488 | apic_id = 0; | |
1489 | } | |
1490 | #endif | |
3c2cbd24 | 1491 | |
b9c61b70 YL |
1492 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1493 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1494 | if (idx == -1) { | |
1495 | if (!notcon) { | |
1496 | notcon = 1; | |
1497 | apic_printk(APIC_VERBOSE, | |
1498 | KERN_DEBUG " %d-%d", | |
1499 | mp_ioapics[apic_id].apicid, pin); | |
1500 | } else | |
1501 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1502 | mp_ioapics[apic_id].apicid, pin); | |
1503 | continue; | |
1504 | } | |
1505 | if (notcon) { | |
1506 | apic_printk(APIC_VERBOSE, | |
1507 | " (apicid-pin) not connected\n"); | |
1508 | notcon = 0; | |
1509 | } | |
33a201fa | 1510 | |
b9c61b70 | 1511 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1512 | |
b9c61b70 YL |
1513 | /* |
1514 | * Skip the timer IRQ if there's a quirk handler | |
1515 | * installed and if it returns 1: | |
1516 | */ | |
1517 | if (apic->multi_timer_check && | |
1518 | apic->multi_timer_check(apic_id, irq)) | |
1519 | continue; | |
36062448 | 1520 | |
b9c61b70 YL |
1521 | desc = irq_to_desc_alloc_node(irq, node); |
1522 | if (!desc) { | |
1523 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1524 | continue; | |
3c2cbd24 | 1525 | } |
b9c61b70 YL |
1526 | cfg = desc->chip_data; |
1527 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1528 | /* |
1529 | * don't mark it in pin_programmed, so later acpi could | |
1530 | * set it correctly when irq < 16 | |
1531 | */ | |
b9c61b70 YL |
1532 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1533 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1534 | } |
1535 | ||
3c2cbd24 CG |
1536 | if (notcon) |
1537 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1538 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1539 | } |
1540 | ||
1541 | /* | |
f7633ce5 | 1542 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1543 | */ |
c8d46cf0 | 1544 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1545 | int vector) |
1da177e4 LT |
1546 | { |
1547 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1548 | |
54168ed7 IM |
1549 | if (intr_remapping_enabled) |
1550 | return; | |
54168ed7 | 1551 | |
36062448 | 1552 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1553 | |
1554 | /* | |
1555 | * We use logical delivery to get the timer IRQ | |
1556 | * to the first CPU. | |
1557 | */ | |
9b5bc8dc | 1558 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1559 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1560 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1561 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1562 | entry.polarity = 0; |
1563 | entry.trigger = 0; | |
1564 | entry.vector = vector; | |
1565 | ||
1566 | /* | |
1567 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1568 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1569 | */ |
54168ed7 | 1570 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1571 | |
1572 | /* | |
1573 | * Add it to the IO-APIC irq-routing table: | |
1574 | */ | |
c8d46cf0 | 1575 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1576 | } |
1577 | ||
32f71aff MR |
1578 | |
1579 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1580 | { |
1581 | int apic, i; | |
1582 | union IO_APIC_reg_00 reg_00; | |
1583 | union IO_APIC_reg_01 reg_01; | |
1584 | union IO_APIC_reg_02 reg_02; | |
1585 | union IO_APIC_reg_03 reg_03; | |
1586 | unsigned long flags; | |
0f978f45 | 1587 | struct irq_cfg *cfg; |
0b8f1efa | 1588 | struct irq_desc *desc; |
8f09cd20 | 1589 | unsigned int irq; |
1da177e4 | 1590 | |
36062448 | 1591 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1592 | for (i = 0; i < nr_ioapics; i++) |
1593 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1594 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1595 | |
1596 | /* | |
1597 | * We are a bit conservative about what we expect. We have to | |
1598 | * know about every hardware change ASAP. | |
1599 | */ | |
1600 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1601 | ||
1602 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1603 | ||
1604 | spin_lock_irqsave(&ioapic_lock, flags); | |
1605 | reg_00.raw = io_apic_read(apic, 0); | |
1606 | reg_01.raw = io_apic_read(apic, 1); | |
1607 | if (reg_01.bits.version >= 0x10) | |
1608 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1609 | if (reg_01.bits.version >= 0x20) |
1610 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1611 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1612 | ||
54168ed7 | 1613 | printk("\n"); |
b5ba7e6d | 1614 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1615 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1616 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1617 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1618 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1619 | |
54168ed7 | 1620 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1621 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1622 | |
1623 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1624 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1625 | |
1626 | /* | |
1627 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1628 | * but the value of reg_02 is read as the previous read register | |
1629 | * value, so ignore it if reg_02 == reg_01. | |
1630 | */ | |
1631 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1632 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1633 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1634 | } |
1635 | ||
1636 | /* | |
1637 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1638 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1639 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1640 | */ | |
1641 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1642 | reg_03.raw != reg_01.raw) { | |
1643 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1644 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1648 | ||
d83e94ac YL |
1649 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1650 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1651 | |
1652 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1653 | struct IO_APIC_route_entry entry; | |
1654 | ||
cf4c6a2f | 1655 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1656 | |
54168ed7 IM |
1657 | printk(KERN_DEBUG " %02x %03X ", |
1658 | i, | |
1659 | entry.dest | |
1660 | ); | |
1da177e4 LT |
1661 | |
1662 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1663 | entry.mask, | |
1664 | entry.trigger, | |
1665 | entry.irr, | |
1666 | entry.polarity, | |
1667 | entry.delivery_status, | |
1668 | entry.dest_mode, | |
1669 | entry.delivery_mode, | |
1670 | entry.vector | |
1671 | ); | |
1672 | } | |
1673 | } | |
1da177e4 | 1674 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1675 | for_each_irq_desc(irq, desc) { |
1676 | struct irq_pin_list *entry; | |
1677 | ||
0b8f1efa YL |
1678 | cfg = desc->chip_data; |
1679 | entry = cfg->irq_2_pin; | |
0f978f45 | 1680 | if (!entry) |
1da177e4 | 1681 | continue; |
8f09cd20 | 1682 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1683 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1684 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1685 | printk("\n"); |
1686 | } | |
1687 | ||
1688 | printk(KERN_INFO ".................................... done.\n"); | |
1689 | ||
1690 | return; | |
1691 | } | |
1692 | ||
251e1e44 | 1693 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1694 | { |
251e1e44 | 1695 | int i; |
1da177e4 | 1696 | |
251e1e44 IM |
1697 | printk(KERN_DEBUG); |
1698 | ||
1699 | for (i = 0; i < 8; i++) | |
1700 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1701 | ||
1702 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1703 | } |
1704 | ||
32f71aff | 1705 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1706 | { |
97a52714 | 1707 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1708 | u64 icr; |
1da177e4 | 1709 | |
251e1e44 | 1710 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1711 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1712 | v = apic_read(APIC_ID); |
54168ed7 | 1713 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1714 | v = apic_read(APIC_LVR); |
1715 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1716 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1717 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1718 | |
1719 | v = apic_read(APIC_TASKPRI); | |
1720 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1721 | ||
54168ed7 | 1722 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1723 | if (!APIC_XAPIC(ver)) { |
1724 | v = apic_read(APIC_ARBPRI); | |
1725 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1726 | v & APIC_ARBPRI_MASK); | |
1727 | } | |
1da177e4 LT |
1728 | v = apic_read(APIC_PROCPRI); |
1729 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1730 | } | |
1731 | ||
a11b5abe YL |
1732 | /* |
1733 | * Remote read supported only in the 82489DX and local APIC for | |
1734 | * Pentium processors. | |
1735 | */ | |
1736 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1737 | v = apic_read(APIC_RRR); | |
1738 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1739 | } | |
1740 | ||
1da177e4 LT |
1741 | v = apic_read(APIC_LDR); |
1742 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1743 | if (!x2apic_enabled()) { |
1744 | v = apic_read(APIC_DFR); | |
1745 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1746 | } | |
1da177e4 LT |
1747 | v = apic_read(APIC_SPIV); |
1748 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1749 | ||
1750 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1751 | print_APIC_field(APIC_ISR); |
1da177e4 | 1752 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1753 | print_APIC_field(APIC_TMR); |
1da177e4 | 1754 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1755 | print_APIC_field(APIC_IRR); |
1da177e4 | 1756 | |
54168ed7 IM |
1757 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1758 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1759 | apic_write(APIC_ESR, 0); |
54168ed7 | 1760 | |
1da177e4 LT |
1761 | v = apic_read(APIC_ESR); |
1762 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1763 | } | |
1764 | ||
7ab6af7a | 1765 | icr = apic_icr_read(); |
0c425cec IM |
1766 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1767 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1768 | |
1769 | v = apic_read(APIC_LVTT); | |
1770 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1771 | ||
1772 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1773 | v = apic_read(APIC_LVTPC); | |
1774 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1775 | } | |
1776 | v = apic_read(APIC_LVT0); | |
1777 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1778 | v = apic_read(APIC_LVT1); | |
1779 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1780 | ||
1781 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1782 | v = apic_read(APIC_LVTERR); | |
1783 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1784 | } | |
1785 | ||
1786 | v = apic_read(APIC_TMICT); | |
1787 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1788 | v = apic_read(APIC_TMCCT); | |
1789 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1790 | v = apic_read(APIC_TDCR); | |
1791 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1792 | |
1793 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1794 | v = apic_read(APIC_EFEAT); | |
1795 | maxlvt = (v >> 16) & 0xff; | |
1796 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1797 | v = apic_read(APIC_ECTRL); | |
1798 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1799 | for (i = 0; i < maxlvt; i++) { | |
1800 | v = apic_read(APIC_EILVTn(i)); | |
1801 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1802 | } | |
1803 | } | |
1da177e4 LT |
1804 | printk("\n"); |
1805 | } | |
1806 | ||
2626eb2b | 1807 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1808 | { |
ffd5aae7 YL |
1809 | int cpu; |
1810 | ||
2626eb2b CG |
1811 | if (!maxcpu) |
1812 | return; | |
1813 | ||
ffd5aae7 | 1814 | preempt_disable(); |
2626eb2b CG |
1815 | for_each_online_cpu(cpu) { |
1816 | if (cpu >= maxcpu) | |
1817 | break; | |
ffd5aae7 | 1818 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1819 | } |
ffd5aae7 | 1820 | preempt_enable(); |
1da177e4 LT |
1821 | } |
1822 | ||
32f71aff | 1823 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1824 | { |
1da177e4 LT |
1825 | unsigned int v; |
1826 | unsigned long flags; | |
1827 | ||
2626eb2b | 1828 | if (!nr_legacy_irqs) |
1da177e4 LT |
1829 | return; |
1830 | ||
1831 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1832 | ||
1833 | spin_lock_irqsave(&i8259A_lock, flags); | |
1834 | ||
1835 | v = inb(0xa1) << 8 | inb(0x21); | |
1836 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1837 | ||
1838 | v = inb(0xa0) << 8 | inb(0x20); | |
1839 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1840 | ||
54168ed7 IM |
1841 | outb(0x0b,0xa0); |
1842 | outb(0x0b,0x20); | |
1da177e4 | 1843 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1844 | outb(0x0a,0xa0); |
1845 | outb(0x0a,0x20); | |
1da177e4 LT |
1846 | |
1847 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1848 | ||
1849 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1850 | ||
1851 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1852 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1853 | } | |
1854 | ||
2626eb2b CG |
1855 | static int __initdata show_lapic = 1; |
1856 | static __init int setup_show_lapic(char *arg) | |
1857 | { | |
1858 | int num = -1; | |
1859 | ||
1860 | if (strcmp(arg, "all") == 0) { | |
1861 | show_lapic = CONFIG_NR_CPUS; | |
1862 | } else { | |
1863 | get_option(&arg, &num); | |
1864 | if (num >= 0) | |
1865 | show_lapic = num; | |
1866 | } | |
1867 | ||
1868 | return 1; | |
1869 | } | |
1870 | __setup("show_lapic=", setup_show_lapic); | |
1871 | ||
1872 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1873 | { |
2626eb2b CG |
1874 | if (apic_verbosity == APIC_QUIET) |
1875 | return 0; | |
1876 | ||
32f71aff | 1877 | print_PIC(); |
4797f6b0 YL |
1878 | |
1879 | /* don't print out if apic is not there */ | |
8312136f | 1880 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1881 | return 0; |
1882 | ||
2626eb2b | 1883 | print_local_APICs(show_lapic); |
32f71aff MR |
1884 | print_IO_APIC(); |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
2626eb2b | 1889 | fs_initcall(print_ICs); |
32f71aff | 1890 | |
1da177e4 | 1891 | |
efa2559f YL |
1892 | /* Where if anywhere is the i8259 connect in external int mode */ |
1893 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1894 | ||
54168ed7 | 1895 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1896 | { |
1897 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1898 | int i8259_apic, i8259_pin; |
54168ed7 | 1899 | int apic; |
1da177e4 LT |
1900 | unsigned long flags; |
1901 | ||
1da177e4 LT |
1902 | /* |
1903 | * The number of IO-APIC IRQ registers (== #pins): | |
1904 | */ | |
fcfd636a | 1905 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1906 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1907 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1908 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1909 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1910 | } | |
bc07844a TG |
1911 | |
1912 | if (!nr_legacy_irqs) | |
1913 | return; | |
1914 | ||
54168ed7 | 1915 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1916 | int pin; |
1917 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1918 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1919 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1920 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1921 | |
fcfd636a EB |
1922 | /* If the interrupt line is enabled and in ExtInt mode |
1923 | * I have found the pin where the i8259 is connected. | |
1924 | */ | |
1925 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1926 | ioapic_i8259.apic = apic; | |
1927 | ioapic_i8259.pin = pin; | |
1928 | goto found_i8259; | |
1929 | } | |
1930 | } | |
1931 | } | |
1932 | found_i8259: | |
1933 | /* Look to see what if the MP table has reported the ExtINT */ | |
1934 | /* If we could not find the appropriate pin by looking at the ioapic | |
1935 | * the i8259 probably is not connected the ioapic but give the | |
1936 | * mptable a chance anyway. | |
1937 | */ | |
1938 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1939 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1940 | /* Trust the MP table if nothing is setup in the hardware */ | |
1941 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1942 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1943 | ioapic_i8259.pin = i8259_pin; | |
1944 | ioapic_i8259.apic = i8259_apic; | |
1945 | } | |
1946 | /* Complain if the MP table and the hardware disagree */ | |
1947 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1948 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1949 | { | |
1950 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1951 | } |
1952 | ||
1953 | /* | |
1954 | * Do not trust the IO-APIC being empty at bootup | |
1955 | */ | |
1956 | clear_IO_APIC(); | |
1957 | } | |
1958 | ||
1959 | /* | |
1960 | * Not an __init, needed by the reboot code | |
1961 | */ | |
1962 | void disable_IO_APIC(void) | |
1963 | { | |
1964 | /* | |
1965 | * Clear the IO-APIC before rebooting: | |
1966 | */ | |
1967 | clear_IO_APIC(); | |
1968 | ||
bc07844a TG |
1969 | if (!nr_legacy_irqs) |
1970 | return; | |
1971 | ||
650927ef | 1972 | /* |
0b968d23 | 1973 | * If the i8259 is routed through an IOAPIC |
650927ef | 1974 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1975 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1976 | * |
1977 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1978 | * as virtual wire B is little complex (need to configure both | |
1979 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1980 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1981 | */ |
7c6d9f97 | 1982 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1983 | struct IO_APIC_route_entry entry; |
650927ef EB |
1984 | |
1985 | memset(&entry, 0, sizeof(entry)); | |
1986 | entry.mask = 0; /* Enabled */ | |
1987 | entry.trigger = 0; /* Edge */ | |
1988 | entry.irr = 0; | |
1989 | entry.polarity = 0; /* High */ | |
1990 | entry.delivery_status = 0; | |
1991 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1992 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1993 | entry.vector = 0; |
54168ed7 | 1994 | entry.dest = read_apic_id(); |
650927ef EB |
1995 | |
1996 | /* | |
1997 | * Add it to the IO-APIC irq-routing table: | |
1998 | */ | |
cf4c6a2f | 1999 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2000 | } |
54168ed7 | 2001 | |
7c6d9f97 SS |
2002 | /* |
2003 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2004 | */ | |
8312136f | 2005 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2006 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2007 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2008 | } |
2009 | ||
54168ed7 | 2010 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2011 | /* |
2012 | * function to set the IO-APIC physical IDs based on the | |
2013 | * values stored in the MPC table. | |
2014 | * | |
2015 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2016 | */ | |
2017 | ||
de934103 | 2018 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2019 | { |
2020 | union IO_APIC_reg_00 reg_00; | |
2021 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2022 | int apic_id; |
1da177e4 LT |
2023 | int i; |
2024 | unsigned char old_id; | |
2025 | unsigned long flags; | |
2026 | ||
de934103 | 2027 | if (acpi_ioapic) |
d49c4288 | 2028 | return; |
ca05fea6 NP |
2029 | /* |
2030 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2031 | * no meaning without the serial APIC bus. | |
2032 | */ | |
7c5c1e42 SL |
2033 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2034 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2035 | return; |
1da177e4 LT |
2036 | /* |
2037 | * This is broken; anything with a real cpu count has to | |
2038 | * circumvent this idiocy regardless. | |
2039 | */ | |
7abc0753 | 2040 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2041 | |
2042 | /* | |
2043 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2044 | */ | |
c8d46cf0 | 2045 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2046 | |
2047 | /* Read the register 0 value */ | |
2048 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2049 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2050 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2051 | |
c8d46cf0 | 2052 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2053 | |
c8d46cf0 | 2054 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2055 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2056 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2057 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2058 | reg_00.bits.ID); | |
c8d46cf0 | 2059 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2060 | } |
2061 | ||
1da177e4 LT |
2062 | /* |
2063 | * Sanity check, is the ID really free? Every APIC in a | |
2064 | * system must have a unique ID or we get lots of nice | |
2065 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2066 | */ | |
7abc0753 | 2067 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2068 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2069 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2070 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2071 | for (i = 0; i < get_physical_broadcast(); i++) |
2072 | if (!physid_isset(i, phys_id_present_map)) | |
2073 | break; | |
2074 | if (i >= get_physical_broadcast()) | |
2075 | panic("Max APIC ID exceeded!\n"); | |
2076 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2077 | i); | |
2078 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2079 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2080 | } else { |
2081 | physid_mask_t tmp; | |
7abc0753 | 2082 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2083 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2084 | "phys_id_present_map\n", | |
c8d46cf0 | 2085 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2086 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2087 | } | |
2088 | ||
2089 | ||
2090 | /* | |
2091 | * We need to adjust the IRQ routing table | |
2092 | * if the ID changed. | |
2093 | */ | |
c8d46cf0 | 2094 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2095 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2096 | if (mp_irqs[i].dstapic == old_id) |
2097 | mp_irqs[i].dstapic | |
c8d46cf0 | 2098 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2099 | |
2100 | /* | |
2101 | * Read the right value from the MPC table and | |
2102 | * write it into the ID register. | |
36062448 | 2103 | */ |
1da177e4 LT |
2104 | apic_printk(APIC_VERBOSE, KERN_INFO |
2105 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2106 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2107 | |
c8d46cf0 | 2108 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2109 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2110 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2111 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2112 | |
2113 | /* | |
2114 | * Sanity check | |
2115 | */ | |
2116 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2117 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2118 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2119 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2120 | printk("could not set ID!\n"); |
2121 | else | |
2122 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2123 | } | |
2124 | } | |
54168ed7 | 2125 | #endif |
1da177e4 | 2126 | |
7ce0bcfd | 2127 | int no_timer_check __initdata; |
8542b200 ZA |
2128 | |
2129 | static int __init notimercheck(char *s) | |
2130 | { | |
2131 | no_timer_check = 1; | |
2132 | return 1; | |
2133 | } | |
2134 | __setup("no_timer_check", notimercheck); | |
2135 | ||
1da177e4 LT |
2136 | /* |
2137 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2138 | * about the timer IRQ. We do the following to work around the situation: | |
2139 | * | |
2140 | * - timer IRQ defaults to IO-APIC IRQ | |
2141 | * - if this function detects that timer IRQs are defunct, then we fall | |
2142 | * back to ISA timer IRQs | |
2143 | */ | |
f0a7a5c9 | 2144 | static int __init timer_irq_works(void) |
1da177e4 LT |
2145 | { |
2146 | unsigned long t1 = jiffies; | |
4aae0702 | 2147 | unsigned long flags; |
1da177e4 | 2148 | |
8542b200 ZA |
2149 | if (no_timer_check) |
2150 | return 1; | |
2151 | ||
4aae0702 | 2152 | local_save_flags(flags); |
1da177e4 LT |
2153 | local_irq_enable(); |
2154 | /* Let ten ticks pass... */ | |
2155 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2156 | local_irq_restore(flags); |
1da177e4 LT |
2157 | |
2158 | /* | |
2159 | * Expect a few ticks at least, to be sure some possible | |
2160 | * glue logic does not lock up after one or two first | |
2161 | * ticks in a non-ExtINT mode. Also the local APIC | |
2162 | * might have cached one ExtINT interrupt. Finally, at | |
2163 | * least one tick may be lost due to delays. | |
2164 | */ | |
54168ed7 IM |
2165 | |
2166 | /* jiffies wrap? */ | |
1d16b53e | 2167 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2168 | return 1; |
1da177e4 LT |
2169 | return 0; |
2170 | } | |
2171 | ||
2172 | /* | |
2173 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2174 | * number of pending IRQ events unhandled. These cases are very rare, | |
2175 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2176 | * better to do it this way as thus we do not have to be aware of | |
2177 | * 'pending' interrupts in the IRQ path, except at this point. | |
2178 | */ | |
2179 | /* | |
2180 | * Edge triggered needs to resend any interrupt | |
2181 | * that was delayed but this is now handled in the device | |
2182 | * independent code. | |
2183 | */ | |
2184 | ||
2185 | /* | |
2186 | * Starting up a edge-triggered IO-APIC interrupt is | |
2187 | * nasty - we need to make sure that we get the edge. | |
2188 | * If it is already asserted for some reason, we need | |
2189 | * return 1 to indicate that is was pending. | |
2190 | * | |
2191 | * This is not complete - we should be able to fake | |
2192 | * an edge even if it isn't on the 8259A... | |
2193 | */ | |
54168ed7 | 2194 | |
f5b9ed7a | 2195 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2196 | { |
2197 | int was_pending = 0; | |
2198 | unsigned long flags; | |
0b8f1efa | 2199 | struct irq_cfg *cfg; |
1da177e4 LT |
2200 | |
2201 | spin_lock_irqsave(&ioapic_lock, flags); | |
bc07844a | 2202 | if (irq < nr_legacy_irqs) { |
1da177e4 LT |
2203 | disable_8259A_irq(irq); |
2204 | if (i8259A_irq_pending(irq)) | |
2205 | was_pending = 1; | |
2206 | } | |
0b8f1efa | 2207 | cfg = irq_cfg(irq); |
3145e941 | 2208 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2209 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2210 | ||
2211 | return was_pending; | |
2212 | } | |
2213 | ||
ace80ab7 | 2214 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2215 | { |
54168ed7 IM |
2216 | |
2217 | struct irq_cfg *cfg = irq_cfg(irq); | |
2218 | unsigned long flags; | |
2219 | ||
2220 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2221 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2222 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2223 | |
2224 | return 1; | |
2225 | } | |
497c9a19 | 2226 | |
54168ed7 IM |
2227 | /* |
2228 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2229 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2230 | * handled with the level-triggered descriptor, but that one has slightly | |
2231 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2232 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2233 | * races. | |
2234 | */ | |
497c9a19 | 2235 | |
54168ed7 | 2236 | #ifdef CONFIG_SMP |
9338ad6f | 2237 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2238 | { |
2239 | cpumask_var_t cleanup_mask; | |
2240 | ||
2241 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2242 | unsigned int i; | |
e85abf8f GH |
2243 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2244 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2245 | } else { | |
2246 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2247 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2248 | free_cpumask_var(cleanup_mask); | |
2249 | } | |
2250 | cfg->move_in_progress = 0; | |
2251 | } | |
2252 | ||
4420471f | 2253 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2254 | { |
2255 | int apic, pin; | |
2256 | struct irq_pin_list *entry; | |
2257 | u8 vector = cfg->vector; | |
2258 | ||
2977fb3f | 2259 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2260 | unsigned int reg; |
2261 | ||
e85abf8f GH |
2262 | apic = entry->apic; |
2263 | pin = entry->pin; | |
2264 | /* | |
2265 | * With interrupt-remapping, destination information comes | |
2266 | * from interrupt-remapping table entry. | |
2267 | */ | |
2268 | if (!irq_remapped(irq)) | |
2269 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2270 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2271 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2272 | reg |= vector; | |
2273 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2274 | } |
2275 | } | |
2276 | ||
2277 | /* | |
2278 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2279 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2280 | * leaves desc->affinity untouched. |
2281 | */ | |
9338ad6f | 2282 | unsigned int |
18374d89 SS |
2283 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2284 | unsigned int *dest_id) | |
e85abf8f GH |
2285 | { |
2286 | struct irq_cfg *cfg; | |
2287 | unsigned int irq; | |
2288 | ||
2289 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2290 | return -1; |
e85abf8f GH |
2291 | |
2292 | irq = desc->irq; | |
2293 | cfg = desc->chip_data; | |
2294 | if (assign_irq_vector(irq, cfg, mask)) | |
18374d89 | 2295 | return -1; |
e85abf8f | 2296 | |
e85abf8f GH |
2297 | cpumask_copy(desc->affinity, mask); |
2298 | ||
18374d89 SS |
2299 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2300 | return 0; | |
e85abf8f GH |
2301 | } |
2302 | ||
4420471f | 2303 | static int |
e85abf8f GH |
2304 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2305 | { | |
2306 | struct irq_cfg *cfg; | |
2307 | unsigned long flags; | |
2308 | unsigned int dest; | |
2309 | unsigned int irq; | |
4420471f | 2310 | int ret = -1; |
e85abf8f GH |
2311 | |
2312 | irq = desc->irq; | |
2313 | cfg = desc->chip_data; | |
2314 | ||
2315 | spin_lock_irqsave(&ioapic_lock, flags); | |
18374d89 SS |
2316 | ret = set_desc_affinity(desc, mask, &dest); |
2317 | if (!ret) { | |
e85abf8f GH |
2318 | /* Only the high 8 bits are valid. */ |
2319 | dest = SET_APIC_LOGICAL_ID(dest); | |
2320 | __target_IO_APIC_irq(irq, dest, cfg); | |
2321 | } | |
2322 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2323 | |
2324 | return ret; | |
e85abf8f GH |
2325 | } |
2326 | ||
4420471f | 2327 | static int |
e85abf8f GH |
2328 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2329 | { | |
2330 | struct irq_desc *desc; | |
2331 | ||
2332 | desc = irq_to_desc(irq); | |
2333 | ||
4420471f | 2334 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2335 | } |
497c9a19 | 2336 | |
54168ed7 | 2337 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2338 | |
54168ed7 IM |
2339 | /* |
2340 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2341 | * | |
0280f7c4 SS |
2342 | * For both level and edge triggered, irq migration is a simple atomic |
2343 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2344 | * |
0280f7c4 SS |
2345 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2346 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2347 | * Real vector that is used for interrupting cpu will be coming from | |
2348 | * the interrupt-remapping table entry. | |
54168ed7 | 2349 | */ |
d5dedd45 | 2350 | static int |
e7986739 | 2351 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2352 | { |
54168ed7 | 2353 | struct irq_cfg *cfg; |
54168ed7 | 2354 | struct irte irte; |
54168ed7 | 2355 | unsigned int dest; |
3145e941 | 2356 | unsigned int irq; |
d5dedd45 | 2357 | int ret = -1; |
497c9a19 | 2358 | |
22f65d31 | 2359 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2360 | return ret; |
497c9a19 | 2361 | |
3145e941 | 2362 | irq = desc->irq; |
54168ed7 | 2363 | if (get_irte(irq, &irte)) |
d5dedd45 | 2364 | return ret; |
497c9a19 | 2365 | |
3145e941 YL |
2366 | cfg = desc->chip_data; |
2367 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2368 | return ret; |
54168ed7 | 2369 | |
debccb3e | 2370 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2371 | |
54168ed7 IM |
2372 | irte.vector = cfg->vector; |
2373 | irte.dest_id = IRTE_DEST(dest); | |
2374 | ||
2375 | /* | |
2376 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2377 | */ | |
2378 | modify_irte(irq, &irte); | |
2379 | ||
22f65d31 MT |
2380 | if (cfg->move_in_progress) |
2381 | send_cleanup_vector(cfg); | |
54168ed7 | 2382 | |
7f7ace0c | 2383 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2384 | |
2385 | return 0; | |
54168ed7 IM |
2386 | } |
2387 | ||
54168ed7 IM |
2388 | /* |
2389 | * Migrates the IRQ destination in the process context. | |
2390 | */ | |
d5dedd45 | 2391 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2392 | const struct cpumask *mask) |
54168ed7 | 2393 | { |
d5dedd45 | 2394 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2395 | } |
d5dedd45 | 2396 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2397 | const struct cpumask *mask) |
3145e941 YL |
2398 | { |
2399 | struct irq_desc *desc = irq_to_desc(irq); | |
2400 | ||
d5dedd45 | 2401 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2402 | } |
29b61be6 | 2403 | #else |
d5dedd45 | 2404 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2405 | const struct cpumask *mask) |
2406 | { | |
d5dedd45 | 2407 | return 0; |
29b61be6 | 2408 | } |
54168ed7 IM |
2409 | #endif |
2410 | ||
2411 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2412 | { | |
2413 | unsigned vector, me; | |
8f2466f4 | 2414 | |
54168ed7 | 2415 | ack_APIC_irq(); |
54168ed7 | 2416 | exit_idle(); |
54168ed7 IM |
2417 | irq_enter(); |
2418 | ||
2419 | me = smp_processor_id(); | |
2420 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2421 | unsigned int irq; | |
68a8ca59 | 2422 | unsigned int irr; |
54168ed7 IM |
2423 | struct irq_desc *desc; |
2424 | struct irq_cfg *cfg; | |
2425 | irq = __get_cpu_var(vector_irq)[vector]; | |
2426 | ||
0b8f1efa YL |
2427 | if (irq == -1) |
2428 | continue; | |
2429 | ||
54168ed7 IM |
2430 | desc = irq_to_desc(irq); |
2431 | if (!desc) | |
2432 | continue; | |
2433 | ||
2434 | cfg = irq_cfg(irq); | |
2435 | spin_lock(&desc->lock); | |
54168ed7 | 2436 | |
22f65d31 | 2437 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2438 | goto unlock; |
2439 | ||
68a8ca59 SS |
2440 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2441 | /* | |
2442 | * Check if the vector that needs to be cleanedup is | |
2443 | * registered at the cpu's IRR. If so, then this is not | |
2444 | * the best time to clean it up. Lets clean it up in the | |
2445 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2446 | * to myself. | |
2447 | */ | |
2448 | if (irr & (1 << (vector % 32))) { | |
2449 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2450 | goto unlock; | |
2451 | } | |
54168ed7 | 2452 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 IM |
2453 | unlock: |
2454 | spin_unlock(&desc->lock); | |
2455 | } | |
2456 | ||
2457 | irq_exit(); | |
2458 | } | |
2459 | ||
a5e74b84 | 2460 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2461 | { |
3145e941 YL |
2462 | struct irq_desc *desc = *descp; |
2463 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2464 | unsigned me; |
54168ed7 | 2465 | |
fcef5911 | 2466 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2467 | return; |
2468 | ||
54168ed7 | 2469 | me = smp_processor_id(); |
10b888d6 | 2470 | |
fcef5911 | 2471 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2472 | send_cleanup_vector(cfg); |
497c9a19 | 2473 | } |
a5e74b84 SS |
2474 | |
2475 | static void irq_complete_move(struct irq_desc **descp) | |
2476 | { | |
2477 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2478 | } | |
2479 | ||
2480 | void irq_force_complete_move(int irq) | |
2481 | { | |
2482 | struct irq_desc *desc = irq_to_desc(irq); | |
2483 | struct irq_cfg *cfg = desc->chip_data; | |
2484 | ||
2485 | __irq_complete_move(&desc, cfg->vector); | |
2486 | } | |
497c9a19 | 2487 | #else |
3145e941 | 2488 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2489 | #endif |
3145e941 | 2490 | |
1d025192 YL |
2491 | static void ack_apic_edge(unsigned int irq) |
2492 | { | |
3145e941 YL |
2493 | struct irq_desc *desc = irq_to_desc(irq); |
2494 | ||
2495 | irq_complete_move(&desc); | |
1d025192 YL |
2496 | move_native_irq(irq); |
2497 | ack_APIC_irq(); | |
2498 | } | |
2499 | ||
3eb2cce8 | 2500 | atomic_t irq_mis_count; |
3eb2cce8 | 2501 | |
c29d9db3 SS |
2502 | /* |
2503 | * IO-APIC versions below 0x20 don't support EOI register. | |
2504 | * For the record, here is the information about various versions: | |
2505 | * 0Xh 82489DX | |
2506 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2507 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2508 | * 30h-FFh Reserved | |
2509 | * | |
2510 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2511 | * version as 0x2. This is an error with documentation and these ICH chips | |
2512 | * use io-apic's of version 0x20. | |
2513 | * | |
2514 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2515 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2516 | * mode to edge and then back to level, with RTE being masked during this. | |
2517 | */ | |
b3ec0a37 SS |
2518 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2519 | { | |
2520 | struct irq_pin_list *entry; | |
2521 | ||
2522 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
c29d9db3 SS |
2523 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2524 | /* | |
2525 | * Intr-remapping uses pin number as the virtual vector | |
2526 | * in the RTE. Actual vector is programmed in | |
2527 | * intr-remapping table entry. Hence for the io-apic | |
2528 | * EOI we use the pin number. | |
2529 | */ | |
2530 | if (irq_remapped(irq)) | |
2531 | io_apic_eoi(entry->apic, entry->pin); | |
2532 | else | |
2533 | io_apic_eoi(entry->apic, cfg->vector); | |
2534 | } else { | |
2535 | __mask_and_edge_IO_APIC_irq(entry); | |
2536 | __unmask_and_level_IO_APIC_irq(entry); | |
2537 | } | |
b3ec0a37 SS |
2538 | } |
2539 | } | |
2540 | ||
2541 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2542 | { | |
2543 | struct irq_cfg *cfg; | |
2544 | unsigned long flags; | |
2545 | unsigned int irq; | |
2546 | ||
2547 | irq = desc->irq; | |
2548 | cfg = desc->chip_data; | |
2549 | ||
2550 | spin_lock_irqsave(&ioapic_lock, flags); | |
2551 | __eoi_ioapic_irq(irq, cfg); | |
2552 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2553 | } | |
2554 | ||
047c8fdb YL |
2555 | static void ack_apic_level(unsigned int irq) |
2556 | { | |
3145e941 | 2557 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2558 | unsigned long v; |
2559 | int i; | |
3145e941 | 2560 | struct irq_cfg *cfg; |
54168ed7 | 2561 | int do_unmask_irq = 0; |
047c8fdb | 2562 | |
3145e941 | 2563 | irq_complete_move(&desc); |
047c8fdb | 2564 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2565 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2566 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2567 | do_unmask_irq = 1; |
3145e941 | 2568 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2569 | } |
047c8fdb YL |
2570 | #endif |
2571 | ||
3eb2cce8 | 2572 | /* |
916a0fe7 JF |
2573 | * It appears there is an erratum which affects at least version 0x11 |
2574 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2575 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2576 | * erroneously delivered as edge-triggered one but the respective IRR | |
2577 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2578 | * message but it will never arrive and further interrupts are blocked | |
2579 | * from the source. The exact reason is so far unknown, but the | |
2580 | * phenomenon was observed when two consecutive interrupt requests | |
2581 | * from a given source get delivered to the same CPU and the source is | |
2582 | * temporarily disabled in between. | |
2583 | * | |
2584 | * A workaround is to simulate an EOI message manually. We achieve it | |
2585 | * by setting the trigger mode to edge and then to level when the edge | |
2586 | * trigger mode gets detected in the TMR of a local APIC for a | |
2587 | * level-triggered interrupt. We mask the source for the time of the | |
2588 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2589 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2590 | * |
2591 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2592 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2593 | * destination that is handling the corresponding interrupt. This | |
2594 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2595 | * level-triggered io-apic interrupt will be seen as an edge | |
2596 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2597 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2598 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2599 | * supporting EOI register, we do an explicit EOI to clear the | |
2600 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2601 | * we use the above logic (mask+edge followed by unmask+level) from | |
2602 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2603 | */ |
3145e941 YL |
2604 | cfg = desc->chip_data; |
2605 | i = cfg->vector; | |
3eb2cce8 | 2606 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2607 | |
54168ed7 IM |
2608 | /* |
2609 | * We must acknowledge the irq before we move it or the acknowledge will | |
2610 | * not propagate properly. | |
2611 | */ | |
2612 | ack_APIC_irq(); | |
2613 | ||
1c83995b SS |
2614 | /* |
2615 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2616 | * message via io-apic EOI register write or simulating it using | |
2617 | * mask+edge followed by unnask+level logic) manually when the | |
2618 | * level triggered interrupt is seen as the edge triggered interrupt | |
2619 | * at the cpu. | |
2620 | */ | |
ca64c47c MR |
2621 | if (!(v & (1 << (i & 0x1f)))) { |
2622 | atomic_inc(&irq_mis_count); | |
2623 | ||
c29d9db3 | 2624 | eoi_ioapic_irq(desc); |
ca64c47c MR |
2625 | } |
2626 | ||
54168ed7 IM |
2627 | /* Now we can move and renable the irq */ |
2628 | if (unlikely(do_unmask_irq)) { | |
2629 | /* Only migrate the irq if the ack has been received. | |
2630 | * | |
2631 | * On rare occasions the broadcast level triggered ack gets | |
2632 | * delayed going to ioapics, and if we reprogram the | |
2633 | * vector while Remote IRR is still set the irq will never | |
2634 | * fire again. | |
2635 | * | |
2636 | * To prevent this scenario we read the Remote IRR bit | |
2637 | * of the ioapic. This has two effects. | |
2638 | * - On any sane system the read of the ioapic will | |
2639 | * flush writes (and acks) going to the ioapic from | |
2640 | * this cpu. | |
2641 | * - We get to see if the ACK has actually been delivered. | |
2642 | * | |
2643 | * Based on failed experiments of reprogramming the | |
2644 | * ioapic entry from outside of irq context starting | |
2645 | * with masking the ioapic entry and then polling until | |
2646 | * Remote IRR was clear before reprogramming the | |
2647 | * ioapic I don't trust the Remote IRR bit to be | |
2648 | * completey accurate. | |
2649 | * | |
2650 | * However there appears to be no other way to plug | |
2651 | * this race, so if the Remote IRR bit is not | |
2652 | * accurate and is causing problems then it is a hardware bug | |
2653 | * and you can go talk to the chipset vendor about it. | |
2654 | */ | |
3145e941 YL |
2655 | cfg = desc->chip_data; |
2656 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2657 | move_masked_irq(irq); |
3145e941 | 2658 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2659 | } |
3eb2cce8 | 2660 | } |
1d025192 | 2661 | |
d0b03bd1 HW |
2662 | #ifdef CONFIG_INTR_REMAP |
2663 | static void ir_ack_apic_edge(unsigned int irq) | |
2664 | { | |
5d0ae2db | 2665 | ack_APIC_irq(); |
d0b03bd1 HW |
2666 | } |
2667 | ||
2668 | static void ir_ack_apic_level(unsigned int irq) | |
2669 | { | |
5d0ae2db WH |
2670 | struct irq_desc *desc = irq_to_desc(irq); |
2671 | ||
2672 | ack_APIC_irq(); | |
2673 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2674 | } |
2675 | #endif /* CONFIG_INTR_REMAP */ | |
2676 | ||
f5b9ed7a | 2677 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2678 | .name = "IO-APIC", |
2679 | .startup = startup_ioapic_irq, | |
2680 | .mask = mask_IO_APIC_irq, | |
2681 | .unmask = unmask_IO_APIC_irq, | |
2682 | .ack = ack_apic_edge, | |
2683 | .eoi = ack_apic_level, | |
54d5d424 | 2684 | #ifdef CONFIG_SMP |
d6c88a50 | 2685 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2686 | #endif |
ace80ab7 | 2687 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2688 | }; |
2689 | ||
54168ed7 | 2690 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2691 | .name = "IR-IO-APIC", |
2692 | .startup = startup_ioapic_irq, | |
2693 | .mask = mask_IO_APIC_irq, | |
2694 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2695 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2696 | .ack = ir_ack_apic_edge, |
2697 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2698 | #ifdef CONFIG_SMP |
d6c88a50 | 2699 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2700 | #endif |
54168ed7 IM |
2701 | #endif |
2702 | .retrigger = ioapic_retrigger_irq, | |
2703 | }; | |
1da177e4 LT |
2704 | |
2705 | static inline void init_IO_APIC_traps(void) | |
2706 | { | |
2707 | int irq; | |
08678b08 | 2708 | struct irq_desc *desc; |
da51a821 | 2709 | struct irq_cfg *cfg; |
1da177e4 LT |
2710 | |
2711 | /* | |
2712 | * NOTE! The local APIC isn't very good at handling | |
2713 | * multiple interrupts at the same interrupt level. | |
2714 | * As the interrupt level is determined by taking the | |
2715 | * vector number and shifting that right by 4, we | |
2716 | * want to spread these out a bit so that they don't | |
2717 | * all fall in the same interrupt level. | |
2718 | * | |
2719 | * Also, we've got to be careful not to trash gate | |
2720 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2721 | */ | |
0b8f1efa | 2722 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2723 | cfg = desc->chip_data; |
2724 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2725 | /* |
2726 | * Hmm.. We don't have an entry for this, | |
2727 | * so default to an old-fashioned 8259 | |
2728 | * interrupt if we can.. | |
2729 | */ | |
bc07844a | 2730 | if (irq < nr_legacy_irqs) |
1da177e4 | 2731 | make_8259A_irq(irq); |
0b8f1efa | 2732 | else |
1da177e4 | 2733 | /* Strange. Oh, well.. */ |
08678b08 | 2734 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2735 | } |
2736 | } | |
2737 | } | |
2738 | ||
f5b9ed7a IM |
2739 | /* |
2740 | * The local APIC irq-chip implementation: | |
2741 | */ | |
1da177e4 | 2742 | |
36062448 | 2743 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2744 | { |
2745 | unsigned long v; | |
2746 | ||
2747 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2748 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2749 | } |
2750 | ||
36062448 | 2751 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2752 | { |
f5b9ed7a | 2753 | unsigned long v; |
1da177e4 | 2754 | |
f5b9ed7a | 2755 | v = apic_read(APIC_LVT0); |
593f4a78 | 2756 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2757 | } |
1da177e4 | 2758 | |
3145e941 | 2759 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2760 | { |
2761 | ack_APIC_irq(); | |
2762 | } | |
2763 | ||
f5b9ed7a | 2764 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2765 | .name = "local-APIC", |
f5b9ed7a IM |
2766 | .mask = mask_lapic_irq, |
2767 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2768 | .ack = ack_lapic_irq, |
1da177e4 LT |
2769 | }; |
2770 | ||
3145e941 | 2771 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2772 | { |
08678b08 | 2773 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2774 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2775 | "edge"); | |
c88ac1df MR |
2776 | } |
2777 | ||
e9427101 | 2778 | static void __init setup_nmi(void) |
1da177e4 LT |
2779 | { |
2780 | /* | |
36062448 | 2781 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2782 | * We put the 8259A master into AEOI mode and |
2783 | * unmask on all local APICs LVT0 as NMI. | |
2784 | * | |
2785 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2786 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2787 | * the NMI handler or the timer interrupt. | |
36062448 | 2788 | */ |
1da177e4 LT |
2789 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2790 | ||
e9427101 | 2791 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2792 | |
2793 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2794 | } | |
2795 | ||
2796 | /* | |
2797 | * This looks a bit hackish but it's about the only one way of sending | |
2798 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2799 | * not support the ExtINT mode, unfortunately. We need to send these | |
2800 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2801 | * 8259A interrupt line asserted until INTA. --macro | |
2802 | */ | |
28acf285 | 2803 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2804 | { |
fcfd636a | 2805 | int apic, pin, i; |
1da177e4 LT |
2806 | struct IO_APIC_route_entry entry0, entry1; |
2807 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2808 | |
fcfd636a | 2809 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2810 | if (pin == -1) { |
2811 | WARN_ON_ONCE(1); | |
2812 | return; | |
2813 | } | |
fcfd636a | 2814 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2815 | if (apic == -1) { |
2816 | WARN_ON_ONCE(1); | |
1da177e4 | 2817 | return; |
956fb531 | 2818 | } |
1da177e4 | 2819 | |
cf4c6a2f | 2820 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2821 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2822 | |
2823 | memset(&entry1, 0, sizeof(entry1)); | |
2824 | ||
2825 | entry1.dest_mode = 0; /* physical delivery */ | |
2826 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2827 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2828 | entry1.delivery_mode = dest_ExtINT; |
2829 | entry1.polarity = entry0.polarity; | |
2830 | entry1.trigger = 0; | |
2831 | entry1.vector = 0; | |
2832 | ||
cf4c6a2f | 2833 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2834 | |
2835 | save_control = CMOS_READ(RTC_CONTROL); | |
2836 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2837 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2838 | RTC_FREQ_SELECT); | |
2839 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2840 | ||
2841 | i = 100; | |
2842 | while (i-- > 0) { | |
2843 | mdelay(10); | |
2844 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2845 | i -= 10; | |
2846 | } | |
2847 | ||
2848 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2849 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2850 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2851 | |
cf4c6a2f | 2852 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2853 | } |
2854 | ||
efa2559f | 2855 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2856 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2857 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2858 | { |
2859 | disable_timer_pin_1 = 1; | |
2860 | return 0; | |
2861 | } | |
54168ed7 | 2862 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2863 | |
2864 | int timer_through_8259 __initdata; | |
2865 | ||
1da177e4 LT |
2866 | /* |
2867 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2868 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2869 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2870 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2871 | * |
2872 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2873 | */ |
8542b200 | 2874 | static inline void __init check_timer(void) |
1da177e4 | 2875 | { |
3145e941 YL |
2876 | struct irq_desc *desc = irq_to_desc(0); |
2877 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2878 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2879 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2880 | unsigned long flags; |
047c8fdb | 2881 | int no_pin1 = 0; |
4aae0702 IM |
2882 | |
2883 | local_irq_save(flags); | |
d4d25dec | 2884 | |
1da177e4 LT |
2885 | /* |
2886 | * get/set the timer IRQ vector: | |
2887 | */ | |
2888 | disable_8259A_irq(0); | |
fe402e1f | 2889 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2890 | |
2891 | /* | |
d11d5794 MR |
2892 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2893 | * wire has to be disabled in the local APIC. Also | |
2894 | * timer interrupts need to be acknowledged manually in | |
2895 | * the 8259A for the i82489DX when using the NMI | |
2896 | * watchdog as that APIC treats NMIs as level-triggered. | |
2897 | * The AEOI mode will finish them in the 8259A | |
2898 | * automatically. | |
1da177e4 | 2899 | */ |
593f4a78 | 2900 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2901 | init_8259A(1); |
54168ed7 | 2902 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2903 | { |
2904 | unsigned int ver; | |
2905 | ||
2906 | ver = apic_read(APIC_LVR); | |
2907 | ver = GET_APIC_VERSION(ver); | |
2908 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2909 | } | |
54168ed7 | 2910 | #endif |
1da177e4 | 2911 | |
fcfd636a EB |
2912 | pin1 = find_isa_irq_pin(0, mp_INT); |
2913 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2914 | pin2 = ioapic_i8259.pin; | |
2915 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2916 | |
49a66a0b MR |
2917 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2918 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2919 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2920 | |
691874fa MR |
2921 | /* |
2922 | * Some BIOS writers are clueless and report the ExtINTA | |
2923 | * I/O APIC input from the cascaded 8259A as the timer | |
2924 | * interrupt input. So just in case, if only one pin | |
2925 | * was found above, try it both directly and through the | |
2926 | * 8259A. | |
2927 | */ | |
2928 | if (pin1 == -1) { | |
54168ed7 IM |
2929 | if (intr_remapping_enabled) |
2930 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2931 | pin1 = pin2; |
2932 | apic1 = apic2; | |
2933 | no_pin1 = 1; | |
2934 | } else if (pin2 == -1) { | |
2935 | pin2 = pin1; | |
2936 | apic2 = apic1; | |
2937 | } | |
2938 | ||
1da177e4 LT |
2939 | if (pin1 != -1) { |
2940 | /* | |
2941 | * Ok, does IRQ0 through the IOAPIC work? | |
2942 | */ | |
691874fa | 2943 | if (no_pin1) { |
85ac16d0 | 2944 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2945 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2946 | } else { |
2947 | /* for edge trigger, setup_IO_APIC_irq already | |
2948 | * leave it unmasked. | |
2949 | * so only need to unmask if it is level-trigger | |
2950 | * do we really have level trigger timer? | |
2951 | */ | |
2952 | int idx; | |
2953 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2954 | if (idx != -1 && irq_trigger(idx)) | |
2955 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2956 | } |
1da177e4 LT |
2957 | if (timer_irq_works()) { |
2958 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2959 | setup_nmi(); |
2960 | enable_8259A_irq(0); | |
1da177e4 | 2961 | } |
66759a01 CE |
2962 | if (disable_timer_pin_1 > 0) |
2963 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2964 | goto out; |
1da177e4 | 2965 | } |
54168ed7 IM |
2966 | if (intr_remapping_enabled) |
2967 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2968 | local_irq_disable(); |
fcfd636a | 2969 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2970 | if (!no_pin1) |
49a66a0b MR |
2971 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2972 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2973 | |
49a66a0b MR |
2974 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2975 | "(IRQ0) through the 8259A ...\n"); | |
2976 | apic_printk(APIC_QUIET, KERN_INFO | |
2977 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2978 | /* |
2979 | * legacy devices should be connected to IO APIC #0 | |
2980 | */ | |
85ac16d0 | 2981 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2982 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2983 | enable_8259A_irq(0); |
1da177e4 | 2984 | if (timer_irq_works()) { |
49a66a0b | 2985 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2986 | timer_through_8259 = 1; |
1da177e4 | 2987 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2988 | disable_8259A_irq(0); |
1da177e4 | 2989 | setup_nmi(); |
60134ebe | 2990 | enable_8259A_irq(0); |
1da177e4 | 2991 | } |
4aae0702 | 2992 | goto out; |
1da177e4 LT |
2993 | } |
2994 | /* | |
2995 | * Cleanup, just in case ... | |
2996 | */ | |
f72dccac | 2997 | local_irq_disable(); |
ecd29476 | 2998 | disable_8259A_irq(0); |
fcfd636a | 2999 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3000 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3001 | } |
1da177e4 LT |
3002 | |
3003 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3004 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3005 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3006 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3007 | } |
54168ed7 | 3008 | #ifdef CONFIG_X86_32 |
d11d5794 | 3009 | timer_ack = 0; |
54168ed7 | 3010 | #endif |
1da177e4 | 3011 | |
49a66a0b MR |
3012 | apic_printk(APIC_QUIET, KERN_INFO |
3013 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3014 | |
3145e941 | 3015 | lapic_register_intr(0, desc); |
497c9a19 | 3016 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3017 | enable_8259A_irq(0); |
3018 | ||
3019 | if (timer_irq_works()) { | |
49a66a0b | 3020 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3021 | goto out; |
1da177e4 | 3022 | } |
f72dccac | 3023 | local_irq_disable(); |
e67465f1 | 3024 | disable_8259A_irq(0); |
497c9a19 | 3025 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3026 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3027 | |
49a66a0b MR |
3028 | apic_printk(APIC_QUIET, KERN_INFO |
3029 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3030 | |
1da177e4 LT |
3031 | init_8259A(0); |
3032 | make_8259A_irq(0); | |
593f4a78 | 3033 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3034 | |
3035 | unlock_ExtINT_logic(); | |
3036 | ||
3037 | if (timer_irq_works()) { | |
49a66a0b | 3038 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3039 | goto out; |
1da177e4 | 3040 | } |
f72dccac | 3041 | local_irq_disable(); |
49a66a0b | 3042 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3043 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3044 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3045 | out: |
3046 | local_irq_restore(flags); | |
1da177e4 LT |
3047 | } |
3048 | ||
3049 | /* | |
af174783 MR |
3050 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3051 | * to devices. However there may be an I/O APIC pin available for | |
3052 | * this interrupt regardless. The pin may be left unconnected, but | |
3053 | * typically it will be reused as an ExtINT cascade interrupt for | |
3054 | * the master 8259A. In the MPS case such a pin will normally be | |
3055 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3056 | * there is no provision for ExtINT interrupts, and in the absence | |
3057 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3058 | * interrupt, that is edge-triggered and unmasked by default. We | |
3059 | * used to do this, but it caused problems on some systems because | |
3060 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3061 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3062 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3063 | * the I/O APIC in all cases now. No actual device should request | |
3064 | * it anyway. --macro | |
1da177e4 | 3065 | */ |
bc07844a | 3066 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3067 | |
3068 | void __init setup_IO_APIC(void) | |
3069 | { | |
54168ed7 | 3070 | |
54168ed7 IM |
3071 | /* |
3072 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3073 | */ | |
bc07844a | 3074 | io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3075 | |
54168ed7 | 3076 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3077 | /* |
54168ed7 IM |
3078 | * Set up IO-APIC IRQ routing. |
3079 | */ | |
de934103 TG |
3080 | x86_init.mpparse.setup_ioapic_ids(); |
3081 | ||
1da177e4 LT |
3082 | sync_Arb_IDs(); |
3083 | setup_IO_APIC_irqs(); | |
3084 | init_IO_APIC_traps(); | |
bc07844a TG |
3085 | if (nr_legacy_irqs) |
3086 | check_timer(); | |
1da177e4 LT |
3087 | } |
3088 | ||
3089 | /* | |
54168ed7 IM |
3090 | * Called after all the initialization is done. If we didnt find any |
3091 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3092 | */ |
36062448 | 3093 | |
1da177e4 LT |
3094 | static int __init io_apic_bug_finalize(void) |
3095 | { | |
d6c88a50 TG |
3096 | if (sis_apic_bug == -1) |
3097 | sis_apic_bug = 0; | |
3098 | return 0; | |
1da177e4 LT |
3099 | } |
3100 | ||
3101 | late_initcall(io_apic_bug_finalize); | |
3102 | ||
3103 | struct sysfs_ioapic_data { | |
3104 | struct sys_device dev; | |
3105 | struct IO_APIC_route_entry entry[0]; | |
3106 | }; | |
54168ed7 | 3107 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3108 | |
438510f6 | 3109 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3110 | { |
3111 | struct IO_APIC_route_entry *entry; | |
3112 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3113 | int i; |
36062448 | 3114 | |
1da177e4 LT |
3115 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3116 | entry = data->entry; | |
54168ed7 IM |
3117 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3118 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3119 | |
3120 | return 0; | |
3121 | } | |
3122 | ||
3123 | static int ioapic_resume(struct sys_device *dev) | |
3124 | { | |
3125 | struct IO_APIC_route_entry *entry; | |
3126 | struct sysfs_ioapic_data *data; | |
3127 | unsigned long flags; | |
3128 | union IO_APIC_reg_00 reg_00; | |
3129 | int i; | |
36062448 | 3130 | |
1da177e4 LT |
3131 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3132 | entry = data->entry; | |
3133 | ||
3134 | spin_lock_irqsave(&ioapic_lock, flags); | |
3135 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3136 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3137 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3138 | io_apic_write(dev->id, 0, reg_00.raw); |
3139 | } | |
1da177e4 | 3140 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3141 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3142 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3143 | |
3144 | return 0; | |
3145 | } | |
3146 | ||
3147 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3148 | .name = "ioapic", |
1da177e4 LT |
3149 | .suspend = ioapic_suspend, |
3150 | .resume = ioapic_resume, | |
3151 | }; | |
3152 | ||
3153 | static int __init ioapic_init_sysfs(void) | |
3154 | { | |
54168ed7 IM |
3155 | struct sys_device * dev; |
3156 | int i, size, error; | |
1da177e4 LT |
3157 | |
3158 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3159 | if (error) | |
3160 | return error; | |
3161 | ||
54168ed7 | 3162 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3163 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3164 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3165 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3166 | if (!mp_ioapic_data[i]) { |
3167 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3168 | continue; | |
3169 | } | |
1da177e4 | 3170 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3171 | dev->id = i; |
1da177e4 LT |
3172 | dev->cls = &ioapic_sysdev_class; |
3173 | error = sysdev_register(dev); | |
3174 | if (error) { | |
3175 | kfree(mp_ioapic_data[i]); | |
3176 | mp_ioapic_data[i] = NULL; | |
3177 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3178 | continue; | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | return 0; | |
3183 | } | |
3184 | ||
3185 | device_initcall(ioapic_init_sysfs); | |
3186 | ||
3fc471ed | 3187 | /* |
95d77884 | 3188 | * Dynamic irq allocate and deallocation |
3fc471ed | 3189 | */ |
d047f53a | 3190 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3191 | { |
ace80ab7 | 3192 | /* Allocate an unused irq */ |
54168ed7 IM |
3193 | unsigned int irq; |
3194 | unsigned int new; | |
3fc471ed | 3195 | unsigned long flags; |
0b8f1efa | 3196 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3197 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3198 | |
3199 | irq = 0; | |
abcaa2b8 YL |
3200 | if (irq_want < nr_irqs_gsi) |
3201 | irq_want = nr_irqs_gsi; | |
3202 | ||
ace80ab7 | 3203 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3204 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3205 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3206 | if (!desc_new) { |
3207 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3208 | continue; |
0b8f1efa YL |
3209 | } |
3210 | cfg_new = desc_new->chip_data; | |
3211 | ||
3212 | if (cfg_new->vector != 0) | |
ace80ab7 | 3213 | continue; |
d047f53a | 3214 | |
15e957d0 | 3215 | desc_new = move_irq_desc(desc_new, node); |
37ef2a30 | 3216 | cfg_new = desc_new->chip_data; |
d047f53a | 3217 | |
fe402e1f | 3218 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3219 | irq = new; |
3220 | break; | |
3221 | } | |
3222 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3223 | |
199751d7 | 3224 | if (irq > 0) { |
3fc471ed | 3225 | dynamic_irq_init(irq); |
0b8f1efa YL |
3226 | /* restore it, in case dynamic_irq_init clear it */ |
3227 | if (desc_new) | |
3228 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3229 | } |
3230 | return irq; | |
3231 | } | |
3232 | ||
199751d7 YL |
3233 | int create_irq(void) |
3234 | { | |
d047f53a | 3235 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3236 | unsigned int irq_want; |
54168ed7 IM |
3237 | int irq; |
3238 | ||
be5d5350 | 3239 | irq_want = nr_irqs_gsi; |
d047f53a | 3240 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3241 | |
3242 | if (irq == 0) | |
3243 | irq = -1; | |
3244 | ||
3245 | return irq; | |
199751d7 YL |
3246 | } |
3247 | ||
3fc471ed EB |
3248 | void destroy_irq(unsigned int irq) |
3249 | { | |
3250 | unsigned long flags; | |
0b8f1efa YL |
3251 | struct irq_cfg *cfg; |
3252 | struct irq_desc *desc; | |
3fc471ed | 3253 | |
0b8f1efa YL |
3254 | /* store it, in case dynamic_irq_cleanup clear it */ |
3255 | desc = irq_to_desc(irq); | |
3256 | cfg = desc->chip_data; | |
3fc471ed | 3257 | dynamic_irq_cleanup(irq); |
0b8f1efa | 3258 | /* connect back irq_cfg */ |
25f6e89b | 3259 | desc->chip_data = cfg; |
3fc471ed | 3260 | |
54168ed7 | 3261 | free_irte(irq); |
3fc471ed | 3262 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3263 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3264 | spin_unlock_irqrestore(&vector_lock, flags); |
3265 | } | |
3fc471ed | 3266 | |
2d3fcc1c | 3267 | /* |
27b46d76 | 3268 | * MSI message composition |
2d3fcc1c EB |
3269 | */ |
3270 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3271 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3272 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3273 | { |
497c9a19 YL |
3274 | struct irq_cfg *cfg; |
3275 | int err; | |
2d3fcc1c EB |
3276 | unsigned dest; |
3277 | ||
f1182638 JB |
3278 | if (disable_apic) |
3279 | return -ENXIO; | |
3280 | ||
3145e941 | 3281 | cfg = irq_cfg(irq); |
fe402e1f | 3282 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3283 | if (err) |
3284 | return err; | |
2d3fcc1c | 3285 | |
debccb3e | 3286 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3287 | |
54168ed7 IM |
3288 | if (irq_remapped(irq)) { |
3289 | struct irte irte; | |
3290 | int ir_index; | |
3291 | u16 sub_handle; | |
3292 | ||
3293 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3294 | BUG_ON(ir_index == -1); | |
3295 | ||
3296 | memset (&irte, 0, sizeof(irte)); | |
3297 | ||
3298 | irte.present = 1; | |
9b5bc8dc | 3299 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3300 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3301 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3302 | irte.vector = cfg->vector; |
3303 | irte.dest_id = IRTE_DEST(dest); | |
3304 | ||
f007e99c | 3305 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3306 | if (pdev) |
3307 | set_msi_sid(&irte, pdev); | |
3308 | else | |
3309 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3310 | |
54168ed7 IM |
3311 | modify_irte(irq, &irte); |
3312 | ||
3313 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3314 | msg->data = sub_handle; | |
3315 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3316 | MSI_ADDR_IR_SHV | | |
3317 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3318 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3319 | } else { |
9d783ba0 SS |
3320 | if (x2apic_enabled()) |
3321 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3322 | MSI_ADDR_EXT_DEST_ID(dest); | |
3323 | else | |
3324 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3325 | ||
54168ed7 IM |
3326 | msg->address_lo = |
3327 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3328 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3329 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3330 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3331 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3332 | MSI_ADDR_REDIRECTION_CPU: |
3333 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3334 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3335 | |
54168ed7 IM |
3336 | msg->data = |
3337 | MSI_DATA_TRIGGER_EDGE | | |
3338 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3339 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3340 | MSI_DATA_DELIVERY_FIXED: |
3341 | MSI_DATA_DELIVERY_LOWPRI) | | |
3342 | MSI_DATA_VECTOR(cfg->vector); | |
3343 | } | |
497c9a19 | 3344 | return err; |
2d3fcc1c EB |
3345 | } |
3346 | ||
3b7d1921 | 3347 | #ifdef CONFIG_SMP |
d5dedd45 | 3348 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3349 | { |
3145e941 | 3350 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3351 | struct irq_cfg *cfg; |
3b7d1921 EB |
3352 | struct msi_msg msg; |
3353 | unsigned int dest; | |
3b7d1921 | 3354 | |
18374d89 | 3355 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3356 | return -1; |
2d3fcc1c | 3357 | |
3145e941 | 3358 | cfg = desc->chip_data; |
2d3fcc1c | 3359 | |
3145e941 | 3360 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3361 | |
3362 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3363 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3364 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3365 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3366 | ||
3145e941 | 3367 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3368 | |
3369 | return 0; | |
2d3fcc1c | 3370 | } |
54168ed7 IM |
3371 | #ifdef CONFIG_INTR_REMAP |
3372 | /* | |
3373 | * Migrate the MSI irq to another cpumask. This migration is | |
3374 | * done in the process context using interrupt-remapping hardware. | |
3375 | */ | |
d5dedd45 | 3376 | static int |
e7986739 | 3377 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3378 | { |
3145e941 | 3379 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3380 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3381 | unsigned int dest; |
54168ed7 | 3382 | struct irte irte; |
54168ed7 IM |
3383 | |
3384 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3385 | return -1; |
54168ed7 | 3386 | |
18374d89 | 3387 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3388 | return -1; |
54168ed7 | 3389 | |
54168ed7 IM |
3390 | irte.vector = cfg->vector; |
3391 | irte.dest_id = IRTE_DEST(dest); | |
3392 | ||
3393 | /* | |
3394 | * atomically update the IRTE with the new destination and vector. | |
3395 | */ | |
3396 | modify_irte(irq, &irte); | |
3397 | ||
3398 | /* | |
3399 | * After this point, all the interrupts will start arriving | |
3400 | * at the new destination. So, time to cleanup the previous | |
3401 | * vector allocation. | |
3402 | */ | |
22f65d31 MT |
3403 | if (cfg->move_in_progress) |
3404 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3405 | |
3406 | return 0; | |
54168ed7 | 3407 | } |
3145e941 | 3408 | |
54168ed7 | 3409 | #endif |
3b7d1921 | 3410 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3411 | |
3b7d1921 EB |
3412 | /* |
3413 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3414 | * which implement the MSI or MSI-X Capability Structure. | |
3415 | */ | |
3416 | static struct irq_chip msi_chip = { | |
3417 | .name = "PCI-MSI", | |
3418 | .unmask = unmask_msi_irq, | |
3419 | .mask = mask_msi_irq, | |
1d025192 | 3420 | .ack = ack_apic_edge, |
3b7d1921 EB |
3421 | #ifdef CONFIG_SMP |
3422 | .set_affinity = set_msi_irq_affinity, | |
3423 | #endif | |
3424 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3425 | }; |
3426 | ||
54168ed7 IM |
3427 | static struct irq_chip msi_ir_chip = { |
3428 | .name = "IR-PCI-MSI", | |
3429 | .unmask = unmask_msi_irq, | |
3430 | .mask = mask_msi_irq, | |
a1e38ca5 | 3431 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3432 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3433 | #ifdef CONFIG_SMP |
3434 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3435 | #endif |
54168ed7 IM |
3436 | #endif |
3437 | .retrigger = ioapic_retrigger_irq, | |
3438 | }; | |
3439 | ||
3440 | /* | |
3441 | * Map the PCI dev to the corresponding remapping hardware unit | |
3442 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3443 | * in it. | |
3444 | */ | |
3445 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3446 | { | |
3447 | struct intel_iommu *iommu; | |
3448 | int index; | |
3449 | ||
3450 | iommu = map_dev_to_ir(dev); | |
3451 | if (!iommu) { | |
3452 | printk(KERN_ERR | |
3453 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3454 | return -ENOENT; | |
3455 | } | |
3456 | ||
3457 | index = alloc_irte(iommu, irq, nvec); | |
3458 | if (index < 0) { | |
3459 | printk(KERN_ERR | |
3460 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3461 | pci_name(dev)); |
54168ed7 IM |
3462 | return -ENOSPC; |
3463 | } | |
3464 | return index; | |
3465 | } | |
1d025192 | 3466 | |
3145e941 | 3467 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3468 | { |
3469 | int ret; | |
3470 | struct msi_msg msg; | |
3471 | ||
c8bc6f3c | 3472 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3473 | if (ret < 0) |
3474 | return ret; | |
3475 | ||
3145e941 | 3476 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3477 | write_msi_msg(irq, &msg); |
3478 | ||
54168ed7 IM |
3479 | if (irq_remapped(irq)) { |
3480 | struct irq_desc *desc = irq_to_desc(irq); | |
3481 | /* | |
3482 | * irq migration in process context | |
3483 | */ | |
3484 | desc->status |= IRQ_MOVE_PCNTXT; | |
3485 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3486 | } else | |
54168ed7 | 3487 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3488 | |
c81bba49 YL |
3489 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3490 | ||
1d025192 YL |
3491 | return 0; |
3492 | } | |
3493 | ||
047c8fdb YL |
3494 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3495 | { | |
54168ed7 IM |
3496 | unsigned int irq; |
3497 | int ret, sub_handle; | |
0b8f1efa | 3498 | struct msi_desc *msidesc; |
54168ed7 | 3499 | unsigned int irq_want; |
1cc18521 | 3500 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3501 | int index = 0; |
d047f53a | 3502 | int node; |
54168ed7 | 3503 | |
1c8d7b0a MW |
3504 | /* x86 doesn't support multiple MSI yet */ |
3505 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3506 | return 1; | |
3507 | ||
d047f53a | 3508 | node = dev_to_node(&dev->dev); |
be5d5350 | 3509 | irq_want = nr_irqs_gsi; |
54168ed7 | 3510 | sub_handle = 0; |
0b8f1efa | 3511 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3512 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3513 | if (irq == 0) |
3514 | return -1; | |
f1ee5548 | 3515 | irq_want = irq + 1; |
54168ed7 IM |
3516 | if (!intr_remapping_enabled) |
3517 | goto no_ir; | |
3518 | ||
3519 | if (!sub_handle) { | |
3520 | /* | |
3521 | * allocate the consecutive block of IRTE's | |
3522 | * for 'nvec' | |
3523 | */ | |
3524 | index = msi_alloc_irte(dev, irq, nvec); | |
3525 | if (index < 0) { | |
3526 | ret = index; | |
3527 | goto error; | |
3528 | } | |
3529 | } else { | |
3530 | iommu = map_dev_to_ir(dev); | |
3531 | if (!iommu) { | |
3532 | ret = -ENOENT; | |
3533 | goto error; | |
3534 | } | |
3535 | /* | |
3536 | * setup the mapping between the irq and the IRTE | |
3537 | * base index, the sub_handle pointing to the | |
3538 | * appropriate interrupt remap table entry. | |
3539 | */ | |
3540 | set_irte_irq(irq, iommu, index, sub_handle); | |
3541 | } | |
3542 | no_ir: | |
0b8f1efa | 3543 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3544 | if (ret < 0) |
3545 | goto error; | |
3546 | sub_handle++; | |
3547 | } | |
3548 | return 0; | |
047c8fdb YL |
3549 | |
3550 | error: | |
54168ed7 IM |
3551 | destroy_irq(irq); |
3552 | return ret; | |
047c8fdb YL |
3553 | } |
3554 | ||
3b7d1921 EB |
3555 | void arch_teardown_msi_irq(unsigned int irq) |
3556 | { | |
f7feaca7 | 3557 | destroy_irq(irq); |
3b7d1921 EB |
3558 | } |
3559 | ||
9d783ba0 | 3560 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3561 | #ifdef CONFIG_SMP |
d5dedd45 | 3562 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3563 | { |
3145e941 | 3564 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3565 | struct irq_cfg *cfg; |
3566 | struct msi_msg msg; | |
3567 | unsigned int dest; | |
54168ed7 | 3568 | |
18374d89 | 3569 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3570 | return -1; |
54168ed7 | 3571 | |
3145e941 | 3572 | cfg = desc->chip_data; |
54168ed7 IM |
3573 | |
3574 | dmar_msi_read(irq, &msg); | |
3575 | ||
3576 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3577 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3578 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3579 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3580 | ||
3581 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3582 | |
3583 | return 0; | |
54168ed7 | 3584 | } |
3145e941 | 3585 | |
54168ed7 IM |
3586 | #endif /* CONFIG_SMP */ |
3587 | ||
8f7007aa | 3588 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3589 | .name = "DMAR_MSI", |
3590 | .unmask = dmar_msi_unmask, | |
3591 | .mask = dmar_msi_mask, | |
3592 | .ack = ack_apic_edge, | |
3593 | #ifdef CONFIG_SMP | |
3594 | .set_affinity = dmar_msi_set_affinity, | |
3595 | #endif | |
3596 | .retrigger = ioapic_retrigger_irq, | |
3597 | }; | |
3598 | ||
3599 | int arch_setup_dmar_msi(unsigned int irq) | |
3600 | { | |
3601 | int ret; | |
3602 | struct msi_msg msg; | |
2d3fcc1c | 3603 | |
c8bc6f3c | 3604 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3605 | if (ret < 0) |
3606 | return ret; | |
3607 | dmar_msi_write(irq, &msg); | |
3608 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3609 | "edge"); | |
3610 | return 0; | |
3611 | } | |
3612 | #endif | |
3613 | ||
58ac1e76 | 3614 | #ifdef CONFIG_HPET_TIMER |
3615 | ||
3616 | #ifdef CONFIG_SMP | |
d5dedd45 | 3617 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3618 | { |
3145e941 | 3619 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3620 | struct irq_cfg *cfg; |
58ac1e76 | 3621 | struct msi_msg msg; |
3622 | unsigned int dest; | |
58ac1e76 | 3623 | |
18374d89 | 3624 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3625 | return -1; |
58ac1e76 | 3626 | |
3145e941 | 3627 | cfg = desc->chip_data; |
58ac1e76 | 3628 | |
3629 | hpet_msi_read(irq, &msg); | |
3630 | ||
3631 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3632 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3633 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3634 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3635 | ||
3636 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3637 | |
3638 | return 0; | |
58ac1e76 | 3639 | } |
3145e941 | 3640 | |
58ac1e76 | 3641 | #endif /* CONFIG_SMP */ |
3642 | ||
c8bc6f3c SS |
3643 | static struct irq_chip ir_hpet_msi_type = { |
3644 | .name = "IR-HPET_MSI", | |
3645 | .unmask = hpet_msi_unmask, | |
3646 | .mask = hpet_msi_mask, | |
3647 | #ifdef CONFIG_INTR_REMAP | |
3648 | .ack = ir_ack_apic_edge, | |
3649 | #ifdef CONFIG_SMP | |
3650 | .set_affinity = ir_set_msi_irq_affinity, | |
3651 | #endif | |
3652 | #endif | |
3653 | .retrigger = ioapic_retrigger_irq, | |
3654 | }; | |
3655 | ||
1cc18521 | 3656 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3657 | .name = "HPET_MSI", |
3658 | .unmask = hpet_msi_unmask, | |
3659 | .mask = hpet_msi_mask, | |
3660 | .ack = ack_apic_edge, | |
3661 | #ifdef CONFIG_SMP | |
3662 | .set_affinity = hpet_msi_set_affinity, | |
3663 | #endif | |
3664 | .retrigger = ioapic_retrigger_irq, | |
3665 | }; | |
3666 | ||
c8bc6f3c | 3667 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3668 | { |
3669 | int ret; | |
3670 | struct msi_msg msg; | |
6ec3cfec | 3671 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3672 | |
c8bc6f3c SS |
3673 | if (intr_remapping_enabled) { |
3674 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3675 | int index; | |
3676 | ||
3677 | if (!iommu) | |
3678 | return -1; | |
3679 | ||
3680 | index = alloc_irte(iommu, irq, 1); | |
3681 | if (index < 0) | |
3682 | return -1; | |
3683 | } | |
3684 | ||
3685 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3686 | if (ret < 0) |
3687 | return ret; | |
3688 | ||
3689 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3690 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3691 | if (irq_remapped(irq)) |
3692 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3693 | handle_edge_irq, "edge"); | |
3694 | else | |
3695 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3696 | handle_edge_irq, "edge"); | |
c81bba49 | 3697 | |
58ac1e76 | 3698 | return 0; |
3699 | } | |
3700 | #endif | |
3701 | ||
54168ed7 | 3702 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3703 | /* |
3704 | * Hypertransport interrupt support | |
3705 | */ | |
3706 | #ifdef CONFIG_HT_IRQ | |
3707 | ||
3708 | #ifdef CONFIG_SMP | |
3709 | ||
497c9a19 | 3710 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3711 | { |
ec68307c EB |
3712 | struct ht_irq_msg msg; |
3713 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3714 | |
497c9a19 | 3715 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3716 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3717 | |
497c9a19 | 3718 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3719 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3720 | |
ec68307c | 3721 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3722 | } |
3723 | ||
d5dedd45 | 3724 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3725 | { |
3145e941 | 3726 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3727 | struct irq_cfg *cfg; |
8b955b0d | 3728 | unsigned int dest; |
8b955b0d | 3729 | |
18374d89 | 3730 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3731 | return -1; |
8b955b0d | 3732 | |
3145e941 | 3733 | cfg = desc->chip_data; |
8b955b0d | 3734 | |
497c9a19 | 3735 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3736 | |
3737 | return 0; | |
8b955b0d | 3738 | } |
3145e941 | 3739 | |
8b955b0d EB |
3740 | #endif |
3741 | ||
c37e108d | 3742 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3743 | .name = "PCI-HT", |
3744 | .mask = mask_ht_irq, | |
3745 | .unmask = unmask_ht_irq, | |
1d025192 | 3746 | .ack = ack_apic_edge, |
8b955b0d EB |
3747 | #ifdef CONFIG_SMP |
3748 | .set_affinity = set_ht_irq_affinity, | |
3749 | #endif | |
3750 | .retrigger = ioapic_retrigger_irq, | |
3751 | }; | |
3752 | ||
3753 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3754 | { | |
497c9a19 YL |
3755 | struct irq_cfg *cfg; |
3756 | int err; | |
8b955b0d | 3757 | |
f1182638 JB |
3758 | if (disable_apic) |
3759 | return -ENXIO; | |
3760 | ||
3145e941 | 3761 | cfg = irq_cfg(irq); |
fe402e1f | 3762 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3763 | if (!err) { |
ec68307c | 3764 | struct ht_irq_msg msg; |
8b955b0d | 3765 | unsigned dest; |
8b955b0d | 3766 | |
debccb3e IM |
3767 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3768 | apic->target_cpus()); | |
8b955b0d | 3769 | |
ec68307c | 3770 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3771 | |
ec68307c EB |
3772 | msg.address_lo = |
3773 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3774 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3775 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3776 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3777 | HT_IRQ_LOW_DM_PHYSICAL : |
3778 | HT_IRQ_LOW_DM_LOGICAL) | | |
3779 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3780 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3781 | HT_IRQ_LOW_MT_FIXED : |
3782 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3783 | HT_IRQ_LOW_IRQ_MASKED; | |
3784 | ||
ec68307c | 3785 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3786 | |
a460e745 IM |
3787 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3788 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3789 | |
3790 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3791 | } |
497c9a19 | 3792 | return err; |
8b955b0d EB |
3793 | } |
3794 | #endif /* CONFIG_HT_IRQ */ | |
3795 | ||
9d6a4d08 YL |
3796 | int __init io_apic_get_redir_entries (int ioapic) |
3797 | { | |
3798 | union IO_APIC_reg_01 reg_01; | |
3799 | unsigned long flags; | |
3800 | ||
3801 | spin_lock_irqsave(&ioapic_lock, flags); | |
3802 | reg_01.raw = io_apic_read(ioapic, 1); | |
3803 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3804 | ||
3805 | return reg_01.bits.entries; | |
3806 | } | |
3807 | ||
be5d5350 | 3808 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3809 | { |
be5d5350 YL |
3810 | int nr = 0; |
3811 | ||
cc6c5006 YL |
3812 | nr = acpi_probe_gsi(); |
3813 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3814 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3815 | } else { |
3816 | /* for acpi=off or acpi is not compiled in */ | |
3817 | int idx; | |
3818 | ||
3819 | nr = 0; | |
3820 | for (idx = 0; idx < nr_ioapics; idx++) | |
3821 | nr += io_apic_get_redir_entries(idx) + 1; | |
3822 | ||
3823 | if (nr > nr_irqs_gsi) | |
3824 | nr_irqs_gsi = nr; | |
3825 | } | |
3826 | ||
3827 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3828 | } |
3829 | ||
4a046d17 YL |
3830 | #ifdef CONFIG_SPARSE_IRQ |
3831 | int __init arch_probe_nr_irqs(void) | |
3832 | { | |
3833 | int nr; | |
3834 | ||
f1ee5548 YL |
3835 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3836 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3837 | |
f1ee5548 YL |
3838 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3839 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3840 | /* | |
3841 | * for MSI and HT dyn irq | |
3842 | */ | |
3843 | nr += nr_irqs_gsi * 16; | |
3844 | #endif | |
3845 | if (nr < nr_irqs) | |
4a046d17 YL |
3846 | nr_irqs = nr; |
3847 | ||
3848 | return 0; | |
3849 | } | |
3850 | #endif | |
3851 | ||
e5198075 YL |
3852 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3853 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3854 | { |
3855 | struct irq_desc *desc; | |
3856 | struct irq_cfg *cfg; | |
3857 | int node; | |
e5198075 YL |
3858 | int ioapic, pin; |
3859 | int trigger, polarity; | |
5ef21837 | 3860 | |
e5198075 | 3861 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3862 | if (!IO_APIC_IRQ(irq)) { |
3863 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3864 | ioapic); | |
3865 | return -EINVAL; | |
3866 | } | |
3867 | ||
3868 | if (dev) | |
3869 | node = dev_to_node(dev); | |
3870 | else | |
3871 | node = cpu_to_node(boot_cpu_id); | |
3872 | ||
3873 | desc = irq_to_desc_alloc_node(irq, node); | |
3874 | if (!desc) { | |
3875 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3876 | return 0; | |
3877 | } | |
3878 | ||
e5198075 YL |
3879 | pin = irq_attr->ioapic_pin; |
3880 | trigger = irq_attr->trigger; | |
3881 | polarity = irq_attr->polarity; | |
3882 | ||
5ef21837 YL |
3883 | /* |
3884 | * IRQs < 16 are already in the irq_2_pin[] map | |
3885 | */ | |
bc07844a | 3886 | if (irq >= nr_legacy_irqs) { |
5ef21837 | 3887 | cfg = desc->chip_data; |
f3d1915a CG |
3888 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3889 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3890 | pin, irq); | |
3891 | return 0; | |
3892 | } | |
5ef21837 YL |
3893 | } |
3894 | ||
e5198075 | 3895 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3896 | |
3897 | return 0; | |
3898 | } | |
3899 | ||
e5198075 YL |
3900 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3901 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3902 | { |
e5198075 | 3903 | int ioapic, pin; |
5ef21837 YL |
3904 | /* |
3905 | * Avoid pin reprogramming. PRTs typically include entries | |
3906 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3907 | * we only program the IOAPIC on the first. | |
3908 | */ | |
e5198075 YL |
3909 | ioapic = irq_attr->ioapic; |
3910 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3911 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3912 | pr_debug("Pin %d-%d already programmed\n", | |
3913 | mp_ioapics[ioapic].apicid, pin); | |
3914 | return 0; | |
3915 | } | |
3916 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3917 | ||
e5198075 | 3918 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3919 | } |
3920 | ||
2a4ab640 FT |
3921 | u8 __init io_apic_unique_id(u8 id) |
3922 | { | |
3923 | #ifdef CONFIG_X86_32 | |
3924 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3925 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3926 | return io_apic_get_unique_id(nr_ioapics, id); | |
3927 | else | |
3928 | return id; | |
3929 | #else | |
3930 | int i; | |
3931 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3932 | |
2a4ab640 FT |
3933 | bitmap_zero(used, 256); |
3934 | for (i = 0; i < nr_ioapics; i++) { | |
3935 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3936 | __set_bit(ia->apicid, used); | |
3937 | } | |
3938 | if (!test_bit(id, used)) | |
3939 | return id; | |
3940 | return find_first_zero_bit(used, 256); | |
3941 | #endif | |
3942 | } | |
1da177e4 | 3943 | |
54168ed7 | 3944 | #ifdef CONFIG_X86_32 |
36062448 | 3945 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3946 | { |
3947 | union IO_APIC_reg_00 reg_00; | |
3948 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3949 | physid_mask_t tmp; | |
3950 | unsigned long flags; | |
3951 | int i = 0; | |
3952 | ||
3953 | /* | |
36062448 PC |
3954 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3955 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3956 | * supports up to 16 on one shared APIC bus. |
36062448 | 3957 | * |
1da177e4 LT |
3958 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3959 | * advantage of new APIC bus architecture. | |
3960 | */ | |
3961 | ||
3962 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3963 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 LT |
3964 | |
3965 | spin_lock_irqsave(&ioapic_lock, flags); | |
3966 | reg_00.raw = io_apic_read(ioapic, 0); | |
3967 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3968 | ||
3969 | if (apic_id >= get_physical_broadcast()) { | |
3970 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3971 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3972 | apic_id = reg_00.bits.ID; | |
3973 | } | |
3974 | ||
3975 | /* | |
36062448 | 3976 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3977 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3978 | */ | |
7abc0753 | 3979 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3980 | |
3981 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3982 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3983 | break; |
3984 | } | |
3985 | ||
3986 | if (i == get_physical_broadcast()) | |
3987 | panic("Max apic_id exceeded!\n"); | |
3988 | ||
3989 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3990 | "trying %d\n", ioapic, apic_id, i); | |
3991 | ||
3992 | apic_id = i; | |
36062448 | 3993 | } |
1da177e4 | 3994 | |
7abc0753 | 3995 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3996 | physids_or(apic_id_map, apic_id_map, tmp); |
3997 | ||
3998 | if (reg_00.bits.ID != apic_id) { | |
3999 | reg_00.bits.ID = apic_id; | |
4000 | ||
4001 | spin_lock_irqsave(&ioapic_lock, flags); | |
4002 | io_apic_write(ioapic, 0, reg_00.raw); | |
4003 | reg_00.raw = io_apic_read(ioapic, 0); | |
4004 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4005 | ||
4006 | /* Sanity check */ | |
6070f9ec AD |
4007 | if (reg_00.bits.ID != apic_id) { |
4008 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4009 | return -1; | |
4010 | } | |
1da177e4 LT |
4011 | } |
4012 | ||
4013 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4014 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4015 | ||
4016 | return apic_id; | |
4017 | } | |
58f892e0 | 4018 | #endif |
1da177e4 | 4019 | |
36062448 | 4020 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4021 | { |
4022 | union IO_APIC_reg_01 reg_01; | |
4023 | unsigned long flags; | |
4024 | ||
4025 | spin_lock_irqsave(&ioapic_lock, flags); | |
4026 | reg_01.raw = io_apic_read(ioapic, 1); | |
4027 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4028 | ||
4029 | return reg_01.bits.version; | |
4030 | } | |
4031 | ||
61fd47e0 SL |
4032 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4033 | { | |
4034 | int i; | |
4035 | ||
4036 | if (skip_ioapic_setup) | |
4037 | return -1; | |
4038 | ||
4039 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
4040 | if (mp_irqs[i].irqtype == mp_INT && |
4041 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
4042 | break; |
4043 | if (i >= mp_irq_entries) | |
4044 | return -1; | |
4045 | ||
4046 | *trigger = irq_trigger(i); | |
4047 | *polarity = irq_polarity(i); | |
4048 | return 0; | |
4049 | } | |
4050 | ||
497c9a19 YL |
4051 | /* |
4052 | * This function currently is only a helper for the i386 smp boot process where | |
4053 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4054 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4055 | */ |
4056 | #ifdef CONFIG_SMP | |
4057 | void __init setup_ioapic_dest(void) | |
4058 | { | |
b9c61b70 | 4059 | int pin, ioapic = 0, irq, irq_entry; |
6c2e9403 | 4060 | struct irq_desc *desc; |
22f65d31 | 4061 | const struct cpumask *mask; |
497c9a19 YL |
4062 | |
4063 | if (skip_ioapic_setup == 1) | |
4064 | return; | |
4065 | ||
b9c61b70 YL |
4066 | #ifdef CONFIG_ACPI |
4067 | if (!acpi_disabled && acpi_ioapic) { | |
4068 | ioapic = mp_find_ioapic(0); | |
4069 | if (ioapic < 0) | |
4070 | ioapic = 0; | |
4071 | } | |
4072 | #endif | |
6c2e9403 | 4073 | |
b9c61b70 YL |
4074 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4075 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4076 | if (irq_entry == -1) | |
4077 | continue; | |
4078 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4079 | |
b9c61b70 | 4080 | desc = irq_to_desc(irq); |
6c2e9403 | 4081 | |
b9c61b70 YL |
4082 | /* |
4083 | * Honour affinities which have been set in early boot | |
4084 | */ | |
4085 | if (desc->status & | |
4086 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4087 | mask = desc->affinity; | |
4088 | else | |
4089 | mask = apic->target_cpus(); | |
497c9a19 | 4090 | |
b9c61b70 YL |
4091 | if (intr_remapping_enabled) |
4092 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4093 | else | |
4094 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4095 | } |
b9c61b70 | 4096 | |
497c9a19 YL |
4097 | } |
4098 | #endif | |
4099 | ||
54168ed7 IM |
4100 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4101 | ||
4102 | static struct resource *ioapic_resources; | |
4103 | ||
ffc43836 | 4104 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4105 | { |
4106 | unsigned long n; | |
4107 | struct resource *res; | |
4108 | char *mem; | |
4109 | int i; | |
4110 | ||
4111 | if (nr_ioapics <= 0) | |
4112 | return NULL; | |
4113 | ||
4114 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4115 | n *= nr_ioapics; | |
4116 | ||
4117 | mem = alloc_bootmem(n); | |
4118 | res = (void *)mem; | |
4119 | ||
ffc43836 | 4120 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4121 | |
ffc43836 CG |
4122 | for (i = 0; i < nr_ioapics; i++) { |
4123 | res[i].name = mem; | |
4124 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4125 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4126 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4127 | } |
4128 | ||
4129 | ioapic_resources = res; | |
4130 | ||
4131 | return res; | |
4132 | } | |
54168ed7 | 4133 | |
f3294a33 YL |
4134 | void __init ioapic_init_mappings(void) |
4135 | { | |
4136 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4137 | struct resource *ioapic_res; |
d6c88a50 | 4138 | int i; |
f3294a33 | 4139 | |
ffc43836 | 4140 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4141 | for (i = 0; i < nr_ioapics; i++) { |
4142 | if (smp_found_config) { | |
b5ba7e6d | 4143 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4144 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4145 | if (!ioapic_phys) { |
4146 | printk(KERN_ERR | |
4147 | "WARNING: bogus zero IO-APIC " | |
4148 | "address found in MPTABLE, " | |
4149 | "disabling IO/APIC support!\n"); | |
4150 | smp_found_config = 0; | |
4151 | skip_ioapic_setup = 1; | |
4152 | goto fake_ioapic_page; | |
4153 | } | |
54168ed7 | 4154 | #endif |
f3294a33 | 4155 | } else { |
54168ed7 | 4156 | #ifdef CONFIG_X86_32 |
f3294a33 | 4157 | fake_ioapic_page: |
54168ed7 | 4158 | #endif |
e79c65a9 | 4159 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4160 | ioapic_phys = __pa(ioapic_phys); |
4161 | } | |
4162 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4163 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4164 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4165 | ioapic_phys); | |
f3294a33 | 4166 | idx++; |
54168ed7 | 4167 | |
ffc43836 | 4168 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4169 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4170 | ioapic_res++; |
f3294a33 YL |
4171 | } |
4172 | } | |
4173 | ||
857fdc53 | 4174 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4175 | { |
4176 | int i; | |
4177 | struct resource *r = ioapic_resources; | |
4178 | ||
4179 | if (!r) { | |
857fdc53 | 4180 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4181 | printk(KERN_ERR |
4182 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4183 | return; |
54168ed7 IM |
4184 | } |
4185 | ||
4186 | for (i = 0; i < nr_ioapics; i++) { | |
4187 | insert_resource(&iomem_resource, r); | |
4188 | r++; | |
4189 | } | |
54168ed7 | 4190 | } |
2a4ab640 FT |
4191 | |
4192 | int mp_find_ioapic(int gsi) | |
4193 | { | |
4194 | int i = 0; | |
4195 | ||
4196 | /* Find the IOAPIC that manages this GSI. */ | |
4197 | for (i = 0; i < nr_ioapics; i++) { | |
4198 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4199 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4200 | return i; | |
4201 | } | |
54168ed7 | 4202 | |
2a4ab640 FT |
4203 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4204 | return -1; | |
4205 | } | |
4206 | ||
4207 | int mp_find_ioapic_pin(int ioapic, int gsi) | |
4208 | { | |
4209 | if (WARN_ON(ioapic == -1)) | |
4210 | return -1; | |
4211 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4212 | return -1; | |
4213 | ||
4214 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4215 | } | |
4216 | ||
4217 | static int bad_ioapic(unsigned long address) | |
4218 | { | |
4219 | if (nr_ioapics >= MAX_IO_APICS) { | |
4220 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4221 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4222 | return 1; | |
4223 | } | |
4224 | if (!address) { | |
4225 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4226 | " found in table, skipping!\n"); | |
4227 | return 1; | |
4228 | } | |
54168ed7 IM |
4229 | return 0; |
4230 | } | |
4231 | ||
2a4ab640 FT |
4232 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4233 | { | |
4234 | int idx = 0; | |
4235 | ||
4236 | if (bad_ioapic(address)) | |
4237 | return; | |
4238 | ||
4239 | idx = nr_ioapics; | |
4240 | ||
4241 | mp_ioapics[idx].type = MP_IOAPIC; | |
4242 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4243 | mp_ioapics[idx].apicaddr = address; | |
4244 | ||
4245 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4246 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4247 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4248 | ||
4249 | /* | |
4250 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4251 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4252 | */ | |
4253 | mp_gsi_routing[idx].gsi_base = gsi_base; | |
4254 | mp_gsi_routing[idx].gsi_end = gsi_base + | |
4255 | io_apic_get_redir_entries(idx); | |
4256 | ||
4257 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4258 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4259 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4260 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4261 | ||
4262 | nr_ioapics++; | |
4263 | } |