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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
32f71aff | 66 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
67 | #define for_each_irq_pin(entry, head) \ |
68 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 TG |
76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
77 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 78 | |
b69c6c3b SS |
79 | static struct ioapic { |
80 | /* | |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_registers; | |
57a6f740 SS |
84 | /* |
85 | * Saved state during suspend/resume, or while enabling intr-remap. | |
86 | */ | |
87 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
88 | /* I/O APIC config */ |
89 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
90 | /* IO APIC gsi routing info */ |
91 | struct mp_ioapic_gsi gsi_config; | |
8f18c971 | 92 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
b69c6c3b | 93 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 94 | |
d5371430 SS |
95 | #define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver |
96 | ||
97 | int mpc_ioapic_id(int id) | |
98 | { | |
99 | return ioapics[id].mp_config.apicid; | |
100 | } | |
101 | ||
102 | unsigned int mpc_ioapic_addr(int id) | |
103 | { | |
104 | return ioapics[id].mp_config.apicaddr; | |
105 | } | |
106 | ||
c040aaeb SS |
107 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id) |
108 | { | |
109 | return &ioapics[id].gsi_config; | |
110 | } | |
9f640ccb | 111 | |
c040aaeb | 112 | int nr_ioapics; |
2a4ab640 | 113 | |
a4384df3 EB |
114 | /* The one past the highest gsi number used */ |
115 | u32 gsi_top; | |
5777372a | 116 | |
584f734d | 117 | /* MP IRQ source entries */ |
c2c21745 | 118 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
119 | |
120 | /* # of MP IRQ source entries */ | |
121 | int mp_irq_entries; | |
122 | ||
bc07844a TG |
123 | /* GSI interrupts */ |
124 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
125 | ||
8732fc4b AS |
126 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
127 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
128 | #endif | |
129 | ||
130 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
131 | ||
efa2559f YL |
132 | int skip_ioapic_setup; |
133 | ||
7167d08e HK |
134 | /** |
135 | * disable_ioapic_support() - disables ioapic support at runtime | |
136 | */ | |
137 | void disable_ioapic_support(void) | |
65a4e574 IM |
138 | { |
139 | #ifdef CONFIG_PCI | |
140 | noioapicquirk = 1; | |
141 | noioapicreroute = -1; | |
142 | #endif | |
143 | skip_ioapic_setup = 1; | |
144 | } | |
145 | ||
54168ed7 | 146 | static int __init parse_noapic(char *str) |
efa2559f YL |
147 | { |
148 | /* disable IO-APIC */ | |
7167d08e | 149 | disable_ioapic_support(); |
efa2559f YL |
150 | return 0; |
151 | } | |
152 | early_param("noapic", parse_noapic); | |
66759a01 | 153 | |
20443598 SAS |
154 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
155 | struct io_apic_irq_attr *attr); | |
710dcda6 | 156 | |
2d8009ba FT |
157 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
158 | void mp_save_irq(struct mpc_intsrc *m) | |
159 | { | |
160 | int i; | |
161 | ||
162 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
163 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
164 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
165 | m->srcbusirq, m->dstapic, m->dstirq); | |
166 | ||
167 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 168 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
169 | return; |
170 | } | |
171 | ||
0e3fa13f | 172 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
173 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
174 | panic("Max # of irq sources exceeded!!\n"); | |
175 | } | |
176 | ||
0b8f1efa YL |
177 | struct irq_pin_list { |
178 | int apic, pin; | |
179 | struct irq_pin_list *next; | |
180 | }; | |
181 | ||
7e495529 | 182 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 183 | { |
2ee39065 | 184 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
185 | } |
186 | ||
2d8009ba | 187 | |
a1420f39 | 188 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 189 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 190 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 191 | #else |
97943390 | 192 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 193 | #endif |
a1420f39 | 194 | |
13a0c3c2 | 195 | int __init arch_early_irq_init(void) |
8f09cd20 | 196 | { |
0b8f1efa | 197 | struct irq_cfg *cfg; |
60c69948 | 198 | int count, node, i; |
d6c88a50 | 199 | |
1f91233c JP |
200 | if (!legacy_pic->nr_legacy_irqs) { |
201 | nr_irqs_gsi = 0; | |
202 | io_apic_irqs = ~0UL; | |
203 | } | |
204 | ||
4c79185c | 205 | for (i = 0; i < nr_ioapics; i++) { |
57a6f740 | 206 | ioapics[i].saved_registers = |
4c79185c | 207 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 208 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 209 | if (!ioapics[i].saved_registers) |
4c79185c SS |
210 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
211 | } | |
212 | ||
0b8f1efa YL |
213 | cfg = irq_cfgx; |
214 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 215 | node = cpu_to_node(0); |
8f09cd20 | 216 | |
fbc6bff0 TG |
217 | /* Make sure the legacy interrupts are marked in the bitmap */ |
218 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
219 | ||
0b8f1efa | 220 | for (i = 0; i < count; i++) { |
2c778651 | 221 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
222 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
223 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
224 | /* |
225 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
226 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
227 | */ | |
54b56170 | 228 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
229 | cfg[i].vector = IRQ0_VECTOR + i; |
230 | cpumask_set_cpu(0, cfg[i].domain); | |
231 | } | |
0b8f1efa | 232 | } |
13a0c3c2 YL |
233 | |
234 | return 0; | |
0b8f1efa | 235 | } |
8f09cd20 | 236 | |
0b8f1efa | 237 | #ifdef CONFIG_SPARSE_IRQ |
48b26501 | 238 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 239 | { |
2c778651 | 240 | return irq_get_chip_data(irq); |
8f09cd20 | 241 | } |
d6c88a50 | 242 | |
f981a3dc | 243 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 244 | { |
0b8f1efa | 245 | struct irq_cfg *cfg; |
0f978f45 | 246 | |
2ee39065 | 247 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
248 | if (!cfg) |
249 | return NULL; | |
2ee39065 | 250 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 251 | goto out_cfg; |
2ee39065 | 252 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 253 | goto out_domain; |
0b8f1efa | 254 | return cfg; |
6e2fff50 TG |
255 | out_domain: |
256 | free_cpumask_var(cfg->domain); | |
257 | out_cfg: | |
258 | kfree(cfg); | |
259 | return NULL; | |
8f09cd20 YL |
260 | } |
261 | ||
f981a3dc | 262 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 263 | { |
fbc6bff0 TG |
264 | if (!cfg) |
265 | return; | |
2c778651 | 266 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
267 | free_cpumask_var(cfg->domain); |
268 | free_cpumask_var(cfg->old_domain); | |
269 | kfree(cfg); | |
270 | } | |
271 | ||
0b8f1efa | 272 | #else |
08c33db6 | 273 | |
9338ad6f | 274 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
275 | { |
276 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 277 | } |
1da177e4 | 278 | |
f981a3dc | 279 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
08c33db6 TG |
280 | { |
281 | return irq_cfgx + irq; | |
282 | } | |
283 | ||
f981a3dc | 284 | static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } |
08c33db6 | 285 | |
0b8f1efa YL |
286 | #endif |
287 | ||
08c33db6 TG |
288 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
289 | { | |
290 | int res = irq_alloc_desc_at(at, node); | |
291 | struct irq_cfg *cfg; | |
292 | ||
293 | if (res < 0) { | |
294 | if (res != -EEXIST) | |
295 | return NULL; | |
2c778651 | 296 | cfg = irq_get_chip_data(at); |
08c33db6 TG |
297 | if (cfg) |
298 | return cfg; | |
299 | } | |
300 | ||
f981a3dc | 301 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 302 | if (cfg) |
2c778651 | 303 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
304 | else |
305 | irq_free_desc(at); | |
306 | return cfg; | |
307 | } | |
308 | ||
309 | static int alloc_irq_from(unsigned int from, int node) | |
310 | { | |
311 | return irq_alloc_desc_from(from, node); | |
312 | } | |
313 | ||
314 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
315 | { | |
f981a3dc | 316 | free_irq_cfg(at, cfg); |
08c33db6 TG |
317 | irq_free_desc(at); |
318 | } | |
319 | ||
130fe05d LT |
320 | struct io_apic { |
321 | unsigned int index; | |
322 | unsigned int unused[3]; | |
323 | unsigned int data; | |
0280f7c4 SS |
324 | unsigned int unused2[11]; |
325 | unsigned int eoi; | |
130fe05d LT |
326 | }; |
327 | ||
328 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
329 | { | |
330 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 331 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
332 | } |
333 | ||
0280f7c4 SS |
334 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
335 | { | |
336 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
337 | writel(vector, &io_apic->eoi); | |
338 | } | |
339 | ||
130fe05d LT |
340 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
341 | { | |
342 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
343 | writel(reg, &io_apic->index); | |
344 | return readl(&io_apic->data); | |
345 | } | |
346 | ||
347 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
348 | { | |
349 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
350 | writel(reg, &io_apic->index); | |
351 | writel(value, &io_apic->data); | |
352 | } | |
353 | ||
354 | /* | |
355 | * Re-write a value: to be used for read-modify-write | |
356 | * cycles where the read already set up the index register. | |
357 | * | |
358 | * Older SiS APIC requires we rewrite the index register | |
359 | */ | |
360 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
361 | { | |
54168ed7 | 362 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
363 | |
364 | if (sis_apic_bug) | |
365 | writel(reg, &io_apic->index); | |
130fe05d LT |
366 | writel(value, &io_apic->data); |
367 | } | |
368 | ||
3145e941 | 369 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
370 | { |
371 | struct irq_pin_list *entry; | |
372 | unsigned long flags; | |
047c8fdb | 373 | |
dade7716 | 374 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 375 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
376 | unsigned int reg; |
377 | int pin; | |
378 | ||
047c8fdb YL |
379 | pin = entry->pin; |
380 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
381 | /* Is the remote IRR bit set? */ | |
382 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 383 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
384 | return true; |
385 | } | |
047c8fdb | 386 | } |
dade7716 | 387 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
388 | |
389 | return false; | |
390 | } | |
047c8fdb | 391 | |
cf4c6a2f AK |
392 | union entry_union { |
393 | struct { u32 w1, w2; }; | |
394 | struct IO_APIC_route_entry entry; | |
395 | }; | |
396 | ||
397 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
398 | { | |
399 | union entry_union eu; | |
400 | unsigned long flags; | |
dade7716 | 401 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
402 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
403 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 404 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
405 | return eu.entry; |
406 | } | |
407 | ||
f9dadfa7 LT |
408 | /* |
409 | * When we write a new IO APIC routing entry, we need to write the high | |
410 | * word first! If the mask bit in the low word is clear, we will enable | |
411 | * the interrupt, and we need to make sure the entry is fully populated | |
412 | * before that happens. | |
413 | */ | |
d15512f4 AK |
414 | static void |
415 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 416 | { |
50a8d4d2 F |
417 | union entry_union eu = {{0, 0}}; |
418 | ||
cf4c6a2f | 419 | eu.entry = e; |
f9dadfa7 LT |
420 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
421 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
422 | } |
423 | ||
1a8ce7ff | 424 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
425 | { |
426 | unsigned long flags; | |
dade7716 | 427 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 428 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 429 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
430 | } |
431 | ||
432 | /* | |
433 | * When we mask an IO APIC routing entry, we need to write the low | |
434 | * word first, in order to set the mask bit before we change the | |
435 | * high bits! | |
436 | */ | |
437 | static void ioapic_mask_entry(int apic, int pin) | |
438 | { | |
439 | unsigned long flags; | |
440 | union entry_union eu = { .entry.mask = 1 }; | |
441 | ||
dade7716 | 442 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
443 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
444 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 445 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
446 | } |
447 | ||
1da177e4 LT |
448 | /* |
449 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
450 | * shared ISA-space IRQs, so we have to support them. We are super | |
451 | * fast in the common case, and fast for shared ISA-space IRQs. | |
452 | */ | |
f3d1915a | 453 | static int |
7e495529 | 454 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 455 | { |
2977fb3f | 456 | struct irq_pin_list **last, *entry; |
0f978f45 | 457 | |
2977fb3f CG |
458 | /* don't allow duplicates */ |
459 | last = &cfg->irq_2_pin; | |
460 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 461 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 462 | return 0; |
2977fb3f | 463 | last = &entry->next; |
1da177e4 | 464 | } |
0f978f45 | 465 | |
7e495529 | 466 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 467 | if (!entry) { |
f3d1915a CG |
468 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
469 | node, apic, pin); | |
470 | return -ENOMEM; | |
a7428cd2 | 471 | } |
1da177e4 LT |
472 | entry->apic = apic; |
473 | entry->pin = pin; | |
875e68ec | 474 | |
2977fb3f | 475 | *last = entry; |
f3d1915a CG |
476 | return 0; |
477 | } | |
478 | ||
479 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
480 | { | |
7e495529 | 481 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 482 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
483 | } |
484 | ||
485 | /* | |
486 | * Reroute an IRQ to a different pin. | |
487 | */ | |
85ac16d0 | 488 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
489 | int oldapic, int oldpin, |
490 | int newapic, int newpin) | |
1da177e4 | 491 | { |
535b6429 | 492 | struct irq_pin_list *entry; |
1da177e4 | 493 | |
2977fb3f | 494 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
495 | if (entry->apic == oldapic && entry->pin == oldpin) { |
496 | entry->apic = newapic; | |
497 | entry->pin = newpin; | |
0f978f45 | 498 | /* every one is different, right? */ |
4eea6fff | 499 | return; |
0f978f45 | 500 | } |
1da177e4 | 501 | } |
0f978f45 | 502 | |
4eea6fff JF |
503 | /* old apic/pin didn't exist, so just add new ones */ |
504 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
505 | } |
506 | ||
c29d9db3 SS |
507 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
508 | int mask_and, int mask_or, | |
509 | void (*final)(struct irq_pin_list *entry)) | |
510 | { | |
511 | unsigned int reg, pin; | |
512 | ||
513 | pin = entry->pin; | |
514 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
515 | reg &= mask_and; | |
516 | reg |= mask_or; | |
517 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
518 | if (final) | |
519 | final(entry); | |
520 | } | |
521 | ||
2f210deb JF |
522 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
523 | int mask_and, int mask_or, | |
524 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 525 | { |
87783be4 | 526 | struct irq_pin_list *entry; |
047c8fdb | 527 | |
c29d9db3 SS |
528 | for_each_irq_pin(entry, cfg->irq_2_pin) |
529 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
530 | } | |
531 | ||
532 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
533 | { | |
534 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
535 | IO_APIC_REDIR_MASKED, NULL); | |
536 | } | |
537 | ||
538 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
539 | { | |
540 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
541 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 542 | } |
047c8fdb | 543 | |
7f3e632f | 544 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 545 | { |
87783be4 CG |
546 | /* |
547 | * Synchronize the IO-APIC and the CPU by doing | |
548 | * a dummy read from the IO-APIC | |
549 | */ | |
550 | struct io_apic __iomem *io_apic; | |
551 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 552 | readl(&io_apic->data); |
1da177e4 LT |
553 | } |
554 | ||
dd5f15e5 | 555 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 556 | { |
dd5f15e5 TG |
557 | unsigned long flags; |
558 | ||
559 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 560 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 561 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 562 | } |
1da177e4 | 563 | |
90297c5f | 564 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 565 | { |
90297c5f | 566 | mask_ioapic(data->chip_data); |
dd5f15e5 | 567 | } |
3145e941 | 568 | |
dd5f15e5 TG |
569 | static void __unmask_ioapic(struct irq_cfg *cfg) |
570 | { | |
571 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
572 | } |
573 | ||
dd5f15e5 | 574 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
575 | { |
576 | unsigned long flags; | |
577 | ||
dade7716 | 578 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 579 | __unmask_ioapic(cfg); |
dade7716 | 580 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
581 | } |
582 | ||
90297c5f | 583 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 584 | { |
90297c5f | 585 | unmask_ioapic(data->chip_data); |
3145e941 YL |
586 | } |
587 | ||
1da177e4 LT |
588 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
589 | { | |
590 | struct IO_APIC_route_entry entry; | |
36062448 | 591 | |
1da177e4 | 592 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 593 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
594 | if (entry.delivery_mode == dest_SMI) |
595 | return; | |
1da177e4 LT |
596 | /* |
597 | * Disable it in the IO-APIC irq-routing table: | |
598 | */ | |
f9dadfa7 | 599 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
600 | } |
601 | ||
54168ed7 | 602 | static void clear_IO_APIC (void) |
1da177e4 LT |
603 | { |
604 | int apic, pin; | |
605 | ||
606 | for (apic = 0; apic < nr_ioapics; apic++) | |
b69c6c3b | 607 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
1da177e4 LT |
608 | clear_IO_APIC_pin(apic, pin); |
609 | } | |
610 | ||
54168ed7 | 611 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
612 | /* |
613 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
614 | * specific CPU-side IRQs. | |
615 | */ | |
616 | ||
617 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
618 | static int pirq_entries[MAX_PIRQS] = { |
619 | [0 ... MAX_PIRQS - 1] = -1 | |
620 | }; | |
1da177e4 | 621 | |
1da177e4 LT |
622 | static int __init ioapic_pirq_setup(char *str) |
623 | { | |
624 | int i, max; | |
625 | int ints[MAX_PIRQS+1]; | |
626 | ||
627 | get_options(str, ARRAY_SIZE(ints), ints); | |
628 | ||
1da177e4 LT |
629 | apic_printk(APIC_VERBOSE, KERN_INFO |
630 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
631 | max = MAX_PIRQS; | |
632 | if (ints[0] < MAX_PIRQS) | |
633 | max = ints[0]; | |
634 | ||
635 | for (i = 0; i < max; i++) { | |
636 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
637 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
638 | /* | |
639 | * PIRQs are mapped upside down, usually. | |
640 | */ | |
641 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
642 | } | |
643 | return 1; | |
644 | } | |
645 | ||
646 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
647 | #endif /* CONFIG_X86_32 */ |
648 | ||
54168ed7 | 649 | /* |
05c3dc2c | 650 | * Saves all the IO-APIC RTE's |
54168ed7 | 651 | */ |
31dce14a | 652 | int save_ioapic_entries(void) |
54168ed7 | 653 | { |
54168ed7 | 654 | int apic, pin; |
31dce14a | 655 | int err = 0; |
54168ed7 IM |
656 | |
657 | for (apic = 0; apic < nr_ioapics; apic++) { | |
57a6f740 | 658 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
659 | err = -ENOMEM; |
660 | continue; | |
661 | } | |
54168ed7 | 662 | |
b69c6c3b | 663 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
57a6f740 | 664 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 665 | ioapic_read_entry(apic, pin); |
b24696bc | 666 | } |
5ffa4eb2 | 667 | |
31dce14a | 668 | return err; |
54168ed7 IM |
669 | } |
670 | ||
b24696bc FY |
671 | /* |
672 | * Mask all IO APIC entries. | |
673 | */ | |
31dce14a | 674 | void mask_ioapic_entries(void) |
05c3dc2c SS |
675 | { |
676 | int apic, pin; | |
677 | ||
678 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2f344d2e | 679 | if (!ioapics[apic].saved_registers) |
31dce14a | 680 | continue; |
b24696bc | 681 | |
b69c6c3b | 682 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
05c3dc2c SS |
683 | struct IO_APIC_route_entry entry; |
684 | ||
57a6f740 | 685 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
686 | if (!entry.mask) { |
687 | entry.mask = 1; | |
688 | ioapic_write_entry(apic, pin, entry); | |
689 | } | |
690 | } | |
691 | } | |
692 | } | |
693 | ||
b24696bc | 694 | /* |
57a6f740 | 695 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 696 | */ |
31dce14a | 697 | int restore_ioapic_entries(void) |
54168ed7 IM |
698 | { |
699 | int apic, pin; | |
700 | ||
5ffa4eb2 | 701 | for (apic = 0; apic < nr_ioapics; apic++) { |
2f344d2e | 702 | if (!ioapics[apic].saved_registers) |
31dce14a | 703 | continue; |
b24696bc | 704 | |
b69c6c3b | 705 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
54168ed7 | 706 | ioapic_write_entry(apic, pin, |
57a6f740 | 707 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 708 | } |
b24696bc | 709 | return 0; |
54168ed7 IM |
710 | } |
711 | ||
1da177e4 LT |
712 | /* |
713 | * Find the IRQ entry number of a certain pin. | |
714 | */ | |
715 | static int find_irq_entry(int apic, int pin, int type) | |
716 | { | |
717 | int i; | |
718 | ||
719 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 720 | if (mp_irqs[i].irqtype == type && |
d5371430 | 721 | (mp_irqs[i].dstapic == mpc_ioapic_id(apic) || |
c2c21745 JSR |
722 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
723 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
724 | return i; |
725 | ||
726 | return -1; | |
727 | } | |
728 | ||
729 | /* | |
730 | * Find the pin to which IRQ[irq] (ISA) is connected | |
731 | */ | |
fcfd636a | 732 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
733 | { |
734 | int i; | |
735 | ||
736 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 737 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 738 | |
d27e2b8e | 739 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
740 | (mp_irqs[i].irqtype == type) && |
741 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 742 | |
c2c21745 | 743 | return mp_irqs[i].dstirq; |
1da177e4 LT |
744 | } |
745 | return -1; | |
746 | } | |
747 | ||
fcfd636a EB |
748 | static int __init find_isa_irq_apic(int irq, int type) |
749 | { | |
750 | int i; | |
751 | ||
752 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 753 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 754 | |
73b2961b | 755 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
756 | (mp_irqs[i].irqtype == type) && |
757 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
758 | break; |
759 | } | |
760 | if (i < mp_irq_entries) { | |
761 | int apic; | |
54168ed7 | 762 | for(apic = 0; apic < nr_ioapics; apic++) { |
d5371430 | 763 | if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic) |
fcfd636a EB |
764 | return apic; |
765 | } | |
766 | } | |
767 | ||
768 | return -1; | |
769 | } | |
770 | ||
c0a282c2 | 771 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
772 | /* |
773 | * EISA Edge/Level control register, ELCR | |
774 | */ | |
775 | static int EISA_ELCR(unsigned int irq) | |
776 | { | |
b81bb373 | 777 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
778 | unsigned int port = 0x4d0 + (irq >> 3); |
779 | return (inb(port) >> (irq & 7)) & 1; | |
780 | } | |
781 | apic_printk(APIC_VERBOSE, KERN_INFO | |
782 | "Broken MPtable reports ISA irq %d\n", irq); | |
783 | return 0; | |
784 | } | |
54168ed7 | 785 | |
c0a282c2 | 786 | #endif |
1da177e4 | 787 | |
6728801d AS |
788 | /* ISA interrupts are always polarity zero edge triggered, |
789 | * when listed as conforming in the MP table. */ | |
790 | ||
791 | #define default_ISA_trigger(idx) (0) | |
792 | #define default_ISA_polarity(idx) (0) | |
793 | ||
1da177e4 LT |
794 | /* EISA interrupts are always polarity zero and can be edge or level |
795 | * trigger depending on the ELCR value. If an interrupt is listed as | |
796 | * EISA conforming in the MP table, that means its trigger type must | |
797 | * be read in from the ELCR */ | |
798 | ||
c2c21745 | 799 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 800 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
801 | |
802 | /* PCI interrupts are always polarity one level triggered, | |
803 | * when listed as conforming in the MP table. */ | |
804 | ||
805 | #define default_PCI_trigger(idx) (1) | |
806 | #define default_PCI_polarity(idx) (1) | |
807 | ||
808 | /* MCA interrupts are always polarity zero level triggered, | |
809 | * when listed as conforming in the MP table. */ | |
810 | ||
811 | #define default_MCA_trigger(idx) (1) | |
6728801d | 812 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 813 | |
b77cf6a8 | 814 | static int irq_polarity(int idx) |
1da177e4 | 815 | { |
c2c21745 | 816 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
817 | int polarity; |
818 | ||
819 | /* | |
820 | * Determine IRQ line polarity (high active or low active): | |
821 | */ | |
c2c21745 | 822 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 823 | { |
54168ed7 IM |
824 | case 0: /* conforms, ie. bus-type dependent polarity */ |
825 | if (test_bit(bus, mp_bus_not_pci)) | |
826 | polarity = default_ISA_polarity(idx); | |
827 | else | |
828 | polarity = default_PCI_polarity(idx); | |
829 | break; | |
830 | case 1: /* high active */ | |
831 | { | |
832 | polarity = 0; | |
833 | break; | |
834 | } | |
835 | case 2: /* reserved */ | |
836 | { | |
837 | printk(KERN_WARNING "broken BIOS!!\n"); | |
838 | polarity = 1; | |
839 | break; | |
840 | } | |
841 | case 3: /* low active */ | |
842 | { | |
843 | polarity = 1; | |
844 | break; | |
845 | } | |
846 | default: /* invalid */ | |
847 | { | |
848 | printk(KERN_WARNING "broken BIOS!!\n"); | |
849 | polarity = 1; | |
850 | break; | |
851 | } | |
1da177e4 LT |
852 | } |
853 | return polarity; | |
854 | } | |
855 | ||
b77cf6a8 | 856 | static int irq_trigger(int idx) |
1da177e4 | 857 | { |
c2c21745 | 858 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
859 | int trigger; |
860 | ||
861 | /* | |
862 | * Determine IRQ trigger mode (edge or level sensitive): | |
863 | */ | |
c2c21745 | 864 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 865 | { |
54168ed7 IM |
866 | case 0: /* conforms, ie. bus-type dependent */ |
867 | if (test_bit(bus, mp_bus_not_pci)) | |
868 | trigger = default_ISA_trigger(idx); | |
869 | else | |
870 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 871 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
872 | switch (mp_bus_id_to_type[bus]) { |
873 | case MP_BUS_ISA: /* ISA pin */ | |
874 | { | |
875 | /* set before the switch */ | |
876 | break; | |
877 | } | |
878 | case MP_BUS_EISA: /* EISA pin */ | |
879 | { | |
880 | trigger = default_EISA_trigger(idx); | |
881 | break; | |
882 | } | |
883 | case MP_BUS_PCI: /* PCI pin */ | |
884 | { | |
885 | /* set before the switch */ | |
886 | break; | |
887 | } | |
888 | case MP_BUS_MCA: /* MCA pin */ | |
889 | { | |
890 | trigger = default_MCA_trigger(idx); | |
891 | break; | |
892 | } | |
893 | default: | |
894 | { | |
895 | printk(KERN_WARNING "broken BIOS!!\n"); | |
896 | trigger = 1; | |
897 | break; | |
898 | } | |
899 | } | |
900 | #endif | |
1da177e4 | 901 | break; |
54168ed7 | 902 | case 1: /* edge */ |
1da177e4 | 903 | { |
54168ed7 | 904 | trigger = 0; |
1da177e4 LT |
905 | break; |
906 | } | |
54168ed7 | 907 | case 2: /* reserved */ |
1da177e4 | 908 | { |
54168ed7 IM |
909 | printk(KERN_WARNING "broken BIOS!!\n"); |
910 | trigger = 1; | |
1da177e4 LT |
911 | break; |
912 | } | |
54168ed7 | 913 | case 3: /* level */ |
1da177e4 | 914 | { |
54168ed7 | 915 | trigger = 1; |
1da177e4 LT |
916 | break; |
917 | } | |
54168ed7 | 918 | default: /* invalid */ |
1da177e4 LT |
919 | { |
920 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 921 | trigger = 0; |
1da177e4 LT |
922 | break; |
923 | } | |
924 | } | |
925 | return trigger; | |
926 | } | |
927 | ||
1da177e4 LT |
928 | static int pin_2_irq(int idx, int apic, int pin) |
929 | { | |
d464207c | 930 | int irq; |
c2c21745 | 931 | int bus = mp_irqs[idx].srcbus; |
c040aaeb | 932 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
1da177e4 LT |
933 | |
934 | /* | |
935 | * Debugging check, we are in big trouble if this message pops up! | |
936 | */ | |
c2c21745 | 937 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
938 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
939 | ||
54168ed7 | 940 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 941 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 942 | } else { |
c040aaeb | 943 | u32 gsi = gsi_cfg->gsi_base + pin; |
988856ee EB |
944 | |
945 | if (gsi >= NR_IRQS_LEGACY) | |
946 | irq = gsi; | |
947 | else | |
a4384df3 | 948 | irq = gsi_top + gsi; |
1da177e4 LT |
949 | } |
950 | ||
54168ed7 | 951 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
952 | /* |
953 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
954 | */ | |
955 | if ((pin >= 16) && (pin <= 23)) { | |
956 | if (pirq_entries[pin-16] != -1) { | |
957 | if (!pirq_entries[pin-16]) { | |
958 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
959 | "disabling PIRQ%d\n", pin-16); | |
960 | } else { | |
961 | irq = pirq_entries[pin-16]; | |
962 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
963 | "using PIRQ%d -> IRQ %d\n", | |
964 | pin-16, irq); | |
965 | } | |
966 | } | |
967 | } | |
54168ed7 IM |
968 | #endif |
969 | ||
1da177e4 LT |
970 | return irq; |
971 | } | |
972 | ||
e20c06fd YL |
973 | /* |
974 | * Find a specific PCI IRQ entry. | |
975 | * Not an __init, possibly needed by modules | |
976 | */ | |
977 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 978 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
979 | { |
980 | int apic, i, best_guess = -1; | |
981 | ||
982 | apic_printk(APIC_DEBUG, | |
983 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
984 | bus, slot, pin); | |
985 | if (test_bit(bus, mp_bus_not_pci)) { | |
986 | apic_printk(APIC_VERBOSE, | |
987 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
988 | return -1; | |
989 | } | |
990 | for (i = 0; i < mp_irq_entries; i++) { | |
991 | int lbus = mp_irqs[i].srcbus; | |
992 | ||
993 | for (apic = 0; apic < nr_ioapics; apic++) | |
d5371430 | 994 | if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic || |
e20c06fd YL |
995 | mp_irqs[i].dstapic == MP_APIC_ALL) |
996 | break; | |
997 | ||
998 | if (!test_bit(lbus, mp_bus_not_pci) && | |
999 | !mp_irqs[i].irqtype && | |
1000 | (bus == lbus) && | |
1001 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1002 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1003 | ||
1004 | if (!(apic || IO_APIC_IRQ(irq))) | |
1005 | continue; | |
1006 | ||
1007 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1008 | set_io_apic_irq_attr(irq_attr, apic, |
1009 | mp_irqs[i].dstirq, | |
1010 | irq_trigger(i), | |
1011 | irq_polarity(i)); | |
e20c06fd YL |
1012 | return irq; |
1013 | } | |
1014 | /* | |
1015 | * Use the first all-but-pin matching entry as a | |
1016 | * best-guess fuzzy result for broken mptables. | |
1017 | */ | |
1018 | if (best_guess < 0) { | |
e5198075 YL |
1019 | set_io_apic_irq_attr(irq_attr, apic, |
1020 | mp_irqs[i].dstirq, | |
1021 | irq_trigger(i), | |
1022 | irq_polarity(i)); | |
e20c06fd YL |
1023 | best_guess = irq; |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | return best_guess; | |
1028 | } | |
1029 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1030 | ||
497c9a19 YL |
1031 | void lock_vector_lock(void) |
1032 | { | |
1033 | /* Used to the online set of cpus does not change | |
1034 | * during assign_irq_vector. | |
1035 | */ | |
dade7716 | 1036 | raw_spin_lock(&vector_lock); |
497c9a19 | 1037 | } |
1da177e4 | 1038 | |
497c9a19 | 1039 | void unlock_vector_lock(void) |
1da177e4 | 1040 | { |
dade7716 | 1041 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1042 | } |
1da177e4 | 1043 | |
e7986739 MT |
1044 | static int |
1045 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1046 | { |
047c8fdb YL |
1047 | /* |
1048 | * NOTE! The local APIC isn't very good at handling | |
1049 | * multiple interrupts at the same interrupt level. | |
1050 | * As the interrupt level is determined by taking the | |
1051 | * vector number and shifting that right by 4, we | |
1052 | * want to spread these out a bit so that they don't | |
1053 | * all fall in the same interrupt level. | |
1054 | * | |
1055 | * Also, we've got to be careful not to trash gate | |
1056 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1057 | */ | |
6579b474 | 1058 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1059 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1060 | unsigned int old_vector; |
22f65d31 MT |
1061 | int cpu, err; |
1062 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1063 | |
23359a88 | 1064 | if (cfg->move_in_progress) |
54168ed7 | 1065 | return -EBUSY; |
0a1ad60d | 1066 | |
22f65d31 MT |
1067 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1068 | return -ENOMEM; | |
ace80ab7 | 1069 | |
54168ed7 IM |
1070 | old_vector = cfg->vector; |
1071 | if (old_vector) { | |
22f65d31 MT |
1072 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1073 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1074 | if (!cpumask_empty(tmp_mask)) { | |
1075 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1076 | return 0; |
22f65d31 | 1077 | } |
54168ed7 | 1078 | } |
497c9a19 | 1079 | |
e7986739 | 1080 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1081 | err = -ENOSPC; |
1082 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1083 | int new_cpu; |
1084 | int vector, offset; | |
497c9a19 | 1085 | |
e2d40b18 | 1086 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1087 | |
54168ed7 IM |
1088 | vector = current_vector; |
1089 | offset = current_offset; | |
497c9a19 | 1090 | next: |
54168ed7 IM |
1091 | vector += 8; |
1092 | if (vector >= first_system_vector) { | |
e7986739 | 1093 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1094 | offset = (offset + 1) % 8; |
6579b474 | 1095 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1096 | } |
1097 | if (unlikely(current_vector == vector)) | |
1098 | continue; | |
b77b881f YL |
1099 | |
1100 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1101 | goto next; |
b77b881f | 1102 | |
22f65d31 | 1103 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1104 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1105 | goto next; | |
1106 | /* Found one! */ | |
1107 | current_vector = vector; | |
1108 | current_offset = offset; | |
1109 | if (old_vector) { | |
1110 | cfg->move_in_progress = 1; | |
22f65d31 | 1111 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1112 | } |
22f65d31 | 1113 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1114 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1115 | cfg->vector = vector; | |
22f65d31 MT |
1116 | cpumask_copy(cfg->domain, tmp_mask); |
1117 | err = 0; | |
1118 | break; | |
54168ed7 | 1119 | } |
22f65d31 MT |
1120 | free_cpumask_var(tmp_mask); |
1121 | return err; | |
497c9a19 YL |
1122 | } |
1123 | ||
9338ad6f | 1124 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1125 | { |
1126 | int err; | |
ace80ab7 | 1127 | unsigned long flags; |
ace80ab7 | 1128 | |
dade7716 | 1129 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1130 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1131 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1132 | return err; |
1133 | } | |
1134 | ||
3145e941 | 1135 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1136 | { |
497c9a19 YL |
1137 | int cpu, vector; |
1138 | ||
497c9a19 YL |
1139 | BUG_ON(!cfg->vector); |
1140 | ||
1141 | vector = cfg->vector; | |
22f65d31 | 1142 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1143 | per_cpu(vector_irq, cpu)[vector] = -1; |
1144 | ||
1145 | cfg->vector = 0; | |
22f65d31 | 1146 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1147 | |
1148 | if (likely(!cfg->move_in_progress)) | |
1149 | return; | |
22f65d31 | 1150 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1151 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1152 | vector++) { | |
1153 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1154 | continue; | |
1155 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1156 | break; | |
1157 | } | |
1158 | } | |
1159 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1160 | } |
1161 | ||
1162 | void __setup_vector_irq(int cpu) | |
1163 | { | |
1164 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1165 | int irq, vector; |
1166 | struct irq_cfg *cfg; | |
1167 | ||
9d133e5d SS |
1168 | /* |
1169 | * vector_lock will make sure that we don't run into irq vector | |
1170 | * assignments that might be happening on another cpu in parallel, | |
1171 | * while we setup our initial vector to irq mappings. | |
1172 | */ | |
dade7716 | 1173 | raw_spin_lock(&vector_lock); |
497c9a19 | 1174 | /* Mark the inuse vectors */ |
ad9f4334 | 1175 | for_each_active_irq(irq) { |
2c778651 | 1176 | cfg = irq_get_chip_data(irq); |
ad9f4334 TG |
1177 | if (!cfg) |
1178 | continue; | |
36e9e1ea SS |
1179 | /* |
1180 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1181 | * will be part of the irq_cfg's domain. | |
1182 | */ | |
1183 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1184 | cpumask_set_cpu(cpu, cfg->domain); | |
1185 | ||
22f65d31 | 1186 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1187 | continue; |
1188 | vector = cfg->vector; | |
497c9a19 YL |
1189 | per_cpu(vector_irq, cpu)[vector] = irq; |
1190 | } | |
1191 | /* Mark the free vectors */ | |
1192 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1193 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1194 | if (irq < 0) | |
1195 | continue; | |
1196 | ||
1197 | cfg = irq_cfg(irq); | |
22f65d31 | 1198 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1199 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1200 | } |
dade7716 | 1201 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1202 | } |
3fde6900 | 1203 | |
f5b9ed7a | 1204 | static struct irq_chip ioapic_chip; |
54168ed7 | 1205 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1206 | |
047c8fdb | 1207 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1208 | static inline int IO_APIC_irq_trigger(int irq) |
1209 | { | |
d6c88a50 | 1210 | int apic, idx, pin; |
1d025192 | 1211 | |
d6c88a50 | 1212 | for (apic = 0; apic < nr_ioapics; apic++) { |
b69c6c3b | 1213 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
d6c88a50 TG |
1214 | idx = find_irq_entry(apic, pin, mp_INT); |
1215 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1216 | return irq_trigger(idx); | |
1217 | } | |
1218 | } | |
1219 | /* | |
54168ed7 IM |
1220 | * nonexistent IRQs are edge default |
1221 | */ | |
d6c88a50 | 1222 | return 0; |
1d025192 | 1223 | } |
047c8fdb YL |
1224 | #else |
1225 | static inline int IO_APIC_irq_trigger(int irq) | |
1226 | { | |
54168ed7 | 1227 | return 1; |
047c8fdb YL |
1228 | } |
1229 | #endif | |
1d025192 | 1230 | |
1a0e62a4 TG |
1231 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1232 | unsigned long trigger) | |
1da177e4 | 1233 | { |
c60eaf25 TG |
1234 | struct irq_chip *chip = &ioapic_chip; |
1235 | irq_flow_handler_t hdl; | |
1236 | bool fasteoi; | |
199751d7 | 1237 | |
6ebcc00e | 1238 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1239 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1240 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1241 | fasteoi = true; |
1242 | } else { | |
60c69948 | 1243 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1244 | fasteoi = false; |
1245 | } | |
047c8fdb | 1246 | |
1a0e62a4 | 1247 | if (irq_remapped(cfg)) { |
60c69948 | 1248 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
1249 | chip = &ir_ioapic_chip; |
1250 | fasteoi = trigger != 0; | |
54168ed7 | 1251 | } |
29b61be6 | 1252 | |
c60eaf25 TG |
1253 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1254 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1255 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1256 | } |
1257 | ||
1a8ce7ff TG |
1258 | static int setup_ioapic_entry(int apic_id, int irq, |
1259 | struct IO_APIC_route_entry *entry, | |
1260 | unsigned int destination, int trigger, | |
1261 | int polarity, int vector, int pin) | |
1da177e4 | 1262 | { |
497c9a19 YL |
1263 | /* |
1264 | * add it to the IO-APIC irq-routing table: | |
1265 | */ | |
1266 | memset(entry,0,sizeof(*entry)); | |
1267 | ||
54168ed7 | 1268 | if (intr_remapping_enabled) { |
c8d46cf0 | 1269 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1270 | struct irte irte; |
1271 | struct IR_IO_APIC_route_entry *ir_entry = | |
1272 | (struct IR_IO_APIC_route_entry *) entry; | |
1273 | int index; | |
1274 | ||
1275 | if (!iommu) | |
c8d46cf0 | 1276 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1277 | |
1278 | index = alloc_irte(iommu, irq, 1); | |
1279 | if (index < 0) | |
c8d46cf0 | 1280 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1281 | |
62a92f4c | 1282 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1283 | |
f007e99c WH |
1284 | /* Set source-id of interrupt request */ |
1285 | set_ioapic_sid(&irte, apic_id); | |
1286 | ||
54168ed7 IM |
1287 | modify_irte(irq, &irte); |
1288 | ||
1289 | ir_entry->index2 = (index >> 15) & 0x1; | |
1290 | ir_entry->zero = 0; | |
1291 | ir_entry->format = 1; | |
1292 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1293 | /* |
1294 | * IO-APIC RTE will be configured with virtual vector. | |
1295 | * irq handler will do the explicit EOI to the io-apic. | |
1296 | */ | |
1297 | ir_entry->vector = pin; | |
3040db92 NC |
1298 | |
1299 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " | |
1300 | "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " | |
1301 | "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " | |
1302 | "Avail:%X Vector:%02X Dest:%08X " | |
1303 | "SID:%04X SQ:%X SVT:%X)\n", | |
1304 | apic_id, irte.present, irte.fpd, irte.dst_mode, | |
1305 | irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, | |
1306 | irte.avail, irte.vector, irte.dest_id, | |
1307 | irte.sid, irte.sq, irte.svt); | |
29b61be6 | 1308 | } else { |
9b5bc8dc IM |
1309 | entry->delivery_mode = apic->irq_delivery_mode; |
1310 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1311 | entry->dest = destination; |
0280f7c4 | 1312 | entry->vector = vector; |
54168ed7 | 1313 | } |
497c9a19 | 1314 | |
54168ed7 | 1315 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1316 | entry->trigger = trigger; |
1317 | entry->polarity = polarity; | |
497c9a19 YL |
1318 | |
1319 | /* Mask level triggered irqs. | |
1320 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1321 | */ | |
1322 | if (trigger) | |
1323 | entry->mask = 1; | |
497c9a19 YL |
1324 | return 0; |
1325 | } | |
1326 | ||
60c69948 TG |
1327 | static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, |
1328 | struct irq_cfg *cfg, int trigger, int polarity) | |
497c9a19 | 1329 | { |
1da177e4 | 1330 | struct IO_APIC_route_entry entry; |
22f65d31 | 1331 | unsigned int dest; |
497c9a19 YL |
1332 | |
1333 | if (!IO_APIC_IRQ(irq)) | |
1334 | return; | |
69c89efb SS |
1335 | /* |
1336 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1337 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1338 | * the cfg->domain. | |
1339 | */ | |
28c6a0ba | 1340 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1341 | apic->vector_allocation_domain(0, cfg->domain); |
1342 | ||
fe402e1f | 1343 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1344 | return; |
1345 | ||
debccb3e | 1346 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1347 | |
1348 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1349 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1350 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
d5371430 | 1351 | apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector, |
7fece832 | 1352 | irq, trigger, polarity, dest); |
497c9a19 YL |
1353 | |
1354 | ||
d5371430 | 1355 | if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry, |
0280f7c4 | 1356 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1357 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
d5371430 | 1358 | mpc_ioapic_id(apic_id), pin); |
3145e941 | 1359 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1360 | return; |
1361 | } | |
1362 | ||
1a0e62a4 | 1363 | ioapic_register_intr(irq, cfg, trigger); |
b81bb373 | 1364 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1365 | legacy_pic->mask(irq); |
497c9a19 | 1366 | |
c8d46cf0 | 1367 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1368 | } |
1369 | ||
c8d6b8fe TG |
1370 | static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) |
1371 | { | |
1372 | if (idx != -1) | |
1373 | return false; | |
1374 | ||
1375 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
d5371430 | 1376 | mpc_ioapic_id(apic_id), pin); |
c8d6b8fe TG |
1377 | return true; |
1378 | } | |
1379 | ||
ed972ccf | 1380 | static void __init __io_apic_setup_irqs(unsigned int apic_id) |
497c9a19 | 1381 | { |
ed972ccf | 1382 | int idx, node = cpu_to_node(0); |
2d57e37d | 1383 | struct io_apic_irq_attr attr; |
ed972ccf | 1384 | unsigned int pin, irq; |
1da177e4 | 1385 | |
b69c6c3b | 1386 | for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) { |
b9c61b70 | 1387 | idx = find_irq_entry(apic_id, pin, mp_INT); |
c8d6b8fe | 1388 | if (io_apic_pin_not_connected(idx, apic_id, pin)) |
b9c61b70 | 1389 | continue; |
33a201fa | 1390 | |
b9c61b70 | 1391 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1392 | |
fad53995 EB |
1393 | if ((apic_id > 0) && (irq > 16)) |
1394 | continue; | |
1395 | ||
b9c61b70 YL |
1396 | /* |
1397 | * Skip the timer IRQ if there's a quirk handler | |
1398 | * installed and if it returns 1: | |
1399 | */ | |
1400 | if (apic->multi_timer_check && | |
2d57e37d | 1401 | apic->multi_timer_check(apic_id, irq)) |
b9c61b70 | 1402 | continue; |
36062448 | 1403 | |
2d57e37d TG |
1404 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1405 | irq_polarity(idx)); | |
fbc6bff0 | 1406 | |
2d57e37d | 1407 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1408 | } |
1da177e4 LT |
1409 | } |
1410 | ||
ed972ccf TG |
1411 | static void __init setup_IO_APIC_irqs(void) |
1412 | { | |
1413 | unsigned int apic_id; | |
1414 | ||
1415 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1416 | ||
1417 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) | |
1418 | __io_apic_setup_irqs(apic_id); | |
1419 | } | |
1420 | ||
18dce6ba YL |
1421 | /* |
1422 | * for the gsit that is not in first ioapic | |
1423 | * but could not use acpi_register_gsi() | |
1424 | * like some special sci in IBM x3330 | |
1425 | */ | |
1426 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1427 | { | |
fbc6bff0 | 1428 | int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1429 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1430 | |
1431 | /* | |
1432 | * Convert 'gsi' to 'ioapic.pin'. | |
1433 | */ | |
1434 | apic_id = mp_find_ioapic(gsi); | |
1435 | if (apic_id < 0) | |
1436 | return; | |
1437 | ||
1438 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1439 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1440 | if (idx == -1) | |
1441 | return; | |
1442 | ||
1443 | irq = pin_2_irq(idx, apic_id, pin); | |
fe6dab4e YL |
1444 | |
1445 | /* Only handle the non legacy irqs on secondary ioapics */ | |
1446 | if (apic_id == 0 || irq < NR_IRQS_LEGACY) | |
18dce6ba | 1447 | return; |
fe6dab4e | 1448 | |
da1ad9d7 TG |
1449 | set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), |
1450 | irq_polarity(idx)); | |
1451 | ||
710dcda6 | 1452 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1453 | } |
1454 | ||
1da177e4 | 1455 | /* |
f7633ce5 | 1456 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1457 | */ |
c8d46cf0 | 1458 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1459 | int vector) |
1da177e4 LT |
1460 | { |
1461 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1462 | |
54168ed7 IM |
1463 | if (intr_remapping_enabled) |
1464 | return; | |
54168ed7 | 1465 | |
36062448 | 1466 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1467 | |
1468 | /* | |
1469 | * We use logical delivery to get the timer IRQ | |
1470 | * to the first CPU. | |
1471 | */ | |
9b5bc8dc | 1472 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1473 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1474 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1475 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1476 | entry.polarity = 0; |
1477 | entry.trigger = 0; | |
1478 | entry.vector = vector; | |
1479 | ||
1480 | /* | |
1481 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1482 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1483 | */ |
2c778651 TG |
1484 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1485 | "edge"); | |
1da177e4 LT |
1486 | |
1487 | /* | |
1488 | * Add it to the IO-APIC irq-routing table: | |
1489 | */ | |
c8d46cf0 | 1490 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1491 | } |
1492 | ||
32f71aff MR |
1493 | |
1494 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1495 | { |
1496 | int apic, i; | |
1497 | union IO_APIC_reg_00 reg_00; | |
1498 | union IO_APIC_reg_01 reg_01; | |
1499 | union IO_APIC_reg_02 reg_02; | |
1500 | union IO_APIC_reg_03 reg_03; | |
1501 | unsigned long flags; | |
0f978f45 | 1502 | struct irq_cfg *cfg; |
8f09cd20 | 1503 | unsigned int irq; |
1da177e4 | 1504 | |
36062448 | 1505 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1506 | for (i = 0; i < nr_ioapics; i++) |
1507 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
d5371430 | 1508 | mpc_ioapic_id(i), ioapics[i].nr_registers); |
1da177e4 LT |
1509 | |
1510 | /* | |
1511 | * We are a bit conservative about what we expect. We have to | |
1512 | * know about every hardware change ASAP. | |
1513 | */ | |
1514 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1515 | ||
1516 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1517 | ||
dade7716 | 1518 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1519 | reg_00.raw = io_apic_read(apic, 0); |
1520 | reg_01.raw = io_apic_read(apic, 1); | |
1521 | if (reg_01.bits.version >= 0x10) | |
1522 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1523 | if (reg_01.bits.version >= 0x20) |
1524 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1525 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1526 | |
54168ed7 | 1527 | printk("\n"); |
d5371430 | 1528 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic)); |
1da177e4 LT |
1529 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1530 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1531 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1532 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1533 | |
54168ed7 | 1534 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1535 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1536 | reg_01.bits.entries); | |
1da177e4 LT |
1537 | |
1538 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1539 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1540 | reg_01.bits.version); | |
1da177e4 LT |
1541 | |
1542 | /* | |
1543 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1544 | * but the value of reg_02 is read as the previous read register | |
1545 | * value, so ignore it if reg_02 == reg_01. | |
1546 | */ | |
1547 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1548 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1549 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1550 | } |
1551 | ||
1552 | /* | |
1553 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1554 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1555 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1556 | */ | |
1557 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1558 | reg_03.raw != reg_01.raw) { | |
1559 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1560 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1561 | } |
1562 | ||
1563 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1564 | ||
d83e94ac | 1565 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1566 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1567 | |
1568 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1569 | struct IO_APIC_route_entry entry; | |
1570 | ||
cf4c6a2f | 1571 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1572 | |
bd6a46e0 | 1573 | printk(KERN_DEBUG " %02x %02X ", |
54168ed7 IM |
1574 | i, |
1575 | entry.dest | |
1576 | ); | |
1da177e4 LT |
1577 | |
1578 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1579 | entry.mask, | |
1580 | entry.trigger, | |
1581 | entry.irr, | |
1582 | entry.polarity, | |
1583 | entry.delivery_status, | |
1584 | entry.dest_mode, | |
1585 | entry.delivery_mode, | |
1586 | entry.vector | |
1587 | ); | |
1588 | } | |
1589 | } | |
1da177e4 | 1590 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1591 | for_each_active_irq(irq) { |
0b8f1efa YL |
1592 | struct irq_pin_list *entry; |
1593 | ||
2c778651 | 1594 | cfg = irq_get_chip_data(irq); |
05e40760 DK |
1595 | if (!cfg) |
1596 | continue; | |
0b8f1efa | 1597 | entry = cfg->irq_2_pin; |
0f978f45 | 1598 | if (!entry) |
1da177e4 | 1599 | continue; |
8f09cd20 | 1600 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1601 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1602 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1603 | printk("\n"); |
1604 | } | |
1605 | ||
1606 | printk(KERN_INFO ".................................... done.\n"); | |
1607 | ||
1608 | return; | |
1609 | } | |
1610 | ||
251e1e44 | 1611 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1612 | { |
251e1e44 | 1613 | int i; |
1da177e4 | 1614 | |
251e1e44 IM |
1615 | printk(KERN_DEBUG); |
1616 | ||
1617 | for (i = 0; i < 8; i++) | |
1618 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1619 | ||
1620 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1621 | } |
1622 | ||
32f71aff | 1623 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1624 | { |
97a52714 | 1625 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1626 | u64 icr; |
1da177e4 | 1627 | |
251e1e44 | 1628 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1629 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1630 | v = apic_read(APIC_ID); |
54168ed7 | 1631 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1632 | v = apic_read(APIC_LVR); |
1633 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1634 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1635 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1636 | |
1637 | v = apic_read(APIC_TASKPRI); | |
1638 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1639 | ||
54168ed7 | 1640 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1641 | if (!APIC_XAPIC(ver)) { |
1642 | v = apic_read(APIC_ARBPRI); | |
1643 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1644 | v & APIC_ARBPRI_MASK); | |
1645 | } | |
1da177e4 LT |
1646 | v = apic_read(APIC_PROCPRI); |
1647 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1648 | } | |
1649 | ||
a11b5abe YL |
1650 | /* |
1651 | * Remote read supported only in the 82489DX and local APIC for | |
1652 | * Pentium processors. | |
1653 | */ | |
1654 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1655 | v = apic_read(APIC_RRR); | |
1656 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1657 | } | |
1658 | ||
1da177e4 LT |
1659 | v = apic_read(APIC_LDR); |
1660 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1661 | if (!x2apic_enabled()) { |
1662 | v = apic_read(APIC_DFR); | |
1663 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1664 | } | |
1da177e4 LT |
1665 | v = apic_read(APIC_SPIV); |
1666 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1667 | ||
1668 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1669 | print_APIC_field(APIC_ISR); |
1da177e4 | 1670 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1671 | print_APIC_field(APIC_TMR); |
1da177e4 | 1672 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1673 | print_APIC_field(APIC_IRR); |
1da177e4 | 1674 | |
54168ed7 IM |
1675 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1676 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1677 | apic_write(APIC_ESR, 0); |
54168ed7 | 1678 | |
1da177e4 LT |
1679 | v = apic_read(APIC_ESR); |
1680 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1681 | } | |
1682 | ||
7ab6af7a | 1683 | icr = apic_icr_read(); |
0c425cec IM |
1684 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1685 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1686 | |
1687 | v = apic_read(APIC_LVTT); | |
1688 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1689 | ||
1690 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1691 | v = apic_read(APIC_LVTPC); | |
1692 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1693 | } | |
1694 | v = apic_read(APIC_LVT0); | |
1695 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1696 | v = apic_read(APIC_LVT1); | |
1697 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1698 | ||
1699 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1700 | v = apic_read(APIC_LVTERR); | |
1701 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1702 | } | |
1703 | ||
1704 | v = apic_read(APIC_TMICT); | |
1705 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1706 | v = apic_read(APIC_TMCCT); | |
1707 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1708 | v = apic_read(APIC_TDCR); | |
1709 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1710 | |
1711 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1712 | v = apic_read(APIC_EFEAT); | |
1713 | maxlvt = (v >> 16) & 0xff; | |
1714 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1715 | v = apic_read(APIC_ECTRL); | |
1716 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1717 | for (i = 0; i < maxlvt; i++) { | |
1718 | v = apic_read(APIC_EILVTn(i)); | |
1719 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1720 | } | |
1721 | } | |
1da177e4 LT |
1722 | printk("\n"); |
1723 | } | |
1724 | ||
2626eb2b | 1725 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1726 | { |
ffd5aae7 YL |
1727 | int cpu; |
1728 | ||
2626eb2b CG |
1729 | if (!maxcpu) |
1730 | return; | |
1731 | ||
ffd5aae7 | 1732 | preempt_disable(); |
2626eb2b CG |
1733 | for_each_online_cpu(cpu) { |
1734 | if (cpu >= maxcpu) | |
1735 | break; | |
ffd5aae7 | 1736 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1737 | } |
ffd5aae7 | 1738 | preempt_enable(); |
1da177e4 LT |
1739 | } |
1740 | ||
32f71aff | 1741 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1742 | { |
1da177e4 LT |
1743 | unsigned int v; |
1744 | unsigned long flags; | |
1745 | ||
b81bb373 | 1746 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1747 | return; |
1748 | ||
1749 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1750 | ||
5619c280 | 1751 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1752 | |
1753 | v = inb(0xa1) << 8 | inb(0x21); | |
1754 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1755 | ||
1756 | v = inb(0xa0) << 8 | inb(0x20); | |
1757 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1758 | ||
54168ed7 IM |
1759 | outb(0x0b,0xa0); |
1760 | outb(0x0b,0x20); | |
1da177e4 | 1761 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1762 | outb(0x0a,0xa0); |
1763 | outb(0x0a,0x20); | |
1da177e4 | 1764 | |
5619c280 | 1765 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1766 | |
1767 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1768 | ||
1769 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1770 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1771 | } | |
1772 | ||
2626eb2b CG |
1773 | static int __initdata show_lapic = 1; |
1774 | static __init int setup_show_lapic(char *arg) | |
1775 | { | |
1776 | int num = -1; | |
1777 | ||
1778 | if (strcmp(arg, "all") == 0) { | |
1779 | show_lapic = CONFIG_NR_CPUS; | |
1780 | } else { | |
1781 | get_option(&arg, &num); | |
1782 | if (num >= 0) | |
1783 | show_lapic = num; | |
1784 | } | |
1785 | ||
1786 | return 1; | |
1787 | } | |
1788 | __setup("show_lapic=", setup_show_lapic); | |
1789 | ||
1790 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1791 | { |
2626eb2b CG |
1792 | if (apic_verbosity == APIC_QUIET) |
1793 | return 0; | |
1794 | ||
32f71aff | 1795 | print_PIC(); |
4797f6b0 YL |
1796 | |
1797 | /* don't print out if apic is not there */ | |
8312136f | 1798 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1799 | return 0; |
1800 | ||
2626eb2b | 1801 | print_local_APICs(show_lapic); |
32f71aff MR |
1802 | print_IO_APIC(); |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
ded1f6ab | 1807 | late_initcall(print_ICs); |
32f71aff | 1808 | |
1da177e4 | 1809 | |
efa2559f YL |
1810 | /* Where if anywhere is the i8259 connect in external int mode */ |
1811 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1812 | ||
54168ed7 | 1813 | void __init enable_IO_APIC(void) |
1da177e4 | 1814 | { |
fcfd636a | 1815 | int i8259_apic, i8259_pin; |
54168ed7 | 1816 | int apic; |
bc07844a | 1817 | |
b81bb373 | 1818 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1819 | return; |
1820 | ||
54168ed7 | 1821 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1822 | int pin; |
1823 | /* See if any of the pins is in ExtINT mode */ | |
b69c6c3b | 1824 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
fcfd636a | 1825 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1826 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1827 | |
fcfd636a EB |
1828 | /* If the interrupt line is enabled and in ExtInt mode |
1829 | * I have found the pin where the i8259 is connected. | |
1830 | */ | |
1831 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1832 | ioapic_i8259.apic = apic; | |
1833 | ioapic_i8259.pin = pin; | |
1834 | goto found_i8259; | |
1835 | } | |
1836 | } | |
1837 | } | |
1838 | found_i8259: | |
1839 | /* Look to see what if the MP table has reported the ExtINT */ | |
1840 | /* If we could not find the appropriate pin by looking at the ioapic | |
1841 | * the i8259 probably is not connected the ioapic but give the | |
1842 | * mptable a chance anyway. | |
1843 | */ | |
1844 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1845 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1846 | /* Trust the MP table if nothing is setup in the hardware */ | |
1847 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1848 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1849 | ioapic_i8259.pin = i8259_pin; | |
1850 | ioapic_i8259.apic = i8259_apic; | |
1851 | } | |
1852 | /* Complain if the MP table and the hardware disagree */ | |
1853 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1854 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1855 | { | |
1856 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1857 | } |
1858 | ||
1859 | /* | |
1860 | * Do not trust the IO-APIC being empty at bootup | |
1861 | */ | |
1862 | clear_IO_APIC(); | |
1863 | } | |
1864 | ||
1865 | /* | |
1866 | * Not an __init, needed by the reboot code | |
1867 | */ | |
1868 | void disable_IO_APIC(void) | |
1869 | { | |
1870 | /* | |
1871 | * Clear the IO-APIC before rebooting: | |
1872 | */ | |
1873 | clear_IO_APIC(); | |
1874 | ||
b81bb373 | 1875 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1876 | return; |
1877 | ||
650927ef | 1878 | /* |
0b968d23 | 1879 | * If the i8259 is routed through an IOAPIC |
650927ef | 1880 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1881 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1882 | * |
1883 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1884 | * as virtual wire B is little complex (need to configure both | |
0d2eb44f | 1885 | * IOAPIC RTE as well as interrupt-remapping table entry). |
7c6d9f97 | 1886 | * As this gets called during crash dump, keep this simple for now. |
650927ef | 1887 | */ |
7c6d9f97 | 1888 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1889 | struct IO_APIC_route_entry entry; |
650927ef EB |
1890 | |
1891 | memset(&entry, 0, sizeof(entry)); | |
1892 | entry.mask = 0; /* Enabled */ | |
1893 | entry.trigger = 0; /* Edge */ | |
1894 | entry.irr = 0; | |
1895 | entry.polarity = 0; /* High */ | |
1896 | entry.delivery_status = 0; | |
1897 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1898 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1899 | entry.vector = 0; |
54168ed7 | 1900 | entry.dest = read_apic_id(); |
650927ef EB |
1901 | |
1902 | /* | |
1903 | * Add it to the IO-APIC irq-routing table: | |
1904 | */ | |
cf4c6a2f | 1905 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1906 | } |
54168ed7 | 1907 | |
7c6d9f97 SS |
1908 | /* |
1909 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1910 | */ | |
8312136f | 1911 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1912 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1913 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1914 | } |
1915 | ||
54168ed7 | 1916 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1917 | /* |
1918 | * function to set the IO-APIC physical IDs based on the | |
1919 | * values stored in the MPC table. | |
1920 | * | |
1921 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1922 | */ | |
a38c5380 | 1923 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1924 | { |
1925 | union IO_APIC_reg_00 reg_00; | |
1926 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1927 | int apic_id; |
1da177e4 LT |
1928 | int i; |
1929 | unsigned char old_id; | |
1930 | unsigned long flags; | |
1931 | ||
1932 | /* | |
1933 | * This is broken; anything with a real cpu count has to | |
1934 | * circumvent this idiocy regardless. | |
1935 | */ | |
7abc0753 | 1936 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1937 | |
1938 | /* | |
1939 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1940 | */ | |
c8d46cf0 | 1941 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
1942 | |
1943 | /* Read the register 0 value */ | |
dade7716 | 1944 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1945 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1946 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1947 | |
d5371430 | 1948 | old_id = mpc_ioapic_id(apic_id); |
1da177e4 | 1949 | |
d5371430 | 1950 | if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) { |
1da177e4 | 1951 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
d5371430 | 1952 | apic_id, mpc_ioapic_id(apic_id)); |
1da177e4 LT |
1953 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1954 | reg_00.bits.ID); | |
d5371430 | 1955 | ioapics[apic_id].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1956 | } |
1957 | ||
1da177e4 LT |
1958 | /* |
1959 | * Sanity check, is the ID really free? Every APIC in a | |
1960 | * system must have a unique ID or we get lots of nice | |
1961 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1962 | */ | |
7abc0753 | 1963 | if (apic->check_apicid_used(&phys_id_present_map, |
d5371430 | 1964 | mpc_ioapic_id(apic_id))) { |
1da177e4 | 1965 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
d5371430 | 1966 | apic_id, mpc_ioapic_id(apic_id)); |
1da177e4 LT |
1967 | for (i = 0; i < get_physical_broadcast(); i++) |
1968 | if (!physid_isset(i, phys_id_present_map)) | |
1969 | break; | |
1970 | if (i >= get_physical_broadcast()) | |
1971 | panic("Max APIC ID exceeded!\n"); | |
1972 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1973 | i); | |
1974 | physid_set(i, phys_id_present_map); | |
d5371430 | 1975 | ioapics[apic_id].mp_config.apicid = i; |
1da177e4 LT |
1976 | } else { |
1977 | physid_mask_t tmp; | |
d5371430 SS |
1978 | apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id), |
1979 | &tmp); | |
1da177e4 LT |
1980 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1981 | "phys_id_present_map\n", | |
d5371430 | 1982 | mpc_ioapic_id(apic_id)); |
1da177e4 LT |
1983 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1984 | } | |
1985 | ||
1da177e4 LT |
1986 | /* |
1987 | * We need to adjust the IRQ routing table | |
1988 | * if the ID changed. | |
1989 | */ | |
d5371430 | 1990 | if (old_id != mpc_ioapic_id(apic_id)) |
1da177e4 | 1991 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1992 | if (mp_irqs[i].dstapic == old_id) |
1993 | mp_irqs[i].dstapic | |
d5371430 | 1994 | = mpc_ioapic_id(apic_id); |
1da177e4 LT |
1995 | |
1996 | /* | |
60d79fd9 YL |
1997 | * Update the ID register according to the right value |
1998 | * from the MPC table if they are different. | |
36062448 | 1999 | */ |
d5371430 | 2000 | if (mpc_ioapic_id(apic_id) == reg_00.bits.ID) |
60d79fd9 YL |
2001 | continue; |
2002 | ||
1da177e4 LT |
2003 | apic_printk(APIC_VERBOSE, KERN_INFO |
2004 | "...changing IO-APIC physical APIC ID to %d ...", | |
d5371430 | 2005 | mpc_ioapic_id(apic_id)); |
1da177e4 | 2006 | |
d5371430 | 2007 | reg_00.bits.ID = mpc_ioapic_id(apic_id); |
dade7716 | 2008 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2009 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2010 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2011 | |
2012 | /* | |
2013 | * Sanity check | |
2014 | */ | |
dade7716 | 2015 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2016 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2017 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
d5371430 | 2018 | if (reg_00.bits.ID != mpc_ioapic_id(apic_id)) |
1da177e4 LT |
2019 | printk("could not set ID!\n"); |
2020 | else | |
2021 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2022 | } | |
2023 | } | |
a38c5380 SAS |
2024 | |
2025 | void __init setup_ioapic_ids_from_mpc(void) | |
2026 | { | |
2027 | ||
2028 | if (acpi_ioapic) | |
2029 | return; | |
2030 | /* | |
2031 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2032 | * no meaning without the serial APIC bus. | |
2033 | */ | |
2034 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2035 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2036 | return; | |
2037 | setup_ioapic_ids_from_mpc_nocheck(); | |
2038 | } | |
54168ed7 | 2039 | #endif |
1da177e4 | 2040 | |
7ce0bcfd | 2041 | int no_timer_check __initdata; |
8542b200 ZA |
2042 | |
2043 | static int __init notimercheck(char *s) | |
2044 | { | |
2045 | no_timer_check = 1; | |
2046 | return 1; | |
2047 | } | |
2048 | __setup("no_timer_check", notimercheck); | |
2049 | ||
1da177e4 LT |
2050 | /* |
2051 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2052 | * about the timer IRQ. We do the following to work around the situation: | |
2053 | * | |
2054 | * - timer IRQ defaults to IO-APIC IRQ | |
2055 | * - if this function detects that timer IRQs are defunct, then we fall | |
2056 | * back to ISA timer IRQs | |
2057 | */ | |
f0a7a5c9 | 2058 | static int __init timer_irq_works(void) |
1da177e4 LT |
2059 | { |
2060 | unsigned long t1 = jiffies; | |
4aae0702 | 2061 | unsigned long flags; |
1da177e4 | 2062 | |
8542b200 ZA |
2063 | if (no_timer_check) |
2064 | return 1; | |
2065 | ||
4aae0702 | 2066 | local_save_flags(flags); |
1da177e4 LT |
2067 | local_irq_enable(); |
2068 | /* Let ten ticks pass... */ | |
2069 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2070 | local_irq_restore(flags); |
1da177e4 LT |
2071 | |
2072 | /* | |
2073 | * Expect a few ticks at least, to be sure some possible | |
2074 | * glue logic does not lock up after one or two first | |
2075 | * ticks in a non-ExtINT mode. Also the local APIC | |
2076 | * might have cached one ExtINT interrupt. Finally, at | |
2077 | * least one tick may be lost due to delays. | |
2078 | */ | |
54168ed7 IM |
2079 | |
2080 | /* jiffies wrap? */ | |
1d16b53e | 2081 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2082 | return 1; |
1da177e4 LT |
2083 | return 0; |
2084 | } | |
2085 | ||
2086 | /* | |
2087 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2088 | * number of pending IRQ events unhandled. These cases are very rare, | |
2089 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2090 | * better to do it this way as thus we do not have to be aware of | |
2091 | * 'pending' interrupts in the IRQ path, except at this point. | |
2092 | */ | |
2093 | /* | |
2094 | * Edge triggered needs to resend any interrupt | |
2095 | * that was delayed but this is now handled in the device | |
2096 | * independent code. | |
2097 | */ | |
2098 | ||
2099 | /* | |
2100 | * Starting up a edge-triggered IO-APIC interrupt is | |
2101 | * nasty - we need to make sure that we get the edge. | |
2102 | * If it is already asserted for some reason, we need | |
2103 | * return 1 to indicate that is was pending. | |
2104 | * | |
2105 | * This is not complete - we should be able to fake | |
2106 | * an edge even if it isn't on the 8259A... | |
2107 | */ | |
54168ed7 | 2108 | |
61a38ce3 | 2109 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2110 | { |
61a38ce3 | 2111 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2112 | unsigned long flags; |
2113 | ||
dade7716 | 2114 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2115 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2116 | legacy_pic->mask(irq); |
b81bb373 | 2117 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2118 | was_pending = 1; |
2119 | } | |
61a38ce3 | 2120 | __unmask_ioapic(data->chip_data); |
dade7716 | 2121 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2122 | |
2123 | return was_pending; | |
2124 | } | |
2125 | ||
90297c5f | 2126 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2127 | { |
90297c5f | 2128 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2129 | unsigned long flags; |
2130 | ||
dade7716 | 2131 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2132 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2133 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2134 | |
2135 | return 1; | |
2136 | } | |
497c9a19 | 2137 | |
54168ed7 IM |
2138 | /* |
2139 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2140 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2141 | * handled with the level-triggered descriptor, but that one has slightly | |
2142 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2143 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2144 | * races. | |
2145 | */ | |
497c9a19 | 2146 | |
54168ed7 | 2147 | #ifdef CONFIG_SMP |
9338ad6f | 2148 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2149 | { |
2150 | cpumask_var_t cleanup_mask; | |
2151 | ||
2152 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2153 | unsigned int i; | |
e85abf8f GH |
2154 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2155 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2156 | } else { | |
2157 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2158 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2159 | free_cpumask_var(cleanup_mask); | |
2160 | } | |
2161 | cfg->move_in_progress = 0; | |
2162 | } | |
2163 | ||
4420471f | 2164 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2165 | { |
2166 | int apic, pin; | |
2167 | struct irq_pin_list *entry; | |
2168 | u8 vector = cfg->vector; | |
2169 | ||
2977fb3f | 2170 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2171 | unsigned int reg; |
2172 | ||
e85abf8f GH |
2173 | apic = entry->apic; |
2174 | pin = entry->pin; | |
2175 | /* | |
2176 | * With interrupt-remapping, destination information comes | |
2177 | * from interrupt-remapping table entry. | |
2178 | */ | |
1a0730d6 | 2179 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2180 | io_apic_write(apic, 0x11 + pin*2, dest); |
2181 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2182 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2183 | reg |= vector; | |
2184 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2185 | } |
2186 | } | |
2187 | ||
2188 | /* | |
f7e909ea | 2189 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2190 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2191 | * leaves data->affinity untouched. |
e85abf8f | 2192 | */ |
f7e909ea TG |
2193 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2194 | unsigned int *dest_id) | |
e85abf8f | 2195 | { |
f7e909ea | 2196 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2197 | |
2198 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2199 | return -1; |
e85abf8f | 2200 | |
f7e909ea | 2201 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2202 | return -1; |
e85abf8f | 2203 | |
f7e909ea | 2204 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2205 | |
f7e909ea | 2206 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2207 | return 0; |
e85abf8f GH |
2208 | } |
2209 | ||
4420471f | 2210 | static int |
f7e909ea TG |
2211 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2212 | bool force) | |
e85abf8f | 2213 | { |
f7e909ea | 2214 | unsigned int dest, irq = data->irq; |
e85abf8f | 2215 | unsigned long flags; |
f7e909ea | 2216 | int ret; |
e85abf8f | 2217 | |
dade7716 | 2218 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2219 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2220 | if (!ret) { |
e85abf8f GH |
2221 | /* Only the high 8 bits are valid. */ |
2222 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2223 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2224 | } |
dade7716 | 2225 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2226 | return ret; |
e85abf8f GH |
2227 | } |
2228 | ||
54168ed7 | 2229 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2230 | |
54168ed7 IM |
2231 | /* |
2232 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2233 | * | |
0280f7c4 SS |
2234 | * For both level and edge triggered, irq migration is a simple atomic |
2235 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2236 | * |
0280f7c4 SS |
2237 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2238 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2239 | * Real vector that is used for interrupting cpu will be coming from | |
2240 | * the interrupt-remapping table entry. | |
54168ed7 | 2241 | */ |
d5dedd45 | 2242 | static int |
f19f5ecc TG |
2243 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2244 | bool force) | |
497c9a19 | 2245 | { |
f19f5ecc TG |
2246 | struct irq_cfg *cfg = data->chip_data; |
2247 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2248 | struct irte irte; |
497c9a19 | 2249 | |
22f65d31 | 2250 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2251 | return -EINVAL; |
497c9a19 | 2252 | |
54168ed7 | 2253 | if (get_irte(irq, &irte)) |
f19f5ecc | 2254 | return -EBUSY; |
497c9a19 | 2255 | |
3145e941 | 2256 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2257 | return -EBUSY; |
54168ed7 | 2258 | |
debccb3e | 2259 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2260 | |
54168ed7 IM |
2261 | irte.vector = cfg->vector; |
2262 | irte.dest_id = IRTE_DEST(dest); | |
2263 | ||
2264 | /* | |
2265 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2266 | */ | |
2267 | modify_irte(irq, &irte); | |
2268 | ||
22f65d31 MT |
2269 | if (cfg->move_in_progress) |
2270 | send_cleanup_vector(cfg); | |
54168ed7 | 2271 | |
f19f5ecc | 2272 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2273 | return 0; |
54168ed7 IM |
2274 | } |
2275 | ||
29b61be6 | 2276 | #else |
f19f5ecc TG |
2277 | static inline int |
2278 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2279 | bool force) | |
29b61be6 | 2280 | { |
d5dedd45 | 2281 | return 0; |
29b61be6 | 2282 | } |
54168ed7 IM |
2283 | #endif |
2284 | ||
2285 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2286 | { | |
2287 | unsigned vector, me; | |
8f2466f4 | 2288 | |
54168ed7 | 2289 | ack_APIC_irq(); |
54168ed7 | 2290 | exit_idle(); |
54168ed7 IM |
2291 | irq_enter(); |
2292 | ||
2293 | me = smp_processor_id(); | |
2294 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2295 | unsigned int irq; | |
68a8ca59 | 2296 | unsigned int irr; |
54168ed7 IM |
2297 | struct irq_desc *desc; |
2298 | struct irq_cfg *cfg; | |
0a3aee0d | 2299 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2300 | |
0b8f1efa YL |
2301 | if (irq == -1) |
2302 | continue; | |
2303 | ||
54168ed7 IM |
2304 | desc = irq_to_desc(irq); |
2305 | if (!desc) | |
2306 | continue; | |
2307 | ||
2308 | cfg = irq_cfg(irq); | |
239007b8 | 2309 | raw_spin_lock(&desc->lock); |
54168ed7 | 2310 | |
7f41c2e1 SS |
2311 | /* |
2312 | * Check if the irq migration is in progress. If so, we | |
2313 | * haven't received the cleanup request yet for this irq. | |
2314 | */ | |
2315 | if (cfg->move_in_progress) | |
2316 | goto unlock; | |
2317 | ||
22f65d31 | 2318 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2319 | goto unlock; |
2320 | ||
68a8ca59 SS |
2321 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2322 | /* | |
2323 | * Check if the vector that needs to be cleanedup is | |
2324 | * registered at the cpu's IRR. If so, then this is not | |
2325 | * the best time to clean it up. Lets clean it up in the | |
2326 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2327 | * to myself. | |
2328 | */ | |
2329 | if (irr & (1 << (vector % 32))) { | |
2330 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2331 | goto unlock; | |
2332 | } | |
0a3aee0d | 2333 | __this_cpu_write(vector_irq[vector], -1); |
54168ed7 | 2334 | unlock: |
239007b8 | 2335 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2336 | } |
2337 | ||
2338 | irq_exit(); | |
2339 | } | |
2340 | ||
dd5f15e5 | 2341 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2342 | { |
a5e74b84 | 2343 | unsigned me; |
54168ed7 | 2344 | |
fcef5911 | 2345 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2346 | return; |
2347 | ||
54168ed7 | 2348 | me = smp_processor_id(); |
10b888d6 | 2349 | |
fcef5911 | 2350 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2351 | send_cleanup_vector(cfg); |
497c9a19 | 2352 | } |
a5e74b84 | 2353 | |
dd5f15e5 | 2354 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2355 | { |
dd5f15e5 | 2356 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2357 | } |
2358 | ||
2359 | void irq_force_complete_move(int irq) | |
2360 | { | |
2c778651 | 2361 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
a5e74b84 | 2362 | |
bbd391a1 PB |
2363 | if (!cfg) |
2364 | return; | |
2365 | ||
dd5f15e5 | 2366 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2367 | } |
497c9a19 | 2368 | #else |
dd5f15e5 | 2369 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2370 | #endif |
3145e941 | 2371 | |
90297c5f | 2372 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2373 | { |
90297c5f | 2374 | irq_complete_move(data->chip_data); |
08221110 | 2375 | irq_move_irq(data); |
1d025192 YL |
2376 | ack_APIC_irq(); |
2377 | } | |
2378 | ||
3eb2cce8 | 2379 | atomic_t irq_mis_count; |
3eb2cce8 | 2380 | |
c29d9db3 SS |
2381 | /* |
2382 | * IO-APIC versions below 0x20 don't support EOI register. | |
2383 | * For the record, here is the information about various versions: | |
2384 | * 0Xh 82489DX | |
2385 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2386 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2387 | * 30h-FFh Reserved | |
2388 | * | |
2389 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2390 | * version as 0x2. This is an error with documentation and these ICH chips | |
2391 | * use io-apic's of version 0x20. | |
2392 | * | |
2393 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2394 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2395 | * mode to edge and then back to level, with RTE being masked during this. | |
2396 | */ | |
dd5f15e5 | 2397 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2398 | { |
2399 | struct irq_pin_list *entry; | |
dd5f15e5 | 2400 | unsigned long flags; |
b3ec0a37 | 2401 | |
dd5f15e5 | 2402 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2403 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
d5371430 | 2404 | if (mpc_ioapic_ver(entry->apic) >= 0x20) { |
c29d9db3 SS |
2405 | /* |
2406 | * Intr-remapping uses pin number as the virtual vector | |
2407 | * in the RTE. Actual vector is programmed in | |
2408 | * intr-remapping table entry. Hence for the io-apic | |
2409 | * EOI we use the pin number. | |
2410 | */ | |
1a0730d6 | 2411 | if (irq_remapped(cfg)) |
c29d9db3 SS |
2412 | io_apic_eoi(entry->apic, entry->pin); |
2413 | else | |
2414 | io_apic_eoi(entry->apic, cfg->vector); | |
2415 | } else { | |
2416 | __mask_and_edge_IO_APIC_irq(entry); | |
2417 | __unmask_and_level_IO_APIC_irq(entry); | |
2418 | } | |
b3ec0a37 | 2419 | } |
dade7716 | 2420 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2421 | } |
2422 | ||
90297c5f | 2423 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2424 | { |
90297c5f TG |
2425 | struct irq_cfg *cfg = data->chip_data; |
2426 | int i, do_unmask_irq = 0, irq = data->irq; | |
3eb2cce8 | 2427 | unsigned long v; |
047c8fdb | 2428 | |
dd5f15e5 | 2429 | irq_complete_move(cfg); |
047c8fdb | 2430 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2431 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2432 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
54168ed7 | 2433 | do_unmask_irq = 1; |
dd5f15e5 | 2434 | mask_ioapic(cfg); |
54168ed7 | 2435 | } |
047c8fdb YL |
2436 | #endif |
2437 | ||
3eb2cce8 | 2438 | /* |
916a0fe7 JF |
2439 | * It appears there is an erratum which affects at least version 0x11 |
2440 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2441 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2442 | * erroneously delivered as edge-triggered one but the respective IRR | |
2443 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2444 | * message but it will never arrive and further interrupts are blocked | |
2445 | * from the source. The exact reason is so far unknown, but the | |
2446 | * phenomenon was observed when two consecutive interrupt requests | |
2447 | * from a given source get delivered to the same CPU and the source is | |
2448 | * temporarily disabled in between. | |
2449 | * | |
2450 | * A workaround is to simulate an EOI message manually. We achieve it | |
2451 | * by setting the trigger mode to edge and then to level when the edge | |
2452 | * trigger mode gets detected in the TMR of a local APIC for a | |
2453 | * level-triggered interrupt. We mask the source for the time of the | |
2454 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2455 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2456 | * |
2457 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2458 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2459 | * destination that is handling the corresponding interrupt. This | |
2460 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2461 | * level-triggered io-apic interrupt will be seen as an edge | |
2462 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2463 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2464 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2465 | * supporting EOI register, we do an explicit EOI to clear the | |
2466 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2467 | * we use the above logic (mask+edge followed by unmask+level) from | |
2468 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2469 | */ |
3145e941 | 2470 | i = cfg->vector; |
3eb2cce8 | 2471 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2472 | |
54168ed7 IM |
2473 | /* |
2474 | * We must acknowledge the irq before we move it or the acknowledge will | |
2475 | * not propagate properly. | |
2476 | */ | |
2477 | ack_APIC_irq(); | |
2478 | ||
1c83995b SS |
2479 | /* |
2480 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2481 | * message via io-apic EOI register write or simulating it using | |
2482 | * mask+edge followed by unnask+level logic) manually when the | |
2483 | * level triggered interrupt is seen as the edge triggered interrupt | |
2484 | * at the cpu. | |
2485 | */ | |
ca64c47c MR |
2486 | if (!(v & (1 << (i & 0x1f)))) { |
2487 | atomic_inc(&irq_mis_count); | |
2488 | ||
dd5f15e5 | 2489 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2490 | } |
2491 | ||
54168ed7 IM |
2492 | /* Now we can move and renable the irq */ |
2493 | if (unlikely(do_unmask_irq)) { | |
2494 | /* Only migrate the irq if the ack has been received. | |
2495 | * | |
2496 | * On rare occasions the broadcast level triggered ack gets | |
2497 | * delayed going to ioapics, and if we reprogram the | |
2498 | * vector while Remote IRR is still set the irq will never | |
2499 | * fire again. | |
2500 | * | |
2501 | * To prevent this scenario we read the Remote IRR bit | |
2502 | * of the ioapic. This has two effects. | |
2503 | * - On any sane system the read of the ioapic will | |
2504 | * flush writes (and acks) going to the ioapic from | |
2505 | * this cpu. | |
2506 | * - We get to see if the ACK has actually been delivered. | |
2507 | * | |
2508 | * Based on failed experiments of reprogramming the | |
2509 | * ioapic entry from outside of irq context starting | |
2510 | * with masking the ioapic entry and then polling until | |
2511 | * Remote IRR was clear before reprogramming the | |
2512 | * ioapic I don't trust the Remote IRR bit to be | |
2513 | * completey accurate. | |
2514 | * | |
2515 | * However there appears to be no other way to plug | |
2516 | * this race, so if the Remote IRR bit is not | |
2517 | * accurate and is causing problems then it is a hardware bug | |
2518 | * and you can go talk to the chipset vendor about it. | |
2519 | */ | |
3145e941 | 2520 | if (!io_apic_level_ack_pending(cfg)) |
08221110 | 2521 | irq_move_masked_irq(data); |
dd5f15e5 | 2522 | unmask_ioapic(cfg); |
54168ed7 | 2523 | } |
3eb2cce8 | 2524 | } |
1d025192 | 2525 | |
d0b03bd1 | 2526 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2527 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2528 | { |
5d0ae2db | 2529 | ack_APIC_irq(); |
d0b03bd1 HW |
2530 | } |
2531 | ||
90297c5f | 2532 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2533 | { |
5d0ae2db | 2534 | ack_APIC_irq(); |
90297c5f | 2535 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2536 | } |
2537 | #endif /* CONFIG_INTR_REMAP */ | |
2538 | ||
f5b9ed7a | 2539 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2540 | .name = "IO-APIC", |
2541 | .irq_startup = startup_ioapic_irq, | |
2542 | .irq_mask = mask_ioapic_irq, | |
2543 | .irq_unmask = unmask_ioapic_irq, | |
2544 | .irq_ack = ack_apic_edge, | |
2545 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2546 | #ifdef CONFIG_SMP |
f7e909ea | 2547 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2548 | #endif |
f7e909ea | 2549 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2550 | }; |
2551 | ||
54168ed7 | 2552 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
f19f5ecc TG |
2553 | .name = "IR-IO-APIC", |
2554 | .irq_startup = startup_ioapic_irq, | |
2555 | .irq_mask = mask_ioapic_irq, | |
2556 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2557 | #ifdef CONFIG_INTR_REMAP |
f19f5ecc TG |
2558 | .irq_ack = ir_ack_apic_edge, |
2559 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2560 | #ifdef CONFIG_SMP |
f19f5ecc | 2561 | .irq_set_affinity = ir_ioapic_set_affinity, |
a1e38ca5 | 2562 | #endif |
54168ed7 | 2563 | #endif |
f19f5ecc | 2564 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2565 | }; |
1da177e4 LT |
2566 | |
2567 | static inline void init_IO_APIC_traps(void) | |
2568 | { | |
da51a821 | 2569 | struct irq_cfg *cfg; |
ad9f4334 | 2570 | unsigned int irq; |
1da177e4 LT |
2571 | |
2572 | /* | |
2573 | * NOTE! The local APIC isn't very good at handling | |
2574 | * multiple interrupts at the same interrupt level. | |
2575 | * As the interrupt level is determined by taking the | |
2576 | * vector number and shifting that right by 4, we | |
2577 | * want to spread these out a bit so that they don't | |
2578 | * all fall in the same interrupt level. | |
2579 | * | |
2580 | * Also, we've got to be careful not to trash gate | |
2581 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2582 | */ | |
ad9f4334 | 2583 | for_each_active_irq(irq) { |
2c778651 | 2584 | cfg = irq_get_chip_data(irq); |
0b8f1efa | 2585 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2586 | /* |
2587 | * Hmm.. We don't have an entry for this, | |
2588 | * so default to an old-fashioned 8259 | |
2589 | * interrupt if we can.. | |
2590 | */ | |
b81bb373 JP |
2591 | if (irq < legacy_pic->nr_legacy_irqs) |
2592 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2593 | else |
1da177e4 | 2594 | /* Strange. Oh, well.. */ |
2c778651 | 2595 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2596 | } |
2597 | } | |
2598 | } | |
2599 | ||
f5b9ed7a IM |
2600 | /* |
2601 | * The local APIC irq-chip implementation: | |
2602 | */ | |
1da177e4 | 2603 | |
90297c5f | 2604 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2605 | { |
2606 | unsigned long v; | |
2607 | ||
2608 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2609 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2610 | } |
2611 | ||
90297c5f | 2612 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2613 | { |
f5b9ed7a | 2614 | unsigned long v; |
1da177e4 | 2615 | |
f5b9ed7a | 2616 | v = apic_read(APIC_LVT0); |
593f4a78 | 2617 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2618 | } |
1da177e4 | 2619 | |
90297c5f | 2620 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2621 | { |
2622 | ack_APIC_irq(); | |
2623 | } | |
2624 | ||
f5b9ed7a | 2625 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2626 | .name = "local-APIC", |
90297c5f TG |
2627 | .irq_mask = mask_lapic_irq, |
2628 | .irq_unmask = unmask_lapic_irq, | |
2629 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2630 | }; |
2631 | ||
60c69948 | 2632 | static void lapic_register_intr(int irq) |
c88ac1df | 2633 | { |
60c69948 | 2634 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2635 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2636 | "edge"); |
c88ac1df MR |
2637 | } |
2638 | ||
1da177e4 LT |
2639 | /* |
2640 | * This looks a bit hackish but it's about the only one way of sending | |
2641 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2642 | * not support the ExtINT mode, unfortunately. We need to send these | |
2643 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2644 | * 8259A interrupt line asserted until INTA. --macro | |
2645 | */ | |
28acf285 | 2646 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2647 | { |
fcfd636a | 2648 | int apic, pin, i; |
1da177e4 LT |
2649 | struct IO_APIC_route_entry entry0, entry1; |
2650 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2651 | |
fcfd636a | 2652 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2653 | if (pin == -1) { |
2654 | WARN_ON_ONCE(1); | |
2655 | return; | |
2656 | } | |
fcfd636a | 2657 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2658 | if (apic == -1) { |
2659 | WARN_ON_ONCE(1); | |
1da177e4 | 2660 | return; |
956fb531 | 2661 | } |
1da177e4 | 2662 | |
cf4c6a2f | 2663 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2664 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2665 | |
2666 | memset(&entry1, 0, sizeof(entry1)); | |
2667 | ||
2668 | entry1.dest_mode = 0; /* physical delivery */ | |
2669 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2670 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2671 | entry1.delivery_mode = dest_ExtINT; |
2672 | entry1.polarity = entry0.polarity; | |
2673 | entry1.trigger = 0; | |
2674 | entry1.vector = 0; | |
2675 | ||
cf4c6a2f | 2676 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2677 | |
2678 | save_control = CMOS_READ(RTC_CONTROL); | |
2679 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2680 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2681 | RTC_FREQ_SELECT); | |
2682 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2683 | ||
2684 | i = 100; | |
2685 | while (i-- > 0) { | |
2686 | mdelay(10); | |
2687 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2688 | i -= 10; | |
2689 | } | |
2690 | ||
2691 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2692 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2693 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2694 | |
cf4c6a2f | 2695 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2696 | } |
2697 | ||
efa2559f | 2698 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2699 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2700 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2701 | { |
2702 | disable_timer_pin_1 = 1; | |
2703 | return 0; | |
2704 | } | |
54168ed7 | 2705 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2706 | |
2707 | int timer_through_8259 __initdata; | |
2708 | ||
1da177e4 LT |
2709 | /* |
2710 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2711 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2712 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2713 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2714 | * |
2715 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2716 | */ |
8542b200 | 2717 | static inline void __init check_timer(void) |
1da177e4 | 2718 | { |
2c778651 | 2719 | struct irq_cfg *cfg = irq_get_chip_data(0); |
f6e9456c | 2720 | int node = cpu_to_node(0); |
fcfd636a | 2721 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2722 | unsigned long flags; |
047c8fdb | 2723 | int no_pin1 = 0; |
4aae0702 IM |
2724 | |
2725 | local_irq_save(flags); | |
d4d25dec | 2726 | |
1da177e4 LT |
2727 | /* |
2728 | * get/set the timer IRQ vector: | |
2729 | */ | |
4305df94 | 2730 | legacy_pic->mask(0); |
fe402e1f | 2731 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2732 | |
2733 | /* | |
d11d5794 MR |
2734 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2735 | * wire has to be disabled in the local APIC. Also | |
2736 | * timer interrupts need to be acknowledged manually in | |
2737 | * the 8259A for the i82489DX when using the NMI | |
2738 | * watchdog as that APIC treats NMIs as level-triggered. | |
2739 | * The AEOI mode will finish them in the 8259A | |
2740 | * automatically. | |
1da177e4 | 2741 | */ |
593f4a78 | 2742 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2743 | legacy_pic->init(1); |
1da177e4 | 2744 | |
fcfd636a EB |
2745 | pin1 = find_isa_irq_pin(0, mp_INT); |
2746 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2747 | pin2 = ioapic_i8259.pin; | |
2748 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2749 | |
49a66a0b MR |
2750 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2751 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2752 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2753 | |
691874fa MR |
2754 | /* |
2755 | * Some BIOS writers are clueless and report the ExtINTA | |
2756 | * I/O APIC input from the cascaded 8259A as the timer | |
2757 | * interrupt input. So just in case, if only one pin | |
2758 | * was found above, try it both directly and through the | |
2759 | * 8259A. | |
2760 | */ | |
2761 | if (pin1 == -1) { | |
54168ed7 IM |
2762 | if (intr_remapping_enabled) |
2763 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2764 | pin1 = pin2; |
2765 | apic1 = apic2; | |
2766 | no_pin1 = 1; | |
2767 | } else if (pin2 == -1) { | |
2768 | pin2 = pin1; | |
2769 | apic2 = apic1; | |
2770 | } | |
2771 | ||
1da177e4 LT |
2772 | if (pin1 != -1) { |
2773 | /* | |
2774 | * Ok, does IRQ0 through the IOAPIC work? | |
2775 | */ | |
691874fa | 2776 | if (no_pin1) { |
85ac16d0 | 2777 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2778 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2779 | } else { |
60c69948 | 2780 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2781 | * leave it unmasked. |
2782 | * so only need to unmask if it is level-trigger | |
2783 | * do we really have level trigger timer? | |
2784 | */ | |
2785 | int idx; | |
2786 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2787 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2788 | unmask_ioapic(cfg); |
691874fa | 2789 | } |
1da177e4 | 2790 | if (timer_irq_works()) { |
66759a01 CE |
2791 | if (disable_timer_pin_1 > 0) |
2792 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2793 | goto out; |
1da177e4 | 2794 | } |
54168ed7 IM |
2795 | if (intr_remapping_enabled) |
2796 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2797 | local_irq_disable(); |
fcfd636a | 2798 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2799 | if (!no_pin1) |
49a66a0b MR |
2800 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2801 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2802 | |
49a66a0b MR |
2803 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2804 | "(IRQ0) through the 8259A ...\n"); | |
2805 | apic_printk(APIC_QUIET, KERN_INFO | |
2806 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2807 | /* |
2808 | * legacy devices should be connected to IO APIC #0 | |
2809 | */ | |
85ac16d0 | 2810 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2811 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2812 | legacy_pic->unmask(0); |
1da177e4 | 2813 | if (timer_irq_works()) { |
49a66a0b | 2814 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2815 | timer_through_8259 = 1; |
4aae0702 | 2816 | goto out; |
1da177e4 LT |
2817 | } |
2818 | /* | |
2819 | * Cleanup, just in case ... | |
2820 | */ | |
f72dccac | 2821 | local_irq_disable(); |
4305df94 | 2822 | legacy_pic->mask(0); |
fcfd636a | 2823 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2824 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2825 | } |
1da177e4 | 2826 | |
49a66a0b MR |
2827 | apic_printk(APIC_QUIET, KERN_INFO |
2828 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2829 | |
60c69948 | 2830 | lapic_register_intr(0); |
497c9a19 | 2831 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2832 | legacy_pic->unmask(0); |
1da177e4 LT |
2833 | |
2834 | if (timer_irq_works()) { | |
49a66a0b | 2835 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2836 | goto out; |
1da177e4 | 2837 | } |
f72dccac | 2838 | local_irq_disable(); |
4305df94 | 2839 | legacy_pic->mask(0); |
497c9a19 | 2840 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2841 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2842 | |
49a66a0b MR |
2843 | apic_printk(APIC_QUIET, KERN_INFO |
2844 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2845 | |
b81bb373 JP |
2846 | legacy_pic->init(0); |
2847 | legacy_pic->make_irq(0); | |
593f4a78 | 2848 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2849 | |
2850 | unlock_ExtINT_logic(); | |
2851 | ||
2852 | if (timer_irq_works()) { | |
49a66a0b | 2853 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2854 | goto out; |
1da177e4 | 2855 | } |
f72dccac | 2856 | local_irq_disable(); |
49a66a0b | 2857 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2858 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2859 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2860 | out: |
2861 | local_irq_restore(flags); | |
1da177e4 LT |
2862 | } |
2863 | ||
2864 | /* | |
af174783 MR |
2865 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2866 | * to devices. However there may be an I/O APIC pin available for | |
2867 | * this interrupt regardless. The pin may be left unconnected, but | |
2868 | * typically it will be reused as an ExtINT cascade interrupt for | |
2869 | * the master 8259A. In the MPS case such a pin will normally be | |
2870 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2871 | * there is no provision for ExtINT interrupts, and in the absence | |
2872 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2873 | * interrupt, that is edge-triggered and unmasked by default. We | |
2874 | * used to do this, but it caused problems on some systems because | |
2875 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2876 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2877 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2878 | * the I/O APIC in all cases now. No actual device should request | |
2879 | * it anyway. --macro | |
1da177e4 | 2880 | */ |
bc07844a | 2881 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2882 | |
2883 | void __init setup_IO_APIC(void) | |
2884 | { | |
54168ed7 | 2885 | |
54168ed7 IM |
2886 | /* |
2887 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2888 | */ | |
b81bb373 | 2889 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2890 | |
54168ed7 | 2891 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2892 | /* |
54168ed7 IM |
2893 | * Set up IO-APIC IRQ routing. |
2894 | */ | |
de934103 TG |
2895 | x86_init.mpparse.setup_ioapic_ids(); |
2896 | ||
1da177e4 LT |
2897 | sync_Arb_IDs(); |
2898 | setup_IO_APIC_irqs(); | |
2899 | init_IO_APIC_traps(); | |
b81bb373 | 2900 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2901 | check_timer(); |
1da177e4 LT |
2902 | } |
2903 | ||
2904 | /* | |
0d2eb44f | 2905 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2906 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2907 | */ |
36062448 | 2908 | |
1da177e4 LT |
2909 | static int __init io_apic_bug_finalize(void) |
2910 | { | |
d6c88a50 TG |
2911 | if (sis_apic_bug == -1) |
2912 | sis_apic_bug = 0; | |
2913 | return 0; | |
1da177e4 LT |
2914 | } |
2915 | ||
2916 | late_initcall(io_apic_bug_finalize); | |
2917 | ||
15bac20b | 2918 | static void resume_ioapic_id(int ioapic_id) |
1da177e4 | 2919 | { |
1da177e4 LT |
2920 | unsigned long flags; |
2921 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2922 | |
1da177e4 | 2923 | |
dade7716 | 2924 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f3c6ea1b | 2925 | reg_00.raw = io_apic_read(ioapic_id, 0); |
d5371430 SS |
2926 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) { |
2927 | reg_00.bits.ID = mpc_ioapic_id(ioapic_id); | |
f3c6ea1b | 2928 | io_apic_write(ioapic_id, 0, reg_00.raw); |
1da177e4 | 2929 | } |
dade7716 | 2930 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2931 | } |
1da177e4 | 2932 | |
f3c6ea1b RW |
2933 | static void ioapic_resume(void) |
2934 | { | |
2935 | int ioapic_id; | |
2936 | ||
2937 | for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--) | |
15bac20b SS |
2938 | resume_ioapic_id(ioapic_id); |
2939 | ||
2940 | restore_ioapic_entries(); | |
1da177e4 LT |
2941 | } |
2942 | ||
f3c6ea1b | 2943 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2944 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2945 | .resume = ioapic_resume, |
2946 | }; | |
2947 | ||
f3c6ea1b | 2948 | static int __init ioapic_init_ops(void) |
1da177e4 | 2949 | { |
f3c6ea1b RW |
2950 | register_syscore_ops(&ioapic_syscore_ops); |
2951 | ||
1da177e4 LT |
2952 | return 0; |
2953 | } | |
2954 | ||
f3c6ea1b | 2955 | device_initcall(ioapic_init_ops); |
1da177e4 | 2956 | |
3fc471ed | 2957 | /* |
95d77884 | 2958 | * Dynamic irq allocate and deallocation |
3fc471ed | 2959 | */ |
fbc6bff0 | 2960 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 2961 | { |
fbc6bff0 | 2962 | struct irq_cfg *cfg; |
3fc471ed | 2963 | unsigned long flags; |
fbc6bff0 TG |
2964 | unsigned int ret = 0; |
2965 | int irq; | |
d047f53a | 2966 | |
fbc6bff0 TG |
2967 | if (from < nr_irqs_gsi) |
2968 | from = nr_irqs_gsi; | |
d047f53a | 2969 | |
fbc6bff0 TG |
2970 | irq = alloc_irq_from(from, node); |
2971 | if (irq < 0) | |
2972 | return 0; | |
2973 | cfg = alloc_irq_cfg(irq, node); | |
2974 | if (!cfg) { | |
2975 | free_irq_at(irq, NULL); | |
2976 | return 0; | |
ace80ab7 | 2977 | } |
3fc471ed | 2978 | |
fbc6bff0 TG |
2979 | raw_spin_lock_irqsave(&vector_lock, flags); |
2980 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
2981 | ret = irq; | |
2982 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2983 | |
fbc6bff0 | 2984 | if (ret) { |
2c778651 | 2985 | irq_set_chip_data(irq, cfg); |
fbc6bff0 TG |
2986 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
2987 | } else { | |
2988 | free_irq_at(irq, cfg); | |
2989 | } | |
2990 | return ret; | |
3fc471ed EB |
2991 | } |
2992 | ||
199751d7 YL |
2993 | int create_irq(void) |
2994 | { | |
f6e9456c | 2995 | int node = cpu_to_node(0); |
be5d5350 | 2996 | unsigned int irq_want; |
54168ed7 IM |
2997 | int irq; |
2998 | ||
be5d5350 | 2999 | irq_want = nr_irqs_gsi; |
d047f53a | 3000 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3001 | |
3002 | if (irq == 0) | |
3003 | irq = -1; | |
3004 | ||
3005 | return irq; | |
199751d7 YL |
3006 | } |
3007 | ||
3fc471ed EB |
3008 | void destroy_irq(unsigned int irq) |
3009 | { | |
2c778651 | 3010 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
3fc471ed | 3011 | unsigned long flags; |
3fc471ed | 3012 | |
fbc6bff0 | 3013 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3014 | |
7b79462a | 3015 | if (irq_remapped(cfg)) |
9717967c | 3016 | free_irte(irq); |
dade7716 | 3017 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3018 | __clear_irq_vector(irq, cfg); |
dade7716 | 3019 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3020 | free_irq_at(irq, cfg); |
3fc471ed | 3021 | } |
3fc471ed | 3022 | |
2d3fcc1c | 3023 | /* |
27b46d76 | 3024 | * MSI message composition |
2d3fcc1c EB |
3025 | */ |
3026 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3027 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3028 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3029 | { |
497c9a19 YL |
3030 | struct irq_cfg *cfg; |
3031 | int err; | |
2d3fcc1c EB |
3032 | unsigned dest; |
3033 | ||
f1182638 JB |
3034 | if (disable_apic) |
3035 | return -ENXIO; | |
3036 | ||
3145e941 | 3037 | cfg = irq_cfg(irq); |
fe402e1f | 3038 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3039 | if (err) |
3040 | return err; | |
2d3fcc1c | 3041 | |
debccb3e | 3042 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3043 | |
1a0e62a4 | 3044 | if (irq_remapped(cfg)) { |
54168ed7 IM |
3045 | struct irte irte; |
3046 | int ir_index; | |
3047 | u16 sub_handle; | |
3048 | ||
3049 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3050 | BUG_ON(ir_index == -1); | |
3051 | ||
62a92f4c | 3052 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3053 | |
f007e99c | 3054 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3055 | if (pdev) |
3056 | set_msi_sid(&irte, pdev); | |
3057 | else | |
3058 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3059 | |
54168ed7 IM |
3060 | modify_irte(irq, &irte); |
3061 | ||
3062 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3063 | msg->data = sub_handle; | |
3064 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3065 | MSI_ADDR_IR_SHV | | |
3066 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3067 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3068 | } else { |
9d783ba0 SS |
3069 | if (x2apic_enabled()) |
3070 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3071 | MSI_ADDR_EXT_DEST_ID(dest); | |
3072 | else | |
3073 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3074 | ||
54168ed7 IM |
3075 | msg->address_lo = |
3076 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3077 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3078 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3079 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3080 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3081 | MSI_ADDR_REDIRECTION_CPU: |
3082 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3083 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3084 | |
54168ed7 IM |
3085 | msg->data = |
3086 | MSI_DATA_TRIGGER_EDGE | | |
3087 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3088 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3089 | MSI_DATA_DELIVERY_FIXED: |
3090 | MSI_DATA_DELIVERY_LOWPRI) | | |
3091 | MSI_DATA_VECTOR(cfg->vector); | |
3092 | } | |
497c9a19 | 3093 | return err; |
2d3fcc1c EB |
3094 | } |
3095 | ||
3b7d1921 | 3096 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3097 | static int |
3098 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3099 | { |
5346b2a7 | 3100 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3101 | struct msi_msg msg; |
3102 | unsigned int dest; | |
3b7d1921 | 3103 | |
5346b2a7 | 3104 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3105 | return -1; |
2d3fcc1c | 3106 | |
5346b2a7 | 3107 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3108 | |
3109 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3110 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3111 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3112 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3113 | ||
5346b2a7 | 3114 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3115 | |
3116 | return 0; | |
2d3fcc1c | 3117 | } |
54168ed7 IM |
3118 | #ifdef CONFIG_INTR_REMAP |
3119 | /* | |
3120 | * Migrate the MSI irq to another cpumask. This migration is | |
3121 | * done in the process context using interrupt-remapping hardware. | |
3122 | */ | |
d5dedd45 | 3123 | static int |
b5d1c465 TG |
3124 | ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3125 | bool force) | |
54168ed7 | 3126 | { |
b5d1c465 TG |
3127 | struct irq_cfg *cfg = data->chip_data; |
3128 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3129 | struct irte irte; |
54168ed7 IM |
3130 | |
3131 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3132 | return -1; |
54168ed7 | 3133 | |
b5d1c465 | 3134 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3135 | return -1; |
54168ed7 | 3136 | |
54168ed7 IM |
3137 | irte.vector = cfg->vector; |
3138 | irte.dest_id = IRTE_DEST(dest); | |
3139 | ||
3140 | /* | |
3141 | * atomically update the IRTE with the new destination and vector. | |
3142 | */ | |
3143 | modify_irte(irq, &irte); | |
3144 | ||
3145 | /* | |
3146 | * After this point, all the interrupts will start arriving | |
3147 | * at the new destination. So, time to cleanup the previous | |
3148 | * vector allocation. | |
3149 | */ | |
22f65d31 MT |
3150 | if (cfg->move_in_progress) |
3151 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3152 | |
3153 | return 0; | |
54168ed7 | 3154 | } |
3145e941 | 3155 | |
54168ed7 | 3156 | #endif |
3b7d1921 | 3157 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3158 | |
3b7d1921 EB |
3159 | /* |
3160 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3161 | * which implement the MSI or MSI-X Capability Structure. | |
3162 | */ | |
3163 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3164 | .name = "PCI-MSI", |
3165 | .irq_unmask = unmask_msi_irq, | |
3166 | .irq_mask = mask_msi_irq, | |
3167 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3168 | #ifdef CONFIG_SMP |
5346b2a7 | 3169 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3170 | #endif |
5346b2a7 | 3171 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3172 | }; |
3173 | ||
54168ed7 | 3174 | static struct irq_chip msi_ir_chip = { |
b5d1c465 TG |
3175 | .name = "IR-PCI-MSI", |
3176 | .irq_unmask = unmask_msi_irq, | |
3177 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3178 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3179 | .irq_ack = ir_ack_apic_edge, |
54168ed7 | 3180 | #ifdef CONFIG_SMP |
b5d1c465 | 3181 | .irq_set_affinity = ir_msi_set_affinity, |
a1e38ca5 | 3182 | #endif |
54168ed7 | 3183 | #endif |
b5d1c465 | 3184 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3185 | }; |
3186 | ||
3187 | /* | |
3188 | * Map the PCI dev to the corresponding remapping hardware unit | |
3189 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3190 | * in it. | |
3191 | */ | |
3192 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3193 | { | |
3194 | struct intel_iommu *iommu; | |
3195 | int index; | |
3196 | ||
3197 | iommu = map_dev_to_ir(dev); | |
3198 | if (!iommu) { | |
3199 | printk(KERN_ERR | |
3200 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3201 | return -ENOENT; | |
3202 | } | |
3203 | ||
3204 | index = alloc_irte(iommu, irq, nvec); | |
3205 | if (index < 0) { | |
3206 | printk(KERN_ERR | |
3207 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3208 | pci_name(dev)); |
54168ed7 IM |
3209 | return -ENOSPC; |
3210 | } | |
3211 | return index; | |
3212 | } | |
1d025192 | 3213 | |
3145e941 | 3214 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3215 | { |
c60eaf25 | 3216 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3217 | struct msi_msg msg; |
60c69948 | 3218 | int ret; |
1d025192 | 3219 | |
c8bc6f3c | 3220 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3221 | if (ret < 0) |
3222 | return ret; | |
3223 | ||
2c778651 | 3224 | irq_set_msi_desc(irq, msidesc); |
1d025192 YL |
3225 | write_msi_msg(irq, &msg); |
3226 | ||
2c778651 | 3227 | if (irq_remapped(irq_get_chip_data(irq))) { |
60c69948 | 3228 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
c60eaf25 TG |
3229 | chip = &msi_ir_chip; |
3230 | } | |
3231 | ||
3232 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3233 | |
c81bba49 YL |
3234 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3235 | ||
1d025192 YL |
3236 | return 0; |
3237 | } | |
3238 | ||
294ee6f8 | 3239 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3240 | { |
60c69948 TG |
3241 | int node, ret, sub_handle, index = 0; |
3242 | unsigned int irq, irq_want; | |
0b8f1efa | 3243 | struct msi_desc *msidesc; |
1cc18521 | 3244 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3245 | |
1c8d7b0a MW |
3246 | /* x86 doesn't support multiple MSI yet */ |
3247 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3248 | return 1; | |
3249 | ||
d047f53a | 3250 | node = dev_to_node(&dev->dev); |
be5d5350 | 3251 | irq_want = nr_irqs_gsi; |
54168ed7 | 3252 | sub_handle = 0; |
0b8f1efa | 3253 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3254 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3255 | if (irq == 0) |
3256 | return -1; | |
f1ee5548 | 3257 | irq_want = irq + 1; |
54168ed7 IM |
3258 | if (!intr_remapping_enabled) |
3259 | goto no_ir; | |
3260 | ||
3261 | if (!sub_handle) { | |
3262 | /* | |
3263 | * allocate the consecutive block of IRTE's | |
3264 | * for 'nvec' | |
3265 | */ | |
3266 | index = msi_alloc_irte(dev, irq, nvec); | |
3267 | if (index < 0) { | |
3268 | ret = index; | |
3269 | goto error; | |
3270 | } | |
3271 | } else { | |
3272 | iommu = map_dev_to_ir(dev); | |
3273 | if (!iommu) { | |
3274 | ret = -ENOENT; | |
3275 | goto error; | |
3276 | } | |
3277 | /* | |
3278 | * setup the mapping between the irq and the IRTE | |
3279 | * base index, the sub_handle pointing to the | |
3280 | * appropriate interrupt remap table entry. | |
3281 | */ | |
3282 | set_irte_irq(irq, iommu, index, sub_handle); | |
3283 | } | |
3284 | no_ir: | |
0b8f1efa | 3285 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3286 | if (ret < 0) |
3287 | goto error; | |
3288 | sub_handle++; | |
3289 | } | |
3290 | return 0; | |
047c8fdb YL |
3291 | |
3292 | error: | |
54168ed7 IM |
3293 | destroy_irq(irq); |
3294 | return ret; | |
047c8fdb YL |
3295 | } |
3296 | ||
294ee6f8 | 3297 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3298 | { |
f7feaca7 | 3299 | destroy_irq(irq); |
3b7d1921 EB |
3300 | } |
3301 | ||
9d783ba0 | 3302 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3303 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3304 | static int |
3305 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3306 | bool force) | |
54168ed7 | 3307 | { |
fe52b2d2 TG |
3308 | struct irq_cfg *cfg = data->chip_data; |
3309 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3310 | struct msi_msg msg; |
54168ed7 | 3311 | |
fe52b2d2 | 3312 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3313 | return -1; |
54168ed7 | 3314 | |
54168ed7 IM |
3315 | dmar_msi_read(irq, &msg); |
3316 | ||
3317 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3318 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3319 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3320 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3321 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3322 | |
3323 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3324 | |
3325 | return 0; | |
54168ed7 | 3326 | } |
3145e941 | 3327 | |
54168ed7 IM |
3328 | #endif /* CONFIG_SMP */ |
3329 | ||
8f7007aa | 3330 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3331 | .name = "DMAR_MSI", |
3332 | .irq_unmask = dmar_msi_unmask, | |
3333 | .irq_mask = dmar_msi_mask, | |
3334 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3335 | #ifdef CONFIG_SMP |
fe52b2d2 | 3336 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3337 | #endif |
fe52b2d2 | 3338 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3339 | }; |
3340 | ||
3341 | int arch_setup_dmar_msi(unsigned int irq) | |
3342 | { | |
3343 | int ret; | |
3344 | struct msi_msg msg; | |
2d3fcc1c | 3345 | |
c8bc6f3c | 3346 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3347 | if (ret < 0) |
3348 | return ret; | |
3349 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3350 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3351 | "edge"); | |
54168ed7 IM |
3352 | return 0; |
3353 | } | |
3354 | #endif | |
3355 | ||
58ac1e76 | 3356 | #ifdef CONFIG_HPET_TIMER |
3357 | ||
3358 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3359 | static int hpet_msi_set_affinity(struct irq_data *data, |
3360 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3361 | { |
d0fbca8f | 3362 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3363 | struct msi_msg msg; |
3364 | unsigned int dest; | |
58ac1e76 | 3365 | |
0e09ddf2 | 3366 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3367 | return -1; |
58ac1e76 | 3368 | |
d0fbca8f | 3369 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3370 | |
3371 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3372 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3373 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3374 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3375 | ||
d0fbca8f | 3376 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3377 | |
3378 | return 0; | |
58ac1e76 | 3379 | } |
3145e941 | 3380 | |
58ac1e76 | 3381 | #endif /* CONFIG_SMP */ |
3382 | ||
c8bc6f3c | 3383 | static struct irq_chip ir_hpet_msi_type = { |
b5d1c465 TG |
3384 | .name = "IR-HPET_MSI", |
3385 | .irq_unmask = hpet_msi_unmask, | |
3386 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3387 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3388 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c | 3389 | #ifdef CONFIG_SMP |
b5d1c465 | 3390 | .irq_set_affinity = ir_msi_set_affinity, |
c8bc6f3c SS |
3391 | #endif |
3392 | #endif | |
b5d1c465 | 3393 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3394 | }; |
3395 | ||
1cc18521 | 3396 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3397 | .name = "HPET_MSI", |
d0fbca8f TG |
3398 | .irq_unmask = hpet_msi_unmask, |
3399 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3400 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3401 | #ifdef CONFIG_SMP |
d0fbca8f | 3402 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3403 | #endif |
90297c5f | 3404 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3405 | }; |
3406 | ||
c8bc6f3c | 3407 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3408 | { |
c60eaf25 | 3409 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3410 | struct msi_msg msg; |
d0fbca8f | 3411 | int ret; |
58ac1e76 | 3412 | |
c8bc6f3c SS |
3413 | if (intr_remapping_enabled) { |
3414 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3415 | int index; | |
3416 | ||
3417 | if (!iommu) | |
3418 | return -1; | |
3419 | ||
3420 | index = alloc_irte(iommu, irq, 1); | |
3421 | if (index < 0) | |
3422 | return -1; | |
3423 | } | |
3424 | ||
3425 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3426 | if (ret < 0) |
3427 | return ret; | |
3428 | ||
2c778651 | 3429 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3430 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
2c778651 | 3431 | if (irq_remapped(irq_get_chip_data(irq))) |
c60eaf25 | 3432 | chip = &ir_hpet_msi_type; |
c81bba49 | 3433 | |
c60eaf25 | 3434 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3435 | return 0; |
3436 | } | |
3437 | #endif | |
3438 | ||
54168ed7 | 3439 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3440 | /* |
3441 | * Hypertransport interrupt support | |
3442 | */ | |
3443 | #ifdef CONFIG_HT_IRQ | |
3444 | ||
3445 | #ifdef CONFIG_SMP | |
3446 | ||
497c9a19 | 3447 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3448 | { |
ec68307c EB |
3449 | struct ht_irq_msg msg; |
3450 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3451 | |
497c9a19 | 3452 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3453 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3454 | |
497c9a19 | 3455 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3456 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3457 | |
ec68307c | 3458 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3459 | } |
3460 | ||
be5b7bf7 TG |
3461 | static int |
3462 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3463 | { |
be5b7bf7 | 3464 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3465 | unsigned int dest; |
8b955b0d | 3466 | |
be5b7bf7 | 3467 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3468 | return -1; |
8b955b0d | 3469 | |
be5b7bf7 | 3470 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3471 | return 0; |
8b955b0d | 3472 | } |
3145e941 | 3473 | |
8b955b0d EB |
3474 | #endif |
3475 | ||
c37e108d | 3476 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3477 | .name = "PCI-HT", |
3478 | .irq_mask = mask_ht_irq, | |
3479 | .irq_unmask = unmask_ht_irq, | |
3480 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3481 | #ifdef CONFIG_SMP |
be5b7bf7 | 3482 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3483 | #endif |
be5b7bf7 | 3484 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3485 | }; |
3486 | ||
3487 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3488 | { | |
497c9a19 YL |
3489 | struct irq_cfg *cfg; |
3490 | int err; | |
8b955b0d | 3491 | |
f1182638 JB |
3492 | if (disable_apic) |
3493 | return -ENXIO; | |
3494 | ||
3145e941 | 3495 | cfg = irq_cfg(irq); |
fe402e1f | 3496 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3497 | if (!err) { |
ec68307c | 3498 | struct ht_irq_msg msg; |
8b955b0d | 3499 | unsigned dest; |
8b955b0d | 3500 | |
debccb3e IM |
3501 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3502 | apic->target_cpus()); | |
8b955b0d | 3503 | |
ec68307c | 3504 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3505 | |
ec68307c EB |
3506 | msg.address_lo = |
3507 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3508 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3509 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3510 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3511 | HT_IRQ_LOW_DM_PHYSICAL : |
3512 | HT_IRQ_LOW_DM_LOGICAL) | | |
3513 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3514 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3515 | HT_IRQ_LOW_MT_FIXED : |
3516 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3517 | HT_IRQ_LOW_IRQ_MASKED; | |
3518 | ||
ec68307c | 3519 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3520 | |
2c778651 | 3521 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
a460e745 | 3522 | handle_edge_irq, "edge"); |
c81bba49 YL |
3523 | |
3524 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3525 | } |
497c9a19 | 3526 | return err; |
8b955b0d EB |
3527 | } |
3528 | #endif /* CONFIG_HT_IRQ */ | |
3529 | ||
20443598 | 3530 | static int |
ff973d04 TG |
3531 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3532 | { | |
3533 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3534 | int ret; | |
3535 | ||
3536 | if (!cfg) | |
3537 | return -EINVAL; | |
3538 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3539 | if (!ret) | |
3540 | setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, | |
3541 | attr->trigger, attr->polarity); | |
3542 | return ret; | |
3543 | } | |
3544 | ||
20443598 SAS |
3545 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3546 | struct io_apic_irq_attr *attr) | |
710dcda6 TG |
3547 | { |
3548 | unsigned int id = attr->ioapic, pin = attr->ioapic_pin; | |
3549 | int ret; | |
3550 | ||
3551 | /* Avoid redundant programming */ | |
8f18c971 | 3552 | if (test_bit(pin, ioapics[id].pin_programmed)) { |
710dcda6 | 3553 | pr_debug("Pin %d-%d already programmed\n", |
d5371430 | 3554 | mpc_ioapic_id(id), pin); |
710dcda6 TG |
3555 | return 0; |
3556 | } | |
3557 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3558 | if (!ret) | |
8f18c971 | 3559 | set_bit(pin, ioapics[id].pin_programmed); |
710dcda6 TG |
3560 | return ret; |
3561 | } | |
3562 | ||
41098ffe | 3563 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3564 | { |
3565 | union IO_APIC_reg_01 reg_01; | |
3566 | unsigned long flags; | |
3567 | ||
dade7716 | 3568 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3569 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3570 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3571 | |
4b6b19a1 EB |
3572 | /* The register returns the maximum index redir index |
3573 | * supported, which is one less than the total number of redir | |
3574 | * entries. | |
3575 | */ | |
3576 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3577 | } |
3578 | ||
23f9b267 | 3579 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3580 | { |
4afc51a8 | 3581 | int nr; |
be5d5350 | 3582 | |
a4384df3 | 3583 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3584 | if (nr > nr_irqs_gsi) |
be5d5350 | 3585 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3586 | |
3587 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3588 | } |
3589 | ||
7b586d71 JF |
3590 | int get_nr_irqs_gsi(void) |
3591 | { | |
3592 | return nr_irqs_gsi; | |
3593 | } | |
3594 | ||
4a046d17 YL |
3595 | #ifdef CONFIG_SPARSE_IRQ |
3596 | int __init arch_probe_nr_irqs(void) | |
3597 | { | |
3598 | int nr; | |
3599 | ||
f1ee5548 YL |
3600 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3601 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3602 | |
f1ee5548 YL |
3603 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3604 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3605 | /* | |
3606 | * for MSI and HT dyn irq | |
3607 | */ | |
3608 | nr += nr_irqs_gsi * 16; | |
3609 | #endif | |
3610 | if (nr < nr_irqs) | |
4a046d17 YL |
3611 | nr_irqs = nr; |
3612 | ||
b683de2b | 3613 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3614 | } |
3615 | #endif | |
3616 | ||
710dcda6 TG |
3617 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3618 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3619 | { |
5ef21837 YL |
3620 | int node; |
3621 | ||
3622 | if (!IO_APIC_IRQ(irq)) { | |
3623 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3624 | irq_attr->ioapic); |
5ef21837 YL |
3625 | return -EINVAL; |
3626 | } | |
3627 | ||
e0799c04 | 3628 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3629 | |
710dcda6 | 3630 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3631 | } |
3632 | ||
54168ed7 | 3633 | #ifdef CONFIG_X86_32 |
41098ffe | 3634 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3635 | { |
3636 | union IO_APIC_reg_00 reg_00; | |
3637 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3638 | physid_mask_t tmp; | |
3639 | unsigned long flags; | |
3640 | int i = 0; | |
3641 | ||
3642 | /* | |
36062448 PC |
3643 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3644 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3645 | * supports up to 16 on one shared APIC bus. |
36062448 | 3646 | * |
1da177e4 LT |
3647 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3648 | * advantage of new APIC bus architecture. | |
3649 | */ | |
3650 | ||
3651 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3652 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3653 | |
dade7716 | 3654 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3655 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3656 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3657 | |
3658 | if (apic_id >= get_physical_broadcast()) { | |
3659 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3660 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3661 | apic_id = reg_00.bits.ID; | |
3662 | } | |
3663 | ||
3664 | /* | |
36062448 | 3665 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3666 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3667 | */ | |
7abc0753 | 3668 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3669 | |
3670 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3671 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3672 | break; |
3673 | } | |
3674 | ||
3675 | if (i == get_physical_broadcast()) | |
3676 | panic("Max apic_id exceeded!\n"); | |
3677 | ||
3678 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3679 | "trying %d\n", ioapic, apic_id, i); | |
3680 | ||
3681 | apic_id = i; | |
36062448 | 3682 | } |
1da177e4 | 3683 | |
7abc0753 | 3684 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3685 | physids_or(apic_id_map, apic_id_map, tmp); |
3686 | ||
3687 | if (reg_00.bits.ID != apic_id) { | |
3688 | reg_00.bits.ID = apic_id; | |
3689 | ||
dade7716 | 3690 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3691 | io_apic_write(ioapic, 0, reg_00.raw); |
3692 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3693 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3694 | |
3695 | /* Sanity check */ | |
6070f9ec AD |
3696 | if (reg_00.bits.ID != apic_id) { |
3697 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3698 | return -1; | |
3699 | } | |
1da177e4 LT |
3700 | } |
3701 | ||
3702 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3703 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3704 | ||
3705 | return apic_id; | |
3706 | } | |
41098ffe TG |
3707 | |
3708 | static u8 __init io_apic_unique_id(u8 id) | |
3709 | { | |
3710 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3711 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3712 | return io_apic_get_unique_id(nr_ioapics, id); | |
3713 | else | |
3714 | return id; | |
3715 | } | |
3716 | #else | |
3717 | static u8 __init io_apic_unique_id(u8 id) | |
3718 | { | |
3719 | int i; | |
3720 | DECLARE_BITMAP(used, 256); | |
3721 | ||
3722 | bitmap_zero(used, 256); | |
3723 | for (i = 0; i < nr_ioapics; i++) { | |
d5371430 | 3724 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3725 | } |
3726 | if (!test_bit(id, used)) | |
3727 | return id; | |
3728 | return find_first_zero_bit(used, 256); | |
3729 | } | |
58f892e0 | 3730 | #endif |
1da177e4 | 3731 | |
41098ffe | 3732 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3733 | { |
3734 | union IO_APIC_reg_01 reg_01; | |
3735 | unsigned long flags; | |
3736 | ||
dade7716 | 3737 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3738 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3739 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3740 | |
3741 | return reg_01.bits.version; | |
3742 | } | |
3743 | ||
9a0a91bb | 3744 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3745 | { |
9a0a91bb | 3746 | int ioapic, pin, idx; |
61fd47e0 SL |
3747 | |
3748 | if (skip_ioapic_setup) | |
3749 | return -1; | |
3750 | ||
9a0a91bb EB |
3751 | ioapic = mp_find_ioapic(gsi); |
3752 | if (ioapic < 0) | |
61fd47e0 SL |
3753 | return -1; |
3754 | ||
9a0a91bb EB |
3755 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3756 | if (pin < 0) | |
3757 | return -1; | |
3758 | ||
3759 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3760 | if (idx < 0) | |
61fd47e0 SL |
3761 | return -1; |
3762 | ||
9a0a91bb EB |
3763 | *trigger = irq_trigger(idx); |
3764 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3765 | return 0; |
3766 | } | |
3767 | ||
497c9a19 YL |
3768 | /* |
3769 | * This function currently is only a helper for the i386 smp boot process where | |
3770 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3771 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3772 | */ |
3773 | #ifdef CONFIG_SMP | |
3774 | void __init setup_ioapic_dest(void) | |
3775 | { | |
fad53995 | 3776 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3777 | const struct cpumask *mask; |
5451ddc5 | 3778 | struct irq_data *idata; |
497c9a19 YL |
3779 | |
3780 | if (skip_ioapic_setup == 1) | |
3781 | return; | |
3782 | ||
fad53995 | 3783 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b69c6c3b | 3784 | for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { |
b9c61b70 YL |
3785 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3786 | if (irq_entry == -1) | |
3787 | continue; | |
3788 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3789 | |
fad53995 EB |
3790 | if ((ioapic > 0) && (irq > 16)) |
3791 | continue; | |
3792 | ||
5451ddc5 | 3793 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3794 | |
b9c61b70 YL |
3795 | /* |
3796 | * Honour affinities which have been set in early boot | |
3797 | */ | |
5451ddc5 TG |
3798 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3799 | mask = idata->affinity; | |
b9c61b70 YL |
3800 | else |
3801 | mask = apic->target_cpus(); | |
497c9a19 | 3802 | |
b9c61b70 | 3803 | if (intr_remapping_enabled) |
5451ddc5 | 3804 | ir_ioapic_set_affinity(idata, mask, false); |
b9c61b70 | 3805 | else |
5451ddc5 | 3806 | ioapic_set_affinity(idata, mask, false); |
497c9a19 | 3807 | } |
b9c61b70 | 3808 | |
497c9a19 YL |
3809 | } |
3810 | #endif | |
3811 | ||
54168ed7 IM |
3812 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3813 | ||
3814 | static struct resource *ioapic_resources; | |
3815 | ||
ffc43836 | 3816 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3817 | { |
3818 | unsigned long n; | |
3819 | struct resource *res; | |
3820 | char *mem; | |
3821 | int i; | |
3822 | ||
3823 | if (nr_ioapics <= 0) | |
3824 | return NULL; | |
3825 | ||
3826 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3827 | n *= nr_ioapics; | |
3828 | ||
3829 | mem = alloc_bootmem(n); | |
3830 | res = (void *)mem; | |
3831 | ||
ffc43836 | 3832 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3833 | |
ffc43836 CG |
3834 | for (i = 0; i < nr_ioapics; i++) { |
3835 | res[i].name = mem; | |
3836 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3837 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3838 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3839 | } |
3840 | ||
3841 | ioapic_resources = res; | |
3842 | ||
3843 | return res; | |
3844 | } | |
54168ed7 | 3845 | |
23f9b267 | 3846 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3847 | { |
3848 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3849 | struct resource *ioapic_res; |
d6c88a50 | 3850 | int i; |
f3294a33 | 3851 | |
ffc43836 | 3852 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3853 | for (i = 0; i < nr_ioapics; i++) { |
3854 | if (smp_found_config) { | |
d5371430 | 3855 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3856 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3857 | if (!ioapic_phys) { |
3858 | printk(KERN_ERR | |
3859 | "WARNING: bogus zero IO-APIC " | |
3860 | "address found in MPTABLE, " | |
3861 | "disabling IO/APIC support!\n"); | |
3862 | smp_found_config = 0; | |
3863 | skip_ioapic_setup = 1; | |
3864 | goto fake_ioapic_page; | |
3865 | } | |
54168ed7 | 3866 | #endif |
f3294a33 | 3867 | } else { |
54168ed7 | 3868 | #ifdef CONFIG_X86_32 |
f3294a33 | 3869 | fake_ioapic_page: |
54168ed7 | 3870 | #endif |
e79c65a9 | 3871 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3872 | ioapic_phys = __pa(ioapic_phys); |
3873 | } | |
3874 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3875 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3876 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3877 | ioapic_phys); | |
f3294a33 | 3878 | idx++; |
54168ed7 | 3879 | |
ffc43836 | 3880 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3881 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3882 | ioapic_res++; |
f3294a33 | 3883 | } |
23f9b267 TG |
3884 | |
3885 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
3886 | } |
3887 | ||
857fdc53 | 3888 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3889 | { |
3890 | int i; | |
3891 | struct resource *r = ioapic_resources; | |
3892 | ||
3893 | if (!r) { | |
857fdc53 | 3894 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3895 | printk(KERN_ERR |
3896 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3897 | return; |
54168ed7 IM |
3898 | } |
3899 | ||
3900 | for (i = 0; i < nr_ioapics; i++) { | |
3901 | insert_resource(&iomem_resource, r); | |
3902 | r++; | |
3903 | } | |
54168ed7 | 3904 | } |
2a4ab640 | 3905 | |
eddb0c55 | 3906 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
3907 | { |
3908 | int i = 0; | |
3909 | ||
678301ec PB |
3910 | if (nr_ioapics == 0) |
3911 | return -1; | |
3912 | ||
2a4ab640 FT |
3913 | /* Find the IOAPIC that manages this GSI. */ |
3914 | for (i = 0; i < nr_ioapics; i++) { | |
c040aaeb SS |
3915 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
3916 | if ((gsi >= gsi_cfg->gsi_base) | |
3917 | && (gsi <= gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3918 | return i; |
3919 | } | |
54168ed7 | 3920 | |
2a4ab640 FT |
3921 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3922 | return -1; | |
3923 | } | |
3924 | ||
eddb0c55 | 3925 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3926 | { |
c040aaeb SS |
3927 | struct mp_ioapic_gsi *gsi_cfg; |
3928 | ||
2a4ab640 FT |
3929 | if (WARN_ON(ioapic == -1)) |
3930 | return -1; | |
c040aaeb SS |
3931 | |
3932 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3933 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3934 | return -1; |
3935 | ||
c040aaeb | 3936 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3937 | } |
3938 | ||
41098ffe | 3939 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3940 | { |
3941 | if (nr_ioapics >= MAX_IO_APICS) { | |
45e8234c | 3942 | printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded " |
2a4ab640 FT |
3943 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); |
3944 | return 1; | |
3945 | } | |
3946 | if (!address) { | |
3947 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
3948 | " found in table, skipping!\n"); | |
3949 | return 1; | |
3950 | } | |
54168ed7 IM |
3951 | return 0; |
3952 | } | |
3953 | ||
2a4ab640 FT |
3954 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3955 | { | |
3956 | int idx = 0; | |
7716a5c4 | 3957 | int entries; |
c040aaeb | 3958 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
3959 | |
3960 | if (bad_ioapic(address)) | |
3961 | return; | |
3962 | ||
3963 | idx = nr_ioapics; | |
3964 | ||
d5371430 SS |
3965 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3966 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3967 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
3968 | |
3969 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
d5371430 SS |
3970 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
3971 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
3972 | |
3973 | /* | |
3974 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3975 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3976 | */ | |
7716a5c4 | 3977 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
3978 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3979 | gsi_cfg->gsi_base = gsi_base; | |
3980 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
3981 | |
3982 | /* | |
3983 | * The number of IO-APIC IRQ registers (== #pins): | |
3984 | */ | |
b69c6c3b | 3985 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3986 | |
c040aaeb SS |
3987 | if (gsi_cfg->gsi_end >= gsi_top) |
3988 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 FT |
3989 | |
3990 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
d5371430 SS |
3991 | "GSI %d-%d\n", idx, mpc_ioapic_id(idx), |
3992 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
c040aaeb | 3993 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); |
2a4ab640 FT |
3994 | |
3995 | nr_ioapics++; | |
3996 | } | |
05ddafb1 JP |
3997 | |
3998 | /* Enable IOAPIC early just for system timer */ | |
3999 | void __init pre_init_apic_IRQ0(void) | |
4000 | { | |
f880ec78 | 4001 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
4002 | |
4003 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4004 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
4005 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
4006 | &phys_cpu_present_map); | |
05ddafb1 | 4007 | #endif |
05ddafb1 JP |
4008 | setup_local_APIC(); |
4009 | ||
f880ec78 | 4010 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
4011 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
4012 | "edge"); | |
05ddafb1 | 4013 | } |