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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
a4384df3 EB |
92 | /* The one past the highest gsi number used */ |
93 | u32 gsi_top; | |
5777372a | 94 | |
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
7e495529 | 134 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 135 | { |
2ee39065 | 136 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
137 | } |
138 | ||
a1420f39 | 139 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 140 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 141 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 142 | #else |
97943390 | 143 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 144 | #endif |
a1420f39 | 145 | |
13a0c3c2 | 146 | int __init arch_early_irq_init(void) |
8f09cd20 | 147 | { |
0b8f1efa | 148 | struct irq_cfg *cfg; |
60c69948 | 149 | int count, node, i; |
d6c88a50 | 150 | |
1f91233c JP |
151 | if (!legacy_pic->nr_legacy_irqs) { |
152 | nr_irqs_gsi = 0; | |
153 | io_apic_irqs = ~0UL; | |
154 | } | |
155 | ||
0b8f1efa YL |
156 | cfg = irq_cfgx; |
157 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 158 | node = cpu_to_node(0); |
8f09cd20 | 159 | |
fbc6bff0 TG |
160 | /* Make sure the legacy interrupts are marked in the bitmap */ |
161 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); | |
162 | ||
0b8f1efa | 163 | for (i = 0; i < count; i++) { |
60c69948 | 164 | set_irq_chip_data(i, &cfg[i]); |
2ee39065 TG |
165 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
166 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
167 | /* |
168 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
169 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
170 | */ | |
54b56170 | 171 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
172 | cfg[i].vector = IRQ0_VECTOR + i; |
173 | cpumask_set_cpu(0, cfg[i].domain); | |
174 | } | |
0b8f1efa | 175 | } |
13a0c3c2 YL |
176 | |
177 | return 0; | |
0b8f1efa | 178 | } |
8f09cd20 | 179 | |
0b8f1efa | 180 | #ifdef CONFIG_SPARSE_IRQ |
48b26501 | 181 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 182 | { |
60c69948 | 183 | return get_irq_chip_data(irq); |
8f09cd20 | 184 | } |
d6c88a50 | 185 | |
f981a3dc | 186 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 187 | { |
0b8f1efa | 188 | struct irq_cfg *cfg; |
0f978f45 | 189 | |
2ee39065 | 190 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
191 | if (!cfg) |
192 | return NULL; | |
2ee39065 | 193 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 194 | goto out_cfg; |
2ee39065 | 195 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 196 | goto out_domain; |
0b8f1efa | 197 | return cfg; |
6e2fff50 TG |
198 | out_domain: |
199 | free_cpumask_var(cfg->domain); | |
200 | out_cfg: | |
201 | kfree(cfg); | |
202 | return NULL; | |
8f09cd20 YL |
203 | } |
204 | ||
f981a3dc | 205 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 206 | { |
fbc6bff0 TG |
207 | if (!cfg) |
208 | return; | |
209 | set_irq_chip_data(at, NULL); | |
08c33db6 TG |
210 | free_cpumask_var(cfg->domain); |
211 | free_cpumask_var(cfg->old_domain); | |
212 | kfree(cfg); | |
213 | } | |
214 | ||
0b8f1efa | 215 | #else |
08c33db6 | 216 | |
9338ad6f | 217 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
218 | { |
219 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 220 | } |
1da177e4 | 221 | |
f981a3dc | 222 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
08c33db6 TG |
223 | { |
224 | return irq_cfgx + irq; | |
225 | } | |
226 | ||
f981a3dc | 227 | static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } |
08c33db6 | 228 | |
0b8f1efa YL |
229 | #endif |
230 | ||
08c33db6 TG |
231 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
232 | { | |
233 | int res = irq_alloc_desc_at(at, node); | |
234 | struct irq_cfg *cfg; | |
235 | ||
236 | if (res < 0) { | |
237 | if (res != -EEXIST) | |
238 | return NULL; | |
239 | cfg = get_irq_chip_data(at); | |
240 | if (cfg) | |
241 | return cfg; | |
242 | } | |
243 | ||
f981a3dc | 244 | cfg = alloc_irq_cfg(at, node); |
08c33db6 TG |
245 | if (cfg) |
246 | set_irq_chip_data(at, cfg); | |
247 | else | |
248 | irq_free_desc(at); | |
249 | return cfg; | |
250 | } | |
251 | ||
252 | static int alloc_irq_from(unsigned int from, int node) | |
253 | { | |
254 | return irq_alloc_desc_from(from, node); | |
255 | } | |
256 | ||
257 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) | |
258 | { | |
f981a3dc | 259 | free_irq_cfg(at, cfg); |
08c33db6 TG |
260 | irq_free_desc(at); |
261 | } | |
262 | ||
130fe05d LT |
263 | struct io_apic { |
264 | unsigned int index; | |
265 | unsigned int unused[3]; | |
266 | unsigned int data; | |
0280f7c4 SS |
267 | unsigned int unused2[11]; |
268 | unsigned int eoi; | |
130fe05d LT |
269 | }; |
270 | ||
271 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
272 | { | |
273 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 274 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
275 | } |
276 | ||
0280f7c4 SS |
277 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
278 | { | |
279 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
280 | writel(vector, &io_apic->eoi); | |
281 | } | |
282 | ||
130fe05d LT |
283 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
284 | { | |
285 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
286 | writel(reg, &io_apic->index); | |
287 | return readl(&io_apic->data); | |
288 | } | |
289 | ||
290 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
291 | { | |
292 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
293 | writel(reg, &io_apic->index); | |
294 | writel(value, &io_apic->data); | |
295 | } | |
296 | ||
297 | /* | |
298 | * Re-write a value: to be used for read-modify-write | |
299 | * cycles where the read already set up the index register. | |
300 | * | |
301 | * Older SiS APIC requires we rewrite the index register | |
302 | */ | |
303 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
304 | { | |
54168ed7 | 305 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
306 | |
307 | if (sis_apic_bug) | |
308 | writel(reg, &io_apic->index); | |
130fe05d LT |
309 | writel(value, &io_apic->data); |
310 | } | |
311 | ||
3145e941 | 312 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
313 | { |
314 | struct irq_pin_list *entry; | |
315 | unsigned long flags; | |
047c8fdb | 316 | |
dade7716 | 317 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 318 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
319 | unsigned int reg; |
320 | int pin; | |
321 | ||
047c8fdb YL |
322 | pin = entry->pin; |
323 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
324 | /* Is the remote IRR bit set? */ | |
325 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 326 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
327 | return true; |
328 | } | |
047c8fdb | 329 | } |
dade7716 | 330 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
331 | |
332 | return false; | |
333 | } | |
047c8fdb | 334 | |
cf4c6a2f AK |
335 | union entry_union { |
336 | struct { u32 w1, w2; }; | |
337 | struct IO_APIC_route_entry entry; | |
338 | }; | |
339 | ||
340 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
341 | { | |
342 | union entry_union eu; | |
343 | unsigned long flags; | |
dade7716 | 344 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
345 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
346 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 347 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
348 | return eu.entry; |
349 | } | |
350 | ||
f9dadfa7 LT |
351 | /* |
352 | * When we write a new IO APIC routing entry, we need to write the high | |
353 | * word first! If the mask bit in the low word is clear, we will enable | |
354 | * the interrupt, and we need to make sure the entry is fully populated | |
355 | * before that happens. | |
356 | */ | |
d15512f4 AK |
357 | static void |
358 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 359 | { |
50a8d4d2 F |
360 | union entry_union eu = {{0, 0}}; |
361 | ||
cf4c6a2f | 362 | eu.entry = e; |
f9dadfa7 LT |
363 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
364 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
365 | } |
366 | ||
1a8ce7ff | 367 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
368 | { |
369 | unsigned long flags; | |
dade7716 | 370 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 371 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 372 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
373 | } |
374 | ||
375 | /* | |
376 | * When we mask an IO APIC routing entry, we need to write the low | |
377 | * word first, in order to set the mask bit before we change the | |
378 | * high bits! | |
379 | */ | |
380 | static void ioapic_mask_entry(int apic, int pin) | |
381 | { | |
382 | unsigned long flags; | |
383 | union entry_union eu = { .entry.mask = 1 }; | |
384 | ||
dade7716 | 385 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
386 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
387 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 388 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
389 | } |
390 | ||
1da177e4 LT |
391 | /* |
392 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
393 | * shared ISA-space IRQs, so we have to support them. We are super | |
394 | * fast in the common case, and fast for shared ISA-space IRQs. | |
395 | */ | |
f3d1915a | 396 | static int |
7e495529 | 397 | __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 398 | { |
2977fb3f | 399 | struct irq_pin_list **last, *entry; |
0f978f45 | 400 | |
2977fb3f CG |
401 | /* don't allow duplicates */ |
402 | last = &cfg->irq_2_pin; | |
403 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 404 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 405 | return 0; |
2977fb3f | 406 | last = &entry->next; |
1da177e4 | 407 | } |
0f978f45 | 408 | |
7e495529 | 409 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 410 | if (!entry) { |
f3d1915a CG |
411 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
412 | node, apic, pin); | |
413 | return -ENOMEM; | |
a7428cd2 | 414 | } |
1da177e4 LT |
415 | entry->apic = apic; |
416 | entry->pin = pin; | |
875e68ec | 417 | |
2977fb3f | 418 | *last = entry; |
f3d1915a CG |
419 | return 0; |
420 | } | |
421 | ||
422 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
423 | { | |
7e495529 | 424 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 425 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
426 | } |
427 | ||
428 | /* | |
429 | * Reroute an IRQ to a different pin. | |
430 | */ | |
85ac16d0 | 431 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
432 | int oldapic, int oldpin, |
433 | int newapic, int newpin) | |
1da177e4 | 434 | { |
535b6429 | 435 | struct irq_pin_list *entry; |
1da177e4 | 436 | |
2977fb3f | 437 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
438 | if (entry->apic == oldapic && entry->pin == oldpin) { |
439 | entry->apic = newapic; | |
440 | entry->pin = newpin; | |
0f978f45 | 441 | /* every one is different, right? */ |
4eea6fff | 442 | return; |
0f978f45 | 443 | } |
1da177e4 | 444 | } |
0f978f45 | 445 | |
4eea6fff JF |
446 | /* old apic/pin didn't exist, so just add new ones */ |
447 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
448 | } |
449 | ||
c29d9db3 SS |
450 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
451 | int mask_and, int mask_or, | |
452 | void (*final)(struct irq_pin_list *entry)) | |
453 | { | |
454 | unsigned int reg, pin; | |
455 | ||
456 | pin = entry->pin; | |
457 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
458 | reg &= mask_and; | |
459 | reg |= mask_or; | |
460 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
461 | if (final) | |
462 | final(entry); | |
463 | } | |
464 | ||
2f210deb JF |
465 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
466 | int mask_and, int mask_or, | |
467 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 468 | { |
87783be4 | 469 | struct irq_pin_list *entry; |
047c8fdb | 470 | |
c29d9db3 SS |
471 | for_each_irq_pin(entry, cfg->irq_2_pin) |
472 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
473 | } | |
474 | ||
475 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
476 | { | |
477 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
478 | IO_APIC_REDIR_MASKED, NULL); | |
479 | } | |
480 | ||
481 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
482 | { | |
483 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
484 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 485 | } |
047c8fdb | 486 | |
7f3e632f | 487 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 488 | { |
87783be4 CG |
489 | /* |
490 | * Synchronize the IO-APIC and the CPU by doing | |
491 | * a dummy read from the IO-APIC | |
492 | */ | |
493 | struct io_apic __iomem *io_apic; | |
494 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 495 | readl(&io_apic->data); |
1da177e4 LT |
496 | } |
497 | ||
dd5f15e5 | 498 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 499 | { |
dd5f15e5 TG |
500 | unsigned long flags; |
501 | ||
502 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 503 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 504 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 505 | } |
1da177e4 | 506 | |
90297c5f | 507 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 508 | { |
90297c5f | 509 | mask_ioapic(data->chip_data); |
dd5f15e5 | 510 | } |
3145e941 | 511 | |
dd5f15e5 TG |
512 | static void __unmask_ioapic(struct irq_cfg *cfg) |
513 | { | |
514 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
515 | } |
516 | ||
dd5f15e5 | 517 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
518 | { |
519 | unsigned long flags; | |
520 | ||
dade7716 | 521 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 522 | __unmask_ioapic(cfg); |
dade7716 | 523 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
524 | } |
525 | ||
90297c5f | 526 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 527 | { |
90297c5f | 528 | unmask_ioapic(data->chip_data); |
3145e941 YL |
529 | } |
530 | ||
1da177e4 LT |
531 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
532 | { | |
533 | struct IO_APIC_route_entry entry; | |
36062448 | 534 | |
1da177e4 | 535 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 536 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
537 | if (entry.delivery_mode == dest_SMI) |
538 | return; | |
1da177e4 LT |
539 | /* |
540 | * Disable it in the IO-APIC irq-routing table: | |
541 | */ | |
f9dadfa7 | 542 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
543 | } |
544 | ||
54168ed7 | 545 | static void clear_IO_APIC (void) |
1da177e4 LT |
546 | { |
547 | int apic, pin; | |
548 | ||
549 | for (apic = 0; apic < nr_ioapics; apic++) | |
550 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
551 | clear_IO_APIC_pin(apic, pin); | |
552 | } | |
553 | ||
54168ed7 | 554 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
555 | /* |
556 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
557 | * specific CPU-side IRQs. | |
558 | */ | |
559 | ||
560 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
561 | static int pirq_entries[MAX_PIRQS] = { |
562 | [0 ... MAX_PIRQS - 1] = -1 | |
563 | }; | |
1da177e4 | 564 | |
1da177e4 LT |
565 | static int __init ioapic_pirq_setup(char *str) |
566 | { | |
567 | int i, max; | |
568 | int ints[MAX_PIRQS+1]; | |
569 | ||
570 | get_options(str, ARRAY_SIZE(ints), ints); | |
571 | ||
1da177e4 LT |
572 | apic_printk(APIC_VERBOSE, KERN_INFO |
573 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
574 | max = MAX_PIRQS; | |
575 | if (ints[0] < MAX_PIRQS) | |
576 | max = ints[0]; | |
577 | ||
578 | for (i = 0; i < max; i++) { | |
579 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
580 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
581 | /* | |
582 | * PIRQs are mapped upside down, usually. | |
583 | */ | |
584 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
585 | } | |
586 | return 1; | |
587 | } | |
588 | ||
589 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
590 | #endif /* CONFIG_X86_32 */ |
591 | ||
b24696bc FY |
592 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
593 | { | |
594 | int apic; | |
595 | struct IO_APIC_route_entry **ioapic_entries; | |
596 | ||
597 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
2ee39065 | 598 | GFP_KERNEL); |
b24696bc FY |
599 | if (!ioapic_entries) |
600 | return 0; | |
601 | ||
602 | for (apic = 0; apic < nr_ioapics; apic++) { | |
603 | ioapic_entries[apic] = | |
604 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
2ee39065 | 605 | nr_ioapic_registers[apic], GFP_KERNEL); |
b24696bc FY |
606 | if (!ioapic_entries[apic]) |
607 | goto nomem; | |
608 | } | |
609 | ||
610 | return ioapic_entries; | |
611 | ||
612 | nomem: | |
613 | while (--apic >= 0) | |
614 | kfree(ioapic_entries[apic]); | |
615 | kfree(ioapic_entries); | |
616 | ||
617 | return 0; | |
618 | } | |
54168ed7 IM |
619 | |
620 | /* | |
05c3dc2c | 621 | * Saves all the IO-APIC RTE's |
54168ed7 | 622 | */ |
b24696bc | 623 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 624 | { |
54168ed7 IM |
625 | int apic, pin; |
626 | ||
b24696bc FY |
627 | if (!ioapic_entries) |
628 | return -ENOMEM; | |
54168ed7 IM |
629 | |
630 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
631 | if (!ioapic_entries[apic]) |
632 | return -ENOMEM; | |
54168ed7 | 633 | |
05c3dc2c | 634 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 635 | ioapic_entries[apic][pin] = |
54168ed7 | 636 | ioapic_read_entry(apic, pin); |
b24696bc | 637 | } |
5ffa4eb2 | 638 | |
54168ed7 IM |
639 | return 0; |
640 | } | |
641 | ||
b24696bc FY |
642 | /* |
643 | * Mask all IO APIC entries. | |
644 | */ | |
645 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
646 | { |
647 | int apic, pin; | |
648 | ||
b24696bc FY |
649 | if (!ioapic_entries) |
650 | return; | |
651 | ||
05c3dc2c | 652 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 653 | if (!ioapic_entries[apic]) |
05c3dc2c | 654 | break; |
b24696bc | 655 | |
05c3dc2c SS |
656 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
657 | struct IO_APIC_route_entry entry; | |
658 | ||
b24696bc | 659 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
660 | if (!entry.mask) { |
661 | entry.mask = 1; | |
662 | ioapic_write_entry(apic, pin, entry); | |
663 | } | |
664 | } | |
665 | } | |
666 | } | |
667 | ||
b24696bc FY |
668 | /* |
669 | * Restore IO APIC entries which was saved in ioapic_entries. | |
670 | */ | |
671 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
672 | { |
673 | int apic, pin; | |
674 | ||
b24696bc FY |
675 | if (!ioapic_entries) |
676 | return -ENOMEM; | |
677 | ||
5ffa4eb2 | 678 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
679 | if (!ioapic_entries[apic]) |
680 | return -ENOMEM; | |
681 | ||
54168ed7 IM |
682 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
683 | ioapic_write_entry(apic, pin, | |
b24696bc | 684 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 685 | } |
b24696bc | 686 | return 0; |
54168ed7 IM |
687 | } |
688 | ||
b24696bc FY |
689 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
690 | { | |
691 | int apic; | |
692 | ||
693 | for (apic = 0; apic < nr_ioapics; apic++) | |
694 | kfree(ioapic_entries[apic]); | |
695 | ||
696 | kfree(ioapic_entries); | |
54168ed7 | 697 | } |
1da177e4 LT |
698 | |
699 | /* | |
700 | * Find the IRQ entry number of a certain pin. | |
701 | */ | |
702 | static int find_irq_entry(int apic, int pin, int type) | |
703 | { | |
704 | int i; | |
705 | ||
706 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
707 | if (mp_irqs[i].irqtype == type && |
708 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
709 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
710 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
711 | return i; |
712 | ||
713 | return -1; | |
714 | } | |
715 | ||
716 | /* | |
717 | * Find the pin to which IRQ[irq] (ISA) is connected | |
718 | */ | |
fcfd636a | 719 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
720 | { |
721 | int i; | |
722 | ||
723 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 724 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 725 | |
d27e2b8e | 726 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
727 | (mp_irqs[i].irqtype == type) && |
728 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 729 | |
c2c21745 | 730 | return mp_irqs[i].dstirq; |
1da177e4 LT |
731 | } |
732 | return -1; | |
733 | } | |
734 | ||
fcfd636a EB |
735 | static int __init find_isa_irq_apic(int irq, int type) |
736 | { | |
737 | int i; | |
738 | ||
739 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 740 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 741 | |
73b2961b | 742 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
743 | (mp_irqs[i].irqtype == type) && |
744 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
745 | break; |
746 | } | |
747 | if (i < mp_irq_entries) { | |
748 | int apic; | |
54168ed7 | 749 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 750 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
751 | return apic; |
752 | } | |
753 | } | |
754 | ||
755 | return -1; | |
756 | } | |
757 | ||
c0a282c2 | 758 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
759 | /* |
760 | * EISA Edge/Level control register, ELCR | |
761 | */ | |
762 | static int EISA_ELCR(unsigned int irq) | |
763 | { | |
b81bb373 | 764 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
765 | unsigned int port = 0x4d0 + (irq >> 3); |
766 | return (inb(port) >> (irq & 7)) & 1; | |
767 | } | |
768 | apic_printk(APIC_VERBOSE, KERN_INFO | |
769 | "Broken MPtable reports ISA irq %d\n", irq); | |
770 | return 0; | |
771 | } | |
54168ed7 | 772 | |
c0a282c2 | 773 | #endif |
1da177e4 | 774 | |
6728801d AS |
775 | /* ISA interrupts are always polarity zero edge triggered, |
776 | * when listed as conforming in the MP table. */ | |
777 | ||
778 | #define default_ISA_trigger(idx) (0) | |
779 | #define default_ISA_polarity(idx) (0) | |
780 | ||
1da177e4 LT |
781 | /* EISA interrupts are always polarity zero and can be edge or level |
782 | * trigger depending on the ELCR value. If an interrupt is listed as | |
783 | * EISA conforming in the MP table, that means its trigger type must | |
784 | * be read in from the ELCR */ | |
785 | ||
c2c21745 | 786 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 787 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
788 | |
789 | /* PCI interrupts are always polarity one level triggered, | |
790 | * when listed as conforming in the MP table. */ | |
791 | ||
792 | #define default_PCI_trigger(idx) (1) | |
793 | #define default_PCI_polarity(idx) (1) | |
794 | ||
795 | /* MCA interrupts are always polarity zero level triggered, | |
796 | * when listed as conforming in the MP table. */ | |
797 | ||
798 | #define default_MCA_trigger(idx) (1) | |
6728801d | 799 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 800 | |
61fd47e0 | 801 | static int MPBIOS_polarity(int idx) |
1da177e4 | 802 | { |
c2c21745 | 803 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
804 | int polarity; |
805 | ||
806 | /* | |
807 | * Determine IRQ line polarity (high active or low active): | |
808 | */ | |
c2c21745 | 809 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 810 | { |
54168ed7 IM |
811 | case 0: /* conforms, ie. bus-type dependent polarity */ |
812 | if (test_bit(bus, mp_bus_not_pci)) | |
813 | polarity = default_ISA_polarity(idx); | |
814 | else | |
815 | polarity = default_PCI_polarity(idx); | |
816 | break; | |
817 | case 1: /* high active */ | |
818 | { | |
819 | polarity = 0; | |
820 | break; | |
821 | } | |
822 | case 2: /* reserved */ | |
823 | { | |
824 | printk(KERN_WARNING "broken BIOS!!\n"); | |
825 | polarity = 1; | |
826 | break; | |
827 | } | |
828 | case 3: /* low active */ | |
829 | { | |
830 | polarity = 1; | |
831 | break; | |
832 | } | |
833 | default: /* invalid */ | |
834 | { | |
835 | printk(KERN_WARNING "broken BIOS!!\n"); | |
836 | polarity = 1; | |
837 | break; | |
838 | } | |
1da177e4 LT |
839 | } |
840 | return polarity; | |
841 | } | |
842 | ||
843 | static int MPBIOS_trigger(int idx) | |
844 | { | |
c2c21745 | 845 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
846 | int trigger; |
847 | ||
848 | /* | |
849 | * Determine IRQ trigger mode (edge or level sensitive): | |
850 | */ | |
c2c21745 | 851 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 852 | { |
54168ed7 IM |
853 | case 0: /* conforms, ie. bus-type dependent */ |
854 | if (test_bit(bus, mp_bus_not_pci)) | |
855 | trigger = default_ISA_trigger(idx); | |
856 | else | |
857 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 858 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
859 | switch (mp_bus_id_to_type[bus]) { |
860 | case MP_BUS_ISA: /* ISA pin */ | |
861 | { | |
862 | /* set before the switch */ | |
863 | break; | |
864 | } | |
865 | case MP_BUS_EISA: /* EISA pin */ | |
866 | { | |
867 | trigger = default_EISA_trigger(idx); | |
868 | break; | |
869 | } | |
870 | case MP_BUS_PCI: /* PCI pin */ | |
871 | { | |
872 | /* set before the switch */ | |
873 | break; | |
874 | } | |
875 | case MP_BUS_MCA: /* MCA pin */ | |
876 | { | |
877 | trigger = default_MCA_trigger(idx); | |
878 | break; | |
879 | } | |
880 | default: | |
881 | { | |
882 | printk(KERN_WARNING "broken BIOS!!\n"); | |
883 | trigger = 1; | |
884 | break; | |
885 | } | |
886 | } | |
887 | #endif | |
1da177e4 | 888 | break; |
54168ed7 | 889 | case 1: /* edge */ |
1da177e4 | 890 | { |
54168ed7 | 891 | trigger = 0; |
1da177e4 LT |
892 | break; |
893 | } | |
54168ed7 | 894 | case 2: /* reserved */ |
1da177e4 | 895 | { |
54168ed7 IM |
896 | printk(KERN_WARNING "broken BIOS!!\n"); |
897 | trigger = 1; | |
1da177e4 LT |
898 | break; |
899 | } | |
54168ed7 | 900 | case 3: /* level */ |
1da177e4 | 901 | { |
54168ed7 | 902 | trigger = 1; |
1da177e4 LT |
903 | break; |
904 | } | |
54168ed7 | 905 | default: /* invalid */ |
1da177e4 LT |
906 | { |
907 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 908 | trigger = 0; |
1da177e4 LT |
909 | break; |
910 | } | |
911 | } | |
912 | return trigger; | |
913 | } | |
914 | ||
915 | static inline int irq_polarity(int idx) | |
916 | { | |
917 | return MPBIOS_polarity(idx); | |
918 | } | |
919 | ||
920 | static inline int irq_trigger(int idx) | |
921 | { | |
922 | return MPBIOS_trigger(idx); | |
923 | } | |
924 | ||
925 | static int pin_2_irq(int idx, int apic, int pin) | |
926 | { | |
d464207c | 927 | int irq; |
c2c21745 | 928 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
929 | |
930 | /* | |
931 | * Debugging check, we are in big trouble if this message pops up! | |
932 | */ | |
c2c21745 | 933 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
934 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
935 | ||
54168ed7 | 936 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 937 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 938 | } else { |
d464207c | 939 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
940 | |
941 | if (gsi >= NR_IRQS_LEGACY) | |
942 | irq = gsi; | |
943 | else | |
a4384df3 | 944 | irq = gsi_top + gsi; |
1da177e4 LT |
945 | } |
946 | ||
54168ed7 | 947 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
948 | /* |
949 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
950 | */ | |
951 | if ((pin >= 16) && (pin <= 23)) { | |
952 | if (pirq_entries[pin-16] != -1) { | |
953 | if (!pirq_entries[pin-16]) { | |
954 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
955 | "disabling PIRQ%d\n", pin-16); | |
956 | } else { | |
957 | irq = pirq_entries[pin-16]; | |
958 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
959 | "using PIRQ%d -> IRQ %d\n", | |
960 | pin-16, irq); | |
961 | } | |
962 | } | |
963 | } | |
54168ed7 IM |
964 | #endif |
965 | ||
1da177e4 LT |
966 | return irq; |
967 | } | |
968 | ||
e20c06fd YL |
969 | /* |
970 | * Find a specific PCI IRQ entry. | |
971 | * Not an __init, possibly needed by modules | |
972 | */ | |
973 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 974 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
975 | { |
976 | int apic, i, best_guess = -1; | |
977 | ||
978 | apic_printk(APIC_DEBUG, | |
979 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
980 | bus, slot, pin); | |
981 | if (test_bit(bus, mp_bus_not_pci)) { | |
982 | apic_printk(APIC_VERBOSE, | |
983 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
984 | return -1; | |
985 | } | |
986 | for (i = 0; i < mp_irq_entries; i++) { | |
987 | int lbus = mp_irqs[i].srcbus; | |
988 | ||
989 | for (apic = 0; apic < nr_ioapics; apic++) | |
990 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
991 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
992 | break; | |
993 | ||
994 | if (!test_bit(lbus, mp_bus_not_pci) && | |
995 | !mp_irqs[i].irqtype && | |
996 | (bus == lbus) && | |
997 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
998 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
999 | ||
1000 | if (!(apic || IO_APIC_IRQ(irq))) | |
1001 | continue; | |
1002 | ||
1003 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1004 | set_io_apic_irq_attr(irq_attr, apic, |
1005 | mp_irqs[i].dstirq, | |
1006 | irq_trigger(i), | |
1007 | irq_polarity(i)); | |
e20c06fd YL |
1008 | return irq; |
1009 | } | |
1010 | /* | |
1011 | * Use the first all-but-pin matching entry as a | |
1012 | * best-guess fuzzy result for broken mptables. | |
1013 | */ | |
1014 | if (best_guess < 0) { | |
e5198075 YL |
1015 | set_io_apic_irq_attr(irq_attr, apic, |
1016 | mp_irqs[i].dstirq, | |
1017 | irq_trigger(i), | |
1018 | irq_polarity(i)); | |
e20c06fd YL |
1019 | best_guess = irq; |
1020 | } | |
1021 | } | |
1022 | } | |
1023 | return best_guess; | |
1024 | } | |
1025 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1026 | ||
497c9a19 YL |
1027 | void lock_vector_lock(void) |
1028 | { | |
1029 | /* Used to the online set of cpus does not change | |
1030 | * during assign_irq_vector. | |
1031 | */ | |
dade7716 | 1032 | raw_spin_lock(&vector_lock); |
497c9a19 | 1033 | } |
1da177e4 | 1034 | |
497c9a19 | 1035 | void unlock_vector_lock(void) |
1da177e4 | 1036 | { |
dade7716 | 1037 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1038 | } |
1da177e4 | 1039 | |
e7986739 MT |
1040 | static int |
1041 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1042 | { |
047c8fdb YL |
1043 | /* |
1044 | * NOTE! The local APIC isn't very good at handling | |
1045 | * multiple interrupts at the same interrupt level. | |
1046 | * As the interrupt level is determined by taking the | |
1047 | * vector number and shifting that right by 4, we | |
1048 | * want to spread these out a bit so that they don't | |
1049 | * all fall in the same interrupt level. | |
1050 | * | |
1051 | * Also, we've got to be careful not to trash gate | |
1052 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1053 | */ | |
6579b474 | 1054 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1055 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1056 | unsigned int old_vector; |
22f65d31 MT |
1057 | int cpu, err; |
1058 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1059 | |
23359a88 | 1060 | if (cfg->move_in_progress) |
54168ed7 | 1061 | return -EBUSY; |
0a1ad60d | 1062 | |
22f65d31 MT |
1063 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1064 | return -ENOMEM; | |
ace80ab7 | 1065 | |
54168ed7 IM |
1066 | old_vector = cfg->vector; |
1067 | if (old_vector) { | |
22f65d31 MT |
1068 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1069 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1070 | if (!cpumask_empty(tmp_mask)) { | |
1071 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1072 | return 0; |
22f65d31 | 1073 | } |
54168ed7 | 1074 | } |
497c9a19 | 1075 | |
e7986739 | 1076 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1077 | err = -ENOSPC; |
1078 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1079 | int new_cpu; |
1080 | int vector, offset; | |
497c9a19 | 1081 | |
e2d40b18 | 1082 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1083 | |
54168ed7 IM |
1084 | vector = current_vector; |
1085 | offset = current_offset; | |
497c9a19 | 1086 | next: |
54168ed7 IM |
1087 | vector += 8; |
1088 | if (vector >= first_system_vector) { | |
e7986739 | 1089 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1090 | offset = (offset + 1) % 8; |
6579b474 | 1091 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1092 | } |
1093 | if (unlikely(current_vector == vector)) | |
1094 | continue; | |
b77b881f YL |
1095 | |
1096 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1097 | goto next; |
b77b881f | 1098 | |
22f65d31 | 1099 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1100 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1101 | goto next; | |
1102 | /* Found one! */ | |
1103 | current_vector = vector; | |
1104 | current_offset = offset; | |
1105 | if (old_vector) { | |
1106 | cfg->move_in_progress = 1; | |
22f65d31 | 1107 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1108 | } |
22f65d31 | 1109 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1110 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1111 | cfg->vector = vector; | |
22f65d31 MT |
1112 | cpumask_copy(cfg->domain, tmp_mask); |
1113 | err = 0; | |
1114 | break; | |
54168ed7 | 1115 | } |
22f65d31 MT |
1116 | free_cpumask_var(tmp_mask); |
1117 | return err; | |
497c9a19 YL |
1118 | } |
1119 | ||
9338ad6f | 1120 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1121 | { |
1122 | int err; | |
ace80ab7 | 1123 | unsigned long flags; |
ace80ab7 | 1124 | |
dade7716 | 1125 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1126 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1127 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1128 | return err; |
1129 | } | |
1130 | ||
3145e941 | 1131 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1132 | { |
497c9a19 YL |
1133 | int cpu, vector; |
1134 | ||
497c9a19 YL |
1135 | BUG_ON(!cfg->vector); |
1136 | ||
1137 | vector = cfg->vector; | |
22f65d31 | 1138 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1139 | per_cpu(vector_irq, cpu)[vector] = -1; |
1140 | ||
1141 | cfg->vector = 0; | |
22f65d31 | 1142 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1143 | |
1144 | if (likely(!cfg->move_in_progress)) | |
1145 | return; | |
22f65d31 | 1146 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1147 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1148 | vector++) { | |
1149 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1150 | continue; | |
1151 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1152 | break; | |
1153 | } | |
1154 | } | |
1155 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1156 | } |
1157 | ||
1158 | void __setup_vector_irq(int cpu) | |
1159 | { | |
1160 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1161 | int irq, vector; |
1162 | struct irq_cfg *cfg; | |
1163 | ||
9d133e5d SS |
1164 | /* |
1165 | * vector_lock will make sure that we don't run into irq vector | |
1166 | * assignments that might be happening on another cpu in parallel, | |
1167 | * while we setup our initial vector to irq mappings. | |
1168 | */ | |
dade7716 | 1169 | raw_spin_lock(&vector_lock); |
497c9a19 | 1170 | /* Mark the inuse vectors */ |
ad9f4334 TG |
1171 | for_each_active_irq(irq) { |
1172 | cfg = get_irq_chip_data(irq); | |
1173 | if (!cfg) | |
1174 | continue; | |
36e9e1ea SS |
1175 | /* |
1176 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1177 | * will be part of the irq_cfg's domain. | |
1178 | */ | |
1179 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1180 | cpumask_set_cpu(cpu, cfg->domain); | |
1181 | ||
22f65d31 | 1182 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1183 | continue; |
1184 | vector = cfg->vector; | |
497c9a19 YL |
1185 | per_cpu(vector_irq, cpu)[vector] = irq; |
1186 | } | |
1187 | /* Mark the free vectors */ | |
1188 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1189 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1190 | if (irq < 0) | |
1191 | continue; | |
1192 | ||
1193 | cfg = irq_cfg(irq); | |
22f65d31 | 1194 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1195 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1196 | } |
dade7716 | 1197 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1198 | } |
3fde6900 | 1199 | |
f5b9ed7a | 1200 | static struct irq_chip ioapic_chip; |
54168ed7 | 1201 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1202 | |
54168ed7 IM |
1203 | #define IOAPIC_AUTO -1 |
1204 | #define IOAPIC_EDGE 0 | |
1205 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1206 | |
047c8fdb | 1207 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1208 | static inline int IO_APIC_irq_trigger(int irq) |
1209 | { | |
d6c88a50 | 1210 | int apic, idx, pin; |
1d025192 | 1211 | |
d6c88a50 TG |
1212 | for (apic = 0; apic < nr_ioapics; apic++) { |
1213 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1214 | idx = find_irq_entry(apic, pin, mp_INT); | |
1215 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1216 | return irq_trigger(idx); | |
1217 | } | |
1218 | } | |
1219 | /* | |
54168ed7 IM |
1220 | * nonexistent IRQs are edge default |
1221 | */ | |
d6c88a50 | 1222 | return 0; |
1d025192 | 1223 | } |
047c8fdb YL |
1224 | #else |
1225 | static inline int IO_APIC_irq_trigger(int irq) | |
1226 | { | |
54168ed7 | 1227 | return 1; |
047c8fdb YL |
1228 | } |
1229 | #endif | |
1d025192 | 1230 | |
60c69948 | 1231 | static void ioapic_register_intr(unsigned int irq, unsigned long trigger) |
1da177e4 | 1232 | { |
199751d7 | 1233 | |
6ebcc00e | 1234 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1235 | trigger == IOAPIC_LEVEL) |
60c69948 | 1236 | irq_set_status_flags(irq, IRQ_LEVEL); |
047c8fdb | 1237 | else |
60c69948 | 1238 | irq_clear_status_flags(irq, IRQ_LEVEL); |
047c8fdb | 1239 | |
1a0730d6 | 1240 | if (irq_remapped(get_irq_chip_data(irq))) { |
60c69948 | 1241 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
54168ed7 IM |
1242 | if (trigger) |
1243 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1244 | handle_fasteoi_irq, | |
1245 | "fasteoi"); | |
1246 | else | |
1247 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1248 | handle_edge_irq, "edge"); | |
1249 | return; | |
1250 | } | |
29b61be6 | 1251 | |
047c8fdb YL |
1252 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1253 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1254 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1255 | handle_fasteoi_irq, |
1256 | "fasteoi"); | |
047c8fdb | 1257 | else |
a460e745 | 1258 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1259 | handle_edge_irq, "edge"); |
1da177e4 LT |
1260 | } |
1261 | ||
1a8ce7ff TG |
1262 | static int setup_ioapic_entry(int apic_id, int irq, |
1263 | struct IO_APIC_route_entry *entry, | |
1264 | unsigned int destination, int trigger, | |
1265 | int polarity, int vector, int pin) | |
1da177e4 | 1266 | { |
497c9a19 YL |
1267 | /* |
1268 | * add it to the IO-APIC irq-routing table: | |
1269 | */ | |
1270 | memset(entry,0,sizeof(*entry)); | |
1271 | ||
54168ed7 | 1272 | if (intr_remapping_enabled) { |
c8d46cf0 | 1273 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1274 | struct irte irte; |
1275 | struct IR_IO_APIC_route_entry *ir_entry = | |
1276 | (struct IR_IO_APIC_route_entry *) entry; | |
1277 | int index; | |
1278 | ||
1279 | if (!iommu) | |
c8d46cf0 | 1280 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1281 | |
1282 | index = alloc_irte(iommu, irq, 1); | |
1283 | if (index < 0) | |
c8d46cf0 | 1284 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1285 | |
62a92f4c | 1286 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1287 | |
f007e99c WH |
1288 | /* Set source-id of interrupt request */ |
1289 | set_ioapic_sid(&irte, apic_id); | |
1290 | ||
54168ed7 IM |
1291 | modify_irte(irq, &irte); |
1292 | ||
1293 | ir_entry->index2 = (index >> 15) & 0x1; | |
1294 | ir_entry->zero = 0; | |
1295 | ir_entry->format = 1; | |
1296 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1297 | /* |
1298 | * IO-APIC RTE will be configured with virtual vector. | |
1299 | * irq handler will do the explicit EOI to the io-apic. | |
1300 | */ | |
1301 | ir_entry->vector = pin; | |
29b61be6 | 1302 | } else { |
9b5bc8dc IM |
1303 | entry->delivery_mode = apic->irq_delivery_mode; |
1304 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1305 | entry->dest = destination; |
0280f7c4 | 1306 | entry->vector = vector; |
54168ed7 | 1307 | } |
497c9a19 | 1308 | |
54168ed7 | 1309 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1310 | entry->trigger = trigger; |
1311 | entry->polarity = polarity; | |
497c9a19 YL |
1312 | |
1313 | /* Mask level triggered irqs. | |
1314 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1315 | */ | |
1316 | if (trigger) | |
1317 | entry->mask = 1; | |
497c9a19 YL |
1318 | return 0; |
1319 | } | |
1320 | ||
60c69948 TG |
1321 | static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, |
1322 | struct irq_cfg *cfg, int trigger, int polarity) | |
497c9a19 | 1323 | { |
1da177e4 | 1324 | struct IO_APIC_route_entry entry; |
22f65d31 | 1325 | unsigned int dest; |
497c9a19 YL |
1326 | |
1327 | if (!IO_APIC_IRQ(irq)) | |
1328 | return; | |
69c89efb SS |
1329 | /* |
1330 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1331 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1332 | * the cfg->domain. | |
1333 | */ | |
28c6a0ba | 1334 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1335 | apic->vector_allocation_domain(0, cfg->domain); |
1336 | ||
fe402e1f | 1337 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1338 | return; |
1339 | ||
debccb3e | 1340 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1341 | |
1342 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1343 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1344 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1345 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1346 | irq, trigger, polarity); |
1347 | ||
1348 | ||
c8d46cf0 | 1349 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1350 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1351 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1352 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1353 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1354 | return; |
1355 | } | |
1356 | ||
60c69948 | 1357 | ioapic_register_intr(irq, trigger); |
b81bb373 | 1358 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1359 | legacy_pic->mask(irq); |
497c9a19 | 1360 | |
c8d46cf0 | 1361 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1362 | } |
1363 | ||
b9c61b70 YL |
1364 | static struct { |
1365 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1366 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1367 | ||
497c9a19 YL |
1368 | static void __init setup_IO_APIC_irqs(void) |
1369 | { | |
fbc6bff0 | 1370 | int apic_id, pin, idx, irq, notcon = 0; |
f6e9456c | 1371 | int node = cpu_to_node(0); |
fbc6bff0 | 1372 | struct irq_cfg *cfg; |
1da177e4 LT |
1373 | |
1374 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1375 | ||
fad53995 | 1376 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1377 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1378 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1379 | if (idx == -1) { | |
1380 | if (!notcon) { | |
1381 | notcon = 1; | |
1382 | apic_printk(APIC_VERBOSE, | |
1383 | KERN_DEBUG " %d-%d", | |
1384 | mp_ioapics[apic_id].apicid, pin); | |
1385 | } else | |
1386 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1387 | mp_ioapics[apic_id].apicid, pin); | |
1388 | continue; | |
1389 | } | |
1390 | if (notcon) { | |
1391 | apic_printk(APIC_VERBOSE, | |
1392 | " (apicid-pin) not connected\n"); | |
1393 | notcon = 0; | |
1394 | } | |
33a201fa | 1395 | |
b9c61b70 | 1396 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1397 | |
fad53995 EB |
1398 | if ((apic_id > 0) && (irq > 16)) |
1399 | continue; | |
1400 | ||
b9c61b70 YL |
1401 | /* |
1402 | * Skip the timer IRQ if there's a quirk handler | |
1403 | * installed and if it returns 1: | |
1404 | */ | |
1405 | if (apic->multi_timer_check && | |
1406 | apic->multi_timer_check(apic_id, irq)) | |
1407 | continue; | |
36062448 | 1408 | |
fbc6bff0 TG |
1409 | cfg = alloc_irq_and_cfg_at(irq, node); |
1410 | if (!cfg) | |
b9c61b70 | 1411 | continue; |
fbc6bff0 | 1412 | |
b9c61b70 | 1413 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
4c6f18fc YL |
1414 | /* |
1415 | * don't mark it in pin_programmed, so later acpi could | |
1416 | * set it correctly when irq < 16 | |
1417 | */ | |
60c69948 TG |
1418 | setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx), |
1419 | irq_polarity(idx)); | |
1da177e4 LT |
1420 | } |
1421 | ||
3c2cbd24 CG |
1422 | if (notcon) |
1423 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1424 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1425 | } |
1426 | ||
18dce6ba YL |
1427 | /* |
1428 | * for the gsit that is not in first ioapic | |
1429 | * but could not use acpi_register_gsi() | |
1430 | * like some special sci in IBM x3330 | |
1431 | */ | |
1432 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1433 | { | |
fbc6bff0 | 1434 | int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); |
18dce6ba YL |
1435 | struct irq_cfg *cfg; |
1436 | ||
1437 | /* | |
1438 | * Convert 'gsi' to 'ioapic.pin'. | |
1439 | */ | |
1440 | apic_id = mp_find_ioapic(gsi); | |
1441 | if (apic_id < 0) | |
1442 | return; | |
1443 | ||
1444 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1445 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1446 | if (idx == -1) | |
1447 | return; | |
1448 | ||
1449 | irq = pin_2_irq(idx, apic_id, pin); | |
fe6dab4e YL |
1450 | |
1451 | /* Only handle the non legacy irqs on secondary ioapics */ | |
1452 | if (apic_id == 0 || irq < NR_IRQS_LEGACY) | |
18dce6ba | 1453 | return; |
fe6dab4e | 1454 | |
fbc6bff0 TG |
1455 | cfg = alloc_irq_and_cfg_at(irq, node); |
1456 | if (!cfg) | |
18dce6ba | 1457 | return; |
18dce6ba | 1458 | |
18dce6ba YL |
1459 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
1460 | ||
1461 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1462 | pr_debug("Pin %d-%d already programmed\n", | |
1463 | mp_ioapics[apic_id].apicid, pin); | |
1464 | return; | |
1465 | } | |
1466 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1467 | ||
60c69948 | 1468 | setup_ioapic_irq(apic_id, pin, irq, cfg, |
18dce6ba YL |
1469 | irq_trigger(idx), irq_polarity(idx)); |
1470 | } | |
1471 | ||
1da177e4 | 1472 | /* |
f7633ce5 | 1473 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1474 | */ |
c8d46cf0 | 1475 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1476 | int vector) |
1da177e4 LT |
1477 | { |
1478 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1479 | |
54168ed7 IM |
1480 | if (intr_remapping_enabled) |
1481 | return; | |
54168ed7 | 1482 | |
36062448 | 1483 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1484 | |
1485 | /* | |
1486 | * We use logical delivery to get the timer IRQ | |
1487 | * to the first CPU. | |
1488 | */ | |
9b5bc8dc | 1489 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1490 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1491 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1492 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1493 | entry.polarity = 0; |
1494 | entry.trigger = 0; | |
1495 | entry.vector = vector; | |
1496 | ||
1497 | /* | |
1498 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1499 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1500 | */ |
54168ed7 | 1501 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1502 | |
1503 | /* | |
1504 | * Add it to the IO-APIC irq-routing table: | |
1505 | */ | |
c8d46cf0 | 1506 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1507 | } |
1508 | ||
32f71aff MR |
1509 | |
1510 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1511 | { |
1512 | int apic, i; | |
1513 | union IO_APIC_reg_00 reg_00; | |
1514 | union IO_APIC_reg_01 reg_01; | |
1515 | union IO_APIC_reg_02 reg_02; | |
1516 | union IO_APIC_reg_03 reg_03; | |
1517 | unsigned long flags; | |
0f978f45 | 1518 | struct irq_cfg *cfg; |
8f09cd20 | 1519 | unsigned int irq; |
1da177e4 | 1520 | |
36062448 | 1521 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1522 | for (i = 0; i < nr_ioapics; i++) |
1523 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1524 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1525 | |
1526 | /* | |
1527 | * We are a bit conservative about what we expect. We have to | |
1528 | * know about every hardware change ASAP. | |
1529 | */ | |
1530 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1531 | ||
1532 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1533 | ||
dade7716 | 1534 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1535 | reg_00.raw = io_apic_read(apic, 0); |
1536 | reg_01.raw = io_apic_read(apic, 1); | |
1537 | if (reg_01.bits.version >= 0x10) | |
1538 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1539 | if (reg_01.bits.version >= 0x20) |
1540 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1541 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1542 | |
54168ed7 | 1543 | printk("\n"); |
b5ba7e6d | 1544 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1545 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1546 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1547 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1548 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1549 | |
54168ed7 | 1550 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1551 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1552 | |
1553 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1554 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1555 | |
1556 | /* | |
1557 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1558 | * but the value of reg_02 is read as the previous read register | |
1559 | * value, so ignore it if reg_02 == reg_01. | |
1560 | */ | |
1561 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1562 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1563 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1564 | } |
1565 | ||
1566 | /* | |
1567 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1568 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1569 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1570 | */ | |
1571 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1572 | reg_03.raw != reg_01.raw) { | |
1573 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1574 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1575 | } |
1576 | ||
1577 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1578 | ||
d83e94ac | 1579 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1580 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1581 | |
1582 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1583 | struct IO_APIC_route_entry entry; | |
1584 | ||
cf4c6a2f | 1585 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1586 | |
54168ed7 IM |
1587 | printk(KERN_DEBUG " %02x %03X ", |
1588 | i, | |
1589 | entry.dest | |
1590 | ); | |
1da177e4 LT |
1591 | |
1592 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1593 | entry.mask, | |
1594 | entry.trigger, | |
1595 | entry.irr, | |
1596 | entry.polarity, | |
1597 | entry.delivery_status, | |
1598 | entry.dest_mode, | |
1599 | entry.delivery_mode, | |
1600 | entry.vector | |
1601 | ); | |
1602 | } | |
1603 | } | |
1da177e4 | 1604 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1605 | for_each_active_irq(irq) { |
0b8f1efa YL |
1606 | struct irq_pin_list *entry; |
1607 | ||
ad9f4334 | 1608 | cfg = get_irq_chip_data(irq); |
05e40760 DK |
1609 | if (!cfg) |
1610 | continue; | |
0b8f1efa | 1611 | entry = cfg->irq_2_pin; |
0f978f45 | 1612 | if (!entry) |
1da177e4 | 1613 | continue; |
8f09cd20 | 1614 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1615 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1616 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1617 | printk("\n"); |
1618 | } | |
1619 | ||
1620 | printk(KERN_INFO ".................................... done.\n"); | |
1621 | ||
1622 | return; | |
1623 | } | |
1624 | ||
251e1e44 | 1625 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1626 | { |
251e1e44 | 1627 | int i; |
1da177e4 | 1628 | |
251e1e44 IM |
1629 | printk(KERN_DEBUG); |
1630 | ||
1631 | for (i = 0; i < 8; i++) | |
1632 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1633 | ||
1634 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1635 | } |
1636 | ||
32f71aff | 1637 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1638 | { |
97a52714 | 1639 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1640 | u64 icr; |
1da177e4 | 1641 | |
251e1e44 | 1642 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1643 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1644 | v = apic_read(APIC_ID); |
54168ed7 | 1645 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1646 | v = apic_read(APIC_LVR); |
1647 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1648 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1649 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1650 | |
1651 | v = apic_read(APIC_TASKPRI); | |
1652 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1653 | ||
54168ed7 | 1654 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1655 | if (!APIC_XAPIC(ver)) { |
1656 | v = apic_read(APIC_ARBPRI); | |
1657 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1658 | v & APIC_ARBPRI_MASK); | |
1659 | } | |
1da177e4 LT |
1660 | v = apic_read(APIC_PROCPRI); |
1661 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1662 | } | |
1663 | ||
a11b5abe YL |
1664 | /* |
1665 | * Remote read supported only in the 82489DX and local APIC for | |
1666 | * Pentium processors. | |
1667 | */ | |
1668 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1669 | v = apic_read(APIC_RRR); | |
1670 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1671 | } | |
1672 | ||
1da177e4 LT |
1673 | v = apic_read(APIC_LDR); |
1674 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1675 | if (!x2apic_enabled()) { |
1676 | v = apic_read(APIC_DFR); | |
1677 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1678 | } | |
1da177e4 LT |
1679 | v = apic_read(APIC_SPIV); |
1680 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1681 | ||
1682 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1683 | print_APIC_field(APIC_ISR); |
1da177e4 | 1684 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1685 | print_APIC_field(APIC_TMR); |
1da177e4 | 1686 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1687 | print_APIC_field(APIC_IRR); |
1da177e4 | 1688 | |
54168ed7 IM |
1689 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1690 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1691 | apic_write(APIC_ESR, 0); |
54168ed7 | 1692 | |
1da177e4 LT |
1693 | v = apic_read(APIC_ESR); |
1694 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1695 | } | |
1696 | ||
7ab6af7a | 1697 | icr = apic_icr_read(); |
0c425cec IM |
1698 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1699 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1700 | |
1701 | v = apic_read(APIC_LVTT); | |
1702 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1703 | ||
1704 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1705 | v = apic_read(APIC_LVTPC); | |
1706 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1707 | } | |
1708 | v = apic_read(APIC_LVT0); | |
1709 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1710 | v = apic_read(APIC_LVT1); | |
1711 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1712 | ||
1713 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1714 | v = apic_read(APIC_LVTERR); | |
1715 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1716 | } | |
1717 | ||
1718 | v = apic_read(APIC_TMICT); | |
1719 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1720 | v = apic_read(APIC_TMCCT); | |
1721 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1722 | v = apic_read(APIC_TDCR); | |
1723 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1724 | |
1725 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1726 | v = apic_read(APIC_EFEAT); | |
1727 | maxlvt = (v >> 16) & 0xff; | |
1728 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1729 | v = apic_read(APIC_ECTRL); | |
1730 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1731 | for (i = 0; i < maxlvt; i++) { | |
1732 | v = apic_read(APIC_EILVTn(i)); | |
1733 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1734 | } | |
1735 | } | |
1da177e4 LT |
1736 | printk("\n"); |
1737 | } | |
1738 | ||
2626eb2b | 1739 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1740 | { |
ffd5aae7 YL |
1741 | int cpu; |
1742 | ||
2626eb2b CG |
1743 | if (!maxcpu) |
1744 | return; | |
1745 | ||
ffd5aae7 | 1746 | preempt_disable(); |
2626eb2b CG |
1747 | for_each_online_cpu(cpu) { |
1748 | if (cpu >= maxcpu) | |
1749 | break; | |
ffd5aae7 | 1750 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1751 | } |
ffd5aae7 | 1752 | preempt_enable(); |
1da177e4 LT |
1753 | } |
1754 | ||
32f71aff | 1755 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1756 | { |
1da177e4 LT |
1757 | unsigned int v; |
1758 | unsigned long flags; | |
1759 | ||
b81bb373 | 1760 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1761 | return; |
1762 | ||
1763 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1764 | ||
5619c280 | 1765 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1766 | |
1767 | v = inb(0xa1) << 8 | inb(0x21); | |
1768 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1769 | ||
1770 | v = inb(0xa0) << 8 | inb(0x20); | |
1771 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1772 | ||
54168ed7 IM |
1773 | outb(0x0b,0xa0); |
1774 | outb(0x0b,0x20); | |
1da177e4 | 1775 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1776 | outb(0x0a,0xa0); |
1777 | outb(0x0a,0x20); | |
1da177e4 | 1778 | |
5619c280 | 1779 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1780 | |
1781 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1782 | ||
1783 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1784 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1785 | } | |
1786 | ||
2626eb2b CG |
1787 | static int __initdata show_lapic = 1; |
1788 | static __init int setup_show_lapic(char *arg) | |
1789 | { | |
1790 | int num = -1; | |
1791 | ||
1792 | if (strcmp(arg, "all") == 0) { | |
1793 | show_lapic = CONFIG_NR_CPUS; | |
1794 | } else { | |
1795 | get_option(&arg, &num); | |
1796 | if (num >= 0) | |
1797 | show_lapic = num; | |
1798 | } | |
1799 | ||
1800 | return 1; | |
1801 | } | |
1802 | __setup("show_lapic=", setup_show_lapic); | |
1803 | ||
1804 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1805 | { |
2626eb2b CG |
1806 | if (apic_verbosity == APIC_QUIET) |
1807 | return 0; | |
1808 | ||
32f71aff | 1809 | print_PIC(); |
4797f6b0 YL |
1810 | |
1811 | /* don't print out if apic is not there */ | |
8312136f | 1812 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1813 | return 0; |
1814 | ||
2626eb2b | 1815 | print_local_APICs(show_lapic); |
32f71aff MR |
1816 | print_IO_APIC(); |
1817 | ||
1818 | return 0; | |
1819 | } | |
1820 | ||
2626eb2b | 1821 | fs_initcall(print_ICs); |
32f71aff | 1822 | |
1da177e4 | 1823 | |
efa2559f YL |
1824 | /* Where if anywhere is the i8259 connect in external int mode */ |
1825 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1826 | ||
54168ed7 | 1827 | void __init enable_IO_APIC(void) |
1da177e4 | 1828 | { |
fcfd636a | 1829 | int i8259_apic, i8259_pin; |
54168ed7 | 1830 | int apic; |
bc07844a | 1831 | |
b81bb373 | 1832 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1833 | return; |
1834 | ||
54168ed7 | 1835 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1836 | int pin; |
1837 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1838 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1839 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1840 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1841 | |
fcfd636a EB |
1842 | /* If the interrupt line is enabled and in ExtInt mode |
1843 | * I have found the pin where the i8259 is connected. | |
1844 | */ | |
1845 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1846 | ioapic_i8259.apic = apic; | |
1847 | ioapic_i8259.pin = pin; | |
1848 | goto found_i8259; | |
1849 | } | |
1850 | } | |
1851 | } | |
1852 | found_i8259: | |
1853 | /* Look to see what if the MP table has reported the ExtINT */ | |
1854 | /* If we could not find the appropriate pin by looking at the ioapic | |
1855 | * the i8259 probably is not connected the ioapic but give the | |
1856 | * mptable a chance anyway. | |
1857 | */ | |
1858 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1859 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1860 | /* Trust the MP table if nothing is setup in the hardware */ | |
1861 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1862 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1863 | ioapic_i8259.pin = i8259_pin; | |
1864 | ioapic_i8259.apic = i8259_apic; | |
1865 | } | |
1866 | /* Complain if the MP table and the hardware disagree */ | |
1867 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1868 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1869 | { | |
1870 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1871 | } |
1872 | ||
1873 | /* | |
1874 | * Do not trust the IO-APIC being empty at bootup | |
1875 | */ | |
1876 | clear_IO_APIC(); | |
1877 | } | |
1878 | ||
1879 | /* | |
1880 | * Not an __init, needed by the reboot code | |
1881 | */ | |
1882 | void disable_IO_APIC(void) | |
1883 | { | |
1884 | /* | |
1885 | * Clear the IO-APIC before rebooting: | |
1886 | */ | |
1887 | clear_IO_APIC(); | |
1888 | ||
b81bb373 | 1889 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1890 | return; |
1891 | ||
650927ef | 1892 | /* |
0b968d23 | 1893 | * If the i8259 is routed through an IOAPIC |
650927ef | 1894 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1895 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1896 | * |
1897 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1898 | * as virtual wire B is little complex (need to configure both | |
1899 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1900 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1901 | */ |
7c6d9f97 | 1902 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1903 | struct IO_APIC_route_entry entry; |
650927ef EB |
1904 | |
1905 | memset(&entry, 0, sizeof(entry)); | |
1906 | entry.mask = 0; /* Enabled */ | |
1907 | entry.trigger = 0; /* Edge */ | |
1908 | entry.irr = 0; | |
1909 | entry.polarity = 0; /* High */ | |
1910 | entry.delivery_status = 0; | |
1911 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1912 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1913 | entry.vector = 0; |
54168ed7 | 1914 | entry.dest = read_apic_id(); |
650927ef EB |
1915 | |
1916 | /* | |
1917 | * Add it to the IO-APIC irq-routing table: | |
1918 | */ | |
cf4c6a2f | 1919 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1920 | } |
54168ed7 | 1921 | |
7c6d9f97 SS |
1922 | /* |
1923 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1924 | */ | |
8312136f | 1925 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
1926 | disconnect_bsp_APIC(!intr_remapping_enabled && |
1927 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
1928 | } |
1929 | ||
54168ed7 | 1930 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1931 | /* |
1932 | * function to set the IO-APIC physical IDs based on the | |
1933 | * values stored in the MPC table. | |
1934 | * | |
1935 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1936 | */ | |
a38c5380 | 1937 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1938 | { |
1939 | union IO_APIC_reg_00 reg_00; | |
1940 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1941 | int apic_id; |
1da177e4 LT |
1942 | int i; |
1943 | unsigned char old_id; | |
1944 | unsigned long flags; | |
1945 | ||
1946 | /* | |
1947 | * This is broken; anything with a real cpu count has to | |
1948 | * circumvent this idiocy regardless. | |
1949 | */ | |
7abc0753 | 1950 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1951 | |
1952 | /* | |
1953 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1954 | */ | |
c8d46cf0 | 1955 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
1956 | |
1957 | /* Read the register 0 value */ | |
dade7716 | 1958 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 1959 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 1960 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1961 | |
c8d46cf0 | 1962 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 1963 | |
c8d46cf0 | 1964 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 1965 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 1966 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1967 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1968 | reg_00.bits.ID); | |
c8d46cf0 | 1969 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
1970 | } |
1971 | ||
1da177e4 LT |
1972 | /* |
1973 | * Sanity check, is the ID really free? Every APIC in a | |
1974 | * system must have a unique ID or we get lots of nice | |
1975 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1976 | */ | |
7abc0753 | 1977 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 1978 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 1979 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 1980 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1981 | for (i = 0; i < get_physical_broadcast(); i++) |
1982 | if (!physid_isset(i, phys_id_present_map)) | |
1983 | break; | |
1984 | if (i >= get_physical_broadcast()) | |
1985 | panic("Max APIC ID exceeded!\n"); | |
1986 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1987 | i); | |
1988 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 1989 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
1990 | } else { |
1991 | physid_mask_t tmp; | |
7abc0753 | 1992 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
1993 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1994 | "phys_id_present_map\n", | |
c8d46cf0 | 1995 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
1996 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1997 | } | |
1998 | ||
1da177e4 LT |
1999 | /* |
2000 | * We need to adjust the IRQ routing table | |
2001 | * if the ID changed. | |
2002 | */ | |
c8d46cf0 | 2003 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2004 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2005 | if (mp_irqs[i].dstapic == old_id) |
2006 | mp_irqs[i].dstapic | |
c8d46cf0 | 2007 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2008 | |
2009 | /* | |
60d79fd9 YL |
2010 | * Update the ID register according to the right value |
2011 | * from the MPC table if they are different. | |
36062448 | 2012 | */ |
60d79fd9 YL |
2013 | if (mp_ioapics[apic_id].apicid == reg_00.bits.ID) |
2014 | continue; | |
2015 | ||
1da177e4 LT |
2016 | apic_printk(APIC_VERBOSE, KERN_INFO |
2017 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2018 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2019 | |
c8d46cf0 | 2020 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2021 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2022 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2023 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2024 | |
2025 | /* | |
2026 | * Sanity check | |
2027 | */ | |
dade7716 | 2028 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2029 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2030 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2031 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2032 | printk("could not set ID!\n"); |
2033 | else | |
2034 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2035 | } | |
2036 | } | |
a38c5380 SAS |
2037 | |
2038 | void __init setup_ioapic_ids_from_mpc(void) | |
2039 | { | |
2040 | ||
2041 | if (acpi_ioapic) | |
2042 | return; | |
2043 | /* | |
2044 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2045 | * no meaning without the serial APIC bus. | |
2046 | */ | |
2047 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2048 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2049 | return; | |
2050 | setup_ioapic_ids_from_mpc_nocheck(); | |
2051 | } | |
54168ed7 | 2052 | #endif |
1da177e4 | 2053 | |
7ce0bcfd | 2054 | int no_timer_check __initdata; |
8542b200 ZA |
2055 | |
2056 | static int __init notimercheck(char *s) | |
2057 | { | |
2058 | no_timer_check = 1; | |
2059 | return 1; | |
2060 | } | |
2061 | __setup("no_timer_check", notimercheck); | |
2062 | ||
1da177e4 LT |
2063 | /* |
2064 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2065 | * about the timer IRQ. We do the following to work around the situation: | |
2066 | * | |
2067 | * - timer IRQ defaults to IO-APIC IRQ | |
2068 | * - if this function detects that timer IRQs are defunct, then we fall | |
2069 | * back to ISA timer IRQs | |
2070 | */ | |
f0a7a5c9 | 2071 | static int __init timer_irq_works(void) |
1da177e4 LT |
2072 | { |
2073 | unsigned long t1 = jiffies; | |
4aae0702 | 2074 | unsigned long flags; |
1da177e4 | 2075 | |
8542b200 ZA |
2076 | if (no_timer_check) |
2077 | return 1; | |
2078 | ||
4aae0702 | 2079 | local_save_flags(flags); |
1da177e4 LT |
2080 | local_irq_enable(); |
2081 | /* Let ten ticks pass... */ | |
2082 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2083 | local_irq_restore(flags); |
1da177e4 LT |
2084 | |
2085 | /* | |
2086 | * Expect a few ticks at least, to be sure some possible | |
2087 | * glue logic does not lock up after one or two first | |
2088 | * ticks in a non-ExtINT mode. Also the local APIC | |
2089 | * might have cached one ExtINT interrupt. Finally, at | |
2090 | * least one tick may be lost due to delays. | |
2091 | */ | |
54168ed7 IM |
2092 | |
2093 | /* jiffies wrap? */ | |
1d16b53e | 2094 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2095 | return 1; |
1da177e4 LT |
2096 | return 0; |
2097 | } | |
2098 | ||
2099 | /* | |
2100 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2101 | * number of pending IRQ events unhandled. These cases are very rare, | |
2102 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2103 | * better to do it this way as thus we do not have to be aware of | |
2104 | * 'pending' interrupts in the IRQ path, except at this point. | |
2105 | */ | |
2106 | /* | |
2107 | * Edge triggered needs to resend any interrupt | |
2108 | * that was delayed but this is now handled in the device | |
2109 | * independent code. | |
2110 | */ | |
2111 | ||
2112 | /* | |
2113 | * Starting up a edge-triggered IO-APIC interrupt is | |
2114 | * nasty - we need to make sure that we get the edge. | |
2115 | * If it is already asserted for some reason, we need | |
2116 | * return 1 to indicate that is was pending. | |
2117 | * | |
2118 | * This is not complete - we should be able to fake | |
2119 | * an edge even if it isn't on the 8259A... | |
2120 | */ | |
54168ed7 | 2121 | |
61a38ce3 | 2122 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2123 | { |
61a38ce3 | 2124 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2125 | unsigned long flags; |
2126 | ||
dade7716 | 2127 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2128 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2129 | legacy_pic->mask(irq); |
b81bb373 | 2130 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2131 | was_pending = 1; |
2132 | } | |
61a38ce3 | 2133 | __unmask_ioapic(data->chip_data); |
dade7716 | 2134 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2135 | |
2136 | return was_pending; | |
2137 | } | |
2138 | ||
90297c5f | 2139 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2140 | { |
90297c5f | 2141 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2142 | unsigned long flags; |
2143 | ||
dade7716 | 2144 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2145 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2146 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2147 | |
2148 | return 1; | |
2149 | } | |
497c9a19 | 2150 | |
54168ed7 IM |
2151 | /* |
2152 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2153 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2154 | * handled with the level-triggered descriptor, but that one has slightly | |
2155 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2156 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2157 | * races. | |
2158 | */ | |
497c9a19 | 2159 | |
54168ed7 | 2160 | #ifdef CONFIG_SMP |
9338ad6f | 2161 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2162 | { |
2163 | cpumask_var_t cleanup_mask; | |
2164 | ||
2165 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2166 | unsigned int i; | |
e85abf8f GH |
2167 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2168 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2169 | } else { | |
2170 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2171 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2172 | free_cpumask_var(cleanup_mask); | |
2173 | } | |
2174 | cfg->move_in_progress = 0; | |
2175 | } | |
2176 | ||
4420471f | 2177 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2178 | { |
2179 | int apic, pin; | |
2180 | struct irq_pin_list *entry; | |
2181 | u8 vector = cfg->vector; | |
2182 | ||
2977fb3f | 2183 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2184 | unsigned int reg; |
2185 | ||
e85abf8f GH |
2186 | apic = entry->apic; |
2187 | pin = entry->pin; | |
2188 | /* | |
2189 | * With interrupt-remapping, destination information comes | |
2190 | * from interrupt-remapping table entry. | |
2191 | */ | |
1a0730d6 | 2192 | if (!irq_remapped(cfg)) |
e85abf8f GH |
2193 | io_apic_write(apic, 0x11 + pin*2, dest); |
2194 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2195 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2196 | reg |= vector; | |
2197 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2198 | } |
2199 | } | |
2200 | ||
2201 | /* | |
f7e909ea | 2202 | * Either sets data->affinity to a valid value, and returns |
18374d89 | 2203 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
f7e909ea | 2204 | * leaves data->affinity untouched. |
e85abf8f | 2205 | */ |
f7e909ea TG |
2206 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2207 | unsigned int *dest_id) | |
e85abf8f | 2208 | { |
f7e909ea | 2209 | struct irq_cfg *cfg = data->chip_data; |
e85abf8f GH |
2210 | |
2211 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2212 | return -1; |
e85abf8f | 2213 | |
f7e909ea | 2214 | if (assign_irq_vector(data->irq, data->chip_data, mask)) |
18374d89 | 2215 | return -1; |
e85abf8f | 2216 | |
f7e909ea | 2217 | cpumask_copy(data->affinity, mask); |
e85abf8f | 2218 | |
f7e909ea | 2219 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); |
18374d89 | 2220 | return 0; |
e85abf8f GH |
2221 | } |
2222 | ||
4420471f | 2223 | static int |
f7e909ea TG |
2224 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2225 | bool force) | |
e85abf8f | 2226 | { |
f7e909ea | 2227 | unsigned int dest, irq = data->irq; |
e85abf8f | 2228 | unsigned long flags; |
f7e909ea | 2229 | int ret; |
e85abf8f | 2230 | |
dade7716 | 2231 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
f7e909ea | 2232 | ret = __ioapic_set_affinity(data, mask, &dest); |
18374d89 | 2233 | if (!ret) { |
e85abf8f GH |
2234 | /* Only the high 8 bits are valid. */ |
2235 | dest = SET_APIC_LOGICAL_ID(dest); | |
f7e909ea | 2236 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
e85abf8f | 2237 | } |
dade7716 | 2238 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f | 2239 | return ret; |
e85abf8f GH |
2240 | } |
2241 | ||
54168ed7 | 2242 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2243 | |
54168ed7 IM |
2244 | /* |
2245 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2246 | * | |
0280f7c4 SS |
2247 | * For both level and edge triggered, irq migration is a simple atomic |
2248 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2249 | * |
0280f7c4 SS |
2250 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2251 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2252 | * Real vector that is used for interrupting cpu will be coming from | |
2253 | * the interrupt-remapping table entry. | |
54168ed7 | 2254 | */ |
d5dedd45 | 2255 | static int |
f19f5ecc TG |
2256 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
2257 | bool force) | |
497c9a19 | 2258 | { |
f19f5ecc TG |
2259 | struct irq_cfg *cfg = data->chip_data; |
2260 | unsigned int dest, irq = data->irq; | |
54168ed7 | 2261 | struct irte irte; |
497c9a19 | 2262 | |
22f65d31 | 2263 | if (!cpumask_intersects(mask, cpu_online_mask)) |
f19f5ecc | 2264 | return -EINVAL; |
497c9a19 | 2265 | |
54168ed7 | 2266 | if (get_irte(irq, &irte)) |
f19f5ecc | 2267 | return -EBUSY; |
497c9a19 | 2268 | |
3145e941 | 2269 | if (assign_irq_vector(irq, cfg, mask)) |
f19f5ecc | 2270 | return -EBUSY; |
54168ed7 | 2271 | |
debccb3e | 2272 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2273 | |
54168ed7 IM |
2274 | irte.vector = cfg->vector; |
2275 | irte.dest_id = IRTE_DEST(dest); | |
2276 | ||
2277 | /* | |
2278 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2279 | */ | |
2280 | modify_irte(irq, &irte); | |
2281 | ||
22f65d31 MT |
2282 | if (cfg->move_in_progress) |
2283 | send_cleanup_vector(cfg); | |
54168ed7 | 2284 | |
f19f5ecc | 2285 | cpumask_copy(data->affinity, mask); |
d5dedd45 | 2286 | return 0; |
54168ed7 IM |
2287 | } |
2288 | ||
29b61be6 | 2289 | #else |
f19f5ecc TG |
2290 | static inline int |
2291 | ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2292 | bool force) | |
29b61be6 | 2293 | { |
d5dedd45 | 2294 | return 0; |
29b61be6 | 2295 | } |
54168ed7 IM |
2296 | #endif |
2297 | ||
2298 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2299 | { | |
2300 | unsigned vector, me; | |
8f2466f4 | 2301 | |
54168ed7 | 2302 | ack_APIC_irq(); |
54168ed7 | 2303 | exit_idle(); |
54168ed7 IM |
2304 | irq_enter(); |
2305 | ||
2306 | me = smp_processor_id(); | |
2307 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2308 | unsigned int irq; | |
68a8ca59 | 2309 | unsigned int irr; |
54168ed7 IM |
2310 | struct irq_desc *desc; |
2311 | struct irq_cfg *cfg; | |
2312 | irq = __get_cpu_var(vector_irq)[vector]; | |
2313 | ||
0b8f1efa YL |
2314 | if (irq == -1) |
2315 | continue; | |
2316 | ||
54168ed7 IM |
2317 | desc = irq_to_desc(irq); |
2318 | if (!desc) | |
2319 | continue; | |
2320 | ||
2321 | cfg = irq_cfg(irq); | |
239007b8 | 2322 | raw_spin_lock(&desc->lock); |
54168ed7 | 2323 | |
7f41c2e1 SS |
2324 | /* |
2325 | * Check if the irq migration is in progress. If so, we | |
2326 | * haven't received the cleanup request yet for this irq. | |
2327 | */ | |
2328 | if (cfg->move_in_progress) | |
2329 | goto unlock; | |
2330 | ||
22f65d31 | 2331 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2332 | goto unlock; |
2333 | ||
68a8ca59 SS |
2334 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2335 | /* | |
2336 | * Check if the vector that needs to be cleanedup is | |
2337 | * registered at the cpu's IRR. If so, then this is not | |
2338 | * the best time to clean it up. Lets clean it up in the | |
2339 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2340 | * to myself. | |
2341 | */ | |
2342 | if (irr & (1 << (vector % 32))) { | |
2343 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2344 | goto unlock; | |
2345 | } | |
54168ed7 | 2346 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2347 | unlock: |
239007b8 | 2348 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2349 | } |
2350 | ||
2351 | irq_exit(); | |
2352 | } | |
2353 | ||
dd5f15e5 | 2354 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2355 | { |
a5e74b84 | 2356 | unsigned me; |
54168ed7 | 2357 | |
fcef5911 | 2358 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2359 | return; |
2360 | ||
54168ed7 | 2361 | me = smp_processor_id(); |
10b888d6 | 2362 | |
fcef5911 | 2363 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2364 | send_cleanup_vector(cfg); |
497c9a19 | 2365 | } |
a5e74b84 | 2366 | |
dd5f15e5 | 2367 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2368 | { |
dd5f15e5 | 2369 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2370 | } |
2371 | ||
2372 | void irq_force_complete_move(int irq) | |
2373 | { | |
dd5f15e5 | 2374 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
a5e74b84 | 2375 | |
bbd391a1 PB |
2376 | if (!cfg) |
2377 | return; | |
2378 | ||
dd5f15e5 | 2379 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2380 | } |
497c9a19 | 2381 | #else |
dd5f15e5 | 2382 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2383 | #endif |
3145e941 | 2384 | |
90297c5f | 2385 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2386 | { |
90297c5f TG |
2387 | irq_complete_move(data->chip_data); |
2388 | move_native_irq(data->irq); | |
1d025192 YL |
2389 | ack_APIC_irq(); |
2390 | } | |
2391 | ||
3eb2cce8 | 2392 | atomic_t irq_mis_count; |
3eb2cce8 | 2393 | |
c29d9db3 SS |
2394 | /* |
2395 | * IO-APIC versions below 0x20 don't support EOI register. | |
2396 | * For the record, here is the information about various versions: | |
2397 | * 0Xh 82489DX | |
2398 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2399 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2400 | * 30h-FFh Reserved | |
2401 | * | |
2402 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2403 | * version as 0x2. This is an error with documentation and these ICH chips | |
2404 | * use io-apic's of version 0x20. | |
2405 | * | |
2406 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2407 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2408 | * mode to edge and then back to level, with RTE being masked during this. | |
2409 | */ | |
dd5f15e5 | 2410 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2411 | { |
2412 | struct irq_pin_list *entry; | |
dd5f15e5 | 2413 | unsigned long flags; |
b3ec0a37 | 2414 | |
dd5f15e5 | 2415 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2416 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2417 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2418 | /* | |
2419 | * Intr-remapping uses pin number as the virtual vector | |
2420 | * in the RTE. Actual vector is programmed in | |
2421 | * intr-remapping table entry. Hence for the io-apic | |
2422 | * EOI we use the pin number. | |
2423 | */ | |
1a0730d6 | 2424 | if (irq_remapped(cfg)) |
c29d9db3 SS |
2425 | io_apic_eoi(entry->apic, entry->pin); |
2426 | else | |
2427 | io_apic_eoi(entry->apic, cfg->vector); | |
2428 | } else { | |
2429 | __mask_and_edge_IO_APIC_irq(entry); | |
2430 | __unmask_and_level_IO_APIC_irq(entry); | |
2431 | } | |
b3ec0a37 | 2432 | } |
dade7716 | 2433 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2434 | } |
2435 | ||
90297c5f | 2436 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2437 | { |
90297c5f TG |
2438 | struct irq_cfg *cfg = data->chip_data; |
2439 | int i, do_unmask_irq = 0, irq = data->irq; | |
3145e941 | 2440 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 | 2441 | unsigned long v; |
047c8fdb | 2442 | |
dd5f15e5 | 2443 | irq_complete_move(cfg); |
047c8fdb | 2444 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2445 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2446 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2447 | do_unmask_irq = 1; |
dd5f15e5 | 2448 | mask_ioapic(cfg); |
54168ed7 | 2449 | } |
047c8fdb YL |
2450 | #endif |
2451 | ||
3eb2cce8 | 2452 | /* |
916a0fe7 JF |
2453 | * It appears there is an erratum which affects at least version 0x11 |
2454 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2455 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2456 | * erroneously delivered as edge-triggered one but the respective IRR | |
2457 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2458 | * message but it will never arrive and further interrupts are blocked | |
2459 | * from the source. The exact reason is so far unknown, but the | |
2460 | * phenomenon was observed when two consecutive interrupt requests | |
2461 | * from a given source get delivered to the same CPU and the source is | |
2462 | * temporarily disabled in between. | |
2463 | * | |
2464 | * A workaround is to simulate an EOI message manually. We achieve it | |
2465 | * by setting the trigger mode to edge and then to level when the edge | |
2466 | * trigger mode gets detected in the TMR of a local APIC for a | |
2467 | * level-triggered interrupt. We mask the source for the time of the | |
2468 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2469 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2470 | * |
2471 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2472 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2473 | * destination that is handling the corresponding interrupt. This | |
2474 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2475 | * level-triggered io-apic interrupt will be seen as an edge | |
2476 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2477 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2478 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2479 | * supporting EOI register, we do an explicit EOI to clear the | |
2480 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2481 | * we use the above logic (mask+edge followed by unmask+level) from | |
2482 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2483 | */ |
3145e941 | 2484 | i = cfg->vector; |
3eb2cce8 | 2485 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2486 | |
54168ed7 IM |
2487 | /* |
2488 | * We must acknowledge the irq before we move it or the acknowledge will | |
2489 | * not propagate properly. | |
2490 | */ | |
2491 | ack_APIC_irq(); | |
2492 | ||
1c83995b SS |
2493 | /* |
2494 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2495 | * message via io-apic EOI register write or simulating it using | |
2496 | * mask+edge followed by unnask+level logic) manually when the | |
2497 | * level triggered interrupt is seen as the edge triggered interrupt | |
2498 | * at the cpu. | |
2499 | */ | |
ca64c47c MR |
2500 | if (!(v & (1 << (i & 0x1f)))) { |
2501 | atomic_inc(&irq_mis_count); | |
2502 | ||
dd5f15e5 | 2503 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2504 | } |
2505 | ||
54168ed7 IM |
2506 | /* Now we can move and renable the irq */ |
2507 | if (unlikely(do_unmask_irq)) { | |
2508 | /* Only migrate the irq if the ack has been received. | |
2509 | * | |
2510 | * On rare occasions the broadcast level triggered ack gets | |
2511 | * delayed going to ioapics, and if we reprogram the | |
2512 | * vector while Remote IRR is still set the irq will never | |
2513 | * fire again. | |
2514 | * | |
2515 | * To prevent this scenario we read the Remote IRR bit | |
2516 | * of the ioapic. This has two effects. | |
2517 | * - On any sane system the read of the ioapic will | |
2518 | * flush writes (and acks) going to the ioapic from | |
2519 | * this cpu. | |
2520 | * - We get to see if the ACK has actually been delivered. | |
2521 | * | |
2522 | * Based on failed experiments of reprogramming the | |
2523 | * ioapic entry from outside of irq context starting | |
2524 | * with masking the ioapic entry and then polling until | |
2525 | * Remote IRR was clear before reprogramming the | |
2526 | * ioapic I don't trust the Remote IRR bit to be | |
2527 | * completey accurate. | |
2528 | * | |
2529 | * However there appears to be no other way to plug | |
2530 | * this race, so if the Remote IRR bit is not | |
2531 | * accurate and is causing problems then it is a hardware bug | |
2532 | * and you can go talk to the chipset vendor about it. | |
2533 | */ | |
3145e941 | 2534 | if (!io_apic_level_ack_pending(cfg)) |
54168ed7 | 2535 | move_masked_irq(irq); |
dd5f15e5 | 2536 | unmask_ioapic(cfg); |
54168ed7 | 2537 | } |
3eb2cce8 | 2538 | } |
1d025192 | 2539 | |
d0b03bd1 | 2540 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2541 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2542 | { |
5d0ae2db | 2543 | ack_APIC_irq(); |
d0b03bd1 HW |
2544 | } |
2545 | ||
90297c5f | 2546 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2547 | { |
5d0ae2db | 2548 | ack_APIC_irq(); |
90297c5f | 2549 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2550 | } |
2551 | #endif /* CONFIG_INTR_REMAP */ | |
2552 | ||
f5b9ed7a | 2553 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2554 | .name = "IO-APIC", |
2555 | .irq_startup = startup_ioapic_irq, | |
2556 | .irq_mask = mask_ioapic_irq, | |
2557 | .irq_unmask = unmask_ioapic_irq, | |
2558 | .irq_ack = ack_apic_edge, | |
2559 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2560 | #ifdef CONFIG_SMP |
f7e909ea | 2561 | .irq_set_affinity = ioapic_set_affinity, |
54d5d424 | 2562 | #endif |
f7e909ea | 2563 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2564 | }; |
2565 | ||
54168ed7 | 2566 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
f19f5ecc TG |
2567 | .name = "IR-IO-APIC", |
2568 | .irq_startup = startup_ioapic_irq, | |
2569 | .irq_mask = mask_ioapic_irq, | |
2570 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2571 | #ifdef CONFIG_INTR_REMAP |
f19f5ecc TG |
2572 | .irq_ack = ir_ack_apic_edge, |
2573 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2574 | #ifdef CONFIG_SMP |
f19f5ecc | 2575 | .irq_set_affinity = ir_ioapic_set_affinity, |
a1e38ca5 | 2576 | #endif |
54168ed7 | 2577 | #endif |
f19f5ecc | 2578 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2579 | }; |
1da177e4 LT |
2580 | |
2581 | static inline void init_IO_APIC_traps(void) | |
2582 | { | |
da51a821 | 2583 | struct irq_cfg *cfg; |
ad9f4334 | 2584 | unsigned int irq; |
1da177e4 LT |
2585 | |
2586 | /* | |
2587 | * NOTE! The local APIC isn't very good at handling | |
2588 | * multiple interrupts at the same interrupt level. | |
2589 | * As the interrupt level is determined by taking the | |
2590 | * vector number and shifting that right by 4, we | |
2591 | * want to spread these out a bit so that they don't | |
2592 | * all fall in the same interrupt level. | |
2593 | * | |
2594 | * Also, we've got to be careful not to trash gate | |
2595 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2596 | */ | |
ad9f4334 TG |
2597 | for_each_active_irq(irq) { |
2598 | cfg = get_irq_chip_data(irq); | |
0b8f1efa | 2599 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2600 | /* |
2601 | * Hmm.. We don't have an entry for this, | |
2602 | * so default to an old-fashioned 8259 | |
2603 | * interrupt if we can.. | |
2604 | */ | |
b81bb373 JP |
2605 | if (irq < legacy_pic->nr_legacy_irqs) |
2606 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2607 | else |
1da177e4 | 2608 | /* Strange. Oh, well.. */ |
ad9f4334 | 2609 | set_irq_chip(irq, &no_irq_chip); |
1da177e4 LT |
2610 | } |
2611 | } | |
2612 | } | |
2613 | ||
f5b9ed7a IM |
2614 | /* |
2615 | * The local APIC irq-chip implementation: | |
2616 | */ | |
1da177e4 | 2617 | |
90297c5f | 2618 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2619 | { |
2620 | unsigned long v; | |
2621 | ||
2622 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2623 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2624 | } |
2625 | ||
90297c5f | 2626 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2627 | { |
f5b9ed7a | 2628 | unsigned long v; |
1da177e4 | 2629 | |
f5b9ed7a | 2630 | v = apic_read(APIC_LVT0); |
593f4a78 | 2631 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2632 | } |
1da177e4 | 2633 | |
90297c5f | 2634 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2635 | { |
2636 | ack_APIC_irq(); | |
2637 | } | |
2638 | ||
f5b9ed7a | 2639 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2640 | .name = "local-APIC", |
90297c5f TG |
2641 | .irq_mask = mask_lapic_irq, |
2642 | .irq_unmask = unmask_lapic_irq, | |
2643 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2644 | }; |
2645 | ||
60c69948 | 2646 | static void lapic_register_intr(int irq) |
c88ac1df | 2647 | { |
60c69948 | 2648 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c88ac1df MR |
2649 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2650 | "edge"); | |
c88ac1df MR |
2651 | } |
2652 | ||
e9427101 | 2653 | static void __init setup_nmi(void) |
1da177e4 LT |
2654 | { |
2655 | /* | |
36062448 | 2656 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2657 | * We put the 8259A master into AEOI mode and |
2658 | * unmask on all local APICs LVT0 as NMI. | |
2659 | * | |
2660 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2661 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2662 | * the NMI handler or the timer interrupt. | |
36062448 | 2663 | */ |
1da177e4 LT |
2664 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2665 | ||
e9427101 | 2666 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2667 | |
2668 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2669 | } | |
2670 | ||
2671 | /* | |
2672 | * This looks a bit hackish but it's about the only one way of sending | |
2673 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2674 | * not support the ExtINT mode, unfortunately. We need to send these | |
2675 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2676 | * 8259A interrupt line asserted until INTA. --macro | |
2677 | */ | |
28acf285 | 2678 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2679 | { |
fcfd636a | 2680 | int apic, pin, i; |
1da177e4 LT |
2681 | struct IO_APIC_route_entry entry0, entry1; |
2682 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2683 | |
fcfd636a | 2684 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2685 | if (pin == -1) { |
2686 | WARN_ON_ONCE(1); | |
2687 | return; | |
2688 | } | |
fcfd636a | 2689 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2690 | if (apic == -1) { |
2691 | WARN_ON_ONCE(1); | |
1da177e4 | 2692 | return; |
956fb531 | 2693 | } |
1da177e4 | 2694 | |
cf4c6a2f | 2695 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2696 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2697 | |
2698 | memset(&entry1, 0, sizeof(entry1)); | |
2699 | ||
2700 | entry1.dest_mode = 0; /* physical delivery */ | |
2701 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2702 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2703 | entry1.delivery_mode = dest_ExtINT; |
2704 | entry1.polarity = entry0.polarity; | |
2705 | entry1.trigger = 0; | |
2706 | entry1.vector = 0; | |
2707 | ||
cf4c6a2f | 2708 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2709 | |
2710 | save_control = CMOS_READ(RTC_CONTROL); | |
2711 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2712 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2713 | RTC_FREQ_SELECT); | |
2714 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2715 | ||
2716 | i = 100; | |
2717 | while (i-- > 0) { | |
2718 | mdelay(10); | |
2719 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2720 | i -= 10; | |
2721 | } | |
2722 | ||
2723 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2724 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2725 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2726 | |
cf4c6a2f | 2727 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2728 | } |
2729 | ||
efa2559f | 2730 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2731 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2732 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2733 | { |
2734 | disable_timer_pin_1 = 1; | |
2735 | return 0; | |
2736 | } | |
54168ed7 | 2737 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2738 | |
2739 | int timer_through_8259 __initdata; | |
2740 | ||
1da177e4 LT |
2741 | /* |
2742 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2743 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2744 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2745 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2746 | * |
2747 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2748 | */ |
8542b200 | 2749 | static inline void __init check_timer(void) |
1da177e4 | 2750 | { |
60c69948 | 2751 | struct irq_cfg *cfg = get_irq_chip_data(0); |
f6e9456c | 2752 | int node = cpu_to_node(0); |
fcfd636a | 2753 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2754 | unsigned long flags; |
047c8fdb | 2755 | int no_pin1 = 0; |
4aae0702 IM |
2756 | |
2757 | local_irq_save(flags); | |
d4d25dec | 2758 | |
1da177e4 LT |
2759 | /* |
2760 | * get/set the timer IRQ vector: | |
2761 | */ | |
4305df94 | 2762 | legacy_pic->mask(0); |
fe402e1f | 2763 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2764 | |
2765 | /* | |
d11d5794 MR |
2766 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2767 | * wire has to be disabled in the local APIC. Also | |
2768 | * timer interrupts need to be acknowledged manually in | |
2769 | * the 8259A for the i82489DX when using the NMI | |
2770 | * watchdog as that APIC treats NMIs as level-triggered. | |
2771 | * The AEOI mode will finish them in the 8259A | |
2772 | * automatically. | |
1da177e4 | 2773 | */ |
593f4a78 | 2774 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2775 | legacy_pic->init(1); |
54168ed7 | 2776 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2777 | { |
2778 | unsigned int ver; | |
2779 | ||
2780 | ver = apic_read(APIC_LVR); | |
2781 | ver = GET_APIC_VERSION(ver); | |
2782 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2783 | } | |
54168ed7 | 2784 | #endif |
1da177e4 | 2785 | |
fcfd636a EB |
2786 | pin1 = find_isa_irq_pin(0, mp_INT); |
2787 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2788 | pin2 = ioapic_i8259.pin; | |
2789 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2790 | |
49a66a0b MR |
2791 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2792 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2793 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2794 | |
691874fa MR |
2795 | /* |
2796 | * Some BIOS writers are clueless and report the ExtINTA | |
2797 | * I/O APIC input from the cascaded 8259A as the timer | |
2798 | * interrupt input. So just in case, if only one pin | |
2799 | * was found above, try it both directly and through the | |
2800 | * 8259A. | |
2801 | */ | |
2802 | if (pin1 == -1) { | |
54168ed7 IM |
2803 | if (intr_remapping_enabled) |
2804 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2805 | pin1 = pin2; |
2806 | apic1 = apic2; | |
2807 | no_pin1 = 1; | |
2808 | } else if (pin2 == -1) { | |
2809 | pin2 = pin1; | |
2810 | apic2 = apic1; | |
2811 | } | |
2812 | ||
1da177e4 LT |
2813 | if (pin1 != -1) { |
2814 | /* | |
2815 | * Ok, does IRQ0 through the IOAPIC work? | |
2816 | */ | |
691874fa | 2817 | if (no_pin1) { |
85ac16d0 | 2818 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2819 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2820 | } else { |
60c69948 | 2821 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2822 | * leave it unmasked. |
2823 | * so only need to unmask if it is level-trigger | |
2824 | * do we really have level trigger timer? | |
2825 | */ | |
2826 | int idx; | |
2827 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2828 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2829 | unmask_ioapic(cfg); |
691874fa | 2830 | } |
1da177e4 LT |
2831 | if (timer_irq_works()) { |
2832 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 2833 | setup_nmi(); |
4305df94 | 2834 | legacy_pic->unmask(0); |
1da177e4 | 2835 | } |
66759a01 CE |
2836 | if (disable_timer_pin_1 > 0) |
2837 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2838 | goto out; |
1da177e4 | 2839 | } |
54168ed7 IM |
2840 | if (intr_remapping_enabled) |
2841 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2842 | local_irq_disable(); |
fcfd636a | 2843 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2844 | if (!no_pin1) |
49a66a0b MR |
2845 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2846 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2847 | |
49a66a0b MR |
2848 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2849 | "(IRQ0) through the 8259A ...\n"); | |
2850 | apic_printk(APIC_QUIET, KERN_INFO | |
2851 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2852 | /* |
2853 | * legacy devices should be connected to IO APIC #0 | |
2854 | */ | |
85ac16d0 | 2855 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2856 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2857 | legacy_pic->unmask(0); |
1da177e4 | 2858 | if (timer_irq_works()) { |
49a66a0b | 2859 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2860 | timer_through_8259 = 1; |
1da177e4 | 2861 | if (nmi_watchdog == NMI_IO_APIC) { |
4305df94 | 2862 | legacy_pic->mask(0); |
1da177e4 | 2863 | setup_nmi(); |
4305df94 | 2864 | legacy_pic->unmask(0); |
1da177e4 | 2865 | } |
4aae0702 | 2866 | goto out; |
1da177e4 LT |
2867 | } |
2868 | /* | |
2869 | * Cleanup, just in case ... | |
2870 | */ | |
f72dccac | 2871 | local_irq_disable(); |
4305df94 | 2872 | legacy_pic->mask(0); |
fcfd636a | 2873 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2874 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2875 | } |
1da177e4 LT |
2876 | |
2877 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2878 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2879 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2880 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2881 | } |
54168ed7 | 2882 | #ifdef CONFIG_X86_32 |
d11d5794 | 2883 | timer_ack = 0; |
54168ed7 | 2884 | #endif |
1da177e4 | 2885 | |
49a66a0b MR |
2886 | apic_printk(APIC_QUIET, KERN_INFO |
2887 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2888 | |
60c69948 | 2889 | lapic_register_intr(0); |
497c9a19 | 2890 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2891 | legacy_pic->unmask(0); |
1da177e4 LT |
2892 | |
2893 | if (timer_irq_works()) { | |
49a66a0b | 2894 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2895 | goto out; |
1da177e4 | 2896 | } |
f72dccac | 2897 | local_irq_disable(); |
4305df94 | 2898 | legacy_pic->mask(0); |
497c9a19 | 2899 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2900 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2901 | |
49a66a0b MR |
2902 | apic_printk(APIC_QUIET, KERN_INFO |
2903 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2904 | |
b81bb373 JP |
2905 | legacy_pic->init(0); |
2906 | legacy_pic->make_irq(0); | |
593f4a78 | 2907 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2908 | |
2909 | unlock_ExtINT_logic(); | |
2910 | ||
2911 | if (timer_irq_works()) { | |
49a66a0b | 2912 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2913 | goto out; |
1da177e4 | 2914 | } |
f72dccac | 2915 | local_irq_disable(); |
49a66a0b | 2916 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2917 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2918 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2919 | out: |
2920 | local_irq_restore(flags); | |
1da177e4 LT |
2921 | } |
2922 | ||
2923 | /* | |
af174783 MR |
2924 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2925 | * to devices. However there may be an I/O APIC pin available for | |
2926 | * this interrupt regardless. The pin may be left unconnected, but | |
2927 | * typically it will be reused as an ExtINT cascade interrupt for | |
2928 | * the master 8259A. In the MPS case such a pin will normally be | |
2929 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2930 | * there is no provision for ExtINT interrupts, and in the absence | |
2931 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2932 | * interrupt, that is edge-triggered and unmasked by default. We | |
2933 | * used to do this, but it caused problems on some systems because | |
2934 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2935 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2936 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2937 | * the I/O APIC in all cases now. No actual device should request | |
2938 | * it anyway. --macro | |
1da177e4 | 2939 | */ |
bc07844a | 2940 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2941 | |
2942 | void __init setup_IO_APIC(void) | |
2943 | { | |
54168ed7 | 2944 | |
54168ed7 IM |
2945 | /* |
2946 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2947 | */ | |
b81bb373 | 2948 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2949 | |
54168ed7 | 2950 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2951 | /* |
54168ed7 IM |
2952 | * Set up IO-APIC IRQ routing. |
2953 | */ | |
de934103 TG |
2954 | x86_init.mpparse.setup_ioapic_ids(); |
2955 | ||
1da177e4 LT |
2956 | sync_Arb_IDs(); |
2957 | setup_IO_APIC_irqs(); | |
2958 | init_IO_APIC_traps(); | |
b81bb373 | 2959 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2960 | check_timer(); |
1da177e4 LT |
2961 | } |
2962 | ||
2963 | /* | |
54168ed7 IM |
2964 | * Called after all the initialization is done. If we didnt find any |
2965 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 2966 | */ |
36062448 | 2967 | |
1da177e4 LT |
2968 | static int __init io_apic_bug_finalize(void) |
2969 | { | |
d6c88a50 TG |
2970 | if (sis_apic_bug == -1) |
2971 | sis_apic_bug = 0; | |
2972 | return 0; | |
1da177e4 LT |
2973 | } |
2974 | ||
2975 | late_initcall(io_apic_bug_finalize); | |
2976 | ||
2977 | struct sysfs_ioapic_data { | |
2978 | struct sys_device dev; | |
2979 | struct IO_APIC_route_entry entry[0]; | |
2980 | }; | |
54168ed7 | 2981 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2982 | |
438510f6 | 2983 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2984 | { |
2985 | struct IO_APIC_route_entry *entry; | |
2986 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2987 | int i; |
36062448 | 2988 | |
1da177e4 LT |
2989 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2990 | entry = data->entry; | |
54168ed7 IM |
2991 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2992 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2993 | |
2994 | return 0; | |
2995 | } | |
2996 | ||
2997 | static int ioapic_resume(struct sys_device *dev) | |
2998 | { | |
2999 | struct IO_APIC_route_entry *entry; | |
3000 | struct sysfs_ioapic_data *data; | |
3001 | unsigned long flags; | |
3002 | union IO_APIC_reg_00 reg_00; | |
3003 | int i; | |
36062448 | 3004 | |
1da177e4 LT |
3005 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3006 | entry = data->entry; | |
3007 | ||
dade7716 | 3008 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3009 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3010 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3011 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3012 | io_apic_write(dev->id, 0, reg_00.raw); |
3013 | } | |
dade7716 | 3014 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3015 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3016 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3017 | |
3018 | return 0; | |
3019 | } | |
3020 | ||
3021 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3022 | .name = "ioapic", |
1da177e4 LT |
3023 | .suspend = ioapic_suspend, |
3024 | .resume = ioapic_resume, | |
3025 | }; | |
3026 | ||
3027 | static int __init ioapic_init_sysfs(void) | |
3028 | { | |
54168ed7 IM |
3029 | struct sys_device * dev; |
3030 | int i, size, error; | |
1da177e4 LT |
3031 | |
3032 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3033 | if (error) | |
3034 | return error; | |
3035 | ||
54168ed7 | 3036 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3037 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3038 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3039 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3040 | if (!mp_ioapic_data[i]) { |
3041 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3042 | continue; | |
3043 | } | |
1da177e4 | 3044 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3045 | dev->id = i; |
1da177e4 LT |
3046 | dev->cls = &ioapic_sysdev_class; |
3047 | error = sysdev_register(dev); | |
3048 | if (error) { | |
3049 | kfree(mp_ioapic_data[i]); | |
3050 | mp_ioapic_data[i] = NULL; | |
3051 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3052 | continue; | |
3053 | } | |
3054 | } | |
3055 | ||
3056 | return 0; | |
3057 | } | |
3058 | ||
3059 | device_initcall(ioapic_init_sysfs); | |
3060 | ||
3fc471ed | 3061 | /* |
95d77884 | 3062 | * Dynamic irq allocate and deallocation |
3fc471ed | 3063 | */ |
fbc6bff0 | 3064 | unsigned int create_irq_nr(unsigned int from, int node) |
3fc471ed | 3065 | { |
fbc6bff0 | 3066 | struct irq_cfg *cfg; |
3fc471ed | 3067 | unsigned long flags; |
fbc6bff0 TG |
3068 | unsigned int ret = 0; |
3069 | int irq; | |
d047f53a | 3070 | |
fbc6bff0 TG |
3071 | if (from < nr_irqs_gsi) |
3072 | from = nr_irqs_gsi; | |
d047f53a | 3073 | |
fbc6bff0 TG |
3074 | irq = alloc_irq_from(from, node); |
3075 | if (irq < 0) | |
3076 | return 0; | |
3077 | cfg = alloc_irq_cfg(irq, node); | |
3078 | if (!cfg) { | |
3079 | free_irq_at(irq, NULL); | |
3080 | return 0; | |
ace80ab7 | 3081 | } |
3fc471ed | 3082 | |
fbc6bff0 TG |
3083 | raw_spin_lock_irqsave(&vector_lock, flags); |
3084 | if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) | |
3085 | ret = irq; | |
3086 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3087 | |
fbc6bff0 TG |
3088 | if (ret) { |
3089 | set_irq_chip_data(irq, cfg); | |
3090 | irq_clear_status_flags(irq, IRQ_NOREQUEST); | |
3091 | } else { | |
3092 | free_irq_at(irq, cfg); | |
3093 | } | |
3094 | return ret; | |
3fc471ed EB |
3095 | } |
3096 | ||
199751d7 YL |
3097 | int create_irq(void) |
3098 | { | |
f6e9456c | 3099 | int node = cpu_to_node(0); |
be5d5350 | 3100 | unsigned int irq_want; |
54168ed7 IM |
3101 | int irq; |
3102 | ||
be5d5350 | 3103 | irq_want = nr_irqs_gsi; |
d047f53a | 3104 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3105 | |
3106 | if (irq == 0) | |
3107 | irq = -1; | |
3108 | ||
3109 | return irq; | |
199751d7 YL |
3110 | } |
3111 | ||
3fc471ed EB |
3112 | void destroy_irq(unsigned int irq) |
3113 | { | |
fbc6bff0 | 3114 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
3fc471ed | 3115 | unsigned long flags; |
3fc471ed | 3116 | |
fbc6bff0 | 3117 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
3fc471ed | 3118 | |
7b79462a | 3119 | if (irq_remapped(cfg)) |
9717967c | 3120 | free_irte(irq); |
dade7716 | 3121 | raw_spin_lock_irqsave(&vector_lock, flags); |
fbc6bff0 | 3122 | __clear_irq_vector(irq, cfg); |
dade7716 | 3123 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
fbc6bff0 | 3124 | free_irq_at(irq, cfg); |
3fc471ed | 3125 | } |
3fc471ed | 3126 | |
2d3fcc1c | 3127 | /* |
27b46d76 | 3128 | * MSI message composition |
2d3fcc1c EB |
3129 | */ |
3130 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3131 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3132 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3133 | { |
497c9a19 YL |
3134 | struct irq_cfg *cfg; |
3135 | int err; | |
2d3fcc1c EB |
3136 | unsigned dest; |
3137 | ||
f1182638 JB |
3138 | if (disable_apic) |
3139 | return -ENXIO; | |
3140 | ||
3145e941 | 3141 | cfg = irq_cfg(irq); |
fe402e1f | 3142 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3143 | if (err) |
3144 | return err; | |
2d3fcc1c | 3145 | |
debccb3e | 3146 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3147 | |
1a0730d6 | 3148 | if (irq_remapped(get_irq_chip_data(irq))) { |
54168ed7 IM |
3149 | struct irte irte; |
3150 | int ir_index; | |
3151 | u16 sub_handle; | |
3152 | ||
3153 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3154 | BUG_ON(ir_index == -1); | |
3155 | ||
62a92f4c | 3156 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3157 | |
f007e99c | 3158 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3159 | if (pdev) |
3160 | set_msi_sid(&irte, pdev); | |
3161 | else | |
3162 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3163 | |
54168ed7 IM |
3164 | modify_irte(irq, &irte); |
3165 | ||
3166 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3167 | msg->data = sub_handle; | |
3168 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3169 | MSI_ADDR_IR_SHV | | |
3170 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3171 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3172 | } else { |
9d783ba0 SS |
3173 | if (x2apic_enabled()) |
3174 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3175 | MSI_ADDR_EXT_DEST_ID(dest); | |
3176 | else | |
3177 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3178 | ||
54168ed7 IM |
3179 | msg->address_lo = |
3180 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3181 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3182 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3183 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3184 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3185 | MSI_ADDR_REDIRECTION_CPU: |
3186 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3187 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3188 | |
54168ed7 IM |
3189 | msg->data = |
3190 | MSI_DATA_TRIGGER_EDGE | | |
3191 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3192 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3193 | MSI_DATA_DELIVERY_FIXED: |
3194 | MSI_DATA_DELIVERY_LOWPRI) | | |
3195 | MSI_DATA_VECTOR(cfg->vector); | |
3196 | } | |
497c9a19 | 3197 | return err; |
2d3fcc1c EB |
3198 | } |
3199 | ||
3b7d1921 | 3200 | #ifdef CONFIG_SMP |
5346b2a7 TG |
3201 | static int |
3202 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3203 | { |
5346b2a7 | 3204 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3205 | struct msi_msg msg; |
3206 | unsigned int dest; | |
3b7d1921 | 3207 | |
5346b2a7 | 3208 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3209 | return -1; |
2d3fcc1c | 3210 | |
5346b2a7 | 3211 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3212 | |
3213 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3214 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3215 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3216 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3217 | ||
5346b2a7 | 3218 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 YL |
3219 | |
3220 | return 0; | |
2d3fcc1c | 3221 | } |
54168ed7 IM |
3222 | #ifdef CONFIG_INTR_REMAP |
3223 | /* | |
3224 | * Migrate the MSI irq to another cpumask. This migration is | |
3225 | * done in the process context using interrupt-remapping hardware. | |
3226 | */ | |
d5dedd45 | 3227 | static int |
b5d1c465 TG |
3228 | ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3229 | bool force) | |
54168ed7 | 3230 | { |
b5d1c465 TG |
3231 | struct irq_cfg *cfg = data->chip_data; |
3232 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3233 | struct irte irte; |
54168ed7 IM |
3234 | |
3235 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3236 | return -1; |
54168ed7 | 3237 | |
b5d1c465 | 3238 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3239 | return -1; |
54168ed7 | 3240 | |
54168ed7 IM |
3241 | irte.vector = cfg->vector; |
3242 | irte.dest_id = IRTE_DEST(dest); | |
3243 | ||
3244 | /* | |
3245 | * atomically update the IRTE with the new destination and vector. | |
3246 | */ | |
3247 | modify_irte(irq, &irte); | |
3248 | ||
3249 | /* | |
3250 | * After this point, all the interrupts will start arriving | |
3251 | * at the new destination. So, time to cleanup the previous | |
3252 | * vector allocation. | |
3253 | */ | |
22f65d31 MT |
3254 | if (cfg->move_in_progress) |
3255 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3256 | |
3257 | return 0; | |
54168ed7 | 3258 | } |
3145e941 | 3259 | |
54168ed7 | 3260 | #endif |
3b7d1921 | 3261 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3262 | |
3b7d1921 EB |
3263 | /* |
3264 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3265 | * which implement the MSI or MSI-X Capability Structure. | |
3266 | */ | |
3267 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3268 | .name = "PCI-MSI", |
3269 | .irq_unmask = unmask_msi_irq, | |
3270 | .irq_mask = mask_msi_irq, | |
3271 | .irq_ack = ack_apic_edge, | |
3b7d1921 | 3272 | #ifdef CONFIG_SMP |
5346b2a7 | 3273 | .irq_set_affinity = msi_set_affinity, |
3b7d1921 | 3274 | #endif |
5346b2a7 | 3275 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3276 | }; |
3277 | ||
54168ed7 | 3278 | static struct irq_chip msi_ir_chip = { |
b5d1c465 TG |
3279 | .name = "IR-PCI-MSI", |
3280 | .irq_unmask = unmask_msi_irq, | |
3281 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3282 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3283 | .irq_ack = ir_ack_apic_edge, |
54168ed7 | 3284 | #ifdef CONFIG_SMP |
b5d1c465 | 3285 | .irq_set_affinity = ir_msi_set_affinity, |
a1e38ca5 | 3286 | #endif |
54168ed7 | 3287 | #endif |
b5d1c465 | 3288 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3289 | }; |
3290 | ||
3291 | /* | |
3292 | * Map the PCI dev to the corresponding remapping hardware unit | |
3293 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3294 | * in it. | |
3295 | */ | |
3296 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3297 | { | |
3298 | struct intel_iommu *iommu; | |
3299 | int index; | |
3300 | ||
3301 | iommu = map_dev_to_ir(dev); | |
3302 | if (!iommu) { | |
3303 | printk(KERN_ERR | |
3304 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3305 | return -ENOENT; | |
3306 | } | |
3307 | ||
3308 | index = alloc_irte(iommu, irq, nvec); | |
3309 | if (index < 0) { | |
3310 | printk(KERN_ERR | |
3311 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3312 | pci_name(dev)); |
54168ed7 IM |
3313 | return -ENOSPC; |
3314 | } | |
3315 | return index; | |
3316 | } | |
1d025192 | 3317 | |
3145e941 | 3318 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 | 3319 | { |
1d025192 | 3320 | struct msi_msg msg; |
60c69948 | 3321 | int ret; |
1d025192 | 3322 | |
c8bc6f3c | 3323 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3324 | if (ret < 0) |
3325 | return ret; | |
3326 | ||
3145e941 | 3327 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3328 | write_msi_msg(irq, &msg); |
3329 | ||
1a0730d6 | 3330 | if (irq_remapped(get_irq_chip_data(irq))) { |
60c69948 | 3331 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
54168ed7 IM |
3332 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); |
3333 | } else | |
54168ed7 | 3334 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3335 | |
c81bba49 YL |
3336 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3337 | ||
1d025192 YL |
3338 | return 0; |
3339 | } | |
3340 | ||
294ee6f8 | 3341 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3342 | { |
60c69948 TG |
3343 | int node, ret, sub_handle, index = 0; |
3344 | unsigned int irq, irq_want; | |
0b8f1efa | 3345 | struct msi_desc *msidesc; |
1cc18521 | 3346 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3347 | |
1c8d7b0a MW |
3348 | /* x86 doesn't support multiple MSI yet */ |
3349 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3350 | return 1; | |
3351 | ||
d047f53a | 3352 | node = dev_to_node(&dev->dev); |
be5d5350 | 3353 | irq_want = nr_irqs_gsi; |
54168ed7 | 3354 | sub_handle = 0; |
0b8f1efa | 3355 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3356 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3357 | if (irq == 0) |
3358 | return -1; | |
f1ee5548 | 3359 | irq_want = irq + 1; |
54168ed7 IM |
3360 | if (!intr_remapping_enabled) |
3361 | goto no_ir; | |
3362 | ||
3363 | if (!sub_handle) { | |
3364 | /* | |
3365 | * allocate the consecutive block of IRTE's | |
3366 | * for 'nvec' | |
3367 | */ | |
3368 | index = msi_alloc_irte(dev, irq, nvec); | |
3369 | if (index < 0) { | |
3370 | ret = index; | |
3371 | goto error; | |
3372 | } | |
3373 | } else { | |
3374 | iommu = map_dev_to_ir(dev); | |
3375 | if (!iommu) { | |
3376 | ret = -ENOENT; | |
3377 | goto error; | |
3378 | } | |
3379 | /* | |
3380 | * setup the mapping between the irq and the IRTE | |
3381 | * base index, the sub_handle pointing to the | |
3382 | * appropriate interrupt remap table entry. | |
3383 | */ | |
3384 | set_irte_irq(irq, iommu, index, sub_handle); | |
3385 | } | |
3386 | no_ir: | |
0b8f1efa | 3387 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3388 | if (ret < 0) |
3389 | goto error; | |
3390 | sub_handle++; | |
3391 | } | |
3392 | return 0; | |
047c8fdb YL |
3393 | |
3394 | error: | |
54168ed7 IM |
3395 | destroy_irq(irq); |
3396 | return ret; | |
047c8fdb YL |
3397 | } |
3398 | ||
294ee6f8 | 3399 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3400 | { |
f7feaca7 | 3401 | destroy_irq(irq); |
3b7d1921 EB |
3402 | } |
3403 | ||
9d783ba0 | 3404 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3405 | #ifdef CONFIG_SMP |
fe52b2d2 TG |
3406 | static int |
3407 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3408 | bool force) | |
54168ed7 | 3409 | { |
fe52b2d2 TG |
3410 | struct irq_cfg *cfg = data->chip_data; |
3411 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3412 | struct msi_msg msg; |
54168ed7 | 3413 | |
fe52b2d2 | 3414 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3415 | return -1; |
54168ed7 | 3416 | |
54168ed7 IM |
3417 | dmar_msi_read(irq, &msg); |
3418 | ||
3419 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3420 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3421 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3422 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3423 | ||
3424 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3425 | |
3426 | return 0; | |
54168ed7 | 3427 | } |
3145e941 | 3428 | |
54168ed7 IM |
3429 | #endif /* CONFIG_SMP */ |
3430 | ||
8f7007aa | 3431 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3432 | .name = "DMAR_MSI", |
3433 | .irq_unmask = dmar_msi_unmask, | |
3434 | .irq_mask = dmar_msi_mask, | |
3435 | .irq_ack = ack_apic_edge, | |
54168ed7 | 3436 | #ifdef CONFIG_SMP |
fe52b2d2 | 3437 | .irq_set_affinity = dmar_msi_set_affinity, |
54168ed7 | 3438 | #endif |
fe52b2d2 | 3439 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3440 | }; |
3441 | ||
3442 | int arch_setup_dmar_msi(unsigned int irq) | |
3443 | { | |
3444 | int ret; | |
3445 | struct msi_msg msg; | |
2d3fcc1c | 3446 | |
c8bc6f3c | 3447 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3448 | if (ret < 0) |
3449 | return ret; | |
3450 | dmar_msi_write(irq, &msg); | |
3451 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3452 | "edge"); | |
3453 | return 0; | |
3454 | } | |
3455 | #endif | |
3456 | ||
58ac1e76 | 3457 | #ifdef CONFIG_HPET_TIMER |
3458 | ||
3459 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3460 | static int hpet_msi_set_affinity(struct irq_data *data, |
3461 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3462 | { |
d0fbca8f | 3463 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3464 | struct msi_msg msg; |
3465 | unsigned int dest; | |
58ac1e76 | 3466 | |
0e09ddf2 | 3467 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3468 | return -1; |
58ac1e76 | 3469 | |
d0fbca8f | 3470 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3471 | |
3472 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3473 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3474 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3475 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3476 | ||
d0fbca8f | 3477 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3478 | |
3479 | return 0; | |
58ac1e76 | 3480 | } |
3145e941 | 3481 | |
58ac1e76 | 3482 | #endif /* CONFIG_SMP */ |
3483 | ||
c8bc6f3c | 3484 | static struct irq_chip ir_hpet_msi_type = { |
b5d1c465 TG |
3485 | .name = "IR-HPET_MSI", |
3486 | .irq_unmask = hpet_msi_unmask, | |
3487 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3488 | #ifdef CONFIG_INTR_REMAP |
b5d1c465 | 3489 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c | 3490 | #ifdef CONFIG_SMP |
b5d1c465 | 3491 | .irq_set_affinity = ir_msi_set_affinity, |
c8bc6f3c SS |
3492 | #endif |
3493 | #endif | |
b5d1c465 | 3494 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3495 | }; |
3496 | ||
1cc18521 | 3497 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3498 | .name = "HPET_MSI", |
d0fbca8f TG |
3499 | .irq_unmask = hpet_msi_unmask, |
3500 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3501 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3502 | #ifdef CONFIG_SMP |
d0fbca8f | 3503 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3504 | #endif |
90297c5f | 3505 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3506 | }; |
3507 | ||
c8bc6f3c | 3508 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3509 | { |
58ac1e76 | 3510 | struct msi_msg msg; |
d0fbca8f | 3511 | int ret; |
58ac1e76 | 3512 | |
c8bc6f3c SS |
3513 | if (intr_remapping_enabled) { |
3514 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3515 | int index; | |
3516 | ||
3517 | if (!iommu) | |
3518 | return -1; | |
3519 | ||
3520 | index = alloc_irte(iommu, irq, 1); | |
3521 | if (index < 0) | |
3522 | return -1; | |
3523 | } | |
3524 | ||
3525 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3526 | if (ret < 0) |
3527 | return ret; | |
3528 | ||
d0fbca8f | 3529 | hpet_msi_write(get_irq_data(irq), &msg); |
60c69948 | 3530 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
1a0730d6 | 3531 | if (irq_remapped(get_irq_chip_data(irq))) |
c8bc6f3c SS |
3532 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, |
3533 | handle_edge_irq, "edge"); | |
3534 | else | |
3535 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3536 | handle_edge_irq, "edge"); | |
c81bba49 | 3537 | |
58ac1e76 | 3538 | return 0; |
3539 | } | |
3540 | #endif | |
3541 | ||
54168ed7 | 3542 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3543 | /* |
3544 | * Hypertransport interrupt support | |
3545 | */ | |
3546 | #ifdef CONFIG_HT_IRQ | |
3547 | ||
3548 | #ifdef CONFIG_SMP | |
3549 | ||
497c9a19 | 3550 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3551 | { |
ec68307c EB |
3552 | struct ht_irq_msg msg; |
3553 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3554 | |
497c9a19 | 3555 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3556 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3557 | |
497c9a19 | 3558 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3559 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3560 | |
ec68307c | 3561 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3562 | } |
3563 | ||
be5b7bf7 TG |
3564 | static int |
3565 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3566 | { |
be5b7bf7 | 3567 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3568 | unsigned int dest; |
8b955b0d | 3569 | |
be5b7bf7 | 3570 | if (__ioapic_set_affinity(data, mask, &dest)) |
d5dedd45 | 3571 | return -1; |
8b955b0d | 3572 | |
be5b7bf7 | 3573 | target_ht_irq(data->irq, dest, cfg->vector); |
d5dedd45 | 3574 | return 0; |
8b955b0d | 3575 | } |
3145e941 | 3576 | |
8b955b0d EB |
3577 | #endif |
3578 | ||
c37e108d | 3579 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3580 | .name = "PCI-HT", |
3581 | .irq_mask = mask_ht_irq, | |
3582 | .irq_unmask = unmask_ht_irq, | |
3583 | .irq_ack = ack_apic_edge, | |
8b955b0d | 3584 | #ifdef CONFIG_SMP |
be5b7bf7 | 3585 | .irq_set_affinity = ht_set_affinity, |
8b955b0d | 3586 | #endif |
be5b7bf7 | 3587 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3588 | }; |
3589 | ||
3590 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3591 | { | |
497c9a19 YL |
3592 | struct irq_cfg *cfg; |
3593 | int err; | |
8b955b0d | 3594 | |
f1182638 JB |
3595 | if (disable_apic) |
3596 | return -ENXIO; | |
3597 | ||
3145e941 | 3598 | cfg = irq_cfg(irq); |
fe402e1f | 3599 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3600 | if (!err) { |
ec68307c | 3601 | struct ht_irq_msg msg; |
8b955b0d | 3602 | unsigned dest; |
8b955b0d | 3603 | |
debccb3e IM |
3604 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3605 | apic->target_cpus()); | |
8b955b0d | 3606 | |
ec68307c | 3607 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3608 | |
ec68307c EB |
3609 | msg.address_lo = |
3610 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3611 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3612 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3613 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3614 | HT_IRQ_LOW_DM_PHYSICAL : |
3615 | HT_IRQ_LOW_DM_LOGICAL) | | |
3616 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3617 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3618 | HT_IRQ_LOW_MT_FIXED : |
3619 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3620 | HT_IRQ_LOW_IRQ_MASKED; | |
3621 | ||
ec68307c | 3622 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3623 | |
a460e745 IM |
3624 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3625 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3626 | |
3627 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3628 | } |
497c9a19 | 3629 | return err; |
8b955b0d EB |
3630 | } |
3631 | #endif /* CONFIG_HT_IRQ */ | |
3632 | ||
9d6a4d08 YL |
3633 | int __init io_apic_get_redir_entries (int ioapic) |
3634 | { | |
3635 | union IO_APIC_reg_01 reg_01; | |
3636 | unsigned long flags; | |
3637 | ||
dade7716 | 3638 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3639 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3640 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3641 | |
4b6b19a1 EB |
3642 | /* The register returns the maximum index redir index |
3643 | * supported, which is one less than the total number of redir | |
3644 | * entries. | |
3645 | */ | |
3646 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3647 | } |
3648 | ||
23f9b267 | 3649 | static void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3650 | { |
4afc51a8 | 3651 | int nr; |
be5d5350 | 3652 | |
a4384df3 | 3653 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3654 | if (nr > nr_irqs_gsi) |
be5d5350 | 3655 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3656 | |
3657 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3658 | } |
3659 | ||
7b586d71 JF |
3660 | int get_nr_irqs_gsi(void) |
3661 | { | |
3662 | return nr_irqs_gsi; | |
3663 | } | |
3664 | ||
4a046d17 YL |
3665 | #ifdef CONFIG_SPARSE_IRQ |
3666 | int __init arch_probe_nr_irqs(void) | |
3667 | { | |
3668 | int nr; | |
3669 | ||
f1ee5548 YL |
3670 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3671 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3672 | |
f1ee5548 YL |
3673 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3674 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3675 | /* | |
3676 | * for MSI and HT dyn irq | |
3677 | */ | |
3678 | nr += nr_irqs_gsi * 16; | |
3679 | #endif | |
3680 | if (nr < nr_irqs) | |
4a046d17 YL |
3681 | nr_irqs = nr; |
3682 | ||
b683de2b | 3683 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3684 | } |
3685 | #endif | |
3686 | ||
e5198075 YL |
3687 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3688 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3689 | { |
5ef21837 YL |
3690 | struct irq_cfg *cfg; |
3691 | int node; | |
e5198075 YL |
3692 | int ioapic, pin; |
3693 | int trigger, polarity; | |
5ef21837 | 3694 | |
e5198075 | 3695 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3696 | if (!IO_APIC_IRQ(irq)) { |
3697 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3698 | ioapic); | |
3699 | return -EINVAL; | |
3700 | } | |
3701 | ||
3702 | if (dev) | |
3703 | node = dev_to_node(dev); | |
3704 | else | |
f6e9456c | 3705 | node = cpu_to_node(0); |
5ef21837 | 3706 | |
fbc6bff0 TG |
3707 | cfg = alloc_irq_and_cfg_at(irq, node); |
3708 | if (!cfg) | |
5ef21837 | 3709 | return 0; |
5ef21837 | 3710 | |
e5198075 YL |
3711 | pin = irq_attr->ioapic_pin; |
3712 | trigger = irq_attr->trigger; | |
3713 | polarity = irq_attr->polarity; | |
3714 | ||
5ef21837 YL |
3715 | /* |
3716 | * IRQs < 16 are already in the irq_2_pin[] map | |
3717 | */ | |
b81bb373 | 3718 | if (irq >= legacy_pic->nr_legacy_irqs) { |
7e495529 | 3719 | if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) { |
f3d1915a CG |
3720 | printk(KERN_INFO "can not add pin %d for irq %d\n", |
3721 | pin, irq); | |
3722 | return 0; | |
3723 | } | |
5ef21837 YL |
3724 | } |
3725 | ||
60c69948 | 3726 | setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity); |
5ef21837 YL |
3727 | |
3728 | return 0; | |
3729 | } | |
3730 | ||
e5198075 YL |
3731 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3732 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3733 | { |
e5198075 | 3734 | int ioapic, pin; |
5ef21837 YL |
3735 | /* |
3736 | * Avoid pin reprogramming. PRTs typically include entries | |
3737 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3738 | * we only program the IOAPIC on the first. | |
3739 | */ | |
e5198075 YL |
3740 | ioapic = irq_attr->ioapic; |
3741 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3742 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3743 | pr_debug("Pin %d-%d already programmed\n", | |
3744 | mp_ioapics[ioapic].apicid, pin); | |
3745 | return 0; | |
3746 | } | |
3747 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3748 | ||
e5198075 | 3749 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3750 | } |
3751 | ||
2a4ab640 FT |
3752 | u8 __init io_apic_unique_id(u8 id) |
3753 | { | |
3754 | #ifdef CONFIG_X86_32 | |
3755 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3756 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3757 | return io_apic_get_unique_id(nr_ioapics, id); | |
3758 | else | |
3759 | return id; | |
3760 | #else | |
3761 | int i; | |
3762 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3763 | |
2a4ab640 FT |
3764 | bitmap_zero(used, 256); |
3765 | for (i = 0; i < nr_ioapics; i++) { | |
3766 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3767 | __set_bit(ia->apicid, used); | |
3768 | } | |
3769 | if (!test_bit(id, used)) | |
3770 | return id; | |
3771 | return find_first_zero_bit(used, 256); | |
3772 | #endif | |
3773 | } | |
1da177e4 | 3774 | |
54168ed7 | 3775 | #ifdef CONFIG_X86_32 |
36062448 | 3776 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3777 | { |
3778 | union IO_APIC_reg_00 reg_00; | |
3779 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3780 | physid_mask_t tmp; | |
3781 | unsigned long flags; | |
3782 | int i = 0; | |
3783 | ||
3784 | /* | |
36062448 PC |
3785 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3786 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3787 | * supports up to 16 on one shared APIC bus. |
36062448 | 3788 | * |
1da177e4 LT |
3789 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3790 | * advantage of new APIC bus architecture. | |
3791 | */ | |
3792 | ||
3793 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3794 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3795 | |
dade7716 | 3796 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3797 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3798 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3799 | |
3800 | if (apic_id >= get_physical_broadcast()) { | |
3801 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3802 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3803 | apic_id = reg_00.bits.ID; | |
3804 | } | |
3805 | ||
3806 | /* | |
36062448 | 3807 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3808 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3809 | */ | |
7abc0753 | 3810 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3811 | |
3812 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3813 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3814 | break; |
3815 | } | |
3816 | ||
3817 | if (i == get_physical_broadcast()) | |
3818 | panic("Max apic_id exceeded!\n"); | |
3819 | ||
3820 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3821 | "trying %d\n", ioapic, apic_id, i); | |
3822 | ||
3823 | apic_id = i; | |
36062448 | 3824 | } |
1da177e4 | 3825 | |
7abc0753 | 3826 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3827 | physids_or(apic_id_map, apic_id_map, tmp); |
3828 | ||
3829 | if (reg_00.bits.ID != apic_id) { | |
3830 | reg_00.bits.ID = apic_id; | |
3831 | ||
dade7716 | 3832 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3833 | io_apic_write(ioapic, 0, reg_00.raw); |
3834 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3835 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3836 | |
3837 | /* Sanity check */ | |
6070f9ec AD |
3838 | if (reg_00.bits.ID != apic_id) { |
3839 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3840 | return -1; | |
3841 | } | |
1da177e4 LT |
3842 | } |
3843 | ||
3844 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3845 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3846 | ||
3847 | return apic_id; | |
3848 | } | |
58f892e0 | 3849 | #endif |
1da177e4 | 3850 | |
36062448 | 3851 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3852 | { |
3853 | union IO_APIC_reg_01 reg_01; | |
3854 | unsigned long flags; | |
3855 | ||
dade7716 | 3856 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3857 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3858 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3859 | |
3860 | return reg_01.bits.version; | |
3861 | } | |
3862 | ||
9a0a91bb | 3863 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3864 | { |
9a0a91bb | 3865 | int ioapic, pin, idx; |
61fd47e0 SL |
3866 | |
3867 | if (skip_ioapic_setup) | |
3868 | return -1; | |
3869 | ||
9a0a91bb EB |
3870 | ioapic = mp_find_ioapic(gsi); |
3871 | if (ioapic < 0) | |
61fd47e0 SL |
3872 | return -1; |
3873 | ||
9a0a91bb EB |
3874 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3875 | if (pin < 0) | |
3876 | return -1; | |
3877 | ||
3878 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3879 | if (idx < 0) | |
61fd47e0 SL |
3880 | return -1; |
3881 | ||
9a0a91bb EB |
3882 | *trigger = irq_trigger(idx); |
3883 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3884 | return 0; |
3885 | } | |
3886 | ||
497c9a19 YL |
3887 | /* |
3888 | * This function currently is only a helper for the i386 smp boot process where | |
3889 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3890 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3891 | */ |
3892 | #ifdef CONFIG_SMP | |
3893 | void __init setup_ioapic_dest(void) | |
3894 | { | |
fad53995 | 3895 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 3896 | struct irq_desc *desc; |
22f65d31 | 3897 | const struct cpumask *mask; |
497c9a19 YL |
3898 | |
3899 | if (skip_ioapic_setup == 1) | |
3900 | return; | |
3901 | ||
fad53995 | 3902 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
3903 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
3904 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3905 | if (irq_entry == -1) | |
3906 | continue; | |
3907 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3908 | |
fad53995 EB |
3909 | if ((ioapic > 0) && (irq > 16)) |
3910 | continue; | |
3911 | ||
b9c61b70 | 3912 | desc = irq_to_desc(irq); |
6c2e9403 | 3913 | |
b9c61b70 YL |
3914 | /* |
3915 | * Honour affinities which have been set in early boot | |
3916 | */ | |
3917 | if (desc->status & | |
3918 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
f7e909ea | 3919 | mask = desc->irq_data.affinity; |
b9c61b70 YL |
3920 | else |
3921 | mask = apic->target_cpus(); | |
497c9a19 | 3922 | |
b9c61b70 | 3923 | if (intr_remapping_enabled) |
f19f5ecc | 3924 | ir_ioapic_set_affinity(&desc->irq_data, mask, false); |
b9c61b70 | 3925 | else |
f7e909ea | 3926 | ioapic_set_affinity(&desc->irq_data, mask, false); |
497c9a19 | 3927 | } |
b9c61b70 | 3928 | |
497c9a19 YL |
3929 | } |
3930 | #endif | |
3931 | ||
54168ed7 IM |
3932 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3933 | ||
3934 | static struct resource *ioapic_resources; | |
3935 | ||
ffc43836 | 3936 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
3937 | { |
3938 | unsigned long n; | |
3939 | struct resource *res; | |
3940 | char *mem; | |
3941 | int i; | |
3942 | ||
3943 | if (nr_ioapics <= 0) | |
3944 | return NULL; | |
3945 | ||
3946 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3947 | n *= nr_ioapics; | |
3948 | ||
3949 | mem = alloc_bootmem(n); | |
3950 | res = (void *)mem; | |
3951 | ||
ffc43836 | 3952 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 3953 | |
ffc43836 CG |
3954 | for (i = 0; i < nr_ioapics; i++) { |
3955 | res[i].name = mem; | |
3956 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3957 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3958 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
3959 | } |
3960 | ||
3961 | ioapic_resources = res; | |
3962 | ||
3963 | return res; | |
3964 | } | |
54168ed7 | 3965 | |
23f9b267 | 3966 | void __init ioapic_and_gsi_init(void) |
f3294a33 YL |
3967 | { |
3968 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3969 | struct resource *ioapic_res; |
d6c88a50 | 3970 | int i; |
f3294a33 | 3971 | |
ffc43836 | 3972 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
3973 | for (i = 0; i < nr_ioapics; i++) { |
3974 | if (smp_found_config) { | |
b5ba7e6d | 3975 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 3976 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3977 | if (!ioapic_phys) { |
3978 | printk(KERN_ERR | |
3979 | "WARNING: bogus zero IO-APIC " | |
3980 | "address found in MPTABLE, " | |
3981 | "disabling IO/APIC support!\n"); | |
3982 | smp_found_config = 0; | |
3983 | skip_ioapic_setup = 1; | |
3984 | goto fake_ioapic_page; | |
3985 | } | |
54168ed7 | 3986 | #endif |
f3294a33 | 3987 | } else { |
54168ed7 | 3988 | #ifdef CONFIG_X86_32 |
f3294a33 | 3989 | fake_ioapic_page: |
54168ed7 | 3990 | #endif |
e79c65a9 | 3991 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3992 | ioapic_phys = __pa(ioapic_phys); |
3993 | } | |
3994 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3995 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3996 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3997 | ioapic_phys); | |
f3294a33 | 3998 | idx++; |
54168ed7 | 3999 | |
ffc43836 | 4000 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4001 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4002 | ioapic_res++; |
f3294a33 | 4003 | } |
23f9b267 TG |
4004 | |
4005 | probe_nr_irqs_gsi(); | |
f3294a33 YL |
4006 | } |
4007 | ||
857fdc53 | 4008 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4009 | { |
4010 | int i; | |
4011 | struct resource *r = ioapic_resources; | |
4012 | ||
4013 | if (!r) { | |
857fdc53 | 4014 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4015 | printk(KERN_ERR |
4016 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4017 | return; |
54168ed7 IM |
4018 | } |
4019 | ||
4020 | for (i = 0; i < nr_ioapics; i++) { | |
4021 | insert_resource(&iomem_resource, r); | |
4022 | r++; | |
4023 | } | |
54168ed7 | 4024 | } |
2a4ab640 | 4025 | |
eddb0c55 | 4026 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4027 | { |
4028 | int i = 0; | |
4029 | ||
4030 | /* Find the IOAPIC that manages this GSI. */ | |
4031 | for (i = 0; i < nr_ioapics; i++) { | |
4032 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4033 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4034 | return i; | |
4035 | } | |
54168ed7 | 4036 | |
2a4ab640 FT |
4037 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4038 | return -1; | |
4039 | } | |
4040 | ||
eddb0c55 | 4041 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4042 | { |
4043 | if (WARN_ON(ioapic == -1)) | |
4044 | return -1; | |
4045 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4046 | return -1; | |
4047 | ||
4048 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4049 | } | |
4050 | ||
4051 | static int bad_ioapic(unsigned long address) | |
4052 | { | |
4053 | if (nr_ioapics >= MAX_IO_APICS) { | |
4054 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4055 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4056 | return 1; | |
4057 | } | |
4058 | if (!address) { | |
4059 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4060 | " found in table, skipping!\n"); | |
4061 | return 1; | |
4062 | } | |
54168ed7 IM |
4063 | return 0; |
4064 | } | |
4065 | ||
2a4ab640 FT |
4066 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4067 | { | |
4068 | int idx = 0; | |
7716a5c4 | 4069 | int entries; |
2a4ab640 FT |
4070 | |
4071 | if (bad_ioapic(address)) | |
4072 | return; | |
4073 | ||
4074 | idx = nr_ioapics; | |
4075 | ||
4076 | mp_ioapics[idx].type = MP_IOAPIC; | |
4077 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4078 | mp_ioapics[idx].apicaddr = address; | |
4079 | ||
4080 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4081 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4082 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4083 | ||
4084 | /* | |
4085 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4086 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4087 | */ | |
7716a5c4 | 4088 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4089 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4090 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4091 | ||
4092 | /* | |
4093 | * The number of IO-APIC IRQ registers (== #pins): | |
4094 | */ | |
4095 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4096 | |
a4384df3 EB |
4097 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4098 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4099 | |
4100 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4101 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4102 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4103 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4104 | ||
4105 | nr_ioapics++; | |
4106 | } | |
05ddafb1 JP |
4107 | |
4108 | /* Enable IOAPIC early just for system timer */ | |
4109 | void __init pre_init_apic_IRQ0(void) | |
4110 | { | |
4111 | struct irq_cfg *cfg; | |
05ddafb1 JP |
4112 | |
4113 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4114 | #ifndef CONFIG_SMP | |
4115 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4116 | #endif | |
fbc6bff0 TG |
4117 | /* Make sure the irq descriptor is set up */ |
4118 | cfg = alloc_irq_and_cfg_at(0, 0); | |
05ddafb1 JP |
4119 | |
4120 | setup_local_APIC(); | |
4121 | ||
05ddafb1 JP |
4122 | add_pin_to_irq_node(cfg, 0, 0, 0); |
4123 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4124 | ||
60c69948 | 4125 | setup_ioapic_irq(0, 0, 0, cfg, 0, 0); |
05ddafb1 | 4126 | } |