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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
d7f3d478 | 34 | #include <linux/irqdomain.h> |
7dfb7103 | 35 | #include <linux/freezer.h> |
f26d6a2b | 36 | #include <linux/kthread.h> |
54168ed7 | 37 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 38 | #include <linux/slab.h> |
d4057bdb | 39 | #include <linux/bootmem.h> |
54d5d424 | 40 | |
d4057bdb | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
6d652ea1 | 44 | #include <asm/cpu.h> |
1da177e4 | 45 | #include <asm/desc.h> |
d4057bdb YL |
46 | #include <asm/proto.h> |
47 | #include <asm/acpi.h> | |
48 | #include <asm/dma.h> | |
1da177e4 | 49 | #include <asm/timer.h> |
306e440d | 50 | #include <asm/i8259.h> |
a4dbc34d | 51 | #include <asm/setup.h> |
8a8f422d | 52 | #include <asm/irq_remapping.h> |
2c1b284e | 53 | #include <asm/hw_irq.h> |
1da177e4 | 54 | |
7b6aa335 | 55 | #include <asm/apic.h> |
1da177e4 | 56 | |
f44d1692 JL |
57 | #define for_each_ioapic(idx) \ |
58 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
59 | #define for_each_ioapic_reverse(idx) \ | |
60 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
61 | #define for_each_pin(idx, pin) \ | |
62 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
63 | #define for_each_ioapic_pin(idx, pin) \ | |
64 | for_each_ioapic((idx)) \ | |
65 | for_each_pin((idx), (pin)) | |
66 | ||
2977fb3f | 67 | #define for_each_irq_pin(entry, head) \ |
a178b87b | 68 | list_for_each_entry(entry, &head, list) |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 | 76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
d7f3d478 | 77 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 78 | static unsigned int ioapic_dynirq_base; |
b81975ea | 79 | static int ioapic_initialized; |
efa2559f | 80 | |
49c7e600 JL |
81 | struct mp_chip_data { |
82 | struct IO_APIC_route_entry entry; | |
83 | int trigger; | |
84 | int polarity; | |
96ed44b2 | 85 | u32 count; |
49c7e600 JL |
86 | bool isa_irq; |
87 | }; | |
88 | ||
b69c6c3b SS |
89 | static struct ioapic { |
90 | /* | |
91 | * # of IRQ routing registers | |
92 | */ | |
93 | int nr_registers; | |
57a6f740 SS |
94 | /* |
95 | * Saved state during suspend/resume, or while enabling intr-remap. | |
96 | */ | |
97 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
98 | /* I/O APIC config */ |
99 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
100 | /* IO APIC gsi routing info */ |
101 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
102 | struct ioapic_domain_cfg irqdomain_cfg; |
103 | struct irq_domain *irqdomain; | |
15516a3b | 104 | struct resource *iomem_res; |
b69c6c3b | 105 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 106 | |
6f50d45f | 107 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 108 | |
6f50d45f | 109 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 110 | { |
6f50d45f | 111 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
112 | } |
113 | ||
6f50d45f | 114 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 115 | { |
6f50d45f | 116 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
117 | } |
118 | ||
6f50d45f | 119 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 120 | { |
6f50d45f | 121 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 122 | } |
9f640ccb | 123 | |
18e48551 JL |
124 | static inline int mp_ioapic_pin_count(int ioapic) |
125 | { | |
126 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
127 | ||
128 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
129 | } | |
130 | ||
131 | u32 mp_pin_to_gsi(int ioapic, int pin) | |
132 | { | |
133 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
134 | } | |
135 | ||
d32932d0 JL |
136 | static inline bool mp_is_legacy_irq(int irq) |
137 | { | |
138 | return irq >= 0 && irq < nr_legacy_irqs(); | |
139 | } | |
140 | ||
95d76acc JL |
141 | /* |
142 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
143 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
144 | * may rely on non-legacy pins on the first IOAPIC. | |
145 | */ | |
18e48551 JL |
146 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
147 | { | |
95d76acc JL |
148 | if (!nr_legacy_irqs()) |
149 | return 0; | |
150 | ||
d32932d0 | 151 | return ioapic == 0 || mp_is_legacy_irq(irq); |
18e48551 JL |
152 | } |
153 | ||
d7f3d478 JL |
154 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
155 | { | |
156 | return ioapics[ioapic].irqdomain; | |
157 | } | |
158 | ||
c040aaeb | 159 | int nr_ioapics; |
2a4ab640 | 160 | |
a4384df3 EB |
161 | /* The one past the highest gsi number used */ |
162 | u32 gsi_top; | |
5777372a | 163 | |
584f734d | 164 | /* MP IRQ source entries */ |
c2c21745 | 165 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
166 | |
167 | /* # of MP IRQ source entries */ | |
168 | int mp_irq_entries; | |
169 | ||
bb8187d3 | 170 | #ifdef CONFIG_EISA |
8732fc4b AS |
171 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
172 | #endif | |
173 | ||
174 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
175 | ||
efa2559f YL |
176 | int skip_ioapic_setup; |
177 | ||
7167d08e HK |
178 | /** |
179 | * disable_ioapic_support() - disables ioapic support at runtime | |
180 | */ | |
181 | void disable_ioapic_support(void) | |
65a4e574 IM |
182 | { |
183 | #ifdef CONFIG_PCI | |
184 | noioapicquirk = 1; | |
185 | noioapicreroute = -1; | |
186 | #endif | |
187 | skip_ioapic_setup = 1; | |
188 | } | |
189 | ||
54168ed7 | 190 | static int __init parse_noapic(char *str) |
efa2559f YL |
191 | { |
192 | /* disable IO-APIC */ | |
7167d08e | 193 | disable_ioapic_support(); |
efa2559f YL |
194 | return 0; |
195 | } | |
196 | early_param("noapic", parse_noapic); | |
66759a01 | 197 | |
2d8009ba FT |
198 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
199 | void mp_save_irq(struct mpc_intsrc *m) | |
200 | { | |
201 | int i; | |
202 | ||
203 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
204 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
205 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
206 | m->srcbusirq, m->dstapic, m->dstirq); | |
207 | ||
208 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 209 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
210 | return; |
211 | } | |
212 | ||
0e3fa13f | 213 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
214 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
215 | panic("Max # of irq sources exceeded!!\n"); | |
216 | } | |
217 | ||
0b8f1efa | 218 | struct irq_pin_list { |
a178b87b | 219 | struct list_head list; |
0b8f1efa | 220 | int apic, pin; |
0b8f1efa YL |
221 | }; |
222 | ||
7e495529 | 223 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 224 | { |
d32932d0 | 225 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); |
0b8f1efa YL |
226 | } |
227 | ||
7e899419 YL |
228 | static void alloc_ioapic_saved_registers(int idx) |
229 | { | |
230 | size_t size; | |
231 | ||
232 | if (ioapics[idx].saved_registers) | |
233 | return; | |
234 | ||
235 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; | |
236 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); | |
237 | if (!ioapics[idx].saved_registers) | |
238 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); | |
239 | } | |
240 | ||
15516a3b JL |
241 | static void free_ioapic_saved_registers(int idx) |
242 | { | |
243 | kfree(ioapics[idx].saved_registers); | |
244 | ioapics[idx].saved_registers = NULL; | |
245 | } | |
246 | ||
11d686e9 | 247 | int __init arch_early_ioapic_init(void) |
8f09cd20 | 248 | { |
13315320 | 249 | int i; |
d6c88a50 | 250 | |
95d76acc | 251 | if (!nr_legacy_irqs()) |
1f91233c | 252 | io_apic_irqs = ~0UL; |
1f91233c | 253 | |
7e899419 YL |
254 | for_each_ioapic(i) |
255 | alloc_ioapic_saved_registers(i); | |
4c79185c | 256 | |
13a0c3c2 | 257 | return 0; |
0b8f1efa | 258 | } |
8f09cd20 | 259 | |
130fe05d LT |
260 | struct io_apic { |
261 | unsigned int index; | |
262 | unsigned int unused[3]; | |
263 | unsigned int data; | |
0280f7c4 SS |
264 | unsigned int unused2[11]; |
265 | unsigned int eoi; | |
130fe05d LT |
266 | }; |
267 | ||
268 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
269 | { | |
270 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 271 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
272 | } |
273 | ||
ad66e1ef | 274 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
275 | { |
276 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
277 | writel(vector, &io_apic->eoi); | |
278 | } | |
279 | ||
4a8e2a31 | 280 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
281 | { |
282 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
283 | writel(reg, &io_apic->index); | |
284 | return readl(&io_apic->data); | |
285 | } | |
286 | ||
4a8e2a31 | 287 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
288 | { |
289 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 290 | |
130fe05d LT |
291 | writel(reg, &io_apic->index); |
292 | writel(value, &io_apic->data); | |
293 | } | |
294 | ||
295 | /* | |
296 | * Re-write a value: to be used for read-modify-write | |
297 | * cycles where the read already set up the index register. | |
298 | * | |
299 | * Older SiS APIC requires we rewrite the index register | |
300 | */ | |
4a8e2a31 | 301 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 302 | { |
54168ed7 | 303 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
304 | |
305 | if (sis_apic_bug) | |
306 | writel(reg, &io_apic->index); | |
130fe05d LT |
307 | writel(value, &io_apic->data); |
308 | } | |
309 | ||
cf4c6a2f AK |
310 | union entry_union { |
311 | struct { u32 w1, w2; }; | |
312 | struct IO_APIC_route_entry entry; | |
313 | }; | |
314 | ||
e57253a8 SS |
315 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
316 | { | |
317 | union entry_union eu; | |
318 | ||
319 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
320 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 321 | |
e57253a8 SS |
322 | return eu.entry; |
323 | } | |
324 | ||
cf4c6a2f AK |
325 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
326 | { | |
327 | union entry_union eu; | |
328 | unsigned long flags; | |
136d249e | 329 | |
dade7716 | 330 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 331 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 332 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 333 | |
cf4c6a2f AK |
334 | return eu.entry; |
335 | } | |
336 | ||
f9dadfa7 LT |
337 | /* |
338 | * When we write a new IO APIC routing entry, we need to write the high | |
339 | * word first! If the mask bit in the low word is clear, we will enable | |
340 | * the interrupt, and we need to make sure the entry is fully populated | |
341 | * before that happens. | |
342 | */ | |
136d249e | 343 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 344 | { |
50a8d4d2 F |
345 | union entry_union eu = {{0, 0}}; |
346 | ||
cf4c6a2f | 347 | eu.entry = e; |
f9dadfa7 LT |
348 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
349 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
350 | } |
351 | ||
1a8ce7ff | 352 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
353 | { |
354 | unsigned long flags; | |
136d249e | 355 | |
dade7716 | 356 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 357 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 358 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
359 | } |
360 | ||
361 | /* | |
362 | * When we mask an IO APIC routing entry, we need to write the low | |
363 | * word first, in order to set the mask bit before we change the | |
364 | * high bits! | |
365 | */ | |
366 | static void ioapic_mask_entry(int apic, int pin) | |
367 | { | |
368 | unsigned long flags; | |
369 | union entry_union eu = { .entry.mask = 1 }; | |
370 | ||
dade7716 | 371 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
372 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
373 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 374 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
375 | } |
376 | ||
1da177e4 LT |
377 | /* |
378 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
379 | * shared ISA-space IRQs, so we have to support them. We are super | |
380 | * fast in the common case, and fast for shared ISA-space IRQs. | |
381 | */ | |
136d249e | 382 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 383 | { |
a178b87b | 384 | struct irq_pin_list *entry; |
0f978f45 | 385 | |
2977fb3f | 386 | /* don't allow duplicates */ |
a178b87b | 387 | for_each_irq_pin(entry, cfg->irq_2_pin) |
0f978f45 | 388 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 389 | return 0; |
0f978f45 | 390 | |
7e495529 | 391 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 392 | if (!entry) { |
c767a54b JP |
393 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
394 | node, apic, pin); | |
f3d1915a | 395 | return -ENOMEM; |
a7428cd2 | 396 | } |
1da177e4 LT |
397 | entry->apic = apic; |
398 | entry->pin = pin; | |
875e68ec | 399 | |
a178b87b | 400 | list_add_tail(&entry->list, &cfg->irq_2_pin); |
f3d1915a CG |
401 | return 0; |
402 | } | |
403 | ||
df334bea JL |
404 | static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin) |
405 | { | |
a178b87b | 406 | struct irq_pin_list *tmp, *entry; |
df334bea | 407 | |
a178b87b | 408 | list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list) |
df334bea | 409 | if (entry->apic == apic && entry->pin == pin) { |
a178b87b | 410 | list_del(&entry->list); |
df334bea JL |
411 | kfree(entry); |
412 | return; | |
df334bea JL |
413 | } |
414 | } | |
415 | ||
f3d1915a CG |
416 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
417 | { | |
7e495529 | 418 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 419 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
420 | } |
421 | ||
422 | /* | |
423 | * Reroute an IRQ to a different pin. | |
424 | */ | |
85ac16d0 | 425 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
426 | int oldapic, int oldpin, |
427 | int newapic, int newpin) | |
1da177e4 | 428 | { |
535b6429 | 429 | struct irq_pin_list *entry; |
1da177e4 | 430 | |
2977fb3f | 431 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
432 | if (entry->apic == oldapic && entry->pin == oldpin) { |
433 | entry->apic = newapic; | |
434 | entry->pin = newpin; | |
0f978f45 | 435 | /* every one is different, right? */ |
4eea6fff | 436 | return; |
0f978f45 | 437 | } |
1da177e4 | 438 | } |
0f978f45 | 439 | |
4eea6fff JF |
440 | /* old apic/pin didn't exist, so just add new ones */ |
441 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
442 | } |
443 | ||
c29d9db3 SS |
444 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
445 | int mask_and, int mask_or, | |
446 | void (*final)(struct irq_pin_list *entry)) | |
447 | { | |
448 | unsigned int reg, pin; | |
449 | ||
450 | pin = entry->pin; | |
451 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
452 | reg &= mask_and; | |
453 | reg |= mask_or; | |
454 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
455 | if (final) | |
456 | final(entry); | |
457 | } | |
458 | ||
2f210deb JF |
459 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
460 | int mask_and, int mask_or, | |
461 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 462 | { |
87783be4 | 463 | struct irq_pin_list *entry; |
047c8fdb | 464 | |
c29d9db3 SS |
465 | for_each_irq_pin(entry, cfg->irq_2_pin) |
466 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
467 | } | |
468 | ||
7f3e632f | 469 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 470 | { |
87783be4 CG |
471 | /* |
472 | * Synchronize the IO-APIC and the CPU by doing | |
473 | * a dummy read from the IO-APIC | |
474 | */ | |
475 | struct io_apic __iomem *io_apic; | |
136d249e | 476 | |
87783be4 | 477 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 478 | readl(&io_apic->data); |
1da177e4 LT |
479 | } |
480 | ||
dd5f15e5 | 481 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 482 | { |
dd5f15e5 TG |
483 | unsigned long flags; |
484 | ||
485 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 486 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 487 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 488 | } |
1da177e4 | 489 | |
90297c5f | 490 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 491 | { |
a9786091 | 492 | mask_ioapic(irqd_cfg(data)); |
dd5f15e5 | 493 | } |
3145e941 | 494 | |
dd5f15e5 TG |
495 | static void __unmask_ioapic(struct irq_cfg *cfg) |
496 | { | |
497 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
498 | } |
499 | ||
dd5f15e5 | 500 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
501 | { |
502 | unsigned long flags; | |
503 | ||
dade7716 | 504 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 505 | __unmask_ioapic(cfg); |
dade7716 | 506 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
507 | } |
508 | ||
90297c5f | 509 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 510 | { |
a9786091 | 511 | unmask_ioapic(irqd_cfg(data)); |
3145e941 YL |
512 | } |
513 | ||
c0205701 SS |
514 | /* |
515 | * IO-APIC versions below 0x20 don't support EOI register. | |
516 | * For the record, here is the information about various versions: | |
517 | * 0Xh 82489DX | |
518 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
519 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
520 | * 30h-FFh Reserved | |
521 | * | |
522 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
523 | * version as 0x2. This is an error with documentation and these ICH chips | |
524 | * use io-apic's of version 0x20. | |
525 | * | |
526 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
527 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
528 | * mode to edge and then back to level, with RTE being masked during this. | |
529 | */ | |
ad66e1ef | 530 | static void __eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
531 | { |
532 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 533 | io_apic_eoi(apic, vector); |
c0205701 SS |
534 | } else { |
535 | struct IO_APIC_route_entry entry, entry1; | |
536 | ||
537 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
538 | ||
539 | /* | |
540 | * Mask the entry and change the trigger mode to edge. | |
541 | */ | |
542 | entry1.mask = 1; | |
543 | entry1.trigger = IOAPIC_EDGE; | |
544 | ||
545 | __ioapic_write_entry(apic, pin, entry1); | |
546 | ||
547 | /* | |
548 | * Restore the previous level triggered entry. | |
549 | */ | |
550 | __ioapic_write_entry(apic, pin, entry); | |
551 | } | |
552 | } | |
553 | ||
d32932d0 JL |
554 | void eoi_ioapic_pin(int vector, struct irq_cfg *cfg) |
555 | { | |
556 | unsigned long flags; | |
557 | struct irq_pin_list *entry; | |
558 | ||
559 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
560 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
ad66e1ef | 561 | __eoi_ioapic_pin(entry->apic, entry->pin, vector); |
c0205701 SS |
562 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
563 | } | |
564 | ||
1da177e4 LT |
565 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
566 | { | |
567 | struct IO_APIC_route_entry entry; | |
36062448 | 568 | |
1da177e4 | 569 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 570 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
571 | if (entry.delivery_mode == dest_SMI) |
572 | return; | |
1e75b31d | 573 | |
1da177e4 | 574 | /* |
1e75b31d SS |
575 | * Make sure the entry is masked and re-read the contents to check |
576 | * if it is a level triggered pin and if the remote-IRR is set. | |
577 | */ | |
578 | if (!entry.mask) { | |
579 | entry.mask = 1; | |
580 | ioapic_write_entry(apic, pin, entry); | |
581 | entry = ioapic_read_entry(apic, pin); | |
582 | } | |
583 | ||
584 | if (entry.irr) { | |
c0205701 SS |
585 | unsigned long flags; |
586 | ||
1e75b31d SS |
587 | /* |
588 | * Make sure the trigger mode is set to level. Explicit EOI | |
589 | * doesn't clear the remote-IRR if the trigger mode is not | |
590 | * set to level. | |
591 | */ | |
592 | if (!entry.trigger) { | |
593 | entry.trigger = IOAPIC_LEVEL; | |
594 | ioapic_write_entry(apic, pin, entry); | |
595 | } | |
c0205701 | 596 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
ad66e1ef | 597 | __eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 598 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
599 | } |
600 | ||
601 | /* | |
602 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
603 | * bit. | |
1da177e4 | 604 | */ |
f9dadfa7 | 605 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
606 | entry = ioapic_read_entry(apic, pin); |
607 | if (entry.irr) | |
c767a54b | 608 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 609 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
610 | } |
611 | ||
54168ed7 | 612 | static void clear_IO_APIC (void) |
1da177e4 LT |
613 | { |
614 | int apic, pin; | |
615 | ||
f44d1692 JL |
616 | for_each_ioapic_pin(apic, pin) |
617 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
618 | } |
619 | ||
54168ed7 | 620 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
621 | /* |
622 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
623 | * specific CPU-side IRQs. | |
624 | */ | |
625 | ||
626 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
627 | static int pirq_entries[MAX_PIRQS] = { |
628 | [0 ... MAX_PIRQS - 1] = -1 | |
629 | }; | |
1da177e4 | 630 | |
1da177e4 LT |
631 | static int __init ioapic_pirq_setup(char *str) |
632 | { | |
633 | int i, max; | |
634 | int ints[MAX_PIRQS+1]; | |
635 | ||
636 | get_options(str, ARRAY_SIZE(ints), ints); | |
637 | ||
1da177e4 LT |
638 | apic_printk(APIC_VERBOSE, KERN_INFO |
639 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
640 | max = MAX_PIRQS; | |
641 | if (ints[0] < MAX_PIRQS) | |
642 | max = ints[0]; | |
643 | ||
644 | for (i = 0; i < max; i++) { | |
645 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
646 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
647 | /* | |
648 | * PIRQs are mapped upside down, usually. | |
649 | */ | |
650 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
651 | } | |
652 | return 1; | |
653 | } | |
654 | ||
655 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
656 | #endif /* CONFIG_X86_32 */ |
657 | ||
54168ed7 | 658 | /* |
05c3dc2c | 659 | * Saves all the IO-APIC RTE's |
54168ed7 | 660 | */ |
31dce14a | 661 | int save_ioapic_entries(void) |
54168ed7 | 662 | { |
54168ed7 | 663 | int apic, pin; |
31dce14a | 664 | int err = 0; |
54168ed7 | 665 | |
f44d1692 | 666 | for_each_ioapic(apic) { |
57a6f740 | 667 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
668 | err = -ENOMEM; |
669 | continue; | |
670 | } | |
54168ed7 | 671 | |
f44d1692 | 672 | for_each_pin(apic, pin) |
57a6f740 | 673 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 674 | ioapic_read_entry(apic, pin); |
b24696bc | 675 | } |
5ffa4eb2 | 676 | |
31dce14a | 677 | return err; |
54168ed7 IM |
678 | } |
679 | ||
b24696bc FY |
680 | /* |
681 | * Mask all IO APIC entries. | |
682 | */ | |
31dce14a | 683 | void mask_ioapic_entries(void) |
05c3dc2c SS |
684 | { |
685 | int apic, pin; | |
686 | ||
f44d1692 | 687 | for_each_ioapic(apic) { |
2f344d2e | 688 | if (!ioapics[apic].saved_registers) |
31dce14a | 689 | continue; |
b24696bc | 690 | |
f44d1692 | 691 | for_each_pin(apic, pin) { |
05c3dc2c SS |
692 | struct IO_APIC_route_entry entry; |
693 | ||
57a6f740 | 694 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
695 | if (!entry.mask) { |
696 | entry.mask = 1; | |
697 | ioapic_write_entry(apic, pin, entry); | |
698 | } | |
699 | } | |
700 | } | |
701 | } | |
702 | ||
b24696bc | 703 | /* |
57a6f740 | 704 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 705 | */ |
31dce14a | 706 | int restore_ioapic_entries(void) |
54168ed7 IM |
707 | { |
708 | int apic, pin; | |
709 | ||
f44d1692 | 710 | for_each_ioapic(apic) { |
2f344d2e | 711 | if (!ioapics[apic].saved_registers) |
31dce14a | 712 | continue; |
b24696bc | 713 | |
f44d1692 | 714 | for_each_pin(apic, pin) |
54168ed7 | 715 | ioapic_write_entry(apic, pin, |
57a6f740 | 716 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 717 | } |
b24696bc | 718 | return 0; |
54168ed7 IM |
719 | } |
720 | ||
1da177e4 LT |
721 | /* |
722 | * Find the IRQ entry number of a certain pin. | |
723 | */ | |
6f50d45f | 724 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
725 | { |
726 | int i; | |
727 | ||
728 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 729 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 730 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
731 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
732 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
733 | return i; |
734 | ||
735 | return -1; | |
736 | } | |
737 | ||
738 | /* | |
739 | * Find the pin to which IRQ[irq] (ISA) is connected | |
740 | */ | |
fcfd636a | 741 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
742 | { |
743 | int i; | |
744 | ||
745 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 746 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 747 | |
d27e2b8e | 748 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
749 | (mp_irqs[i].irqtype == type) && |
750 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 751 | |
c2c21745 | 752 | return mp_irqs[i].dstirq; |
1da177e4 LT |
753 | } |
754 | return -1; | |
755 | } | |
756 | ||
fcfd636a EB |
757 | static int __init find_isa_irq_apic(int irq, int type) |
758 | { | |
759 | int i; | |
760 | ||
761 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 762 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 763 | |
73b2961b | 764 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
765 | (mp_irqs[i].irqtype == type) && |
766 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
767 | break; |
768 | } | |
6f50d45f | 769 | |
fcfd636a | 770 | if (i < mp_irq_entries) { |
6f50d45f YL |
771 | int ioapic_idx; |
772 | ||
f44d1692 | 773 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
774 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
775 | return ioapic_idx; | |
fcfd636a EB |
776 | } |
777 | ||
778 | return -1; | |
779 | } | |
780 | ||
bb8187d3 | 781 | #ifdef CONFIG_EISA |
1da177e4 LT |
782 | /* |
783 | * EISA Edge/Level control register, ELCR | |
784 | */ | |
785 | static int EISA_ELCR(unsigned int irq) | |
786 | { | |
95d76acc | 787 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
788 | unsigned int port = 0x4d0 + (irq >> 3); |
789 | return (inb(port) >> (irq & 7)) & 1; | |
790 | } | |
791 | apic_printk(APIC_VERBOSE, KERN_INFO | |
792 | "Broken MPtable reports ISA irq %d\n", irq); | |
793 | return 0; | |
794 | } | |
54168ed7 | 795 | |
c0a282c2 | 796 | #endif |
1da177e4 | 797 | |
6728801d AS |
798 | /* ISA interrupts are always polarity zero edge triggered, |
799 | * when listed as conforming in the MP table. */ | |
800 | ||
801 | #define default_ISA_trigger(idx) (0) | |
802 | #define default_ISA_polarity(idx) (0) | |
803 | ||
1da177e4 LT |
804 | /* EISA interrupts are always polarity zero and can be edge or level |
805 | * trigger depending on the ELCR value. If an interrupt is listed as | |
806 | * EISA conforming in the MP table, that means its trigger type must | |
807 | * be read in from the ELCR */ | |
808 | ||
c2c21745 | 809 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 810 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
811 | |
812 | /* PCI interrupts are always polarity one level triggered, | |
813 | * when listed as conforming in the MP table. */ | |
814 | ||
815 | #define default_PCI_trigger(idx) (1) | |
816 | #define default_PCI_polarity(idx) (1) | |
817 | ||
b77cf6a8 | 818 | static int irq_polarity(int idx) |
1da177e4 | 819 | { |
c2c21745 | 820 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
821 | int polarity; |
822 | ||
823 | /* | |
824 | * Determine IRQ line polarity (high active or low active): | |
825 | */ | |
c2c21745 | 826 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 827 | { |
54168ed7 IM |
828 | case 0: /* conforms, ie. bus-type dependent polarity */ |
829 | if (test_bit(bus, mp_bus_not_pci)) | |
830 | polarity = default_ISA_polarity(idx); | |
831 | else | |
832 | polarity = default_PCI_polarity(idx); | |
833 | break; | |
834 | case 1: /* high active */ | |
835 | { | |
836 | polarity = 0; | |
837 | break; | |
838 | } | |
839 | case 2: /* reserved */ | |
840 | { | |
c767a54b | 841 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
842 | polarity = 1; |
843 | break; | |
844 | } | |
845 | case 3: /* low active */ | |
846 | { | |
847 | polarity = 1; | |
848 | break; | |
849 | } | |
850 | default: /* invalid */ | |
851 | { | |
c767a54b | 852 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
853 | polarity = 1; |
854 | break; | |
855 | } | |
1da177e4 LT |
856 | } |
857 | return polarity; | |
858 | } | |
859 | ||
b77cf6a8 | 860 | static int irq_trigger(int idx) |
1da177e4 | 861 | { |
c2c21745 | 862 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
863 | int trigger; |
864 | ||
865 | /* | |
866 | * Determine IRQ trigger mode (edge or level sensitive): | |
867 | */ | |
c2c21745 | 868 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 869 | { |
54168ed7 IM |
870 | case 0: /* conforms, ie. bus-type dependent */ |
871 | if (test_bit(bus, mp_bus_not_pci)) | |
872 | trigger = default_ISA_trigger(idx); | |
873 | else | |
874 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 875 | #ifdef CONFIG_EISA |
54168ed7 IM |
876 | switch (mp_bus_id_to_type[bus]) { |
877 | case MP_BUS_ISA: /* ISA pin */ | |
878 | { | |
879 | /* set before the switch */ | |
880 | break; | |
881 | } | |
882 | case MP_BUS_EISA: /* EISA pin */ | |
883 | { | |
884 | trigger = default_EISA_trigger(idx); | |
885 | break; | |
886 | } | |
887 | case MP_BUS_PCI: /* PCI pin */ | |
888 | { | |
889 | /* set before the switch */ | |
890 | break; | |
891 | } | |
54168ed7 IM |
892 | default: |
893 | { | |
c767a54b | 894 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
895 | trigger = 1; |
896 | break; | |
897 | } | |
898 | } | |
899 | #endif | |
1da177e4 | 900 | break; |
54168ed7 | 901 | case 1: /* edge */ |
1da177e4 | 902 | { |
54168ed7 | 903 | trigger = 0; |
1da177e4 LT |
904 | break; |
905 | } | |
54168ed7 | 906 | case 2: /* reserved */ |
1da177e4 | 907 | { |
c767a54b | 908 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 909 | trigger = 1; |
1da177e4 LT |
910 | break; |
911 | } | |
54168ed7 | 912 | case 3: /* level */ |
1da177e4 | 913 | { |
54168ed7 | 914 | trigger = 1; |
1da177e4 LT |
915 | break; |
916 | } | |
54168ed7 | 917 | default: /* invalid */ |
1da177e4 | 918 | { |
c767a54b | 919 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 920 | trigger = 0; |
1da177e4 LT |
921 | break; |
922 | } | |
923 | } | |
924 | return trigger; | |
925 | } | |
926 | ||
c4d05a2c JL |
927 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
928 | int trigger, int polarity) | |
929 | { | |
930 | init_irq_alloc_info(info, NULL); | |
931 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
932 | info->ioapic_node = node; | |
933 | info->ioapic_trigger = trigger; | |
934 | info->ioapic_polarity = polarity; | |
935 | info->ioapic_valid = 1; | |
936 | } | |
937 | ||
96ed44b2 JL |
938 | #ifndef CONFIG_ACPI |
939 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity); | |
940 | #endif | |
941 | ||
942 | static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst, | |
943 | struct irq_alloc_info *src, | |
944 | u32 gsi, int ioapic_idx, int pin) | |
945 | { | |
946 | int trigger, polarity; | |
947 | ||
948 | copy_irq_alloc_info(dst, src); | |
949 | dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
950 | dst->ioapic_id = mpc_ioapic_id(ioapic_idx); | |
951 | dst->ioapic_pin = pin; | |
952 | dst->ioapic_valid = 1; | |
953 | if (src && src->ioapic_valid) { | |
954 | dst->ioapic_node = src->ioapic_node; | |
955 | dst->ioapic_trigger = src->ioapic_trigger; | |
956 | dst->ioapic_polarity = src->ioapic_polarity; | |
957 | } else { | |
958 | dst->ioapic_node = NUMA_NO_NODE; | |
959 | if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { | |
960 | dst->ioapic_trigger = trigger; | |
961 | dst->ioapic_polarity = polarity; | |
962 | } else { | |
963 | /* | |
964 | * PCI interrupts are always polarity one level | |
965 | * triggered. | |
966 | */ | |
967 | dst->ioapic_trigger = 1; | |
968 | dst->ioapic_polarity = 1; | |
969 | } | |
970 | } | |
971 | } | |
972 | ||
973 | static int ioapic_alloc_attr_node(struct irq_alloc_info *info) | |
974 | { | |
975 | return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; | |
976 | } | |
977 | ||
49c7e600 JL |
978 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
979 | { | |
980 | irq_flow_handler_t hdl; | |
981 | bool fasteoi; | |
982 | ||
983 | if (trigger) { | |
984 | irq_set_status_flags(irq, IRQ_LEVEL); | |
985 | fasteoi = true; | |
986 | } else { | |
987 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
988 | fasteoi = false; | |
989 | } | |
990 | ||
991 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; | |
992 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); | |
993 | } | |
994 | ||
96ed44b2 JL |
995 | static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) |
996 | { | |
997 | struct mp_chip_data *data = irq_get_chip_data(irq); | |
998 | ||
999 | /* | |
1000 | * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger | |
1001 | * and polarity attirbutes. So allow the first user to reprogram the | |
1002 | * pin with real trigger and polarity attributes. | |
1003 | */ | |
1004 | if (irq < nr_legacy_irqs() && data->count == 1) { | |
1005 | if (info->ioapic_trigger != data->trigger) | |
1006 | mp_register_handler(irq, data->trigger); | |
1007 | data->entry.trigger = data->trigger = info->ioapic_trigger; | |
1008 | data->entry.polarity = data->polarity = info->ioapic_polarity; | |
1009 | } | |
1010 | ||
1011 | return data->trigger == info->ioapic_trigger && | |
1012 | data->polarity == info->ioapic_polarity; | |
1013 | } | |
1014 | ||
d32932d0 | 1015 | static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, |
c4d05a2c | 1016 | struct irq_alloc_info *info) |
6b9fb708 | 1017 | { |
d32932d0 | 1018 | bool legacy = false; |
d7f3d478 | 1019 | int irq = -1; |
d7f3d478 JL |
1020 | int type = ioapics[ioapic].irqdomain_cfg.type; |
1021 | ||
1022 | switch (type) { | |
1023 | case IOAPIC_DOMAIN_LEGACY: | |
1024 | /* | |
d32932d0 JL |
1025 | * Dynamically allocate IRQ number for non-ISA IRQs in the first |
1026 | * 16 GSIs on some weird platforms. | |
d7f3d478 | 1027 | */ |
d32932d0 | 1028 | if (!ioapic_initialized || gsi >= nr_legacy_irqs()) |
d7f3d478 | 1029 | irq = gsi; |
d32932d0 | 1030 | legacy = mp_is_legacy_irq(irq); |
d7f3d478 JL |
1031 | break; |
1032 | case IOAPIC_DOMAIN_STRICT: | |
d32932d0 | 1033 | irq = gsi; |
d7f3d478 JL |
1034 | break; |
1035 | case IOAPIC_DOMAIN_DYNAMIC: | |
d7f3d478 JL |
1036 | break; |
1037 | default: | |
1038 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
d32932d0 JL |
1039 | return -1; |
1040 | } | |
1041 | ||
1042 | return __irq_domain_alloc_irqs(domain, irq, 1, | |
1043 | ioapic_alloc_attr_node(info), | |
1044 | info, legacy); | |
1045 | } | |
1046 | ||
1047 | /* | |
1048 | * Need special handling for ISA IRQs because there may be multiple IOAPIC pins | |
1049 | * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping | |
1050 | * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are | |
1051 | * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
1052 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and | |
1053 | * some BIOSes may use MP Interrupt Source records to override IRQ numbers for | |
1054 | * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be | |
1055 | * multiple pins sharing the same legacy IRQ number when ACPI is disabled. | |
1056 | */ | |
1057 | static int alloc_isa_irq_from_domain(struct irq_domain *domain, | |
1058 | int irq, int ioapic, int pin, | |
1059 | struct irq_alloc_info *info) | |
1060 | { | |
1061 | struct mp_chip_data *data; | |
1062 | struct irq_data *irq_data = irq_get_irq_data(irq); | |
1063 | int node = ioapic_alloc_attr_node(info); | |
1064 | ||
1065 | /* | |
1066 | * Legacy ISA IRQ has already been allocated, just add pin to | |
1067 | * the pin list assoicated with this IRQ and program the IOAPIC | |
1068 | * entry. The IOAPIC entry | |
1069 | */ | |
1070 | if (irq_data && irq_data->parent_data) { | |
1071 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
1072 | ||
1073 | if (!mp_check_pin_attr(irq, info)) | |
1074 | return -EBUSY; | |
1075 | if (__add_pin_to_irq_node(cfg, node, ioapic, info->ioapic_pin)) | |
1076 | return -ENOMEM; | |
1077 | } else { | |
1078 | irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true); | |
1079 | if (irq >= 0) { | |
1080 | irq_data = irq_domain_get_irq_data(domain, irq); | |
1081 | data = irq_data->chip_data; | |
1082 | data->isa_irq = true; | |
1083 | } | |
d7f3d478 JL |
1084 | } |
1085 | ||
d32932d0 | 1086 | return irq; |
d7f3d478 JL |
1087 | } |
1088 | ||
1089 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
c4d05a2c | 1090 | unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1091 | { |
1092 | int irq; | |
d32932d0 JL |
1093 | bool legacy = false; |
1094 | struct irq_alloc_info tmp; | |
1095 | struct mp_chip_data *data; | |
d7f3d478 JL |
1096 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
1097 | ||
b81975ea | 1098 | if (!domain) |
d32932d0 | 1099 | return -ENOSYS; |
16ee7b3d | 1100 | |
16ee7b3d JL |
1101 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1102 | irq = mp_irqs[idx].srcbusirq; | |
d32932d0 JL |
1103 | legacy = mp_is_legacy_irq(irq); |
1104 | } | |
16ee7b3d | 1105 | |
d32932d0 JL |
1106 | mutex_lock(&ioapic_mutex); |
1107 | if (!(flags & IOAPIC_MAP_ALLOC)) { | |
1108 | if (!legacy) { | |
1109 | irq = irq_find_mapping(domain, pin); | |
16ee7b3d | 1110 | if (irq == 0) |
d32932d0 | 1111 | irq = -ENOENT; |
16ee7b3d JL |
1112 | } |
1113 | } else { | |
d32932d0 JL |
1114 | ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); |
1115 | if (legacy) | |
1116 | irq = alloc_isa_irq_from_domain(domain, irq, | |
1117 | ioapic, pin, &tmp); | |
1118 | else if ((irq = irq_find_mapping(domain, pin)) == 0) | |
1119 | irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp); | |
1120 | else if (!mp_check_pin_attr(irq, &tmp)) | |
1121 | irq = -EBUSY; | |
1122 | if (irq >= 0) { | |
1123 | data = irq_get_chip_data(irq); | |
1124 | data->count++; | |
1125 | } | |
15a3c7cc | 1126 | } |
d7f3d478 JL |
1127 | mutex_unlock(&ioapic_mutex); |
1128 | ||
d32932d0 | 1129 | return irq; |
6b9fb708 JL |
1130 | } |
1131 | ||
d7f3d478 | 1132 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1133 | { |
d7f3d478 | 1134 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1135 | |
1136 | /* | |
1137 | * Debugging check, we are in big trouble if this message pops up! | |
1138 | */ | |
c2c21745 | 1139 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1140 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1141 | |
54168ed7 | 1142 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1143 | /* |
1144 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1145 | */ | |
1146 | if ((pin >= 16) && (pin <= 23)) { | |
1147 | if (pirq_entries[pin-16] != -1) { | |
1148 | if (!pirq_entries[pin-16]) { | |
1149 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1150 | "disabling PIRQ%d\n", pin-16); | |
1151 | } else { | |
d7f3d478 | 1152 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1153 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1154 | "using PIRQ%d -> IRQ %d\n", | |
1155 | pin-16, irq); | |
6b9fb708 | 1156 | return irq; |
1da177e4 LT |
1157 | } |
1158 | } | |
1159 | } | |
54168ed7 IM |
1160 | #endif |
1161 | ||
c4d05a2c | 1162 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
d7f3d478 | 1163 | } |
6b9fb708 | 1164 | |
c4d05a2c JL |
1165 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
1166 | struct irq_alloc_info *info) | |
d7f3d478 JL |
1167 | { |
1168 | int ioapic, pin, idx; | |
1169 | ||
1170 | ioapic = mp_find_ioapic(gsi); | |
1171 | if (ioapic < 0) | |
1172 | return -1; | |
1173 | ||
1174 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1175 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1176 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
1177 | return -1; | |
1178 | ||
c4d05a2c | 1179 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
1da177e4 LT |
1180 | } |
1181 | ||
df334bea JL |
1182 | void mp_unmap_irq(int irq) |
1183 | { | |
d32932d0 JL |
1184 | struct irq_data *irq_data = irq_get_irq_data(irq); |
1185 | struct mp_chip_data *data; | |
df334bea | 1186 | |
d32932d0 | 1187 | if (!irq_data || !irq_data->domain) |
df334bea JL |
1188 | return; |
1189 | ||
d32932d0 JL |
1190 | data = irq_data->chip_data; |
1191 | if (!data || data->isa_irq) | |
1192 | return; | |
df334bea JL |
1193 | |
1194 | mutex_lock(&ioapic_mutex); | |
d32932d0 JL |
1195 | if (--data->count == 0) |
1196 | irq_domain_free_irqs(irq, 1); | |
df334bea JL |
1197 | mutex_unlock(&ioapic_mutex); |
1198 | } | |
1199 | ||
e20c06fd YL |
1200 | /* |
1201 | * Find a specific PCI IRQ entry. | |
1202 | * Not an __init, possibly needed by modules | |
1203 | */ | |
25d0d35e | 1204 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
e20c06fd | 1205 | { |
d7f3d478 | 1206 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1207 | |
1208 | apic_printk(APIC_DEBUG, | |
1209 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1210 | bus, slot, pin); | |
1211 | if (test_bit(bus, mp_bus_not_pci)) { | |
1212 | apic_printk(APIC_VERBOSE, | |
1213 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1214 | return -1; | |
1215 | } | |
79598505 | 1216 | |
e20c06fd YL |
1217 | for (i = 0; i < mp_irq_entries; i++) { |
1218 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1219 | int ioapic_idx, found = 0; |
1220 | ||
1221 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1222 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1223 | continue; | |
e20c06fd | 1224 | |
f44d1692 | 1225 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1226 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1227 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1228 | found = 1; | |
e20c06fd | 1229 | break; |
e20c06fd | 1230 | } |
79598505 JL |
1231 | if (!found) |
1232 | continue; | |
1233 | ||
1234 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1235 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1236 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1237 | continue; |
1238 | ||
1239 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1240 | best_idx = i; |
1241 | best_ioapic = ioapic_idx; | |
1242 | goto out; | |
79598505 | 1243 | } |
d7f3d478 | 1244 | |
79598505 JL |
1245 | /* |
1246 | * Use the first all-but-pin matching entry as a | |
1247 | * best-guess fuzzy result for broken mptables. | |
1248 | */ | |
d7f3d478 JL |
1249 | if (best_idx < 0) { |
1250 | best_idx = i; | |
1251 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1252 | } |
1253 | } | |
d7f3d478 JL |
1254 | if (best_idx < 0) |
1255 | return -1; | |
1256 | ||
1257 | out: | |
25d0d35e JL |
1258 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
1259 | IOAPIC_MAP_ALLOC); | |
e20c06fd YL |
1260 | } |
1261 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1262 | ||
d32932d0 | 1263 | static struct irq_chip ioapic_chip, ioapic_ir_chip; |
1da177e4 | 1264 | |
047c8fdb | 1265 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1266 | static inline int IO_APIC_irq_trigger(int irq) |
1267 | { | |
d6c88a50 | 1268 | int apic, idx, pin; |
1d025192 | 1269 | |
f44d1692 JL |
1270 | for_each_ioapic_pin(apic, pin) { |
1271 | idx = find_irq_entry(apic, pin, mp_INT); | |
d7f3d478 | 1272 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
f44d1692 | 1273 | return irq_trigger(idx); |
d6c88a50 TG |
1274 | } |
1275 | /* | |
54168ed7 IM |
1276 | * nonexistent IRQs are edge default |
1277 | */ | |
d6c88a50 | 1278 | return 0; |
1d025192 | 1279 | } |
047c8fdb YL |
1280 | #else |
1281 | static inline int IO_APIC_irq_trigger(int irq) | |
1282 | { | |
54168ed7 | 1283 | return 1; |
047c8fdb YL |
1284 | } |
1285 | #endif | |
1d025192 | 1286 | |
ed972ccf TG |
1287 | static void __init setup_IO_APIC_irqs(void) |
1288 | { | |
16ee7b3d JL |
1289 | unsigned int ioapic, pin; |
1290 | int idx; | |
ed972ccf TG |
1291 | |
1292 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1293 | ||
16ee7b3d JL |
1294 | for_each_ioapic_pin(ioapic, pin) { |
1295 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1296 | if (idx < 0) | |
1297 | apic_printk(APIC_VERBOSE, | |
1298 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1299 | mpc_ioapic_id(ioapic), pin); | |
1300 | else | |
1301 | pin_2_irq(idx, ioapic, pin, | |
1302 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1303 | } | |
ed972ccf TG |
1304 | } |
1305 | ||
17405453 YY |
1306 | void ioapic_zap_locks(void) |
1307 | { | |
1308 | raw_spin_lock_init(&ioapic_lock); | |
1309 | } | |
1310 | ||
a44174ee JL |
1311 | static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1312 | { | |
1313 | int i; | |
1314 | char buf[256]; | |
1315 | struct IO_APIC_route_entry entry; | |
1316 | struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry; | |
1317 | ||
1318 | printk(KERN_DEBUG "IOAPIC %d:\n", apic); | |
1319 | for (i = 0; i <= nr_entries; i++) { | |
1320 | entry = ioapic_read_entry(apic, i); | |
1321 | snprintf(buf, sizeof(buf), | |
1322 | " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", | |
1323 | i, entry.mask ? "disabled" : "enabled ", | |
1324 | entry.trigger ? "level" : "edge ", | |
1325 | entry.polarity ? "low " : "high", | |
1326 | entry.vector, entry.irr, entry.delivery_status); | |
1327 | if (ir_entry->format) | |
1328 | printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", | |
1329 | buf, (ir_entry->index << 15) | ir_entry->index, | |
1330 | ir_entry->zero); | |
1331 | else | |
1332 | printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", | |
1333 | buf, entry.dest_mode ? "logical " : "physical", | |
1334 | entry.dest, entry.delivery_mode); | |
1335 | } | |
1336 | } | |
1337 | ||
74afab7a | 1338 | static void __init print_IO_APIC(int ioapic_idx) |
afcc8a40 | 1339 | { |
1da177e4 LT |
1340 | union IO_APIC_reg_00 reg_00; |
1341 | union IO_APIC_reg_01 reg_01; | |
1342 | union IO_APIC_reg_02 reg_02; | |
1343 | union IO_APIC_reg_03 reg_03; | |
1344 | unsigned long flags; | |
1da177e4 | 1345 | |
dade7716 | 1346 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1347 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1348 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1349 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1350 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1351 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1352 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1353 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1354 | |
6f50d45f | 1355 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1356 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1357 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1358 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1359 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1360 | |
54168ed7 | 1361 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1362 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1363 | reg_01.bits.entries); | |
1da177e4 LT |
1364 | |
1365 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1366 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1367 | reg_01.bits.version); | |
1da177e4 LT |
1368 | |
1369 | /* | |
1370 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1371 | * but the value of reg_02 is read as the previous read register | |
1372 | * value, so ignore it if reg_02 == reg_01. | |
1373 | */ | |
1374 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1375 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1376 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1377 | } |
1378 | ||
1379 | /* | |
1380 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1381 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1382 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1383 | */ | |
1384 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1385 | reg_03.raw != reg_01.raw) { | |
1386 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1387 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1388 | } |
1389 | ||
1390 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
a44174ee | 1391 | io_apic_print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1392 | } |
1393 | ||
74afab7a | 1394 | void __init print_IO_APICs(void) |
cda417dd | 1395 | { |
6f50d45f | 1396 | int ioapic_idx; |
cda417dd YL |
1397 | struct irq_cfg *cfg; |
1398 | unsigned int irq; | |
6fd36ba0 | 1399 | struct irq_chip *chip; |
cda417dd YL |
1400 | |
1401 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1402 | for_each_ioapic(ioapic_idx) |
cda417dd | 1403 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1404 | mpc_ioapic_id(ioapic_idx), |
1405 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1406 | |
1407 | /* | |
1408 | * We are a bit conservative about what we expect. We have to | |
1409 | * know about every hardware change ASAP. | |
1410 | */ | |
1411 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1412 | ||
f44d1692 | 1413 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1414 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1415 | |
1da177e4 | 1416 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1417 | for_each_active_irq(irq) { |
0b8f1efa YL |
1418 | struct irq_pin_list *entry; |
1419 | ||
6fd36ba0 | 1420 | chip = irq_get_chip(irq); |
d32932d0 | 1421 | if (chip != &ioapic_chip && chip != &ioapic_ir_chip) |
6fd36ba0 MN |
1422 | continue; |
1423 | ||
32f5ef5d | 1424 | cfg = irq_cfg(irq); |
05e40760 DK |
1425 | if (!cfg) |
1426 | continue; | |
a178b87b | 1427 | if (list_empty(&cfg->irq_2_pin)) |
1da177e4 | 1428 | continue; |
8f09cd20 | 1429 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1430 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1431 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1432 | pr_cont("\n"); | |
1da177e4 LT |
1433 | } |
1434 | ||
1435 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1436 | } |
1437 | ||
efa2559f YL |
1438 | /* Where if anywhere is the i8259 connect in external int mode */ |
1439 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1440 | ||
54168ed7 | 1441 | void __init enable_IO_APIC(void) |
1da177e4 | 1442 | { |
fcfd636a | 1443 | int i8259_apic, i8259_pin; |
f44d1692 | 1444 | int apic, pin; |
bc07844a | 1445 | |
a46f5c89 TG |
1446 | if (skip_ioapic_setup) |
1447 | nr_ioapics = 0; | |
1448 | ||
1449 | if (!nr_legacy_irqs() || !nr_ioapics) | |
bc07844a TG |
1450 | return; |
1451 | ||
f44d1692 | 1452 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1453 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1454 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1455 | |
f44d1692 JL |
1456 | /* If the interrupt line is enabled and in ExtInt mode |
1457 | * I have found the pin where the i8259 is connected. | |
1458 | */ | |
1459 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1460 | ioapic_i8259.apic = apic; | |
1461 | ioapic_i8259.pin = pin; | |
1462 | goto found_i8259; | |
fcfd636a EB |
1463 | } |
1464 | } | |
1465 | found_i8259: | |
1466 | /* Look to see what if the MP table has reported the ExtINT */ | |
1467 | /* If we could not find the appropriate pin by looking at the ioapic | |
1468 | * the i8259 probably is not connected the ioapic but give the | |
1469 | * mptable a chance anyway. | |
1470 | */ | |
1471 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1472 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1473 | /* Trust the MP table if nothing is setup in the hardware */ | |
1474 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1475 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1476 | ioapic_i8259.pin = i8259_pin; | |
1477 | ioapic_i8259.apic = i8259_apic; | |
1478 | } | |
1479 | /* Complain if the MP table and the hardware disagree */ | |
1480 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1481 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1482 | { | |
1483 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1484 | } |
1485 | ||
1486 | /* | |
1487 | * Do not trust the IO-APIC being empty at bootup | |
1488 | */ | |
1489 | clear_IO_APIC(); | |
1490 | } | |
1491 | ||
1c4248ca | 1492 | void native_disable_io_apic(void) |
1da177e4 | 1493 | { |
650927ef | 1494 | /* |
0b968d23 | 1495 | * If the i8259 is routed through an IOAPIC |
650927ef | 1496 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1497 | * so legacy interrupts can be delivered. |
650927ef | 1498 | */ |
1c4248ca | 1499 | if (ioapic_i8259.pin != -1) { |
650927ef | 1500 | struct IO_APIC_route_entry entry; |
650927ef EB |
1501 | |
1502 | memset(&entry, 0, sizeof(entry)); | |
1503 | entry.mask = 0; /* Enabled */ | |
1504 | entry.trigger = 0; /* Edge */ | |
1505 | entry.irr = 0; | |
1506 | entry.polarity = 0; /* High */ | |
1507 | entry.delivery_status = 0; | |
1508 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1509 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1510 | entry.vector = 0; |
54168ed7 | 1511 | entry.dest = read_apic_id(); |
650927ef EB |
1512 | |
1513 | /* | |
1514 | * Add it to the IO-APIC irq-routing table: | |
1515 | */ | |
cf4c6a2f | 1516 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1517 | } |
54168ed7 | 1518 | |
1c4248ca JR |
1519 | if (cpu_has_apic || apic_from_smp_config()) |
1520 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1521 | ||
1522 | } | |
1523 | ||
1524 | /* | |
1525 | * Not an __init, needed by the reboot code | |
1526 | */ | |
1527 | void disable_IO_APIC(void) | |
1528 | { | |
7c6d9f97 | 1529 | /* |
1c4248ca | 1530 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1531 | */ |
1c4248ca JR |
1532 | clear_IO_APIC(); |
1533 | ||
95d76acc | 1534 | if (!nr_legacy_irqs()) |
1c4248ca JR |
1535 | return; |
1536 | ||
1537 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1538 | } |
1539 | ||
54168ed7 | 1540 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1541 | /* |
1542 | * function to set the IO-APIC physical IDs based on the | |
1543 | * values stored in the MPC table. | |
1544 | * | |
1545 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1546 | */ | |
a38c5380 | 1547 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1548 | { |
1549 | union IO_APIC_reg_00 reg_00; | |
1550 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1551 | int ioapic_idx; |
1da177e4 LT |
1552 | int i; |
1553 | unsigned char old_id; | |
1554 | unsigned long flags; | |
1555 | ||
1556 | /* | |
1557 | * This is broken; anything with a real cpu count has to | |
1558 | * circumvent this idiocy regardless. | |
1559 | */ | |
7abc0753 | 1560 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1561 | |
1562 | /* | |
1563 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1564 | */ | |
f44d1692 | 1565 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1566 | /* Read the register 0 value */ |
dade7716 | 1567 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1568 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1569 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1570 | |
6f50d45f | 1571 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1572 | |
6f50d45f | 1573 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1574 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1575 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1576 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1577 | reg_00.bits.ID); | |
6f50d45f | 1578 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1579 | } |
1580 | ||
1da177e4 LT |
1581 | /* |
1582 | * Sanity check, is the ID really free? Every APIC in a | |
1583 | * system must have a unique ID or we get lots of nice | |
1584 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1585 | */ | |
7abc0753 | 1586 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1587 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1588 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1589 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1590 | for (i = 0; i < get_physical_broadcast(); i++) |
1591 | if (!physid_isset(i, phys_id_present_map)) | |
1592 | break; | |
1593 | if (i >= get_physical_broadcast()) | |
1594 | panic("Max APIC ID exceeded!\n"); | |
1595 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1596 | i); | |
1597 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1598 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1599 | } else { |
1600 | physid_mask_t tmp; | |
6f50d45f | 1601 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1602 | &tmp); |
1da177e4 LT |
1603 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1604 | "phys_id_present_map\n", | |
6f50d45f | 1605 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1606 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1607 | } | |
1608 | ||
1da177e4 LT |
1609 | /* |
1610 | * We need to adjust the IRQ routing table | |
1611 | * if the ID changed. | |
1612 | */ | |
6f50d45f | 1613 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 1614 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1615 | if (mp_irqs[i].dstapic == old_id) |
1616 | mp_irqs[i].dstapic | |
6f50d45f | 1617 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
1618 | |
1619 | /* | |
60d79fd9 YL |
1620 | * Update the ID register according to the right value |
1621 | * from the MPC table if they are different. | |
36062448 | 1622 | */ |
6f50d45f | 1623 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
1624 | continue; |
1625 | ||
1da177e4 LT |
1626 | apic_printk(APIC_VERBOSE, KERN_INFO |
1627 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 1628 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 1629 | |
6f50d45f | 1630 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 1631 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1632 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 1633 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1634 | |
1635 | /* | |
1636 | * Sanity check | |
1637 | */ | |
dade7716 | 1638 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1639 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1640 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 1641 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 1642 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
1643 | else |
1644 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1645 | } | |
1646 | } | |
a38c5380 SAS |
1647 | |
1648 | void __init setup_ioapic_ids_from_mpc(void) | |
1649 | { | |
1650 | ||
1651 | if (acpi_ioapic) | |
1652 | return; | |
1653 | /* | |
1654 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1655 | * no meaning without the serial APIC bus. | |
1656 | */ | |
1657 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
1658 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
1659 | return; | |
1660 | setup_ioapic_ids_from_mpc_nocheck(); | |
1661 | } | |
54168ed7 | 1662 | #endif |
1da177e4 | 1663 | |
7ce0bcfd | 1664 | int no_timer_check __initdata; |
8542b200 ZA |
1665 | |
1666 | static int __init notimercheck(char *s) | |
1667 | { | |
1668 | no_timer_check = 1; | |
1669 | return 1; | |
1670 | } | |
1671 | __setup("no_timer_check", notimercheck); | |
1672 | ||
1da177e4 LT |
1673 | /* |
1674 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1675 | * about the timer IRQ. We do the following to work around the situation: | |
1676 | * | |
1677 | * - timer IRQ defaults to IO-APIC IRQ | |
1678 | * - if this function detects that timer IRQs are defunct, then we fall | |
1679 | * back to ISA timer IRQs | |
1680 | */ | |
f0a7a5c9 | 1681 | static int __init timer_irq_works(void) |
1da177e4 LT |
1682 | { |
1683 | unsigned long t1 = jiffies; | |
4aae0702 | 1684 | unsigned long flags; |
1da177e4 | 1685 | |
8542b200 ZA |
1686 | if (no_timer_check) |
1687 | return 1; | |
1688 | ||
4aae0702 | 1689 | local_save_flags(flags); |
1da177e4 LT |
1690 | local_irq_enable(); |
1691 | /* Let ten ticks pass... */ | |
1692 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1693 | local_irq_restore(flags); |
1da177e4 LT |
1694 | |
1695 | /* | |
1696 | * Expect a few ticks at least, to be sure some possible | |
1697 | * glue logic does not lock up after one or two first | |
1698 | * ticks in a non-ExtINT mode. Also the local APIC | |
1699 | * might have cached one ExtINT interrupt. Finally, at | |
1700 | * least one tick may be lost due to delays. | |
1701 | */ | |
54168ed7 IM |
1702 | |
1703 | /* jiffies wrap? */ | |
1d16b53e | 1704 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 1705 | return 1; |
1da177e4 LT |
1706 | return 0; |
1707 | } | |
1708 | ||
1709 | /* | |
1710 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1711 | * number of pending IRQ events unhandled. These cases are very rare, | |
1712 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1713 | * better to do it this way as thus we do not have to be aware of | |
1714 | * 'pending' interrupts in the IRQ path, except at this point. | |
1715 | */ | |
1716 | /* | |
1717 | * Edge triggered needs to resend any interrupt | |
1718 | * that was delayed but this is now handled in the device | |
1719 | * independent code. | |
1720 | */ | |
1721 | ||
1722 | /* | |
1723 | * Starting up a edge-triggered IO-APIC interrupt is | |
1724 | * nasty - we need to make sure that we get the edge. | |
1725 | * If it is already asserted for some reason, we need | |
1726 | * return 1 to indicate that is was pending. | |
1727 | * | |
1728 | * This is not complete - we should be able to fake | |
1729 | * an edge even if it isn't on the 8259A... | |
1730 | */ | |
54168ed7 | 1731 | |
61a38ce3 | 1732 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 1733 | { |
61a38ce3 | 1734 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
1735 | unsigned long flags; |
1736 | ||
dade7716 | 1737 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 1738 | if (irq < nr_legacy_irqs()) { |
4305df94 | 1739 | legacy_pic->mask(irq); |
b81bb373 | 1740 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
1741 | was_pending = 1; |
1742 | } | |
a9786091 | 1743 | __unmask_ioapic(irqd_cfg(data)); |
dade7716 | 1744 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1745 | |
1746 | return was_pending; | |
1747 | } | |
1748 | ||
54168ed7 IM |
1749 | /* |
1750 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1751 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1752 | * handled with the level-triggered descriptor, but that one has slightly | |
1753 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1754 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1755 | * races. | |
1756 | */ | |
497c9a19 | 1757 | |
7eb9ae07 SS |
1758 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
1759 | { | |
1760 | int apic, pin; | |
1761 | struct irq_pin_list *entry; | |
1762 | u8 vector = cfg->vector; | |
1763 | ||
1764 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
1765 | unsigned int reg; | |
1766 | ||
1767 | apic = entry->apic; | |
1768 | pin = entry->pin; | |
9f9d39e4 JR |
1769 | |
1770 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
1771 | reg = io_apic_read(apic, 0x10 + pin*2); |
1772 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
1773 | reg |= vector; | |
1774 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
1775 | } | |
1776 | } | |
1777 | ||
3eb2cce8 | 1778 | atomic_t irq_mis_count; |
3eb2cce8 | 1779 | |
047c8fdb | 1780 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
1781 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
1782 | { | |
1783 | struct irq_pin_list *entry; | |
1784 | unsigned long flags; | |
1785 | ||
1786 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
1787 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
1788 | unsigned int reg; | |
1789 | int pin; | |
1790 | ||
1791 | pin = entry->pin; | |
1792 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
1793 | /* Is the remote IRR bit set? */ | |
1794 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
1795 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1796 | return true; | |
1797 | } | |
1798 | } | |
1799 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1800 | ||
1801 | return false; | |
1802 | } | |
1803 | ||
4da7072a AG |
1804 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
1805 | { | |
54168ed7 | 1806 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 1807 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 1808 | mask_ioapic(cfg); |
4da7072a | 1809 | return true; |
54168ed7 | 1810 | } |
4da7072a AG |
1811 | return false; |
1812 | } | |
1813 | ||
1814 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
1815 | struct irq_cfg *cfg, bool masked) | |
1816 | { | |
1817 | if (unlikely(masked)) { | |
1818 | /* Only migrate the irq if the ack has been received. | |
1819 | * | |
1820 | * On rare occasions the broadcast level triggered ack gets | |
1821 | * delayed going to ioapics, and if we reprogram the | |
1822 | * vector while Remote IRR is still set the irq will never | |
1823 | * fire again. | |
1824 | * | |
1825 | * To prevent this scenario we read the Remote IRR bit | |
1826 | * of the ioapic. This has two effects. | |
1827 | * - On any sane system the read of the ioapic will | |
1828 | * flush writes (and acks) going to the ioapic from | |
1829 | * this cpu. | |
1830 | * - We get to see if the ACK has actually been delivered. | |
1831 | * | |
1832 | * Based on failed experiments of reprogramming the | |
1833 | * ioapic entry from outside of irq context starting | |
1834 | * with masking the ioapic entry and then polling until | |
1835 | * Remote IRR was clear before reprogramming the | |
1836 | * ioapic I don't trust the Remote IRR bit to be | |
1837 | * completey accurate. | |
1838 | * | |
1839 | * However there appears to be no other way to plug | |
1840 | * this race, so if the Remote IRR bit is not | |
1841 | * accurate and is causing problems then it is a hardware bug | |
1842 | * and you can go talk to the chipset vendor about it. | |
1843 | */ | |
1844 | if (!io_apic_level_ack_pending(cfg)) | |
1845 | irq_move_masked_irq(data); | |
1846 | unmask_ioapic(cfg); | |
1847 | } | |
1848 | } | |
1849 | #else | |
1850 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
1851 | { | |
1852 | return false; | |
1853 | } | |
1854 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
1855 | struct irq_cfg *cfg, bool masked) | |
1856 | { | |
1857 | } | |
047c8fdb YL |
1858 | #endif |
1859 | ||
d32932d0 | 1860 | static void ioapic_ack_level(struct irq_data *data) |
4da7072a | 1861 | { |
a9786091 | 1862 | struct irq_cfg *cfg = irqd_cfg(data); |
4da7072a AG |
1863 | unsigned long v; |
1864 | bool masked; | |
d32932d0 | 1865 | int i; |
4da7072a AG |
1866 | |
1867 | irq_complete_move(cfg); | |
1868 | masked = ioapic_irqd_mask(data, cfg); | |
1869 | ||
3eb2cce8 | 1870 | /* |
916a0fe7 JF |
1871 | * It appears there is an erratum which affects at least version 0x11 |
1872 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1873 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1874 | * erroneously delivered as edge-triggered one but the respective IRR | |
1875 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1876 | * message but it will never arrive and further interrupts are blocked | |
1877 | * from the source. The exact reason is so far unknown, but the | |
1878 | * phenomenon was observed when two consecutive interrupt requests | |
1879 | * from a given source get delivered to the same CPU and the source is | |
1880 | * temporarily disabled in between. | |
1881 | * | |
1882 | * A workaround is to simulate an EOI message manually. We achieve it | |
1883 | * by setting the trigger mode to edge and then to level when the edge | |
1884 | * trigger mode gets detected in the TMR of a local APIC for a | |
1885 | * level-triggered interrupt. We mask the source for the time of the | |
1886 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1887 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
1888 | * |
1889 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
1890 | * any unhandled interrupt on the offlined cpu to the new cpu | |
1891 | * destination that is handling the corresponding interrupt. This | |
1892 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
1893 | * level-triggered io-apic interrupt will be seen as an edge | |
1894 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
1895 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
1896 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
1897 | * supporting EOI register, we do an explicit EOI to clear the | |
1898 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
1899 | * we use the above logic (mask+edge followed by unmask+level) from | |
1900 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 1901 | */ |
3145e941 | 1902 | i = cfg->vector; |
3eb2cce8 | 1903 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 1904 | |
54168ed7 IM |
1905 | /* |
1906 | * We must acknowledge the irq before we move it or the acknowledge will | |
1907 | * not propagate properly. | |
1908 | */ | |
1909 | ack_APIC_irq(); | |
1910 | ||
1c83995b SS |
1911 | /* |
1912 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
1913 | * message via io-apic EOI register write or simulating it using | |
1914 | * mask+edge followed by unnask+level logic) manually when the | |
1915 | * level triggered interrupt is seen as the edge triggered interrupt | |
1916 | * at the cpu. | |
1917 | */ | |
ca64c47c MR |
1918 | if (!(v & (1 << (i & 0x1f)))) { |
1919 | atomic_inc(&irq_mis_count); | |
d32932d0 | 1920 | eoi_ioapic_pin(cfg->vector, cfg); |
ca64c47c MR |
1921 | } |
1922 | ||
4da7072a | 1923 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 1924 | } |
1d025192 | 1925 | |
d32932d0 JL |
1926 | static void ioapic_ir_ack_level(struct irq_data *irq_data) |
1927 | { | |
1928 | struct mp_chip_data *data = irq_data->chip_data; | |
1929 | ||
1930 | /* | |
1931 | * Intr-remapping uses pin number as the virtual vector | |
1932 | * in the RTE. Actual vector is programmed in | |
1933 | * intr-remapping table entry. Hence for the io-apic | |
1934 | * EOI we use the pin number. | |
1935 | */ | |
1936 | ack_APIC_irq(); | |
1937 | eoi_ioapic_pin(data->entry.vector, irqd_cfg(irq_data)); | |
1938 | } | |
1939 | ||
1940 | static int ioapic_set_affinity(struct irq_data *irq_data, | |
1941 | const struct cpumask *mask, bool force) | |
1942 | { | |
1943 | struct irq_data *parent = irq_data->parent_data; | |
1944 | struct mp_chip_data *data = irq_data->chip_data; | |
1945 | unsigned int dest, irq = irq_data->irq; | |
1946 | struct irq_cfg *cfg; | |
1947 | unsigned long flags; | |
1948 | int ret; | |
1949 | ||
1950 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
1951 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
1952 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { | |
1953 | cfg = irqd_cfg(irq_data); | |
1954 | data->entry.dest = cfg->dest_apicid; | |
1955 | data->entry.vector = cfg->vector; | |
1956 | /* Only the high 8 bits are valid. */ | |
1957 | dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid); | |
1958 | __target_IO_APIC_irq(irq, dest, cfg); | |
1959 | } | |
1960 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1961 | ||
1962 | return ret; | |
1963 | } | |
1964 | ||
f5b9ed7a | 1965 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
1966 | .name = "IO-APIC", |
1967 | .irq_startup = startup_ioapic_irq, | |
1968 | .irq_mask = mask_ioapic_irq, | |
1969 | .irq_unmask = unmask_ioapic_irq, | |
d32932d0 JL |
1970 | .irq_ack = irq_chip_ack_parent, |
1971 | .irq_eoi = ioapic_ack_level, | |
1972 | .irq_set_affinity = ioapic_set_affinity, | |
1973 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
1974 | }; | |
1975 | ||
1976 | static struct irq_chip ioapic_ir_chip __read_mostly = { | |
1977 | .name = "IR-IO-APIC", | |
1978 | .irq_startup = startup_ioapic_irq, | |
1979 | .irq_mask = mask_ioapic_irq, | |
1980 | .irq_unmask = unmask_ioapic_irq, | |
1981 | .irq_ack = irq_chip_ack_parent, | |
1982 | .irq_eoi = ioapic_ir_ack_level, | |
1983 | .irq_set_affinity = ioapic_set_affinity, | |
5613570b | 1984 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
1985 | }; |
1986 | ||
1da177e4 LT |
1987 | static inline void init_IO_APIC_traps(void) |
1988 | { | |
da51a821 | 1989 | struct irq_cfg *cfg; |
ad9f4334 | 1990 | unsigned int irq; |
1da177e4 | 1991 | |
ad9f4334 | 1992 | for_each_active_irq(irq) { |
32f5ef5d | 1993 | cfg = irq_cfg(irq); |
0b8f1efa | 1994 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
1995 | /* |
1996 | * Hmm.. We don't have an entry for this, | |
1997 | * so default to an old-fashioned 8259 | |
1998 | * interrupt if we can.. | |
1999 | */ | |
95d76acc | 2000 | if (irq < nr_legacy_irqs()) |
b81bb373 | 2001 | legacy_pic->make_irq(irq); |
0b8f1efa | 2002 | else |
1da177e4 | 2003 | /* Strange. Oh, well.. */ |
2c778651 | 2004 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2005 | } |
2006 | } | |
2007 | } | |
2008 | ||
f5b9ed7a IM |
2009 | /* |
2010 | * The local APIC irq-chip implementation: | |
2011 | */ | |
1da177e4 | 2012 | |
90297c5f | 2013 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2014 | { |
2015 | unsigned long v; | |
2016 | ||
2017 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2018 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2019 | } |
2020 | ||
90297c5f | 2021 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2022 | { |
f5b9ed7a | 2023 | unsigned long v; |
1da177e4 | 2024 | |
f5b9ed7a | 2025 | v = apic_read(APIC_LVT0); |
593f4a78 | 2026 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2027 | } |
1da177e4 | 2028 | |
90297c5f | 2029 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2030 | { |
2031 | ack_APIC_irq(); | |
2032 | } | |
2033 | ||
f5b9ed7a | 2034 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2035 | .name = "local-APIC", |
90297c5f TG |
2036 | .irq_mask = mask_lapic_irq, |
2037 | .irq_unmask = unmask_lapic_irq, | |
2038 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2039 | }; |
2040 | ||
60c69948 | 2041 | static void lapic_register_intr(int irq) |
c88ac1df | 2042 | { |
60c69948 | 2043 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2044 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2045 | "edge"); |
c88ac1df MR |
2046 | } |
2047 | ||
1da177e4 LT |
2048 | /* |
2049 | * This looks a bit hackish but it's about the only one way of sending | |
2050 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2051 | * not support the ExtINT mode, unfortunately. We need to send these | |
2052 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2053 | * 8259A interrupt line asserted until INTA. --macro | |
2054 | */ | |
28acf285 | 2055 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2056 | { |
fcfd636a | 2057 | int apic, pin, i; |
1da177e4 LT |
2058 | struct IO_APIC_route_entry entry0, entry1; |
2059 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2060 | |
fcfd636a | 2061 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2062 | if (pin == -1) { |
2063 | WARN_ON_ONCE(1); | |
2064 | return; | |
2065 | } | |
fcfd636a | 2066 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2067 | if (apic == -1) { |
2068 | WARN_ON_ONCE(1); | |
1da177e4 | 2069 | return; |
956fb531 | 2070 | } |
1da177e4 | 2071 | |
cf4c6a2f | 2072 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2073 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2074 | |
2075 | memset(&entry1, 0, sizeof(entry1)); | |
2076 | ||
2077 | entry1.dest_mode = 0; /* physical delivery */ | |
2078 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2079 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2080 | entry1.delivery_mode = dest_ExtINT; |
2081 | entry1.polarity = entry0.polarity; | |
2082 | entry1.trigger = 0; | |
2083 | entry1.vector = 0; | |
2084 | ||
cf4c6a2f | 2085 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2086 | |
2087 | save_control = CMOS_READ(RTC_CONTROL); | |
2088 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2089 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2090 | RTC_FREQ_SELECT); | |
2091 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2092 | ||
2093 | i = 100; | |
2094 | while (i-- > 0) { | |
2095 | mdelay(10); | |
2096 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2097 | i -= 10; | |
2098 | } | |
2099 | ||
2100 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2101 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2102 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2103 | |
cf4c6a2f | 2104 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2105 | } |
2106 | ||
efa2559f | 2107 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2108 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2109 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2110 | { |
2111 | disable_timer_pin_1 = 1; | |
2112 | return 0; | |
2113 | } | |
54168ed7 | 2114 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2115 | |
d32932d0 JL |
2116 | static int mp_alloc_timer_irq(int ioapic, int pin) |
2117 | { | |
2118 | int irq = -1; | |
2119 | struct irq_alloc_info info; | |
2120 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); | |
2121 | ||
2122 | if (domain) { | |
2123 | ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); | |
2124 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2125 | info.ioapic_pin = pin; | |
2126 | mutex_lock(&ioapic_mutex); | |
2127 | irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); | |
2128 | mutex_unlock(&ioapic_mutex); | |
2129 | } | |
2130 | ||
2131 | return irq; | |
2132 | } | |
2133 | ||
1da177e4 LT |
2134 | /* |
2135 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2136 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2137 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2138 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2139 | * |
2140 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2141 | */ |
8542b200 | 2142 | static inline void __init check_timer(void) |
1da177e4 | 2143 | { |
32f5ef5d | 2144 | struct irq_cfg *cfg = irq_cfg(0); |
f6e9456c | 2145 | int node = cpu_to_node(0); |
fcfd636a | 2146 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2147 | unsigned long flags; |
047c8fdb | 2148 | int no_pin1 = 0; |
4aae0702 IM |
2149 | |
2150 | local_irq_save(flags); | |
d4d25dec | 2151 | |
1da177e4 LT |
2152 | /* |
2153 | * get/set the timer IRQ vector: | |
2154 | */ | |
4305df94 | 2155 | legacy_pic->mask(0); |
1da177e4 LT |
2156 | |
2157 | /* | |
d11d5794 MR |
2158 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2159 | * wire has to be disabled in the local APIC. Also | |
2160 | * timer interrupts need to be acknowledged manually in | |
2161 | * the 8259A for the i82489DX when using the NMI | |
2162 | * watchdog as that APIC treats NMIs as level-triggered. | |
2163 | * The AEOI mode will finish them in the 8259A | |
2164 | * automatically. | |
1da177e4 | 2165 | */ |
593f4a78 | 2166 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2167 | legacy_pic->init(1); |
1da177e4 | 2168 | |
fcfd636a EB |
2169 | pin1 = find_isa_irq_pin(0, mp_INT); |
2170 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2171 | pin2 = ioapic_i8259.pin; | |
2172 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2173 | |
49a66a0b MR |
2174 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2175 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2176 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2177 | |
691874fa MR |
2178 | /* |
2179 | * Some BIOS writers are clueless and report the ExtINTA | |
2180 | * I/O APIC input from the cascaded 8259A as the timer | |
2181 | * interrupt input. So just in case, if only one pin | |
2182 | * was found above, try it both directly and through the | |
2183 | * 8259A. | |
2184 | */ | |
2185 | if (pin1 == -1) { | |
6a9f5de2 | 2186 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2187 | pin1 = pin2; |
2188 | apic1 = apic2; | |
2189 | no_pin1 = 1; | |
2190 | } else if (pin2 == -1) { | |
2191 | pin2 = pin1; | |
2192 | apic2 = apic1; | |
2193 | } | |
2194 | ||
1da177e4 | 2195 | if (pin1 != -1) { |
d32932d0 | 2196 | /* Ok, does IRQ0 through the IOAPIC work? */ |
691874fa | 2197 | if (no_pin1) { |
d32932d0 | 2198 | mp_alloc_timer_irq(apic1, pin1); |
f72dccac | 2199 | } else { |
d32932d0 JL |
2200 | /* |
2201 | * for edge trigger, it's already unmasked, | |
f72dccac YL |
2202 | * so only need to unmask if it is level-trigger |
2203 | * do we really have level trigger timer? | |
2204 | */ | |
2205 | int idx; | |
2206 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2207 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2208 | unmask_ioapic(cfg); |
691874fa | 2209 | } |
d32932d0 | 2210 | irq_domain_activate_irq(irq_get_irq_data(0)); |
1da177e4 | 2211 | if (timer_irq_works()) { |
66759a01 CE |
2212 | if (disable_timer_pin_1 > 0) |
2213 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2214 | goto out; |
1da177e4 | 2215 | } |
6a9f5de2 | 2216 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2217 | local_irq_disable(); |
fcfd636a | 2218 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2219 | if (!no_pin1) |
49a66a0b MR |
2220 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2221 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2222 | |
49a66a0b MR |
2223 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2224 | "(IRQ0) through the 8259A ...\n"); | |
2225 | apic_printk(APIC_QUIET, KERN_INFO | |
2226 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2227 | /* |
2228 | * legacy devices should be connected to IO APIC #0 | |
2229 | */ | |
85ac16d0 | 2230 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
d32932d0 | 2231 | irq_domain_activate_irq(irq_get_irq_data(0)); |
4305df94 | 2232 | legacy_pic->unmask(0); |
1da177e4 | 2233 | if (timer_irq_works()) { |
49a66a0b | 2234 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2235 | goto out; |
1da177e4 LT |
2236 | } |
2237 | /* | |
2238 | * Cleanup, just in case ... | |
2239 | */ | |
f72dccac | 2240 | local_irq_disable(); |
4305df94 | 2241 | legacy_pic->mask(0); |
fcfd636a | 2242 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2243 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2244 | } |
1da177e4 | 2245 | |
49a66a0b MR |
2246 | apic_printk(APIC_QUIET, KERN_INFO |
2247 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2248 | |
60c69948 | 2249 | lapic_register_intr(0); |
497c9a19 | 2250 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2251 | legacy_pic->unmask(0); |
1da177e4 LT |
2252 | |
2253 | if (timer_irq_works()) { | |
49a66a0b | 2254 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2255 | goto out; |
1da177e4 | 2256 | } |
f72dccac | 2257 | local_irq_disable(); |
4305df94 | 2258 | legacy_pic->mask(0); |
497c9a19 | 2259 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2260 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2261 | |
49a66a0b MR |
2262 | apic_printk(APIC_QUIET, KERN_INFO |
2263 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2264 | |
b81bb373 JP |
2265 | legacy_pic->init(0); |
2266 | legacy_pic->make_irq(0); | |
593f4a78 | 2267 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2268 | |
2269 | unlock_ExtINT_logic(); | |
2270 | ||
2271 | if (timer_irq_works()) { | |
49a66a0b | 2272 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2273 | goto out; |
1da177e4 | 2274 | } |
f72dccac | 2275 | local_irq_disable(); |
49a66a0b | 2276 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2ca5b404 | 2277 | if (apic_is_x2apic_enabled()) |
fb209bd8 YL |
2278 | apic_printk(APIC_QUIET, KERN_INFO |
2279 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2280 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2281 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2282 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2283 | out: |
2284 | local_irq_restore(flags); | |
1da177e4 LT |
2285 | } |
2286 | ||
2287 | /* | |
af174783 MR |
2288 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2289 | * to devices. However there may be an I/O APIC pin available for | |
2290 | * this interrupt regardless. The pin may be left unconnected, but | |
2291 | * typically it will be reused as an ExtINT cascade interrupt for | |
2292 | * the master 8259A. In the MPS case such a pin will normally be | |
2293 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2294 | * there is no provision for ExtINT interrupts, and in the absence | |
2295 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2296 | * interrupt, that is edge-triggered and unmasked by default. We | |
2297 | * used to do this, but it caused problems on some systems because | |
2298 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2299 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2300 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2301 | * the I/O APIC in all cases now. No actual device should request | |
2302 | * it anyway. --macro | |
1da177e4 | 2303 | */ |
bc07844a | 2304 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2305 | |
44767bfa JL |
2306 | static int mp_irqdomain_create(int ioapic) |
2307 | { | |
d32932d0 JL |
2308 | struct irq_alloc_info info; |
2309 | struct irq_domain *parent; | |
44767bfa JL |
2310 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2311 | struct ioapic *ip = &ioapics[ioapic]; | |
2312 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2313 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2314 | ||
2315 | if (cfg->type == IOAPIC_DOMAIN_INVALID) | |
2316 | return 0; | |
2317 | ||
d32932d0 JL |
2318 | init_irq_alloc_info(&info, NULL); |
2319 | info.type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
2320 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2321 | parent = irq_remapping_get_ir_irq_domain(&info); | |
2322 | if (!parent) | |
2323 | parent = x86_vector_domain; | |
2324 | ||
44767bfa JL |
2325 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, |
2326 | (void *)(long)ioapic); | |
b75e818f | 2327 | if (!ip->irqdomain) |
44767bfa | 2328 | return -ENOMEM; |
b75e818f JL |
2329 | |
2330 | ip->irqdomain->parent = parent; | |
44767bfa JL |
2331 | |
2332 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2333 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2334 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2335 | gsi_cfg->gsi_end + 1); | |
2336 | ||
44767bfa JL |
2337 | return 0; |
2338 | } | |
2339 | ||
15516a3b JL |
2340 | static void ioapic_destroy_irqdomain(int idx) |
2341 | { | |
2342 | if (ioapics[idx].irqdomain) { | |
2343 | irq_domain_remove(ioapics[idx].irqdomain); | |
2344 | ioapics[idx].irqdomain = NULL; | |
2345 | } | |
15516a3b JL |
2346 | } |
2347 | ||
1da177e4 LT |
2348 | void __init setup_IO_APIC(void) |
2349 | { | |
44767bfa | 2350 | int ioapic; |
54168ed7 | 2351 | |
a46f5c89 TG |
2352 | if (skip_ioapic_setup || !nr_ioapics) |
2353 | return; | |
2354 | ||
95d76acc | 2355 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2356 | |
54168ed7 | 2357 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2358 | for_each_ioapic(ioapic) |
2359 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2360 | ||
d6c88a50 | 2361 | /* |
54168ed7 IM |
2362 | * Set up IO-APIC IRQ routing. |
2363 | */ | |
de934103 TG |
2364 | x86_init.mpparse.setup_ioapic_ids(); |
2365 | ||
1da177e4 LT |
2366 | sync_Arb_IDs(); |
2367 | setup_IO_APIC_irqs(); | |
2368 | init_IO_APIC_traps(); | |
95d76acc | 2369 | if (nr_legacy_irqs()) |
bc07844a | 2370 | check_timer(); |
b81975ea JL |
2371 | |
2372 | ioapic_initialized = 1; | |
1da177e4 LT |
2373 | } |
2374 | ||
2375 | /* | |
0d2eb44f | 2376 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2377 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2378 | */ |
36062448 | 2379 | |
1da177e4 LT |
2380 | static int __init io_apic_bug_finalize(void) |
2381 | { | |
d6c88a50 TG |
2382 | if (sis_apic_bug == -1) |
2383 | sis_apic_bug = 0; | |
2384 | return 0; | |
1da177e4 LT |
2385 | } |
2386 | ||
2387 | late_initcall(io_apic_bug_finalize); | |
2388 | ||
6f50d45f | 2389 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2390 | { |
1da177e4 LT |
2391 | unsigned long flags; |
2392 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2393 | |
dade7716 | 2394 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2395 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2396 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2397 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2398 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2399 | } |
dade7716 | 2400 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2401 | } |
1da177e4 | 2402 | |
f3c6ea1b RW |
2403 | static void ioapic_resume(void) |
2404 | { | |
6f50d45f | 2405 | int ioapic_idx; |
f3c6ea1b | 2406 | |
f44d1692 | 2407 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2408 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2409 | |
2410 | restore_ioapic_entries(); | |
1da177e4 LT |
2411 | } |
2412 | ||
f3c6ea1b | 2413 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2414 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2415 | .resume = ioapic_resume, |
2416 | }; | |
2417 | ||
f3c6ea1b | 2418 | static int __init ioapic_init_ops(void) |
1da177e4 | 2419 | { |
f3c6ea1b RW |
2420 | register_syscore_ops(&ioapic_syscore_ops); |
2421 | ||
1da177e4 LT |
2422 | return 0; |
2423 | } | |
2424 | ||
f3c6ea1b | 2425 | device_initcall(ioapic_init_ops); |
1da177e4 | 2426 | |
67dc5e70 | 2427 | static int io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
2428 | { |
2429 | union IO_APIC_reg_01 reg_01; | |
2430 | unsigned long flags; | |
2431 | ||
dade7716 | 2432 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 2433 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2434 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 2435 | |
4b6b19a1 EB |
2436 | /* The register returns the maximum index redir index |
2437 | * supported, which is one less than the total number of redir | |
2438 | * entries. | |
2439 | */ | |
2440 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
2441 | } |
2442 | ||
62a08ae2 TG |
2443 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
2444 | { | |
b81975ea JL |
2445 | /* |
2446 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
2447 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
2448 | */ | |
2449 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
2450 | } |
2451 | ||
54168ed7 | 2452 | #ifdef CONFIG_X86_32 |
67dc5e70 | 2453 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2454 | { |
2455 | union IO_APIC_reg_00 reg_00; | |
2456 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2457 | physid_mask_t tmp; | |
2458 | unsigned long flags; | |
2459 | int i = 0; | |
2460 | ||
2461 | /* | |
36062448 PC |
2462 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2463 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2464 | * supports up to 16 on one shared APIC bus. |
36062448 | 2465 | * |
1da177e4 LT |
2466 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2467 | * advantage of new APIC bus architecture. | |
2468 | */ | |
2469 | ||
2470 | if (physids_empty(apic_id_map)) | |
7abc0753 | 2471 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 2472 | |
dade7716 | 2473 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2474 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 2475 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2476 | |
2477 | if (apic_id >= get_physical_broadcast()) { | |
2478 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2479 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2480 | apic_id = reg_00.bits.ID; | |
2481 | } | |
2482 | ||
2483 | /* | |
36062448 | 2484 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2485 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2486 | */ | |
7abc0753 | 2487 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
2488 | |
2489 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 2490 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
2491 | break; |
2492 | } | |
2493 | ||
2494 | if (i == get_physical_broadcast()) | |
2495 | panic("Max apic_id exceeded!\n"); | |
2496 | ||
2497 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2498 | "trying %d\n", ioapic, apic_id, i); | |
2499 | ||
2500 | apic_id = i; | |
36062448 | 2501 | } |
1da177e4 | 2502 | |
7abc0753 | 2503 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
2504 | physids_or(apic_id_map, apic_id_map, tmp); |
2505 | ||
2506 | if (reg_00.bits.ID != apic_id) { | |
2507 | reg_00.bits.ID = apic_id; | |
2508 | ||
dade7716 | 2509 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2510 | io_apic_write(ioapic, 0, reg_00.raw); |
2511 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 2512 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2513 | |
2514 | /* Sanity check */ | |
6070f9ec | 2515 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
2516 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
2517 | ioapic); | |
6070f9ec AD |
2518 | return -1; |
2519 | } | |
1da177e4 LT |
2520 | } |
2521 | ||
2522 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2523 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2524 | ||
2525 | return apic_id; | |
2526 | } | |
41098ffe | 2527 | |
67dc5e70 | 2528 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe TG |
2529 | { |
2530 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
2531 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
5411dc4c | 2532 | return io_apic_get_unique_id(idx, id); |
41098ffe TG |
2533 | else |
2534 | return id; | |
2535 | } | |
2536 | #else | |
67dc5e70 | 2537 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe | 2538 | { |
5411dc4c | 2539 | union IO_APIC_reg_00 reg_00; |
41098ffe | 2540 | DECLARE_BITMAP(used, 256); |
5411dc4c YL |
2541 | unsigned long flags; |
2542 | u8 new_id; | |
2543 | int i; | |
41098ffe TG |
2544 | |
2545 | bitmap_zero(used, 256); | |
f44d1692 | 2546 | for_each_ioapic(i) |
d5371430 | 2547 | __set_bit(mpc_ioapic_id(i), used); |
5411dc4c YL |
2548 | |
2549 | /* Hand out the requested id if available */ | |
41098ffe TG |
2550 | if (!test_bit(id, used)) |
2551 | return id; | |
5411dc4c YL |
2552 | |
2553 | /* | |
2554 | * Read the current id from the ioapic and keep it if | |
2555 | * available. | |
2556 | */ | |
2557 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2558 | reg_00.raw = io_apic_read(idx, 0); | |
2559 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2560 | new_id = reg_00.bits.ID; | |
2561 | if (!test_bit(new_id, used)) { | |
2562 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2563 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", | |
2564 | idx, new_id, id); | |
2565 | return new_id; | |
2566 | } | |
2567 | ||
2568 | /* | |
2569 | * Get the next free id and write it to the ioapic. | |
2570 | */ | |
2571 | new_id = find_first_zero_bit(used, 256); | |
2572 | reg_00.bits.ID = new_id; | |
2573 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2574 | io_apic_write(idx, 0, reg_00.raw); | |
2575 | reg_00.raw = io_apic_read(idx, 0); | |
2576 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2577 | /* Sanity check */ | |
2578 | BUG_ON(reg_00.bits.ID != new_id); | |
2579 | ||
2580 | return new_id; | |
41098ffe | 2581 | } |
58f892e0 | 2582 | #endif |
1da177e4 | 2583 | |
67dc5e70 | 2584 | static int io_apic_get_version(int ioapic) |
1da177e4 LT |
2585 | { |
2586 | union IO_APIC_reg_01 reg_01; | |
2587 | unsigned long flags; | |
2588 | ||
dade7716 | 2589 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2590 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2591 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2592 | |
2593 | return reg_01.bits.version; | |
2594 | } | |
2595 | ||
9a0a91bb | 2596 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 2597 | { |
9a0a91bb | 2598 | int ioapic, pin, idx; |
61fd47e0 SL |
2599 | |
2600 | if (skip_ioapic_setup) | |
2601 | return -1; | |
2602 | ||
9a0a91bb EB |
2603 | ioapic = mp_find_ioapic(gsi); |
2604 | if (ioapic < 0) | |
61fd47e0 SL |
2605 | return -1; |
2606 | ||
9a0a91bb EB |
2607 | pin = mp_find_ioapic_pin(ioapic, gsi); |
2608 | if (pin < 0) | |
2609 | return -1; | |
2610 | ||
2611 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
2612 | if (idx < 0) | |
61fd47e0 SL |
2613 | return -1; |
2614 | ||
9a0a91bb EB |
2615 | *trigger = irq_trigger(idx); |
2616 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
2617 | return 0; |
2618 | } | |
2619 | ||
497c9a19 YL |
2620 | /* |
2621 | * This function currently is only a helper for the i386 smp boot process where | |
2622 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 2623 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
2624 | */ |
2625 | #ifdef CONFIG_SMP | |
2626 | void __init setup_ioapic_dest(void) | |
2627 | { | |
fad53995 | 2628 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 2629 | const struct cpumask *mask; |
5451ddc5 | 2630 | struct irq_data *idata; |
497c9a19 YL |
2631 | |
2632 | if (skip_ioapic_setup == 1) | |
2633 | return; | |
2634 | ||
f44d1692 | 2635 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
2636 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
2637 | if (irq_entry == -1) | |
2638 | continue; | |
6c2e9403 | 2639 | |
d7f3d478 JL |
2640 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
2641 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
2642 | continue; |
2643 | ||
5451ddc5 | 2644 | idata = irq_get_irq_data(irq); |
6c2e9403 | 2645 | |
b9c61b70 YL |
2646 | /* |
2647 | * Honour affinities which have been set in early boot | |
2648 | */ | |
5451ddc5 TG |
2649 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
2650 | mask = idata->affinity; | |
b9c61b70 YL |
2651 | else |
2652 | mask = apic->target_cpus(); | |
497c9a19 | 2653 | |
aa5cb97f | 2654 | irq_set_affinity(irq, mask); |
497c9a19 | 2655 | } |
b9c61b70 | 2656 | |
497c9a19 YL |
2657 | } |
2658 | #endif | |
2659 | ||
54168ed7 IM |
2660 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2661 | ||
2662 | static struct resource *ioapic_resources; | |
2663 | ||
f44d1692 | 2664 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
2665 | { |
2666 | unsigned long n; | |
2667 | struct resource *res; | |
2668 | char *mem; | |
f44d1692 | 2669 | int i, num = 0; |
54168ed7 | 2670 | |
f44d1692 JL |
2671 | for_each_ioapic(i) |
2672 | num++; | |
2673 | if (num == 0) | |
54168ed7 IM |
2674 | return NULL; |
2675 | ||
2676 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 2677 | n *= num; |
54168ed7 IM |
2678 | |
2679 | mem = alloc_bootmem(n); | |
2680 | res = (void *)mem; | |
2681 | ||
f44d1692 | 2682 | mem += sizeof(struct resource) * num; |
54168ed7 | 2683 | |
f44d1692 JL |
2684 | num = 0; |
2685 | for_each_ioapic(i) { | |
2686 | res[num].name = mem; | |
2687 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 2688 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 2689 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 2690 | num++; |
15516a3b | 2691 | ioapics[i].iomem_res = res; |
54168ed7 IM |
2692 | } |
2693 | ||
2694 | ioapic_resources = res; | |
2695 | ||
2696 | return res; | |
2697 | } | |
54168ed7 | 2698 | |
4a8e2a31 | 2699 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
2700 | { |
2701 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 2702 | struct resource *ioapic_res; |
d6c88a50 | 2703 | int i; |
f3294a33 | 2704 | |
f44d1692 JL |
2705 | ioapic_res = ioapic_setup_resources(); |
2706 | for_each_ioapic(i) { | |
f3294a33 | 2707 | if (smp_found_config) { |
d5371430 | 2708 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 2709 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
2710 | if (!ioapic_phys) { |
2711 | printk(KERN_ERR | |
2712 | "WARNING: bogus zero IO-APIC " | |
2713 | "address found in MPTABLE, " | |
2714 | "disabling IO/APIC support!\n"); | |
2715 | smp_found_config = 0; | |
2716 | skip_ioapic_setup = 1; | |
2717 | goto fake_ioapic_page; | |
2718 | } | |
54168ed7 | 2719 | #endif |
f3294a33 | 2720 | } else { |
54168ed7 | 2721 | #ifdef CONFIG_X86_32 |
f3294a33 | 2722 | fake_ioapic_page: |
54168ed7 | 2723 | #endif |
e79c65a9 | 2724 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
2725 | ioapic_phys = __pa(ioapic_phys); |
2726 | } | |
2727 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
2728 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
2729 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
2730 | ioapic_phys); | |
f3294a33 | 2731 | idx++; |
54168ed7 | 2732 | |
ffc43836 | 2733 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 2734 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 2735 | ioapic_res++; |
f3294a33 YL |
2736 | } |
2737 | } | |
2738 | ||
857fdc53 | 2739 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
2740 | { |
2741 | int i; | |
2742 | struct resource *r = ioapic_resources; | |
2743 | ||
2744 | if (!r) { | |
857fdc53 | 2745 | if (nr_ioapics > 0) |
04c93ce4 BZ |
2746 | printk(KERN_ERR |
2747 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 2748 | return; |
54168ed7 IM |
2749 | } |
2750 | ||
f44d1692 | 2751 | for_each_ioapic(i) { |
54168ed7 IM |
2752 | insert_resource(&iomem_resource, r); |
2753 | r++; | |
2754 | } | |
54168ed7 | 2755 | } |
2a4ab640 | 2756 | |
eddb0c55 | 2757 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 2758 | { |
f44d1692 | 2759 | int i; |
2a4ab640 | 2760 | |
678301ec PB |
2761 | if (nr_ioapics == 0) |
2762 | return -1; | |
2763 | ||
2a4ab640 | 2764 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 2765 | for_each_ioapic(i) { |
c040aaeb | 2766 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 2767 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
2768 | return i; |
2769 | } | |
54168ed7 | 2770 | |
2a4ab640 FT |
2771 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
2772 | return -1; | |
2773 | } | |
2774 | ||
eddb0c55 | 2775 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 2776 | { |
c040aaeb SS |
2777 | struct mp_ioapic_gsi *gsi_cfg; |
2778 | ||
f44d1692 | 2779 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 2780 | return -1; |
c040aaeb SS |
2781 | |
2782 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2783 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
2784 | return -1; |
2785 | ||
c040aaeb | 2786 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
2787 | } |
2788 | ||
67dc5e70 | 2789 | static int bad_ioapic_register(int idx) |
73d63d03 SS |
2790 | { |
2791 | union IO_APIC_reg_00 reg_00; | |
2792 | union IO_APIC_reg_01 reg_01; | |
2793 | union IO_APIC_reg_02 reg_02; | |
2794 | ||
2795 | reg_00.raw = io_apic_read(idx, 0); | |
2796 | reg_01.raw = io_apic_read(idx, 1); | |
2797 | reg_02.raw = io_apic_read(idx, 2); | |
2798 | ||
2799 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
2800 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
2801 | mpc_ioapic_addr(idx)); | |
2802 | return 1; | |
2803 | } | |
2804 | ||
2805 | return 0; | |
2806 | } | |
2807 | ||
35ef9c94 JL |
2808 | static int find_free_ioapic_entry(void) |
2809 | { | |
7db298cb JL |
2810 | int idx; |
2811 | ||
2812 | for (idx = 0; idx < MAX_IO_APICS; idx++) | |
2813 | if (ioapics[idx].nr_registers == 0) | |
2814 | return idx; | |
2815 | ||
2816 | return MAX_IO_APICS; | |
35ef9c94 JL |
2817 | } |
2818 | ||
2819 | /** | |
2820 | * mp_register_ioapic - Register an IOAPIC device | |
2821 | * @id: hardware IOAPIC ID | |
2822 | * @address: physical address of IOAPIC register area | |
2823 | * @gsi_base: base of GSI associated with the IOAPIC | |
2824 | * @cfg: configuration information for the IOAPIC | |
2825 | */ | |
2826 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, | |
2827 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 | 2828 | { |
7db298cb | 2829 | bool hotplug = !!ioapic_initialized; |
c040aaeb | 2830 | struct mp_ioapic_gsi *gsi_cfg; |
35ef9c94 JL |
2831 | int idx, ioapic, entries; |
2832 | u32 gsi_end; | |
2a4ab640 | 2833 | |
35ef9c94 JL |
2834 | if (!address) { |
2835 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); | |
2836 | return -EINVAL; | |
2837 | } | |
2838 | for_each_ioapic(ioapic) | |
2839 | if (ioapics[ioapic].mp_config.apicaddr == address) { | |
2840 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", | |
2841 | address, ioapic); | |
2842 | return -EEXIST; | |
2843 | } | |
2a4ab640 | 2844 | |
35ef9c94 JL |
2845 | idx = find_free_ioapic_entry(); |
2846 | if (idx >= MAX_IO_APICS) { | |
2847 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", | |
2848 | MAX_IO_APICS, idx); | |
2849 | return -ENOSPC; | |
2850 | } | |
2a4ab640 | 2851 | |
d5371430 SS |
2852 | ioapics[idx].mp_config.type = MP_IOAPIC; |
2853 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
2854 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
2855 | |
2856 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
2857 | if (bad_ioapic_register(idx)) { |
2858 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
35ef9c94 | 2859 | return -ENODEV; |
73d63d03 SS |
2860 | } |
2861 | ||
5411dc4c | 2862 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
d5371430 | 2863 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
2a4ab640 FT |
2864 | |
2865 | /* | |
2866 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
2867 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
2868 | */ | |
7716a5c4 | 2869 | entries = io_apic_get_redir_entries(idx); |
35ef9c94 JL |
2870 | gsi_end = gsi_base + entries - 1; |
2871 | for_each_ioapic(ioapic) { | |
2872 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2873 | if ((gsi_base >= gsi_cfg->gsi_base && | |
2874 | gsi_base <= gsi_cfg->gsi_end) || | |
2875 | (gsi_end >= gsi_cfg->gsi_base && | |
2876 | gsi_end <= gsi_cfg->gsi_end)) { | |
2877 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", | |
2878 | gsi_base, gsi_end, | |
2879 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2880 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2881 | return -ENOSPC; | |
2882 | } | |
2883 | } | |
c040aaeb SS |
2884 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
2885 | gsi_cfg->gsi_base = gsi_base; | |
35ef9c94 | 2886 | gsi_cfg->gsi_end = gsi_end; |
7716a5c4 | 2887 | |
35ef9c94 JL |
2888 | ioapics[idx].irqdomain = NULL; |
2889 | ioapics[idx].irqdomain_cfg = *cfg; | |
2a4ab640 | 2890 | |
7db298cb JL |
2891 | /* |
2892 | * If mp_register_ioapic() is called during early boot stage when | |
2893 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, | |
2894 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). | |
2895 | */ | |
2896 | if (hotplug) { | |
2897 | if (mp_irqdomain_create(idx)) { | |
2898 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2899 | return -ENOMEM; | |
2900 | } | |
2901 | alloc_ioapic_saved_registers(idx); | |
2902 | } | |
2903 | ||
c040aaeb SS |
2904 | if (gsi_cfg->gsi_end >= gsi_top) |
2905 | gsi_top = gsi_cfg->gsi_end + 1; | |
35ef9c94 JL |
2906 | if (nr_ioapics <= idx) |
2907 | nr_ioapics = idx + 1; | |
2908 | ||
2909 | /* Set nr_registers to mark entry present */ | |
2910 | ioapics[idx].nr_registers = entries; | |
2a4ab640 | 2911 | |
73d63d03 SS |
2912 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
2913 | idx, mpc_ioapic_id(idx), | |
2914 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
2915 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 | 2916 | |
35ef9c94 | 2917 | return 0; |
2a4ab640 | 2918 | } |
05ddafb1 | 2919 | |
15516a3b JL |
2920 | int mp_unregister_ioapic(u32 gsi_base) |
2921 | { | |
2922 | int ioapic, pin; | |
2923 | int found = 0; | |
15516a3b JL |
2924 | |
2925 | for_each_ioapic(ioapic) | |
2926 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { | |
2927 | found = 1; | |
2928 | break; | |
2929 | } | |
2930 | if (!found) { | |
2931 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); | |
2932 | return -ENODEV; | |
2933 | } | |
2934 | ||
2935 | for_each_pin(ioapic, pin) { | |
d32932d0 JL |
2936 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
2937 | int irq = mp_map_gsi_to_irq(gsi, 0, NULL); | |
2938 | struct mp_chip_data *data; | |
2939 | ||
2940 | if (irq >= 0) { | |
2941 | data = irq_get_chip_data(irq); | |
2942 | if (data && data->count) { | |
2943 | pr_warn("pin%d on IOAPIC%d is still in use.\n", | |
2944 | pin, ioapic); | |
2945 | return -EBUSY; | |
2946 | } | |
15516a3b JL |
2947 | } |
2948 | } | |
2949 | ||
2950 | /* Mark entry not present */ | |
2951 | ioapics[ioapic].nr_registers = 0; | |
2952 | ioapic_destroy_irqdomain(ioapic); | |
2953 | free_ioapic_saved_registers(ioapic); | |
2954 | if (ioapics[ioapic].iomem_res) | |
2955 | release_resource(ioapics[ioapic].iomem_res); | |
2956 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); | |
2957 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); | |
2958 | ||
2959 | return 0; | |
2960 | } | |
2961 | ||
e89900c9 JL |
2962 | int mp_ioapic_registered(u32 gsi_base) |
2963 | { | |
2964 | int ioapic; | |
2965 | ||
2966 | for_each_ioapic(ioapic) | |
2967 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) | |
2968 | return 1; | |
2969 | ||
2970 | return 0; | |
2971 | } | |
2972 | ||
8643e28d JL |
2973 | static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr, |
2974 | int ioapic, int ioapic_pin, | |
2975 | int trigger, int polarity) | |
2976 | { | |
2977 | irq_attr->ioapic = ioapic; | |
2978 | irq_attr->ioapic_pin = ioapic_pin; | |
2979 | irq_attr->trigger = trigger; | |
2980 | irq_attr->polarity = polarity; | |
2981 | } | |
2982 | ||
49c7e600 | 2983 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
5ad274d4 | 2984 | struct irq_alloc_info *info) |
49c7e600 JL |
2985 | { |
2986 | if (info && info->ioapic_valid) { | |
2987 | data->trigger = info->ioapic_trigger; | |
2988 | data->polarity = info->ioapic_polarity; | |
2989 | } else if (acpi_get_override_irq(gsi, &data->trigger, | |
2990 | &data->polarity) < 0) { | |
2991 | /* PCI interrupts are always polarity one level triggered. */ | |
2992 | data->trigger = 1; | |
2993 | data->polarity = 1; | |
2994 | } | |
2995 | } | |
2996 | ||
2997 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, | |
2998 | struct IO_APIC_route_entry *entry) | |
2999 | { | |
3000 | memset(entry, 0, sizeof(*entry)); | |
3001 | entry->delivery_mode = apic->irq_delivery_mode; | |
3002 | entry->dest_mode = apic->irq_dest_mode; | |
3003 | entry->dest = cfg->dest_apicid; | |
3004 | entry->vector = cfg->vector; | |
3005 | entry->mask = 0; /* enable IRQ */ | |
3006 | entry->trigger = data->trigger; | |
3007 | entry->polarity = data->polarity; | |
3008 | /* | |
3009 | * Mask level triggered irqs. | |
3010 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
3011 | */ | |
3012 | if (data->trigger) | |
3013 | entry->mask = 1; | |
3014 | } | |
3015 | ||
3016 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, | |
3017 | unsigned int nr_irqs, void *arg) | |
3018 | { | |
3019 | int ret, ioapic, pin; | |
3020 | struct irq_cfg *cfg; | |
3021 | struct irq_data *irq_data; | |
3022 | struct mp_chip_data *data; | |
3023 | struct irq_alloc_info *info = arg; | |
3024 | ||
3025 | if (!info || nr_irqs > 1) | |
3026 | return -EINVAL; | |
3027 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3028 | if (!irq_data) | |
3029 | return -EINVAL; | |
3030 | ||
3031 | ioapic = mp_irqdomain_ioapic_idx(domain); | |
3032 | pin = info->ioapic_pin; | |
3033 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) | |
3034 | return -EEXIST; | |
3035 | ||
3036 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3037 | if (!data) | |
3038 | return -ENOMEM; | |
3039 | ||
3040 | info->ioapic_entry = &data->entry; | |
3041 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); | |
3042 | if (ret < 0) { | |
3043 | kfree(data); | |
3044 | return ret; | |
3045 | } | |
3046 | ||
3047 | irq_data->hwirq = info->ioapic_pin; | |
d32932d0 JL |
3048 | irq_data->chip = (domain->parent == x86_vector_domain) ? |
3049 | &ioapic_chip : &ioapic_ir_chip; | |
49c7e600 JL |
3050 | irq_data->chip_data = data; |
3051 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); | |
3052 | ||
3053 | cfg = irqd_cfg(irq_data); | |
3054 | add_pin_to_irq_node(cfg, info->ioapic_node, ioapic, pin); | |
3055 | if (info->ioapic_entry) | |
3056 | mp_setup_entry(cfg, data, info->ioapic_entry); | |
3057 | mp_register_handler(virq, data->trigger); | |
3058 | if (virq < nr_legacy_irqs()) | |
3059 | legacy_pic->mask(virq); | |
3060 | ||
3061 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
3062 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", | |
3063 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, | |
3064 | virq, data->trigger, data->polarity, cfg->dest_apicid); | |
3065 | ||
3066 | return 0; | |
3067 | } | |
3068 | ||
3069 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, | |
3070 | unsigned int nr_irqs) | |
3071 | { | |
3072 | struct irq_cfg *cfg = irq_cfg(virq); | |
3073 | struct irq_data *irq_data; | |
3074 | ||
3075 | BUG_ON(nr_irqs != 1); | |
3076 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3077 | if (irq_data && irq_data->chip_data) { | |
3078 | __remove_pin_from_irq(cfg, mp_irqdomain_ioapic_idx(domain), | |
3079 | (int)irq_data->hwirq); | |
3080 | WARN_ON(!list_empty(&cfg->irq_2_pin)); | |
3081 | kfree(irq_data->chip_data); | |
3082 | } | |
3083 | irq_domain_free_irqs_top(domain, virq, nr_irqs); | |
3084 | } | |
3085 | ||
3086 | void mp_irqdomain_activate(struct irq_domain *domain, | |
3087 | struct irq_data *irq_data) | |
3088 | { | |
3089 | unsigned long flags; | |
3090 | struct irq_pin_list *entry; | |
3091 | struct mp_chip_data *data = irq_data->chip_data; | |
3092 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
3093 | ||
3094 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3095 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
3096 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); | |
3097 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
3098 | } | |
3099 | ||
3100 | void mp_irqdomain_deactivate(struct irq_domain *domain, | |
3101 | struct irq_data *irq_data) | |
3102 | { | |
3103 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ | |
3104 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), | |
3105 | (int)irq_data->hwirq); | |
3106 | } | |
3107 | ||
49c7e600 JL |
3108 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) |
3109 | { | |
3110 | return (int)(long)domain->host_data; | |
3111 | } |