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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
a4384df3 EB |
92 | /* The one past the highest gsi number used */ |
93 | u32 gsi_top; | |
5777372a | 94 | |
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
a1420f39 | 143 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 144 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 146 | #else |
97943390 | 147 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 148 | #endif |
a1420f39 | 149 | |
13a0c3c2 | 150 | int __init arch_early_irq_init(void) |
8f09cd20 | 151 | { |
0b8f1efa YL |
152 | struct irq_cfg *cfg; |
153 | struct irq_desc *desc; | |
154 | int count; | |
dad213ae | 155 | int node; |
0b8f1efa | 156 | int i; |
d6c88a50 | 157 | |
1f91233c JP |
158 | if (!legacy_pic->nr_legacy_irqs) { |
159 | nr_irqs_gsi = 0; | |
160 | io_apic_irqs = ~0UL; | |
161 | } | |
162 | ||
0b8f1efa YL |
163 | cfg = irq_cfgx; |
164 | count = ARRAY_SIZE(irq_cfgx); | |
dad213ae | 165 | node= cpu_to_node(boot_cpu_id); |
8f09cd20 | 166 | |
0b8f1efa YL |
167 | for (i = 0; i < count; i++) { |
168 | desc = irq_to_desc(i); | |
169 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
170 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
171 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
172 | /* |
173 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
174 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
175 | */ | |
54b56170 | 176 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
177 | cfg[i].vector = IRQ0_VECTOR + i; |
178 | cpumask_set_cpu(0, cfg[i].domain); | |
179 | } | |
0b8f1efa | 180 | } |
13a0c3c2 YL |
181 | |
182 | return 0; | |
0b8f1efa | 183 | } |
8f09cd20 | 184 | |
0b8f1efa | 185 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 186 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 187 | { |
0b8f1efa YL |
188 | struct irq_cfg *cfg = NULL; |
189 | struct irq_desc *desc; | |
1da177e4 | 190 | |
0b8f1efa YL |
191 | desc = irq_to_desc(irq); |
192 | if (desc) | |
193 | cfg = desc->chip_data; | |
0f978f45 | 194 | |
0b8f1efa | 195 | return cfg; |
8f09cd20 | 196 | } |
d6c88a50 | 197 | |
85ac16d0 | 198 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 199 | { |
0b8f1efa | 200 | struct irq_cfg *cfg; |
0f978f45 | 201 | |
0b8f1efa | 202 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 203 | if (cfg) { |
79f55997 | 204 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
205 | kfree(cfg); |
206 | cfg = NULL; | |
79f55997 | 207 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 208 | GFP_ATOMIC, node)) { |
22f65d31 MT |
209 | free_cpumask_var(cfg->domain); |
210 | kfree(cfg); | |
211 | cfg = NULL; | |
22f65d31 MT |
212 | } |
213 | } | |
0f978f45 | 214 | |
0b8f1efa | 215 | return cfg; |
8f09cd20 YL |
216 | } |
217 | ||
85ac16d0 | 218 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 219 | { |
0b8f1efa | 220 | struct irq_cfg *cfg; |
d6c88a50 | 221 | |
0b8f1efa YL |
222 | cfg = desc->chip_data; |
223 | if (!cfg) { | |
85ac16d0 | 224 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
225 | if (!desc->chip_data) { |
226 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
227 | BUG_ON(1); | |
228 | } | |
229 | } | |
1da177e4 | 230 | |
13a0c3c2 | 231 | return 0; |
0b8f1efa | 232 | } |
0f978f45 | 233 | |
fcef5911 | 234 | /* for move_irq_desc */ |
48a1b10a | 235 | static void |
85ac16d0 | 236 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 237 | { |
48a1b10a YL |
238 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
239 | ||
240 | cfg->irq_2_pin = NULL; | |
241 | old_entry = old_cfg->irq_2_pin; | |
242 | if (!old_entry) | |
243 | return; | |
0f978f45 | 244 | |
85ac16d0 | 245 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
246 | if (!entry) |
247 | return; | |
0f978f45 | 248 | |
48a1b10a YL |
249 | entry->apic = old_entry->apic; |
250 | entry->pin = old_entry->pin; | |
251 | head = entry; | |
252 | tail = entry; | |
253 | old_entry = old_entry->next; | |
254 | while (old_entry) { | |
85ac16d0 | 255 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
256 | if (!entry) { |
257 | entry = head; | |
258 | while (entry) { | |
259 | head = entry->next; | |
260 | kfree(entry); | |
261 | entry = head; | |
262 | } | |
263 | /* still use the old one */ | |
264 | return; | |
265 | } | |
266 | entry->apic = old_entry->apic; | |
267 | entry->pin = old_entry->pin; | |
268 | tail->next = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | } | |
0f978f45 | 272 | |
48a1b10a YL |
273 | tail->next = NULL; |
274 | cfg->irq_2_pin = head; | |
0f978f45 | 275 | } |
0f978f45 | 276 | |
48a1b10a | 277 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 278 | { |
48a1b10a | 279 | struct irq_pin_list *entry, *next; |
0f978f45 | 280 | |
48a1b10a YL |
281 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
282 | return; | |
301e6190 | 283 | |
48a1b10a | 284 | entry = old_cfg->irq_2_pin; |
0f978f45 | 285 | |
48a1b10a YL |
286 | while (entry) { |
287 | next = entry->next; | |
288 | kfree(entry); | |
289 | entry = next; | |
290 | } | |
291 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 295 | struct irq_desc *desc, int node) |
0f978f45 | 296 | { |
48a1b10a YL |
297 | struct irq_cfg *cfg; |
298 | struct irq_cfg *old_cfg; | |
0f978f45 | 299 | |
85ac16d0 | 300 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 301 | |
48a1b10a YL |
302 | if (!cfg) |
303 | return; | |
304 | ||
305 | desc->chip_data = cfg; | |
306 | ||
307 | old_cfg = old_desc->chip_data; | |
308 | ||
309 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
310 | ||
85ac16d0 | 311 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 312 | } |
1da177e4 | 313 | |
48a1b10a YL |
314 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
315 | { | |
316 | kfree(old_cfg); | |
317 | } | |
318 | ||
319 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
320 | { | |
321 | struct irq_cfg *old_cfg, *cfg; | |
322 | ||
323 | old_cfg = old_desc->chip_data; | |
324 | cfg = desc->chip_data; | |
325 | ||
326 | if (old_cfg == cfg) | |
327 | return; | |
328 | ||
329 | if (old_cfg) { | |
330 | free_irq_2_pin(old_cfg, cfg); | |
331 | free_irq_cfg(old_cfg); | |
332 | old_desc->chip_data = NULL; | |
333 | } | |
334 | } | |
fcef5911 | 335 | /* end for move_irq_desc */ |
48a1b10a | 336 | |
0b8f1efa | 337 | #else |
9338ad6f | 338 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
339 | { |
340 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 341 | } |
1da177e4 | 342 | |
0b8f1efa YL |
343 | #endif |
344 | ||
130fe05d LT |
345 | struct io_apic { |
346 | unsigned int index; | |
347 | unsigned int unused[3]; | |
348 | unsigned int data; | |
0280f7c4 SS |
349 | unsigned int unused2[11]; |
350 | unsigned int eoi; | |
130fe05d LT |
351 | }; |
352 | ||
353 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
354 | { | |
355 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 356 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
357 | } |
358 | ||
0280f7c4 SS |
359 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
360 | { | |
361 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
362 | writel(vector, &io_apic->eoi); | |
363 | } | |
364 | ||
130fe05d LT |
365 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
366 | { | |
367 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
368 | writel(reg, &io_apic->index); | |
369 | return readl(&io_apic->data); | |
370 | } | |
371 | ||
372 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
373 | { | |
374 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
375 | writel(reg, &io_apic->index); | |
376 | writel(value, &io_apic->data); | |
377 | } | |
378 | ||
379 | /* | |
380 | * Re-write a value: to be used for read-modify-write | |
381 | * cycles where the read already set up the index register. | |
382 | * | |
383 | * Older SiS APIC requires we rewrite the index register | |
384 | */ | |
385 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
386 | { | |
54168ed7 | 387 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
388 | |
389 | if (sis_apic_bug) | |
390 | writel(reg, &io_apic->index); | |
130fe05d LT |
391 | writel(value, &io_apic->data); |
392 | } | |
393 | ||
3145e941 | 394 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
395 | { |
396 | struct irq_pin_list *entry; | |
397 | unsigned long flags; | |
047c8fdb | 398 | |
dade7716 | 399 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 400 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
401 | unsigned int reg; |
402 | int pin; | |
403 | ||
047c8fdb YL |
404 | pin = entry->pin; |
405 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
406 | /* Is the remote IRR bit set? */ | |
407 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 408 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
409 | return true; |
410 | } | |
047c8fdb | 411 | } |
dade7716 | 412 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
413 | |
414 | return false; | |
415 | } | |
047c8fdb | 416 | |
cf4c6a2f AK |
417 | union entry_union { |
418 | struct { u32 w1, w2; }; | |
419 | struct IO_APIC_route_entry entry; | |
420 | }; | |
421 | ||
422 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
423 | { | |
424 | union entry_union eu; | |
425 | unsigned long flags; | |
dade7716 | 426 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
427 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
428 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 429 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
430 | return eu.entry; |
431 | } | |
432 | ||
f9dadfa7 LT |
433 | /* |
434 | * When we write a new IO APIC routing entry, we need to write the high | |
435 | * word first! If the mask bit in the low word is clear, we will enable | |
436 | * the interrupt, and we need to make sure the entry is fully populated | |
437 | * before that happens. | |
438 | */ | |
d15512f4 AK |
439 | static void |
440 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 441 | { |
50a8d4d2 F |
442 | union entry_union eu = {{0, 0}}; |
443 | ||
cf4c6a2f | 444 | eu.entry = e; |
f9dadfa7 LT |
445 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
446 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
447 | } |
448 | ||
ca97ab90 | 449 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
450 | { |
451 | unsigned long flags; | |
dade7716 | 452 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 453 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 454 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
455 | } |
456 | ||
457 | /* | |
458 | * When we mask an IO APIC routing entry, we need to write the low | |
459 | * word first, in order to set the mask bit before we change the | |
460 | * high bits! | |
461 | */ | |
462 | static void ioapic_mask_entry(int apic, int pin) | |
463 | { | |
464 | unsigned long flags; | |
465 | union entry_union eu = { .entry.mask = 1 }; | |
466 | ||
dade7716 | 467 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
468 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
469 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 470 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
471 | } |
472 | ||
1da177e4 LT |
473 | /* |
474 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
475 | * shared ISA-space IRQs, so we have to support them. We are super | |
476 | * fast in the common case, and fast for shared ISA-space IRQs. | |
477 | */ | |
f3d1915a CG |
478 | static int |
479 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 480 | { |
2977fb3f | 481 | struct irq_pin_list **last, *entry; |
0f978f45 | 482 | |
2977fb3f CG |
483 | /* don't allow duplicates */ |
484 | last = &cfg->irq_2_pin; | |
485 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 486 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 487 | return 0; |
2977fb3f | 488 | last = &entry->next; |
1da177e4 | 489 | } |
0f978f45 | 490 | |
875e68ec | 491 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 492 | if (!entry) { |
f3d1915a CG |
493 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
494 | node, apic, pin); | |
495 | return -ENOMEM; | |
a7428cd2 | 496 | } |
1da177e4 LT |
497 | entry->apic = apic; |
498 | entry->pin = pin; | |
875e68ec | 499 | |
2977fb3f | 500 | *last = entry; |
f3d1915a CG |
501 | return 0; |
502 | } | |
503 | ||
504 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
505 | { | |
506 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
507 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
508 | } |
509 | ||
510 | /* | |
511 | * Reroute an IRQ to a different pin. | |
512 | */ | |
85ac16d0 | 513 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
514 | int oldapic, int oldpin, |
515 | int newapic, int newpin) | |
1da177e4 | 516 | { |
535b6429 | 517 | struct irq_pin_list *entry; |
1da177e4 | 518 | |
2977fb3f | 519 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
520 | if (entry->apic == oldapic && entry->pin == oldpin) { |
521 | entry->apic = newapic; | |
522 | entry->pin = newpin; | |
0f978f45 | 523 | /* every one is different, right? */ |
4eea6fff | 524 | return; |
0f978f45 | 525 | } |
1da177e4 | 526 | } |
0f978f45 | 527 | |
4eea6fff JF |
528 | /* old apic/pin didn't exist, so just add new ones */ |
529 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
530 | } |
531 | ||
c29d9db3 SS |
532 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
533 | int mask_and, int mask_or, | |
534 | void (*final)(struct irq_pin_list *entry)) | |
535 | { | |
536 | unsigned int reg, pin; | |
537 | ||
538 | pin = entry->pin; | |
539 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
540 | reg &= mask_and; | |
541 | reg |= mask_or; | |
542 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
543 | if (final) | |
544 | final(entry); | |
545 | } | |
546 | ||
2f210deb JF |
547 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
548 | int mask_and, int mask_or, | |
549 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 550 | { |
87783be4 | 551 | struct irq_pin_list *entry; |
047c8fdb | 552 | |
c29d9db3 SS |
553 | for_each_irq_pin(entry, cfg->irq_2_pin) |
554 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
555 | } | |
556 | ||
557 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
558 | { | |
559 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
560 | IO_APIC_REDIR_MASKED, NULL); | |
561 | } | |
562 | ||
563 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
564 | { | |
565 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
566 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 567 | } |
047c8fdb | 568 | |
3145e941 | 569 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 570 | { |
3145e941 | 571 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 572 | } |
047c8fdb | 573 | |
7f3e632f | 574 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 575 | { |
87783be4 CG |
576 | /* |
577 | * Synchronize the IO-APIC and the CPU by doing | |
578 | * a dummy read from the IO-APIC | |
579 | */ | |
580 | struct io_apic __iomem *io_apic; | |
581 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 582 | readl(&io_apic->data); |
1da177e4 LT |
583 | } |
584 | ||
3145e941 | 585 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 586 | { |
3145e941 | 587 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 | 588 | } |
1da177e4 | 589 | |
3145e941 | 590 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 591 | { |
3145e941 | 592 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
593 | unsigned long flags; |
594 | ||
3145e941 YL |
595 | BUG_ON(!cfg); |
596 | ||
dade7716 | 597 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 598 | __mask_IO_APIC_irq(cfg); |
dade7716 | 599 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
600 | } |
601 | ||
3145e941 | 602 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 603 | { |
3145e941 | 604 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
605 | unsigned long flags; |
606 | ||
dade7716 | 607 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 608 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 609 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
610 | } |
611 | ||
3145e941 YL |
612 | static void mask_IO_APIC_irq(unsigned int irq) |
613 | { | |
614 | struct irq_desc *desc = irq_to_desc(irq); | |
615 | ||
616 | mask_IO_APIC_irq_desc(desc); | |
617 | } | |
618 | static void unmask_IO_APIC_irq(unsigned int irq) | |
619 | { | |
620 | struct irq_desc *desc = irq_to_desc(irq); | |
621 | ||
622 | unmask_IO_APIC_irq_desc(desc); | |
623 | } | |
624 | ||
1da177e4 LT |
625 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
626 | { | |
627 | struct IO_APIC_route_entry entry; | |
36062448 | 628 | |
1da177e4 | 629 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 630 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
631 | if (entry.delivery_mode == dest_SMI) |
632 | return; | |
1da177e4 LT |
633 | /* |
634 | * Disable it in the IO-APIC irq-routing table: | |
635 | */ | |
f9dadfa7 | 636 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
637 | } |
638 | ||
54168ed7 | 639 | static void clear_IO_APIC (void) |
1da177e4 LT |
640 | { |
641 | int apic, pin; | |
642 | ||
643 | for (apic = 0; apic < nr_ioapics; apic++) | |
644 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
645 | clear_IO_APIC_pin(apic, pin); | |
646 | } | |
647 | ||
54168ed7 | 648 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
649 | /* |
650 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
651 | * specific CPU-side IRQs. | |
652 | */ | |
653 | ||
654 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
655 | static int pirq_entries[MAX_PIRQS] = { |
656 | [0 ... MAX_PIRQS - 1] = -1 | |
657 | }; | |
1da177e4 | 658 | |
1da177e4 LT |
659 | static int __init ioapic_pirq_setup(char *str) |
660 | { | |
661 | int i, max; | |
662 | int ints[MAX_PIRQS+1]; | |
663 | ||
664 | get_options(str, ARRAY_SIZE(ints), ints); | |
665 | ||
1da177e4 LT |
666 | apic_printk(APIC_VERBOSE, KERN_INFO |
667 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
668 | max = MAX_PIRQS; | |
669 | if (ints[0] < MAX_PIRQS) | |
670 | max = ints[0]; | |
671 | ||
672 | for (i = 0; i < max; i++) { | |
673 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
674 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
675 | /* | |
676 | * PIRQs are mapped upside down, usually. | |
677 | */ | |
678 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
679 | } | |
680 | return 1; | |
681 | } | |
682 | ||
683 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
684 | #endif /* CONFIG_X86_32 */ |
685 | ||
b24696bc FY |
686 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
687 | { | |
688 | int apic; | |
689 | struct IO_APIC_route_entry **ioapic_entries; | |
690 | ||
691 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
692 | GFP_ATOMIC); | |
693 | if (!ioapic_entries) | |
694 | return 0; | |
695 | ||
696 | for (apic = 0; apic < nr_ioapics; apic++) { | |
697 | ioapic_entries[apic] = | |
698 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
699 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
700 | if (!ioapic_entries[apic]) | |
701 | goto nomem; | |
702 | } | |
703 | ||
704 | return ioapic_entries; | |
705 | ||
706 | nomem: | |
707 | while (--apic >= 0) | |
708 | kfree(ioapic_entries[apic]); | |
709 | kfree(ioapic_entries); | |
710 | ||
711 | return 0; | |
712 | } | |
54168ed7 IM |
713 | |
714 | /* | |
05c3dc2c | 715 | * Saves all the IO-APIC RTE's |
54168ed7 | 716 | */ |
b24696bc | 717 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 718 | { |
54168ed7 IM |
719 | int apic, pin; |
720 | ||
b24696bc FY |
721 | if (!ioapic_entries) |
722 | return -ENOMEM; | |
54168ed7 IM |
723 | |
724 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
725 | if (!ioapic_entries[apic]) |
726 | return -ENOMEM; | |
54168ed7 | 727 | |
05c3dc2c | 728 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 729 | ioapic_entries[apic][pin] = |
54168ed7 | 730 | ioapic_read_entry(apic, pin); |
b24696bc | 731 | } |
5ffa4eb2 | 732 | |
54168ed7 IM |
733 | return 0; |
734 | } | |
735 | ||
b24696bc FY |
736 | /* |
737 | * Mask all IO APIC entries. | |
738 | */ | |
739 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
740 | { |
741 | int apic, pin; | |
742 | ||
b24696bc FY |
743 | if (!ioapic_entries) |
744 | return; | |
745 | ||
05c3dc2c | 746 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 747 | if (!ioapic_entries[apic]) |
05c3dc2c | 748 | break; |
b24696bc | 749 | |
05c3dc2c SS |
750 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
751 | struct IO_APIC_route_entry entry; | |
752 | ||
b24696bc | 753 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
754 | if (!entry.mask) { |
755 | entry.mask = 1; | |
756 | ioapic_write_entry(apic, pin, entry); | |
757 | } | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
b24696bc FY |
762 | /* |
763 | * Restore IO APIC entries which was saved in ioapic_entries. | |
764 | */ | |
765 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
766 | { |
767 | int apic, pin; | |
768 | ||
b24696bc FY |
769 | if (!ioapic_entries) |
770 | return -ENOMEM; | |
771 | ||
5ffa4eb2 | 772 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
773 | if (!ioapic_entries[apic]) |
774 | return -ENOMEM; | |
775 | ||
54168ed7 IM |
776 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
777 | ioapic_write_entry(apic, pin, | |
b24696bc | 778 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 779 | } |
b24696bc | 780 | return 0; |
54168ed7 IM |
781 | } |
782 | ||
b24696bc FY |
783 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
784 | { | |
785 | int apic; | |
786 | ||
787 | for (apic = 0; apic < nr_ioapics; apic++) | |
788 | kfree(ioapic_entries[apic]); | |
789 | ||
790 | kfree(ioapic_entries); | |
54168ed7 | 791 | } |
1da177e4 LT |
792 | |
793 | /* | |
794 | * Find the IRQ entry number of a certain pin. | |
795 | */ | |
796 | static int find_irq_entry(int apic, int pin, int type) | |
797 | { | |
798 | int i; | |
799 | ||
800 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
801 | if (mp_irqs[i].irqtype == type && |
802 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
803 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
804 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
805 | return i; |
806 | ||
807 | return -1; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Find the pin to which IRQ[irq] (ISA) is connected | |
812 | */ | |
fcfd636a | 813 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
814 | { |
815 | int i; | |
816 | ||
817 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 818 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 819 | |
d27e2b8e | 820 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
821 | (mp_irqs[i].irqtype == type) && |
822 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 823 | |
c2c21745 | 824 | return mp_irqs[i].dstirq; |
1da177e4 LT |
825 | } |
826 | return -1; | |
827 | } | |
828 | ||
fcfd636a EB |
829 | static int __init find_isa_irq_apic(int irq, int type) |
830 | { | |
831 | int i; | |
832 | ||
833 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 834 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 835 | |
73b2961b | 836 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
837 | (mp_irqs[i].irqtype == type) && |
838 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
839 | break; |
840 | } | |
841 | if (i < mp_irq_entries) { | |
842 | int apic; | |
54168ed7 | 843 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 844 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
845 | return apic; |
846 | } | |
847 | } | |
848 | ||
849 | return -1; | |
850 | } | |
851 | ||
c0a282c2 | 852 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
853 | /* |
854 | * EISA Edge/Level control register, ELCR | |
855 | */ | |
856 | static int EISA_ELCR(unsigned int irq) | |
857 | { | |
b81bb373 | 858 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
859 | unsigned int port = 0x4d0 + (irq >> 3); |
860 | return (inb(port) >> (irq & 7)) & 1; | |
861 | } | |
862 | apic_printk(APIC_VERBOSE, KERN_INFO | |
863 | "Broken MPtable reports ISA irq %d\n", irq); | |
864 | return 0; | |
865 | } | |
54168ed7 | 866 | |
c0a282c2 | 867 | #endif |
1da177e4 | 868 | |
6728801d AS |
869 | /* ISA interrupts are always polarity zero edge triggered, |
870 | * when listed as conforming in the MP table. */ | |
871 | ||
872 | #define default_ISA_trigger(idx) (0) | |
873 | #define default_ISA_polarity(idx) (0) | |
874 | ||
1da177e4 LT |
875 | /* EISA interrupts are always polarity zero and can be edge or level |
876 | * trigger depending on the ELCR value. If an interrupt is listed as | |
877 | * EISA conforming in the MP table, that means its trigger type must | |
878 | * be read in from the ELCR */ | |
879 | ||
c2c21745 | 880 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 881 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
882 | |
883 | /* PCI interrupts are always polarity one level triggered, | |
884 | * when listed as conforming in the MP table. */ | |
885 | ||
886 | #define default_PCI_trigger(idx) (1) | |
887 | #define default_PCI_polarity(idx) (1) | |
888 | ||
889 | /* MCA interrupts are always polarity zero level triggered, | |
890 | * when listed as conforming in the MP table. */ | |
891 | ||
892 | #define default_MCA_trigger(idx) (1) | |
6728801d | 893 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 894 | |
61fd47e0 | 895 | static int MPBIOS_polarity(int idx) |
1da177e4 | 896 | { |
c2c21745 | 897 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
898 | int polarity; |
899 | ||
900 | /* | |
901 | * Determine IRQ line polarity (high active or low active): | |
902 | */ | |
c2c21745 | 903 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 904 | { |
54168ed7 IM |
905 | case 0: /* conforms, ie. bus-type dependent polarity */ |
906 | if (test_bit(bus, mp_bus_not_pci)) | |
907 | polarity = default_ISA_polarity(idx); | |
908 | else | |
909 | polarity = default_PCI_polarity(idx); | |
910 | break; | |
911 | case 1: /* high active */ | |
912 | { | |
913 | polarity = 0; | |
914 | break; | |
915 | } | |
916 | case 2: /* reserved */ | |
917 | { | |
918 | printk(KERN_WARNING "broken BIOS!!\n"); | |
919 | polarity = 1; | |
920 | break; | |
921 | } | |
922 | case 3: /* low active */ | |
923 | { | |
924 | polarity = 1; | |
925 | break; | |
926 | } | |
927 | default: /* invalid */ | |
928 | { | |
929 | printk(KERN_WARNING "broken BIOS!!\n"); | |
930 | polarity = 1; | |
931 | break; | |
932 | } | |
1da177e4 LT |
933 | } |
934 | return polarity; | |
935 | } | |
936 | ||
937 | static int MPBIOS_trigger(int idx) | |
938 | { | |
c2c21745 | 939 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
940 | int trigger; |
941 | ||
942 | /* | |
943 | * Determine IRQ trigger mode (edge or level sensitive): | |
944 | */ | |
c2c21745 | 945 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 946 | { |
54168ed7 IM |
947 | case 0: /* conforms, ie. bus-type dependent */ |
948 | if (test_bit(bus, mp_bus_not_pci)) | |
949 | trigger = default_ISA_trigger(idx); | |
950 | else | |
951 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 952 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
953 | switch (mp_bus_id_to_type[bus]) { |
954 | case MP_BUS_ISA: /* ISA pin */ | |
955 | { | |
956 | /* set before the switch */ | |
957 | break; | |
958 | } | |
959 | case MP_BUS_EISA: /* EISA pin */ | |
960 | { | |
961 | trigger = default_EISA_trigger(idx); | |
962 | break; | |
963 | } | |
964 | case MP_BUS_PCI: /* PCI pin */ | |
965 | { | |
966 | /* set before the switch */ | |
967 | break; | |
968 | } | |
969 | case MP_BUS_MCA: /* MCA pin */ | |
970 | { | |
971 | trigger = default_MCA_trigger(idx); | |
972 | break; | |
973 | } | |
974 | default: | |
975 | { | |
976 | printk(KERN_WARNING "broken BIOS!!\n"); | |
977 | trigger = 1; | |
978 | break; | |
979 | } | |
980 | } | |
981 | #endif | |
1da177e4 | 982 | break; |
54168ed7 | 983 | case 1: /* edge */ |
1da177e4 | 984 | { |
54168ed7 | 985 | trigger = 0; |
1da177e4 LT |
986 | break; |
987 | } | |
54168ed7 | 988 | case 2: /* reserved */ |
1da177e4 | 989 | { |
54168ed7 IM |
990 | printk(KERN_WARNING "broken BIOS!!\n"); |
991 | trigger = 1; | |
1da177e4 LT |
992 | break; |
993 | } | |
54168ed7 | 994 | case 3: /* level */ |
1da177e4 | 995 | { |
54168ed7 | 996 | trigger = 1; |
1da177e4 LT |
997 | break; |
998 | } | |
54168ed7 | 999 | default: /* invalid */ |
1da177e4 LT |
1000 | { |
1001 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1002 | trigger = 0; |
1da177e4 LT |
1003 | break; |
1004 | } | |
1005 | } | |
1006 | return trigger; | |
1007 | } | |
1008 | ||
1009 | static inline int irq_polarity(int idx) | |
1010 | { | |
1011 | return MPBIOS_polarity(idx); | |
1012 | } | |
1013 | ||
1014 | static inline int irq_trigger(int idx) | |
1015 | { | |
1016 | return MPBIOS_trigger(idx); | |
1017 | } | |
1018 | ||
1019 | static int pin_2_irq(int idx, int apic, int pin) | |
1020 | { | |
d464207c | 1021 | int irq; |
c2c21745 | 1022 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1023 | |
1024 | /* | |
1025 | * Debugging check, we are in big trouble if this message pops up! | |
1026 | */ | |
c2c21745 | 1027 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1028 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1029 | ||
54168ed7 | 1030 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1031 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1032 | } else { |
d464207c | 1033 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
1034 | |
1035 | if (gsi >= NR_IRQS_LEGACY) | |
1036 | irq = gsi; | |
1037 | else | |
a4384df3 | 1038 | irq = gsi_top + gsi; |
1da177e4 LT |
1039 | } |
1040 | ||
54168ed7 | 1041 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1042 | /* |
1043 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1044 | */ | |
1045 | if ((pin >= 16) && (pin <= 23)) { | |
1046 | if (pirq_entries[pin-16] != -1) { | |
1047 | if (!pirq_entries[pin-16]) { | |
1048 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1049 | "disabling PIRQ%d\n", pin-16); | |
1050 | } else { | |
1051 | irq = pirq_entries[pin-16]; | |
1052 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1053 | "using PIRQ%d -> IRQ %d\n", | |
1054 | pin-16, irq); | |
1055 | } | |
1056 | } | |
1057 | } | |
54168ed7 IM |
1058 | #endif |
1059 | ||
1da177e4 LT |
1060 | return irq; |
1061 | } | |
1062 | ||
e20c06fd YL |
1063 | /* |
1064 | * Find a specific PCI IRQ entry. | |
1065 | * Not an __init, possibly needed by modules | |
1066 | */ | |
1067 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1068 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1069 | { |
1070 | int apic, i, best_guess = -1; | |
1071 | ||
1072 | apic_printk(APIC_DEBUG, | |
1073 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1074 | bus, slot, pin); | |
1075 | if (test_bit(bus, mp_bus_not_pci)) { | |
1076 | apic_printk(APIC_VERBOSE, | |
1077 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1078 | return -1; | |
1079 | } | |
1080 | for (i = 0; i < mp_irq_entries; i++) { | |
1081 | int lbus = mp_irqs[i].srcbus; | |
1082 | ||
1083 | for (apic = 0; apic < nr_ioapics; apic++) | |
1084 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1085 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1086 | break; | |
1087 | ||
1088 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1089 | !mp_irqs[i].irqtype && | |
1090 | (bus == lbus) && | |
1091 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1092 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1093 | ||
1094 | if (!(apic || IO_APIC_IRQ(irq))) | |
1095 | continue; | |
1096 | ||
1097 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1098 | set_io_apic_irq_attr(irq_attr, apic, |
1099 | mp_irqs[i].dstirq, | |
1100 | irq_trigger(i), | |
1101 | irq_polarity(i)); | |
e20c06fd YL |
1102 | return irq; |
1103 | } | |
1104 | /* | |
1105 | * Use the first all-but-pin matching entry as a | |
1106 | * best-guess fuzzy result for broken mptables. | |
1107 | */ | |
1108 | if (best_guess < 0) { | |
e5198075 YL |
1109 | set_io_apic_irq_attr(irq_attr, apic, |
1110 | mp_irqs[i].dstirq, | |
1111 | irq_trigger(i), | |
1112 | irq_polarity(i)); | |
e20c06fd YL |
1113 | best_guess = irq; |
1114 | } | |
1115 | } | |
1116 | } | |
1117 | return best_guess; | |
1118 | } | |
1119 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1120 | ||
497c9a19 YL |
1121 | void lock_vector_lock(void) |
1122 | { | |
1123 | /* Used to the online set of cpus does not change | |
1124 | * during assign_irq_vector. | |
1125 | */ | |
dade7716 | 1126 | raw_spin_lock(&vector_lock); |
497c9a19 | 1127 | } |
1da177e4 | 1128 | |
497c9a19 | 1129 | void unlock_vector_lock(void) |
1da177e4 | 1130 | { |
dade7716 | 1131 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1132 | } |
1da177e4 | 1133 | |
e7986739 MT |
1134 | static int |
1135 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1136 | { |
047c8fdb YL |
1137 | /* |
1138 | * NOTE! The local APIC isn't very good at handling | |
1139 | * multiple interrupts at the same interrupt level. | |
1140 | * As the interrupt level is determined by taking the | |
1141 | * vector number and shifting that right by 4, we | |
1142 | * want to spread these out a bit so that they don't | |
1143 | * all fall in the same interrupt level. | |
1144 | * | |
1145 | * Also, we've got to be careful not to trash gate | |
1146 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1147 | */ | |
6579b474 | 1148 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1149 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1150 | unsigned int old_vector; |
22f65d31 MT |
1151 | int cpu, err; |
1152 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1153 | |
23359a88 | 1154 | if (cfg->move_in_progress) |
54168ed7 | 1155 | return -EBUSY; |
0a1ad60d | 1156 | |
22f65d31 MT |
1157 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1158 | return -ENOMEM; | |
ace80ab7 | 1159 | |
54168ed7 IM |
1160 | old_vector = cfg->vector; |
1161 | if (old_vector) { | |
22f65d31 MT |
1162 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1163 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1164 | if (!cpumask_empty(tmp_mask)) { | |
1165 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1166 | return 0; |
22f65d31 | 1167 | } |
54168ed7 | 1168 | } |
497c9a19 | 1169 | |
e7986739 | 1170 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1171 | err = -ENOSPC; |
1172 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1173 | int new_cpu; |
1174 | int vector, offset; | |
497c9a19 | 1175 | |
e2d40b18 | 1176 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1177 | |
54168ed7 IM |
1178 | vector = current_vector; |
1179 | offset = current_offset; | |
497c9a19 | 1180 | next: |
54168ed7 IM |
1181 | vector += 8; |
1182 | if (vector >= first_system_vector) { | |
e7986739 | 1183 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1184 | offset = (offset + 1) % 8; |
6579b474 | 1185 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1186 | } |
1187 | if (unlikely(current_vector == vector)) | |
1188 | continue; | |
b77b881f YL |
1189 | |
1190 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1191 | goto next; |
b77b881f | 1192 | |
22f65d31 | 1193 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1194 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1195 | goto next; | |
1196 | /* Found one! */ | |
1197 | current_vector = vector; | |
1198 | current_offset = offset; | |
1199 | if (old_vector) { | |
1200 | cfg->move_in_progress = 1; | |
22f65d31 | 1201 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1202 | } |
22f65d31 | 1203 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1204 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1205 | cfg->vector = vector; | |
22f65d31 MT |
1206 | cpumask_copy(cfg->domain, tmp_mask); |
1207 | err = 0; | |
1208 | break; | |
54168ed7 | 1209 | } |
22f65d31 MT |
1210 | free_cpumask_var(tmp_mask); |
1211 | return err; | |
497c9a19 YL |
1212 | } |
1213 | ||
9338ad6f | 1214 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1215 | { |
1216 | int err; | |
ace80ab7 | 1217 | unsigned long flags; |
ace80ab7 | 1218 | |
dade7716 | 1219 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1220 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1221 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1222 | return err; |
1223 | } | |
1224 | ||
3145e941 | 1225 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1226 | { |
497c9a19 YL |
1227 | int cpu, vector; |
1228 | ||
497c9a19 YL |
1229 | BUG_ON(!cfg->vector); |
1230 | ||
1231 | vector = cfg->vector; | |
22f65d31 | 1232 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1233 | per_cpu(vector_irq, cpu)[vector] = -1; |
1234 | ||
1235 | cfg->vector = 0; | |
22f65d31 | 1236 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1237 | |
1238 | if (likely(!cfg->move_in_progress)) | |
1239 | return; | |
22f65d31 | 1240 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1241 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1242 | vector++) { | |
1243 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1244 | continue; | |
1245 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1246 | break; | |
1247 | } | |
1248 | } | |
1249 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1250 | } |
1251 | ||
1252 | void __setup_vector_irq(int cpu) | |
1253 | { | |
1254 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1255 | int irq, vector; |
1256 | struct irq_cfg *cfg; | |
0b8f1efa | 1257 | struct irq_desc *desc; |
497c9a19 | 1258 | |
9d133e5d SS |
1259 | /* |
1260 | * vector_lock will make sure that we don't run into irq vector | |
1261 | * assignments that might be happening on another cpu in parallel, | |
1262 | * while we setup our initial vector to irq mappings. | |
1263 | */ | |
dade7716 | 1264 | raw_spin_lock(&vector_lock); |
497c9a19 | 1265 | /* Mark the inuse vectors */ |
0b8f1efa | 1266 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1267 | cfg = desc->chip_data; |
36e9e1ea SS |
1268 | |
1269 | /* | |
1270 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1271 | * will be part of the irq_cfg's domain. | |
1272 | */ | |
1273 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1274 | cpumask_set_cpu(cpu, cfg->domain); | |
1275 | ||
22f65d31 | 1276 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1277 | continue; |
1278 | vector = cfg->vector; | |
497c9a19 YL |
1279 | per_cpu(vector_irq, cpu)[vector] = irq; |
1280 | } | |
1281 | /* Mark the free vectors */ | |
1282 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1283 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1284 | if (irq < 0) | |
1285 | continue; | |
1286 | ||
1287 | cfg = irq_cfg(irq); | |
22f65d31 | 1288 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1289 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1290 | } |
dade7716 | 1291 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1292 | } |
3fde6900 | 1293 | |
f5b9ed7a | 1294 | static struct irq_chip ioapic_chip; |
54168ed7 | 1295 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1296 | |
54168ed7 IM |
1297 | #define IOAPIC_AUTO -1 |
1298 | #define IOAPIC_EDGE 0 | |
1299 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1300 | |
047c8fdb | 1301 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1302 | static inline int IO_APIC_irq_trigger(int irq) |
1303 | { | |
d6c88a50 | 1304 | int apic, idx, pin; |
1d025192 | 1305 | |
d6c88a50 TG |
1306 | for (apic = 0; apic < nr_ioapics; apic++) { |
1307 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1308 | idx = find_irq_entry(apic, pin, mp_INT); | |
1309 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1310 | return irq_trigger(idx); | |
1311 | } | |
1312 | } | |
1313 | /* | |
54168ed7 IM |
1314 | * nonexistent IRQs are edge default |
1315 | */ | |
d6c88a50 | 1316 | return 0; |
1d025192 | 1317 | } |
047c8fdb YL |
1318 | #else |
1319 | static inline int IO_APIC_irq_trigger(int irq) | |
1320 | { | |
54168ed7 | 1321 | return 1; |
047c8fdb YL |
1322 | } |
1323 | #endif | |
1d025192 | 1324 | |
3145e941 | 1325 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1326 | { |
199751d7 | 1327 | |
6ebcc00e | 1328 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1329 | trigger == IOAPIC_LEVEL) |
08678b08 | 1330 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1331 | else |
1332 | desc->status &= ~IRQ_LEVEL; | |
1333 | ||
54168ed7 IM |
1334 | if (irq_remapped(irq)) { |
1335 | desc->status |= IRQ_MOVE_PCNTXT; | |
1336 | if (trigger) | |
1337 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1338 | handle_fasteoi_irq, | |
1339 | "fasteoi"); | |
1340 | else | |
1341 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1342 | handle_edge_irq, "edge"); | |
1343 | return; | |
1344 | } | |
29b61be6 | 1345 | |
047c8fdb YL |
1346 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1347 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1348 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1349 | handle_fasteoi_irq, |
1350 | "fasteoi"); | |
047c8fdb | 1351 | else |
a460e745 | 1352 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1353 | handle_edge_irq, "edge"); |
1da177e4 LT |
1354 | } |
1355 | ||
ca97ab90 JF |
1356 | int setup_ioapic_entry(int apic_id, int irq, |
1357 | struct IO_APIC_route_entry *entry, | |
1358 | unsigned int destination, int trigger, | |
0280f7c4 | 1359 | int polarity, int vector, int pin) |
1da177e4 | 1360 | { |
497c9a19 YL |
1361 | /* |
1362 | * add it to the IO-APIC irq-routing table: | |
1363 | */ | |
1364 | memset(entry,0,sizeof(*entry)); | |
1365 | ||
54168ed7 | 1366 | if (intr_remapping_enabled) { |
c8d46cf0 | 1367 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1368 | struct irte irte; |
1369 | struct IR_IO_APIC_route_entry *ir_entry = | |
1370 | (struct IR_IO_APIC_route_entry *) entry; | |
1371 | int index; | |
1372 | ||
1373 | if (!iommu) | |
c8d46cf0 | 1374 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1375 | |
1376 | index = alloc_irte(iommu, irq, 1); | |
1377 | if (index < 0) | |
c8d46cf0 | 1378 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1379 | |
1380 | memset(&irte, 0, sizeof(irte)); | |
1381 | ||
1382 | irte.present = 1; | |
9b5bc8dc | 1383 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1384 | /* |
1385 | * Trigger mode in the IRTE will always be edge, and the | |
1386 | * actual level or edge trigger will be setup in the IO-APIC | |
1387 | * RTE. This will help simplify level triggered irq migration. | |
1388 | * For more details, see the comments above explainig IO-APIC | |
1389 | * irq migration in the presence of interrupt-remapping. | |
1390 | */ | |
1391 | irte.trigger_mode = 0; | |
9b5bc8dc | 1392 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1393 | irte.vector = vector; |
1394 | irte.dest_id = IRTE_DEST(destination); | |
1395 | ||
f007e99c WH |
1396 | /* Set source-id of interrupt request */ |
1397 | set_ioapic_sid(&irte, apic_id); | |
1398 | ||
54168ed7 IM |
1399 | modify_irte(irq, &irte); |
1400 | ||
1401 | ir_entry->index2 = (index >> 15) & 0x1; | |
1402 | ir_entry->zero = 0; | |
1403 | ir_entry->format = 1; | |
1404 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1405 | /* |
1406 | * IO-APIC RTE will be configured with virtual vector. | |
1407 | * irq handler will do the explicit EOI to the io-apic. | |
1408 | */ | |
1409 | ir_entry->vector = pin; | |
29b61be6 | 1410 | } else { |
9b5bc8dc IM |
1411 | entry->delivery_mode = apic->irq_delivery_mode; |
1412 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1413 | entry->dest = destination; |
0280f7c4 | 1414 | entry->vector = vector; |
54168ed7 | 1415 | } |
497c9a19 | 1416 | |
54168ed7 | 1417 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1418 | entry->trigger = trigger; |
1419 | entry->polarity = polarity; | |
497c9a19 YL |
1420 | |
1421 | /* Mask level triggered irqs. | |
1422 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1423 | */ | |
1424 | if (trigger) | |
1425 | entry->mask = 1; | |
497c9a19 YL |
1426 | return 0; |
1427 | } | |
1428 | ||
c8d46cf0 | 1429 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1430 | int trigger, int polarity) |
497c9a19 YL |
1431 | { |
1432 | struct irq_cfg *cfg; | |
1da177e4 | 1433 | struct IO_APIC_route_entry entry; |
22f65d31 | 1434 | unsigned int dest; |
497c9a19 YL |
1435 | |
1436 | if (!IO_APIC_IRQ(irq)) | |
1437 | return; | |
1438 | ||
3145e941 | 1439 | cfg = desc->chip_data; |
497c9a19 | 1440 | |
69c89efb SS |
1441 | /* |
1442 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1443 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1444 | * the cfg->domain. | |
1445 | */ | |
28c6a0ba | 1446 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1447 | apic->vector_allocation_domain(0, cfg->domain); |
1448 | ||
fe402e1f | 1449 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1450 | return; |
1451 | ||
debccb3e | 1452 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1453 | |
1454 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1455 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1456 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1457 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1458 | irq, trigger, polarity); |
1459 | ||
1460 | ||
c8d46cf0 | 1461 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1462 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1463 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1464 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1465 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1466 | return; |
1467 | } | |
1468 | ||
3145e941 | 1469 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 JP |
1470 | if (irq < legacy_pic->nr_legacy_irqs) |
1471 | legacy_pic->chip->mask(irq); | |
497c9a19 | 1472 | |
c8d46cf0 | 1473 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1474 | } |
1475 | ||
b9c61b70 YL |
1476 | static struct { |
1477 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1478 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1479 | ||
497c9a19 YL |
1480 | static void __init setup_IO_APIC_irqs(void) |
1481 | { | |
fad53995 | 1482 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1483 | int notcon = 0; |
0b8f1efa | 1484 | struct irq_desc *desc; |
3145e941 | 1485 | struct irq_cfg *cfg; |
85ac16d0 | 1486 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1487 | |
1488 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1489 | ||
fad53995 | 1490 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1491 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1492 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1493 | if (idx == -1) { | |
1494 | if (!notcon) { | |
1495 | notcon = 1; | |
1496 | apic_printk(APIC_VERBOSE, | |
1497 | KERN_DEBUG " %d-%d", | |
1498 | mp_ioapics[apic_id].apicid, pin); | |
1499 | } else | |
1500 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1501 | mp_ioapics[apic_id].apicid, pin); | |
1502 | continue; | |
1503 | } | |
1504 | if (notcon) { | |
1505 | apic_printk(APIC_VERBOSE, | |
1506 | " (apicid-pin) not connected\n"); | |
1507 | notcon = 0; | |
1508 | } | |
33a201fa | 1509 | |
b9c61b70 | 1510 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1511 | |
fad53995 EB |
1512 | if ((apic_id > 0) && (irq > 16)) |
1513 | continue; | |
1514 | ||
b9c61b70 YL |
1515 | /* |
1516 | * Skip the timer IRQ if there's a quirk handler | |
1517 | * installed and if it returns 1: | |
1518 | */ | |
1519 | if (apic->multi_timer_check && | |
1520 | apic->multi_timer_check(apic_id, irq)) | |
1521 | continue; | |
36062448 | 1522 | |
b9c61b70 YL |
1523 | desc = irq_to_desc_alloc_node(irq, node); |
1524 | if (!desc) { | |
1525 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1526 | continue; | |
3c2cbd24 | 1527 | } |
b9c61b70 YL |
1528 | cfg = desc->chip_data; |
1529 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
4c6f18fc YL |
1530 | /* |
1531 | * don't mark it in pin_programmed, so later acpi could | |
1532 | * set it correctly when irq < 16 | |
1533 | */ | |
b9c61b70 YL |
1534 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1535 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1536 | } |
1537 | ||
3c2cbd24 CG |
1538 | if (notcon) |
1539 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1540 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1541 | } |
1542 | ||
18dce6ba YL |
1543 | /* |
1544 | * for the gsit that is not in first ioapic | |
1545 | * but could not use acpi_register_gsi() | |
1546 | * like some special sci in IBM x3330 | |
1547 | */ | |
1548 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1549 | { | |
1550 | int apic_id = 0, pin, idx, irq; | |
1551 | int node = cpu_to_node(boot_cpu_id); | |
1552 | struct irq_desc *desc; | |
1553 | struct irq_cfg *cfg; | |
1554 | ||
1555 | /* | |
1556 | * Convert 'gsi' to 'ioapic.pin'. | |
1557 | */ | |
1558 | apic_id = mp_find_ioapic(gsi); | |
1559 | if (apic_id < 0) | |
1560 | return; | |
1561 | ||
1562 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1563 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1564 | if (idx == -1) | |
1565 | return; | |
1566 | ||
1567 | irq = pin_2_irq(idx, apic_id, pin); | |
1568 | #ifdef CONFIG_SPARSE_IRQ | |
1569 | desc = irq_to_desc(irq); | |
1570 | if (desc) | |
1571 | return; | |
1572 | #endif | |
1573 | desc = irq_to_desc_alloc_node(irq, node); | |
1574 | if (!desc) { | |
1575 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1576 | return; | |
1577 | } | |
1578 | ||
1579 | cfg = desc->chip_data; | |
1580 | add_pin_to_irq_node(cfg, node, apic_id, pin); | |
1581 | ||
1582 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1583 | pr_debug("Pin %d-%d already programmed\n", | |
1584 | mp_ioapics[apic_id].apicid, pin); | |
1585 | return; | |
1586 | } | |
1587 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1588 | ||
1589 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1590 | irq_trigger(idx), irq_polarity(idx)); | |
1591 | } | |
1592 | ||
1da177e4 | 1593 | /* |
f7633ce5 | 1594 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1595 | */ |
c8d46cf0 | 1596 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1597 | int vector) |
1da177e4 LT |
1598 | { |
1599 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1600 | |
54168ed7 IM |
1601 | if (intr_remapping_enabled) |
1602 | return; | |
54168ed7 | 1603 | |
36062448 | 1604 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1605 | |
1606 | /* | |
1607 | * We use logical delivery to get the timer IRQ | |
1608 | * to the first CPU. | |
1609 | */ | |
9b5bc8dc | 1610 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1611 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1612 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1613 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1614 | entry.polarity = 0; |
1615 | entry.trigger = 0; | |
1616 | entry.vector = vector; | |
1617 | ||
1618 | /* | |
1619 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1620 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1621 | */ |
54168ed7 | 1622 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1623 | |
1624 | /* | |
1625 | * Add it to the IO-APIC irq-routing table: | |
1626 | */ | |
c8d46cf0 | 1627 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1628 | } |
1629 | ||
32f71aff MR |
1630 | |
1631 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1632 | { |
1633 | int apic, i; | |
1634 | union IO_APIC_reg_00 reg_00; | |
1635 | union IO_APIC_reg_01 reg_01; | |
1636 | union IO_APIC_reg_02 reg_02; | |
1637 | union IO_APIC_reg_03 reg_03; | |
1638 | unsigned long flags; | |
0f978f45 | 1639 | struct irq_cfg *cfg; |
0b8f1efa | 1640 | struct irq_desc *desc; |
8f09cd20 | 1641 | unsigned int irq; |
1da177e4 | 1642 | |
36062448 | 1643 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1644 | for (i = 0; i < nr_ioapics; i++) |
1645 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1646 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1647 | |
1648 | /* | |
1649 | * We are a bit conservative about what we expect. We have to | |
1650 | * know about every hardware change ASAP. | |
1651 | */ | |
1652 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1653 | ||
1654 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1655 | ||
dade7716 | 1656 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1657 | reg_00.raw = io_apic_read(apic, 0); |
1658 | reg_01.raw = io_apic_read(apic, 1); | |
1659 | if (reg_01.bits.version >= 0x10) | |
1660 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1661 | if (reg_01.bits.version >= 0x20) |
1662 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1663 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1664 | |
54168ed7 | 1665 | printk("\n"); |
b5ba7e6d | 1666 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1667 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1668 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1669 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1670 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1671 | |
54168ed7 | 1672 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1673 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1674 | |
1675 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1676 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1677 | |
1678 | /* | |
1679 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1680 | * but the value of reg_02 is read as the previous read register | |
1681 | * value, so ignore it if reg_02 == reg_01. | |
1682 | */ | |
1683 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1684 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1685 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1686 | } |
1687 | ||
1688 | /* | |
1689 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1690 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1691 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1692 | */ | |
1693 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1694 | reg_03.raw != reg_01.raw) { | |
1695 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1696 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1697 | } |
1698 | ||
1699 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1700 | ||
d83e94ac | 1701 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1702 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1703 | |
1704 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1705 | struct IO_APIC_route_entry entry; | |
1706 | ||
cf4c6a2f | 1707 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1708 | |
54168ed7 IM |
1709 | printk(KERN_DEBUG " %02x %03X ", |
1710 | i, | |
1711 | entry.dest | |
1712 | ); | |
1da177e4 LT |
1713 | |
1714 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1715 | entry.mask, | |
1716 | entry.trigger, | |
1717 | entry.irr, | |
1718 | entry.polarity, | |
1719 | entry.delivery_status, | |
1720 | entry.dest_mode, | |
1721 | entry.delivery_mode, | |
1722 | entry.vector | |
1723 | ); | |
1724 | } | |
1725 | } | |
1da177e4 | 1726 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1727 | for_each_irq_desc(irq, desc) { |
1728 | struct irq_pin_list *entry; | |
1729 | ||
0b8f1efa | 1730 | cfg = desc->chip_data; |
05e40760 DK |
1731 | if (!cfg) |
1732 | continue; | |
0b8f1efa | 1733 | entry = cfg->irq_2_pin; |
0f978f45 | 1734 | if (!entry) |
1da177e4 | 1735 | continue; |
8f09cd20 | 1736 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1737 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1738 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1739 | printk("\n"); |
1740 | } | |
1741 | ||
1742 | printk(KERN_INFO ".................................... done.\n"); | |
1743 | ||
1744 | return; | |
1745 | } | |
1746 | ||
251e1e44 | 1747 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1748 | { |
251e1e44 | 1749 | int i; |
1da177e4 | 1750 | |
251e1e44 IM |
1751 | printk(KERN_DEBUG); |
1752 | ||
1753 | for (i = 0; i < 8; i++) | |
1754 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1755 | ||
1756 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1757 | } |
1758 | ||
32f71aff | 1759 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1760 | { |
97a52714 | 1761 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1762 | u64 icr; |
1da177e4 | 1763 | |
251e1e44 | 1764 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1765 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1766 | v = apic_read(APIC_ID); |
54168ed7 | 1767 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1768 | v = apic_read(APIC_LVR); |
1769 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1770 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1771 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1772 | |
1773 | v = apic_read(APIC_TASKPRI); | |
1774 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1775 | ||
54168ed7 | 1776 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1777 | if (!APIC_XAPIC(ver)) { |
1778 | v = apic_read(APIC_ARBPRI); | |
1779 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1780 | v & APIC_ARBPRI_MASK); | |
1781 | } | |
1da177e4 LT |
1782 | v = apic_read(APIC_PROCPRI); |
1783 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1784 | } | |
1785 | ||
a11b5abe YL |
1786 | /* |
1787 | * Remote read supported only in the 82489DX and local APIC for | |
1788 | * Pentium processors. | |
1789 | */ | |
1790 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1791 | v = apic_read(APIC_RRR); | |
1792 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1793 | } | |
1794 | ||
1da177e4 LT |
1795 | v = apic_read(APIC_LDR); |
1796 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1797 | if (!x2apic_enabled()) { |
1798 | v = apic_read(APIC_DFR); | |
1799 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1800 | } | |
1da177e4 LT |
1801 | v = apic_read(APIC_SPIV); |
1802 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1803 | ||
1804 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1805 | print_APIC_field(APIC_ISR); |
1da177e4 | 1806 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1807 | print_APIC_field(APIC_TMR); |
1da177e4 | 1808 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1809 | print_APIC_field(APIC_IRR); |
1da177e4 | 1810 | |
54168ed7 IM |
1811 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1812 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1813 | apic_write(APIC_ESR, 0); |
54168ed7 | 1814 | |
1da177e4 LT |
1815 | v = apic_read(APIC_ESR); |
1816 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1817 | } | |
1818 | ||
7ab6af7a | 1819 | icr = apic_icr_read(); |
0c425cec IM |
1820 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1821 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1822 | |
1823 | v = apic_read(APIC_LVTT); | |
1824 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1825 | ||
1826 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1827 | v = apic_read(APIC_LVTPC); | |
1828 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1829 | } | |
1830 | v = apic_read(APIC_LVT0); | |
1831 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1832 | v = apic_read(APIC_LVT1); | |
1833 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1834 | ||
1835 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1836 | v = apic_read(APIC_LVTERR); | |
1837 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1838 | } | |
1839 | ||
1840 | v = apic_read(APIC_TMICT); | |
1841 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1842 | v = apic_read(APIC_TMCCT); | |
1843 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1844 | v = apic_read(APIC_TDCR); | |
1845 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1846 | |
1847 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1848 | v = apic_read(APIC_EFEAT); | |
1849 | maxlvt = (v >> 16) & 0xff; | |
1850 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1851 | v = apic_read(APIC_ECTRL); | |
1852 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1853 | for (i = 0; i < maxlvt; i++) { | |
1854 | v = apic_read(APIC_EILVTn(i)); | |
1855 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1856 | } | |
1857 | } | |
1da177e4 LT |
1858 | printk("\n"); |
1859 | } | |
1860 | ||
2626eb2b | 1861 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1862 | { |
ffd5aae7 YL |
1863 | int cpu; |
1864 | ||
2626eb2b CG |
1865 | if (!maxcpu) |
1866 | return; | |
1867 | ||
ffd5aae7 | 1868 | preempt_disable(); |
2626eb2b CG |
1869 | for_each_online_cpu(cpu) { |
1870 | if (cpu >= maxcpu) | |
1871 | break; | |
ffd5aae7 | 1872 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1873 | } |
ffd5aae7 | 1874 | preempt_enable(); |
1da177e4 LT |
1875 | } |
1876 | ||
32f71aff | 1877 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1878 | { |
1da177e4 LT |
1879 | unsigned int v; |
1880 | unsigned long flags; | |
1881 | ||
b81bb373 | 1882 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1883 | return; |
1884 | ||
1885 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1886 | ||
5619c280 | 1887 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1888 | |
1889 | v = inb(0xa1) << 8 | inb(0x21); | |
1890 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1891 | ||
1892 | v = inb(0xa0) << 8 | inb(0x20); | |
1893 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1894 | ||
54168ed7 IM |
1895 | outb(0x0b,0xa0); |
1896 | outb(0x0b,0x20); | |
1da177e4 | 1897 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1898 | outb(0x0a,0xa0); |
1899 | outb(0x0a,0x20); | |
1da177e4 | 1900 | |
5619c280 | 1901 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1902 | |
1903 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1904 | ||
1905 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1906 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1907 | } | |
1908 | ||
2626eb2b CG |
1909 | static int __initdata show_lapic = 1; |
1910 | static __init int setup_show_lapic(char *arg) | |
1911 | { | |
1912 | int num = -1; | |
1913 | ||
1914 | if (strcmp(arg, "all") == 0) { | |
1915 | show_lapic = CONFIG_NR_CPUS; | |
1916 | } else { | |
1917 | get_option(&arg, &num); | |
1918 | if (num >= 0) | |
1919 | show_lapic = num; | |
1920 | } | |
1921 | ||
1922 | return 1; | |
1923 | } | |
1924 | __setup("show_lapic=", setup_show_lapic); | |
1925 | ||
1926 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1927 | { |
2626eb2b CG |
1928 | if (apic_verbosity == APIC_QUIET) |
1929 | return 0; | |
1930 | ||
32f71aff | 1931 | print_PIC(); |
4797f6b0 YL |
1932 | |
1933 | /* don't print out if apic is not there */ | |
8312136f | 1934 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1935 | return 0; |
1936 | ||
2626eb2b | 1937 | print_local_APICs(show_lapic); |
32f71aff MR |
1938 | print_IO_APIC(); |
1939 | ||
1940 | return 0; | |
1941 | } | |
1942 | ||
2626eb2b | 1943 | fs_initcall(print_ICs); |
32f71aff | 1944 | |
1da177e4 | 1945 | |
efa2559f YL |
1946 | /* Where if anywhere is the i8259 connect in external int mode */ |
1947 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1948 | ||
54168ed7 | 1949 | void __init enable_IO_APIC(void) |
1da177e4 | 1950 | { |
fcfd636a | 1951 | int i8259_apic, i8259_pin; |
54168ed7 | 1952 | int apic; |
bc07844a | 1953 | |
b81bb373 | 1954 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1955 | return; |
1956 | ||
54168ed7 | 1957 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1958 | int pin; |
1959 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1960 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1961 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1962 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1963 | |
fcfd636a EB |
1964 | /* If the interrupt line is enabled and in ExtInt mode |
1965 | * I have found the pin where the i8259 is connected. | |
1966 | */ | |
1967 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1968 | ioapic_i8259.apic = apic; | |
1969 | ioapic_i8259.pin = pin; | |
1970 | goto found_i8259; | |
1971 | } | |
1972 | } | |
1973 | } | |
1974 | found_i8259: | |
1975 | /* Look to see what if the MP table has reported the ExtINT */ | |
1976 | /* If we could not find the appropriate pin by looking at the ioapic | |
1977 | * the i8259 probably is not connected the ioapic but give the | |
1978 | * mptable a chance anyway. | |
1979 | */ | |
1980 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1981 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1982 | /* Trust the MP table if nothing is setup in the hardware */ | |
1983 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1984 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1985 | ioapic_i8259.pin = i8259_pin; | |
1986 | ioapic_i8259.apic = i8259_apic; | |
1987 | } | |
1988 | /* Complain if the MP table and the hardware disagree */ | |
1989 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1990 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1991 | { | |
1992 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1993 | } |
1994 | ||
1995 | /* | |
1996 | * Do not trust the IO-APIC being empty at bootup | |
1997 | */ | |
1998 | clear_IO_APIC(); | |
1999 | } | |
2000 | ||
2001 | /* | |
2002 | * Not an __init, needed by the reboot code | |
2003 | */ | |
2004 | void disable_IO_APIC(void) | |
2005 | { | |
2006 | /* | |
2007 | * Clear the IO-APIC before rebooting: | |
2008 | */ | |
2009 | clear_IO_APIC(); | |
2010 | ||
b81bb373 | 2011 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
2012 | return; |
2013 | ||
650927ef | 2014 | /* |
0b968d23 | 2015 | * If the i8259 is routed through an IOAPIC |
650927ef | 2016 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2017 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
2018 | * |
2019 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2020 | * as virtual wire B is little complex (need to configure both | |
2021 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2022 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2023 | */ |
7c6d9f97 | 2024 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2025 | struct IO_APIC_route_entry entry; |
650927ef EB |
2026 | |
2027 | memset(&entry, 0, sizeof(entry)); | |
2028 | entry.mask = 0; /* Enabled */ | |
2029 | entry.trigger = 0; /* Edge */ | |
2030 | entry.irr = 0; | |
2031 | entry.polarity = 0; /* High */ | |
2032 | entry.delivery_status = 0; | |
2033 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2034 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2035 | entry.vector = 0; |
54168ed7 | 2036 | entry.dest = read_apic_id(); |
650927ef EB |
2037 | |
2038 | /* | |
2039 | * Add it to the IO-APIC irq-routing table: | |
2040 | */ | |
cf4c6a2f | 2041 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2042 | } |
54168ed7 | 2043 | |
7c6d9f97 SS |
2044 | /* |
2045 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2046 | */ | |
8312136f | 2047 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2048 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2049 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2050 | } |
2051 | ||
54168ed7 | 2052 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2053 | /* |
2054 | * function to set the IO-APIC physical IDs based on the | |
2055 | * values stored in the MPC table. | |
2056 | * | |
2057 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2058 | */ | |
2059 | ||
de934103 | 2060 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2061 | { |
2062 | union IO_APIC_reg_00 reg_00; | |
2063 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2064 | int apic_id; |
1da177e4 LT |
2065 | int i; |
2066 | unsigned char old_id; | |
2067 | unsigned long flags; | |
2068 | ||
de934103 | 2069 | if (acpi_ioapic) |
d49c4288 | 2070 | return; |
ca05fea6 NP |
2071 | /* |
2072 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2073 | * no meaning without the serial APIC bus. | |
2074 | */ | |
7c5c1e42 SL |
2075 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2076 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2077 | return; |
1da177e4 LT |
2078 | /* |
2079 | * This is broken; anything with a real cpu count has to | |
2080 | * circumvent this idiocy regardless. | |
2081 | */ | |
7abc0753 | 2082 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2083 | |
2084 | /* | |
2085 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2086 | */ | |
c8d46cf0 | 2087 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2088 | |
2089 | /* Read the register 0 value */ | |
dade7716 | 2090 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2091 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2092 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2093 | |
c8d46cf0 | 2094 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2095 | |
c8d46cf0 | 2096 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2097 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2098 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2099 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2100 | reg_00.bits.ID); | |
c8d46cf0 | 2101 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2102 | } |
2103 | ||
1da177e4 LT |
2104 | /* |
2105 | * Sanity check, is the ID really free? Every APIC in a | |
2106 | * system must have a unique ID or we get lots of nice | |
2107 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2108 | */ | |
7abc0753 | 2109 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2110 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2111 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2112 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2113 | for (i = 0; i < get_physical_broadcast(); i++) |
2114 | if (!physid_isset(i, phys_id_present_map)) | |
2115 | break; | |
2116 | if (i >= get_physical_broadcast()) | |
2117 | panic("Max APIC ID exceeded!\n"); | |
2118 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2119 | i); | |
2120 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2121 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2122 | } else { |
2123 | physid_mask_t tmp; | |
7abc0753 | 2124 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2125 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2126 | "phys_id_present_map\n", | |
c8d46cf0 | 2127 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2128 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2129 | } | |
2130 | ||
2131 | ||
2132 | /* | |
2133 | * We need to adjust the IRQ routing table | |
2134 | * if the ID changed. | |
2135 | */ | |
c8d46cf0 | 2136 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2137 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2138 | if (mp_irqs[i].dstapic == old_id) |
2139 | mp_irqs[i].dstapic | |
c8d46cf0 | 2140 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2141 | |
2142 | /* | |
2143 | * Read the right value from the MPC table and | |
2144 | * write it into the ID register. | |
36062448 | 2145 | */ |
1da177e4 LT |
2146 | apic_printk(APIC_VERBOSE, KERN_INFO |
2147 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2148 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2149 | |
c8d46cf0 | 2150 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2151 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2152 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2153 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2154 | |
2155 | /* | |
2156 | * Sanity check | |
2157 | */ | |
dade7716 | 2158 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2159 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2160 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2161 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2162 | printk("could not set ID!\n"); |
2163 | else | |
2164 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2165 | } | |
2166 | } | |
54168ed7 | 2167 | #endif |
1da177e4 | 2168 | |
7ce0bcfd | 2169 | int no_timer_check __initdata; |
8542b200 ZA |
2170 | |
2171 | static int __init notimercheck(char *s) | |
2172 | { | |
2173 | no_timer_check = 1; | |
2174 | return 1; | |
2175 | } | |
2176 | __setup("no_timer_check", notimercheck); | |
2177 | ||
1da177e4 LT |
2178 | /* |
2179 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2180 | * about the timer IRQ. We do the following to work around the situation: | |
2181 | * | |
2182 | * - timer IRQ defaults to IO-APIC IRQ | |
2183 | * - if this function detects that timer IRQs are defunct, then we fall | |
2184 | * back to ISA timer IRQs | |
2185 | */ | |
f0a7a5c9 | 2186 | static int __init timer_irq_works(void) |
1da177e4 LT |
2187 | { |
2188 | unsigned long t1 = jiffies; | |
4aae0702 | 2189 | unsigned long flags; |
1da177e4 | 2190 | |
8542b200 ZA |
2191 | if (no_timer_check) |
2192 | return 1; | |
2193 | ||
4aae0702 | 2194 | local_save_flags(flags); |
1da177e4 LT |
2195 | local_irq_enable(); |
2196 | /* Let ten ticks pass... */ | |
2197 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2198 | local_irq_restore(flags); |
1da177e4 LT |
2199 | |
2200 | /* | |
2201 | * Expect a few ticks at least, to be sure some possible | |
2202 | * glue logic does not lock up after one or two first | |
2203 | * ticks in a non-ExtINT mode. Also the local APIC | |
2204 | * might have cached one ExtINT interrupt. Finally, at | |
2205 | * least one tick may be lost due to delays. | |
2206 | */ | |
54168ed7 IM |
2207 | |
2208 | /* jiffies wrap? */ | |
1d16b53e | 2209 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2210 | return 1; |
1da177e4 LT |
2211 | return 0; |
2212 | } | |
2213 | ||
2214 | /* | |
2215 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2216 | * number of pending IRQ events unhandled. These cases are very rare, | |
2217 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2218 | * better to do it this way as thus we do not have to be aware of | |
2219 | * 'pending' interrupts in the IRQ path, except at this point. | |
2220 | */ | |
2221 | /* | |
2222 | * Edge triggered needs to resend any interrupt | |
2223 | * that was delayed but this is now handled in the device | |
2224 | * independent code. | |
2225 | */ | |
2226 | ||
2227 | /* | |
2228 | * Starting up a edge-triggered IO-APIC interrupt is | |
2229 | * nasty - we need to make sure that we get the edge. | |
2230 | * If it is already asserted for some reason, we need | |
2231 | * return 1 to indicate that is was pending. | |
2232 | * | |
2233 | * This is not complete - we should be able to fake | |
2234 | * an edge even if it isn't on the 8259A... | |
2235 | */ | |
54168ed7 | 2236 | |
f5b9ed7a | 2237 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2238 | { |
2239 | int was_pending = 0; | |
2240 | unsigned long flags; | |
0b8f1efa | 2241 | struct irq_cfg *cfg; |
1da177e4 | 2242 | |
dade7716 | 2243 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 JP |
2244 | if (irq < legacy_pic->nr_legacy_irqs) { |
2245 | legacy_pic->chip->mask(irq); | |
2246 | if (legacy_pic->irq_pending(irq)) | |
1da177e4 LT |
2247 | was_pending = 1; |
2248 | } | |
0b8f1efa | 2249 | cfg = irq_cfg(irq); |
3145e941 | 2250 | __unmask_IO_APIC_irq(cfg); |
dade7716 | 2251 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2252 | |
2253 | return was_pending; | |
2254 | } | |
2255 | ||
ace80ab7 | 2256 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2257 | { |
54168ed7 IM |
2258 | |
2259 | struct irq_cfg *cfg = irq_cfg(irq); | |
2260 | unsigned long flags; | |
2261 | ||
dade7716 | 2262 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2263 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2264 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2265 | |
2266 | return 1; | |
2267 | } | |
497c9a19 | 2268 | |
54168ed7 IM |
2269 | /* |
2270 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2271 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2272 | * handled with the level-triggered descriptor, but that one has slightly | |
2273 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2274 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2275 | * races. | |
2276 | */ | |
497c9a19 | 2277 | |
54168ed7 | 2278 | #ifdef CONFIG_SMP |
9338ad6f | 2279 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2280 | { |
2281 | cpumask_var_t cleanup_mask; | |
2282 | ||
2283 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2284 | unsigned int i; | |
e85abf8f GH |
2285 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2286 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2287 | } else { | |
2288 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2289 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2290 | free_cpumask_var(cleanup_mask); | |
2291 | } | |
2292 | cfg->move_in_progress = 0; | |
2293 | } | |
2294 | ||
4420471f | 2295 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2296 | { |
2297 | int apic, pin; | |
2298 | struct irq_pin_list *entry; | |
2299 | u8 vector = cfg->vector; | |
2300 | ||
2977fb3f | 2301 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2302 | unsigned int reg; |
2303 | ||
e85abf8f GH |
2304 | apic = entry->apic; |
2305 | pin = entry->pin; | |
2306 | /* | |
2307 | * With interrupt-remapping, destination information comes | |
2308 | * from interrupt-remapping table entry. | |
2309 | */ | |
2310 | if (!irq_remapped(irq)) | |
2311 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2312 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2313 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2314 | reg |= vector; | |
2315 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2316 | } |
2317 | } | |
2318 | ||
2319 | /* | |
2320 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2321 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2322 | * leaves desc->affinity untouched. |
2323 | */ | |
9338ad6f | 2324 | unsigned int |
18374d89 SS |
2325 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2326 | unsigned int *dest_id) | |
e85abf8f GH |
2327 | { |
2328 | struct irq_cfg *cfg; | |
2329 | unsigned int irq; | |
2330 | ||
2331 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2332 | return -1; |
e85abf8f GH |
2333 | |
2334 | irq = desc->irq; | |
2335 | cfg = desc->chip_data; | |
2336 | if (assign_irq_vector(irq, cfg, mask)) | |
18374d89 | 2337 | return -1; |
e85abf8f | 2338 | |
e85abf8f GH |
2339 | cpumask_copy(desc->affinity, mask); |
2340 | ||
18374d89 SS |
2341 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2342 | return 0; | |
e85abf8f GH |
2343 | } |
2344 | ||
4420471f | 2345 | static int |
e85abf8f GH |
2346 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2347 | { | |
2348 | struct irq_cfg *cfg; | |
2349 | unsigned long flags; | |
2350 | unsigned int dest; | |
2351 | unsigned int irq; | |
4420471f | 2352 | int ret = -1; |
e85abf8f GH |
2353 | |
2354 | irq = desc->irq; | |
2355 | cfg = desc->chip_data; | |
2356 | ||
dade7716 | 2357 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2358 | ret = set_desc_affinity(desc, mask, &dest); |
2359 | if (!ret) { | |
e85abf8f GH |
2360 | /* Only the high 8 bits are valid. */ |
2361 | dest = SET_APIC_LOGICAL_ID(dest); | |
2362 | __target_IO_APIC_irq(irq, dest, cfg); | |
2363 | } | |
dade7716 | 2364 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2365 | |
2366 | return ret; | |
e85abf8f GH |
2367 | } |
2368 | ||
4420471f | 2369 | static int |
e85abf8f GH |
2370 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2371 | { | |
2372 | struct irq_desc *desc; | |
2373 | ||
2374 | desc = irq_to_desc(irq); | |
2375 | ||
4420471f | 2376 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2377 | } |
497c9a19 | 2378 | |
54168ed7 | 2379 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2380 | |
54168ed7 IM |
2381 | /* |
2382 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2383 | * | |
0280f7c4 SS |
2384 | * For both level and edge triggered, irq migration is a simple atomic |
2385 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2386 | * |
0280f7c4 SS |
2387 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2388 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2389 | * Real vector that is used for interrupting cpu will be coming from | |
2390 | * the interrupt-remapping table entry. | |
54168ed7 | 2391 | */ |
d5dedd45 | 2392 | static int |
e7986739 | 2393 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2394 | { |
54168ed7 | 2395 | struct irq_cfg *cfg; |
54168ed7 | 2396 | struct irte irte; |
54168ed7 | 2397 | unsigned int dest; |
3145e941 | 2398 | unsigned int irq; |
d5dedd45 | 2399 | int ret = -1; |
497c9a19 | 2400 | |
22f65d31 | 2401 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2402 | return ret; |
497c9a19 | 2403 | |
3145e941 | 2404 | irq = desc->irq; |
54168ed7 | 2405 | if (get_irte(irq, &irte)) |
d5dedd45 | 2406 | return ret; |
497c9a19 | 2407 | |
3145e941 YL |
2408 | cfg = desc->chip_data; |
2409 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2410 | return ret; |
54168ed7 | 2411 | |
debccb3e | 2412 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2413 | |
54168ed7 IM |
2414 | irte.vector = cfg->vector; |
2415 | irte.dest_id = IRTE_DEST(dest); | |
2416 | ||
2417 | /* | |
2418 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2419 | */ | |
2420 | modify_irte(irq, &irte); | |
2421 | ||
22f65d31 MT |
2422 | if (cfg->move_in_progress) |
2423 | send_cleanup_vector(cfg); | |
54168ed7 | 2424 | |
7f7ace0c | 2425 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2426 | |
2427 | return 0; | |
54168ed7 IM |
2428 | } |
2429 | ||
54168ed7 IM |
2430 | /* |
2431 | * Migrates the IRQ destination in the process context. | |
2432 | */ | |
d5dedd45 | 2433 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2434 | const struct cpumask *mask) |
54168ed7 | 2435 | { |
d5dedd45 | 2436 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2437 | } |
d5dedd45 | 2438 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2439 | const struct cpumask *mask) |
3145e941 YL |
2440 | { |
2441 | struct irq_desc *desc = irq_to_desc(irq); | |
2442 | ||
d5dedd45 | 2443 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2444 | } |
29b61be6 | 2445 | #else |
d5dedd45 | 2446 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2447 | const struct cpumask *mask) |
2448 | { | |
d5dedd45 | 2449 | return 0; |
29b61be6 | 2450 | } |
54168ed7 IM |
2451 | #endif |
2452 | ||
2453 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2454 | { | |
2455 | unsigned vector, me; | |
8f2466f4 | 2456 | |
54168ed7 | 2457 | ack_APIC_irq(); |
54168ed7 | 2458 | exit_idle(); |
54168ed7 IM |
2459 | irq_enter(); |
2460 | ||
2461 | me = smp_processor_id(); | |
2462 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2463 | unsigned int irq; | |
68a8ca59 | 2464 | unsigned int irr; |
54168ed7 IM |
2465 | struct irq_desc *desc; |
2466 | struct irq_cfg *cfg; | |
2467 | irq = __get_cpu_var(vector_irq)[vector]; | |
2468 | ||
0b8f1efa YL |
2469 | if (irq == -1) |
2470 | continue; | |
2471 | ||
54168ed7 IM |
2472 | desc = irq_to_desc(irq); |
2473 | if (!desc) | |
2474 | continue; | |
2475 | ||
2476 | cfg = irq_cfg(irq); | |
239007b8 | 2477 | raw_spin_lock(&desc->lock); |
54168ed7 | 2478 | |
7f41c2e1 SS |
2479 | /* |
2480 | * Check if the irq migration is in progress. If so, we | |
2481 | * haven't received the cleanup request yet for this irq. | |
2482 | */ | |
2483 | if (cfg->move_in_progress) | |
2484 | goto unlock; | |
2485 | ||
22f65d31 | 2486 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2487 | goto unlock; |
2488 | ||
68a8ca59 SS |
2489 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2490 | /* | |
2491 | * Check if the vector that needs to be cleanedup is | |
2492 | * registered at the cpu's IRR. If so, then this is not | |
2493 | * the best time to clean it up. Lets clean it up in the | |
2494 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2495 | * to myself. | |
2496 | */ | |
2497 | if (irr & (1 << (vector % 32))) { | |
2498 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2499 | goto unlock; | |
2500 | } | |
54168ed7 | 2501 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2502 | unlock: |
239007b8 | 2503 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2504 | } |
2505 | ||
2506 | irq_exit(); | |
2507 | } | |
2508 | ||
a5e74b84 | 2509 | static void __irq_complete_move(struct irq_desc **descp, unsigned vector) |
54168ed7 | 2510 | { |
3145e941 YL |
2511 | struct irq_desc *desc = *descp; |
2512 | struct irq_cfg *cfg = desc->chip_data; | |
a5e74b84 | 2513 | unsigned me; |
54168ed7 | 2514 | |
fcef5911 | 2515 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2516 | return; |
2517 | ||
54168ed7 | 2518 | me = smp_processor_id(); |
10b888d6 | 2519 | |
fcef5911 | 2520 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2521 | send_cleanup_vector(cfg); |
497c9a19 | 2522 | } |
a5e74b84 SS |
2523 | |
2524 | static void irq_complete_move(struct irq_desc **descp) | |
2525 | { | |
2526 | __irq_complete_move(descp, ~get_irq_regs()->orig_ax); | |
2527 | } | |
2528 | ||
2529 | void irq_force_complete_move(int irq) | |
2530 | { | |
2531 | struct irq_desc *desc = irq_to_desc(irq); | |
2532 | struct irq_cfg *cfg = desc->chip_data; | |
2533 | ||
bbd391a1 PB |
2534 | if (!cfg) |
2535 | return; | |
2536 | ||
a5e74b84 SS |
2537 | __irq_complete_move(&desc, cfg->vector); |
2538 | } | |
497c9a19 | 2539 | #else |
3145e941 | 2540 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2541 | #endif |
3145e941 | 2542 | |
1d025192 YL |
2543 | static void ack_apic_edge(unsigned int irq) |
2544 | { | |
3145e941 YL |
2545 | struct irq_desc *desc = irq_to_desc(irq); |
2546 | ||
2547 | irq_complete_move(&desc); | |
1d025192 YL |
2548 | move_native_irq(irq); |
2549 | ack_APIC_irq(); | |
2550 | } | |
2551 | ||
3eb2cce8 | 2552 | atomic_t irq_mis_count; |
3eb2cce8 | 2553 | |
c29d9db3 SS |
2554 | /* |
2555 | * IO-APIC versions below 0x20 don't support EOI register. | |
2556 | * For the record, here is the information about various versions: | |
2557 | * 0Xh 82489DX | |
2558 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2559 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2560 | * 30h-FFh Reserved | |
2561 | * | |
2562 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2563 | * version as 0x2. This is an error with documentation and these ICH chips | |
2564 | * use io-apic's of version 0x20. | |
2565 | * | |
2566 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2567 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2568 | * mode to edge and then back to level, with RTE being masked during this. | |
2569 | */ | |
b3ec0a37 SS |
2570 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2571 | { | |
2572 | struct irq_pin_list *entry; | |
2573 | ||
2574 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
c29d9db3 SS |
2575 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2576 | /* | |
2577 | * Intr-remapping uses pin number as the virtual vector | |
2578 | * in the RTE. Actual vector is programmed in | |
2579 | * intr-remapping table entry. Hence for the io-apic | |
2580 | * EOI we use the pin number. | |
2581 | */ | |
2582 | if (irq_remapped(irq)) | |
2583 | io_apic_eoi(entry->apic, entry->pin); | |
2584 | else | |
2585 | io_apic_eoi(entry->apic, cfg->vector); | |
2586 | } else { | |
2587 | __mask_and_edge_IO_APIC_irq(entry); | |
2588 | __unmask_and_level_IO_APIC_irq(entry); | |
2589 | } | |
b3ec0a37 SS |
2590 | } |
2591 | } | |
2592 | ||
2593 | static void eoi_ioapic_irq(struct irq_desc *desc) | |
2594 | { | |
2595 | struct irq_cfg *cfg; | |
2596 | unsigned long flags; | |
2597 | unsigned int irq; | |
2598 | ||
2599 | irq = desc->irq; | |
2600 | cfg = desc->chip_data; | |
2601 | ||
dade7716 | 2602 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2603 | __eoi_ioapic_irq(irq, cfg); |
dade7716 | 2604 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2605 | } |
2606 | ||
047c8fdb YL |
2607 | static void ack_apic_level(unsigned int irq) |
2608 | { | |
3145e941 | 2609 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 YL |
2610 | unsigned long v; |
2611 | int i; | |
3145e941 | 2612 | struct irq_cfg *cfg; |
54168ed7 | 2613 | int do_unmask_irq = 0; |
047c8fdb | 2614 | |
3145e941 | 2615 | irq_complete_move(&desc); |
047c8fdb | 2616 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2617 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2618 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2619 | do_unmask_irq = 1; |
3145e941 | 2620 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2621 | } |
047c8fdb YL |
2622 | #endif |
2623 | ||
3eb2cce8 | 2624 | /* |
916a0fe7 JF |
2625 | * It appears there is an erratum which affects at least version 0x11 |
2626 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2627 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2628 | * erroneously delivered as edge-triggered one but the respective IRR | |
2629 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2630 | * message but it will never arrive and further interrupts are blocked | |
2631 | * from the source. The exact reason is so far unknown, but the | |
2632 | * phenomenon was observed when two consecutive interrupt requests | |
2633 | * from a given source get delivered to the same CPU and the source is | |
2634 | * temporarily disabled in between. | |
2635 | * | |
2636 | * A workaround is to simulate an EOI message manually. We achieve it | |
2637 | * by setting the trigger mode to edge and then to level when the edge | |
2638 | * trigger mode gets detected in the TMR of a local APIC for a | |
2639 | * level-triggered interrupt. We mask the source for the time of the | |
2640 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2641 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2642 | * |
2643 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2644 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2645 | * destination that is handling the corresponding interrupt. This | |
2646 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2647 | * level-triggered io-apic interrupt will be seen as an edge | |
2648 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2649 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2650 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2651 | * supporting EOI register, we do an explicit EOI to clear the | |
2652 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2653 | * we use the above logic (mask+edge followed by unmask+level) from | |
2654 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2655 | */ |
3145e941 YL |
2656 | cfg = desc->chip_data; |
2657 | i = cfg->vector; | |
3eb2cce8 | 2658 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2659 | |
54168ed7 IM |
2660 | /* |
2661 | * We must acknowledge the irq before we move it or the acknowledge will | |
2662 | * not propagate properly. | |
2663 | */ | |
2664 | ack_APIC_irq(); | |
2665 | ||
1c83995b SS |
2666 | /* |
2667 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2668 | * message via io-apic EOI register write or simulating it using | |
2669 | * mask+edge followed by unnask+level logic) manually when the | |
2670 | * level triggered interrupt is seen as the edge triggered interrupt | |
2671 | * at the cpu. | |
2672 | */ | |
ca64c47c MR |
2673 | if (!(v & (1 << (i & 0x1f)))) { |
2674 | atomic_inc(&irq_mis_count); | |
2675 | ||
c29d9db3 | 2676 | eoi_ioapic_irq(desc); |
ca64c47c MR |
2677 | } |
2678 | ||
54168ed7 IM |
2679 | /* Now we can move and renable the irq */ |
2680 | if (unlikely(do_unmask_irq)) { | |
2681 | /* Only migrate the irq if the ack has been received. | |
2682 | * | |
2683 | * On rare occasions the broadcast level triggered ack gets | |
2684 | * delayed going to ioapics, and if we reprogram the | |
2685 | * vector while Remote IRR is still set the irq will never | |
2686 | * fire again. | |
2687 | * | |
2688 | * To prevent this scenario we read the Remote IRR bit | |
2689 | * of the ioapic. This has two effects. | |
2690 | * - On any sane system the read of the ioapic will | |
2691 | * flush writes (and acks) going to the ioapic from | |
2692 | * this cpu. | |
2693 | * - We get to see if the ACK has actually been delivered. | |
2694 | * | |
2695 | * Based on failed experiments of reprogramming the | |
2696 | * ioapic entry from outside of irq context starting | |
2697 | * with masking the ioapic entry and then polling until | |
2698 | * Remote IRR was clear before reprogramming the | |
2699 | * ioapic I don't trust the Remote IRR bit to be | |
2700 | * completey accurate. | |
2701 | * | |
2702 | * However there appears to be no other way to plug | |
2703 | * this race, so if the Remote IRR bit is not | |
2704 | * accurate and is causing problems then it is a hardware bug | |
2705 | * and you can go talk to the chipset vendor about it. | |
2706 | */ | |
3145e941 YL |
2707 | cfg = desc->chip_data; |
2708 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2709 | move_masked_irq(irq); |
3145e941 | 2710 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2711 | } |
3eb2cce8 | 2712 | } |
1d025192 | 2713 | |
d0b03bd1 HW |
2714 | #ifdef CONFIG_INTR_REMAP |
2715 | static void ir_ack_apic_edge(unsigned int irq) | |
2716 | { | |
5d0ae2db | 2717 | ack_APIC_irq(); |
d0b03bd1 HW |
2718 | } |
2719 | ||
2720 | static void ir_ack_apic_level(unsigned int irq) | |
2721 | { | |
5d0ae2db WH |
2722 | struct irq_desc *desc = irq_to_desc(irq); |
2723 | ||
2724 | ack_APIC_irq(); | |
2725 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2726 | } |
2727 | #endif /* CONFIG_INTR_REMAP */ | |
2728 | ||
f5b9ed7a | 2729 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2730 | .name = "IO-APIC", |
2731 | .startup = startup_ioapic_irq, | |
2732 | .mask = mask_IO_APIC_irq, | |
2733 | .unmask = unmask_IO_APIC_irq, | |
2734 | .ack = ack_apic_edge, | |
2735 | .eoi = ack_apic_level, | |
54d5d424 | 2736 | #ifdef CONFIG_SMP |
d6c88a50 | 2737 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2738 | #endif |
ace80ab7 | 2739 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2740 | }; |
2741 | ||
54168ed7 | 2742 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2743 | .name = "IR-IO-APIC", |
2744 | .startup = startup_ioapic_irq, | |
2745 | .mask = mask_IO_APIC_irq, | |
2746 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2747 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2748 | .ack = ir_ack_apic_edge, |
2749 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2750 | #ifdef CONFIG_SMP |
d6c88a50 | 2751 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2752 | #endif |
54168ed7 IM |
2753 | #endif |
2754 | .retrigger = ioapic_retrigger_irq, | |
2755 | }; | |
1da177e4 LT |
2756 | |
2757 | static inline void init_IO_APIC_traps(void) | |
2758 | { | |
2759 | int irq; | |
08678b08 | 2760 | struct irq_desc *desc; |
da51a821 | 2761 | struct irq_cfg *cfg; |
1da177e4 LT |
2762 | |
2763 | /* | |
2764 | * NOTE! The local APIC isn't very good at handling | |
2765 | * multiple interrupts at the same interrupt level. | |
2766 | * As the interrupt level is determined by taking the | |
2767 | * vector number and shifting that right by 4, we | |
2768 | * want to spread these out a bit so that they don't | |
2769 | * all fall in the same interrupt level. | |
2770 | * | |
2771 | * Also, we've got to be careful not to trash gate | |
2772 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2773 | */ | |
0b8f1efa | 2774 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2775 | cfg = desc->chip_data; |
2776 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2777 | /* |
2778 | * Hmm.. We don't have an entry for this, | |
2779 | * so default to an old-fashioned 8259 | |
2780 | * interrupt if we can.. | |
2781 | */ | |
b81bb373 JP |
2782 | if (irq < legacy_pic->nr_legacy_irqs) |
2783 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2784 | else |
1da177e4 | 2785 | /* Strange. Oh, well.. */ |
08678b08 | 2786 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2787 | } |
2788 | } | |
2789 | } | |
2790 | ||
f5b9ed7a IM |
2791 | /* |
2792 | * The local APIC irq-chip implementation: | |
2793 | */ | |
1da177e4 | 2794 | |
36062448 | 2795 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2796 | { |
2797 | unsigned long v; | |
2798 | ||
2799 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2800 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2801 | } |
2802 | ||
36062448 | 2803 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2804 | { |
f5b9ed7a | 2805 | unsigned long v; |
1da177e4 | 2806 | |
f5b9ed7a | 2807 | v = apic_read(APIC_LVT0); |
593f4a78 | 2808 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2809 | } |
1da177e4 | 2810 | |
3145e941 | 2811 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2812 | { |
2813 | ack_APIC_irq(); | |
2814 | } | |
2815 | ||
f5b9ed7a | 2816 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2817 | .name = "local-APIC", |
f5b9ed7a IM |
2818 | .mask = mask_lapic_irq, |
2819 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2820 | .ack = ack_lapic_irq, |
1da177e4 LT |
2821 | }; |
2822 | ||
3145e941 | 2823 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2824 | { |
08678b08 | 2825 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2826 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2827 | "edge"); | |
c88ac1df MR |
2828 | } |
2829 | ||
e9427101 | 2830 | static void __init setup_nmi(void) |
1da177e4 LT |
2831 | { |
2832 | /* | |
36062448 | 2833 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2834 | * We put the 8259A master into AEOI mode and |
2835 | * unmask on all local APICs LVT0 as NMI. | |
2836 | * | |
2837 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2838 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2839 | * the NMI handler or the timer interrupt. | |
36062448 | 2840 | */ |
1da177e4 LT |
2841 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2842 | ||
e9427101 | 2843 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2844 | |
2845 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2846 | } | |
2847 | ||
2848 | /* | |
2849 | * This looks a bit hackish but it's about the only one way of sending | |
2850 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2851 | * not support the ExtINT mode, unfortunately. We need to send these | |
2852 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2853 | * 8259A interrupt line asserted until INTA. --macro | |
2854 | */ | |
28acf285 | 2855 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2856 | { |
fcfd636a | 2857 | int apic, pin, i; |
1da177e4 LT |
2858 | struct IO_APIC_route_entry entry0, entry1; |
2859 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2860 | |
fcfd636a | 2861 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2862 | if (pin == -1) { |
2863 | WARN_ON_ONCE(1); | |
2864 | return; | |
2865 | } | |
fcfd636a | 2866 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2867 | if (apic == -1) { |
2868 | WARN_ON_ONCE(1); | |
1da177e4 | 2869 | return; |
956fb531 | 2870 | } |
1da177e4 | 2871 | |
cf4c6a2f | 2872 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2873 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2874 | |
2875 | memset(&entry1, 0, sizeof(entry1)); | |
2876 | ||
2877 | entry1.dest_mode = 0; /* physical delivery */ | |
2878 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2879 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2880 | entry1.delivery_mode = dest_ExtINT; |
2881 | entry1.polarity = entry0.polarity; | |
2882 | entry1.trigger = 0; | |
2883 | entry1.vector = 0; | |
2884 | ||
cf4c6a2f | 2885 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2886 | |
2887 | save_control = CMOS_READ(RTC_CONTROL); | |
2888 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2889 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2890 | RTC_FREQ_SELECT); | |
2891 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2892 | ||
2893 | i = 100; | |
2894 | while (i-- > 0) { | |
2895 | mdelay(10); | |
2896 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2897 | i -= 10; | |
2898 | } | |
2899 | ||
2900 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2901 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2902 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2903 | |
cf4c6a2f | 2904 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2905 | } |
2906 | ||
efa2559f | 2907 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2908 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2909 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2910 | { |
2911 | disable_timer_pin_1 = 1; | |
2912 | return 0; | |
2913 | } | |
54168ed7 | 2914 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2915 | |
2916 | int timer_through_8259 __initdata; | |
2917 | ||
1da177e4 LT |
2918 | /* |
2919 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2920 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2921 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2922 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2923 | * |
2924 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2925 | */ |
8542b200 | 2926 | static inline void __init check_timer(void) |
1da177e4 | 2927 | { |
3145e941 YL |
2928 | struct irq_desc *desc = irq_to_desc(0); |
2929 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2930 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2931 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2932 | unsigned long flags; |
047c8fdb | 2933 | int no_pin1 = 0; |
4aae0702 IM |
2934 | |
2935 | local_irq_save(flags); | |
d4d25dec | 2936 | |
1da177e4 LT |
2937 | /* |
2938 | * get/set the timer IRQ vector: | |
2939 | */ | |
b81bb373 | 2940 | legacy_pic->chip->mask(0); |
fe402e1f | 2941 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2942 | |
2943 | /* | |
d11d5794 MR |
2944 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2945 | * wire has to be disabled in the local APIC. Also | |
2946 | * timer interrupts need to be acknowledged manually in | |
2947 | * the 8259A for the i82489DX when using the NMI | |
2948 | * watchdog as that APIC treats NMIs as level-triggered. | |
2949 | * The AEOI mode will finish them in the 8259A | |
2950 | * automatically. | |
1da177e4 | 2951 | */ |
593f4a78 | 2952 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2953 | legacy_pic->init(1); |
54168ed7 | 2954 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2955 | { |
2956 | unsigned int ver; | |
2957 | ||
2958 | ver = apic_read(APIC_LVR); | |
2959 | ver = GET_APIC_VERSION(ver); | |
2960 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2961 | } | |
54168ed7 | 2962 | #endif |
1da177e4 | 2963 | |
fcfd636a EB |
2964 | pin1 = find_isa_irq_pin(0, mp_INT); |
2965 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2966 | pin2 = ioapic_i8259.pin; | |
2967 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2968 | |
49a66a0b MR |
2969 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2970 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2971 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2972 | |
691874fa MR |
2973 | /* |
2974 | * Some BIOS writers are clueless and report the ExtINTA | |
2975 | * I/O APIC input from the cascaded 8259A as the timer | |
2976 | * interrupt input. So just in case, if only one pin | |
2977 | * was found above, try it both directly and through the | |
2978 | * 8259A. | |
2979 | */ | |
2980 | if (pin1 == -1) { | |
54168ed7 IM |
2981 | if (intr_remapping_enabled) |
2982 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2983 | pin1 = pin2; |
2984 | apic1 = apic2; | |
2985 | no_pin1 = 1; | |
2986 | } else if (pin2 == -1) { | |
2987 | pin2 = pin1; | |
2988 | apic2 = apic1; | |
2989 | } | |
2990 | ||
1da177e4 LT |
2991 | if (pin1 != -1) { |
2992 | /* | |
2993 | * Ok, does IRQ0 through the IOAPIC work? | |
2994 | */ | |
691874fa | 2995 | if (no_pin1) { |
85ac16d0 | 2996 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2997 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2998 | } else { |
2999 | /* for edge trigger, setup_IO_APIC_irq already | |
3000 | * leave it unmasked. | |
3001 | * so only need to unmask if it is level-trigger | |
3002 | * do we really have level trigger timer? | |
3003 | */ | |
3004 | int idx; | |
3005 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
3006 | if (idx != -1 && irq_trigger(idx)) | |
3007 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 3008 | } |
1da177e4 LT |
3009 | if (timer_irq_works()) { |
3010 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 3011 | setup_nmi(); |
b81bb373 | 3012 | legacy_pic->chip->unmask(0); |
1da177e4 | 3013 | } |
66759a01 CE |
3014 | if (disable_timer_pin_1 > 0) |
3015 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 3016 | goto out; |
1da177e4 | 3017 | } |
54168ed7 IM |
3018 | if (intr_remapping_enabled) |
3019 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 3020 | local_irq_disable(); |
fcfd636a | 3021 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 3022 | if (!no_pin1) |
49a66a0b MR |
3023 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
3024 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 3025 | |
49a66a0b MR |
3026 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
3027 | "(IRQ0) through the 8259A ...\n"); | |
3028 | apic_printk(APIC_QUIET, KERN_INFO | |
3029 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
3030 | /* |
3031 | * legacy devices should be connected to IO APIC #0 | |
3032 | */ | |
85ac16d0 | 3033 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 3034 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
b81bb373 | 3035 | legacy_pic->chip->unmask(0); |
1da177e4 | 3036 | if (timer_irq_works()) { |
49a66a0b | 3037 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 3038 | timer_through_8259 = 1; |
1da177e4 | 3039 | if (nmi_watchdog == NMI_IO_APIC) { |
b81bb373 | 3040 | legacy_pic->chip->mask(0); |
1da177e4 | 3041 | setup_nmi(); |
b81bb373 | 3042 | legacy_pic->chip->unmask(0); |
1da177e4 | 3043 | } |
4aae0702 | 3044 | goto out; |
1da177e4 LT |
3045 | } |
3046 | /* | |
3047 | * Cleanup, just in case ... | |
3048 | */ | |
f72dccac | 3049 | local_irq_disable(); |
b81bb373 | 3050 | legacy_pic->chip->mask(0); |
fcfd636a | 3051 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3052 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3053 | } |
1da177e4 LT |
3054 | |
3055 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3056 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3057 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3058 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3059 | } |
54168ed7 | 3060 | #ifdef CONFIG_X86_32 |
d11d5794 | 3061 | timer_ack = 0; |
54168ed7 | 3062 | #endif |
1da177e4 | 3063 | |
49a66a0b MR |
3064 | apic_printk(APIC_QUIET, KERN_INFO |
3065 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3066 | |
3145e941 | 3067 | lapic_register_intr(0, desc); |
497c9a19 | 3068 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
b81bb373 | 3069 | legacy_pic->chip->unmask(0); |
1da177e4 LT |
3070 | |
3071 | if (timer_irq_works()) { | |
49a66a0b | 3072 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3073 | goto out; |
1da177e4 | 3074 | } |
f72dccac | 3075 | local_irq_disable(); |
b81bb373 | 3076 | legacy_pic->chip->mask(0); |
497c9a19 | 3077 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3078 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3079 | |
49a66a0b MR |
3080 | apic_printk(APIC_QUIET, KERN_INFO |
3081 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3082 | |
b81bb373 JP |
3083 | legacy_pic->init(0); |
3084 | legacy_pic->make_irq(0); | |
593f4a78 | 3085 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3086 | |
3087 | unlock_ExtINT_logic(); | |
3088 | ||
3089 | if (timer_irq_works()) { | |
49a66a0b | 3090 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3091 | goto out; |
1da177e4 | 3092 | } |
f72dccac | 3093 | local_irq_disable(); |
49a66a0b | 3094 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3095 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3096 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3097 | out: |
3098 | local_irq_restore(flags); | |
1da177e4 LT |
3099 | } |
3100 | ||
3101 | /* | |
af174783 MR |
3102 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3103 | * to devices. However there may be an I/O APIC pin available for | |
3104 | * this interrupt regardless. The pin may be left unconnected, but | |
3105 | * typically it will be reused as an ExtINT cascade interrupt for | |
3106 | * the master 8259A. In the MPS case such a pin will normally be | |
3107 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3108 | * there is no provision for ExtINT interrupts, and in the absence | |
3109 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3110 | * interrupt, that is edge-triggered and unmasked by default. We | |
3111 | * used to do this, but it caused problems on some systems because | |
3112 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3113 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3114 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3115 | * the I/O APIC in all cases now. No actual device should request | |
3116 | * it anyway. --macro | |
1da177e4 | 3117 | */ |
bc07844a | 3118 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3119 | |
3120 | void __init setup_IO_APIC(void) | |
3121 | { | |
54168ed7 | 3122 | |
54168ed7 IM |
3123 | /* |
3124 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3125 | */ | |
b81bb373 | 3126 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3127 | |
54168ed7 | 3128 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3129 | /* |
54168ed7 IM |
3130 | * Set up IO-APIC IRQ routing. |
3131 | */ | |
de934103 TG |
3132 | x86_init.mpparse.setup_ioapic_ids(); |
3133 | ||
1da177e4 LT |
3134 | sync_Arb_IDs(); |
3135 | setup_IO_APIC_irqs(); | |
3136 | init_IO_APIC_traps(); | |
b81bb373 | 3137 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3138 | check_timer(); |
1da177e4 LT |
3139 | } |
3140 | ||
3141 | /* | |
54168ed7 IM |
3142 | * Called after all the initialization is done. If we didnt find any |
3143 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3144 | */ |
36062448 | 3145 | |
1da177e4 LT |
3146 | static int __init io_apic_bug_finalize(void) |
3147 | { | |
d6c88a50 TG |
3148 | if (sis_apic_bug == -1) |
3149 | sis_apic_bug = 0; | |
3150 | return 0; | |
1da177e4 LT |
3151 | } |
3152 | ||
3153 | late_initcall(io_apic_bug_finalize); | |
3154 | ||
3155 | struct sysfs_ioapic_data { | |
3156 | struct sys_device dev; | |
3157 | struct IO_APIC_route_entry entry[0]; | |
3158 | }; | |
54168ed7 | 3159 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3160 | |
438510f6 | 3161 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3162 | { |
3163 | struct IO_APIC_route_entry *entry; | |
3164 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3165 | int i; |
36062448 | 3166 | |
1da177e4 LT |
3167 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3168 | entry = data->entry; | |
54168ed7 IM |
3169 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3170 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3171 | |
3172 | return 0; | |
3173 | } | |
3174 | ||
3175 | static int ioapic_resume(struct sys_device *dev) | |
3176 | { | |
3177 | struct IO_APIC_route_entry *entry; | |
3178 | struct sysfs_ioapic_data *data; | |
3179 | unsigned long flags; | |
3180 | union IO_APIC_reg_00 reg_00; | |
3181 | int i; | |
36062448 | 3182 | |
1da177e4 LT |
3183 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3184 | entry = data->entry; | |
3185 | ||
dade7716 | 3186 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3187 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3188 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3189 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3190 | io_apic_write(dev->id, 0, reg_00.raw); |
3191 | } | |
dade7716 | 3192 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3193 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3194 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3195 | |
3196 | return 0; | |
3197 | } | |
3198 | ||
3199 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3200 | .name = "ioapic", |
1da177e4 LT |
3201 | .suspend = ioapic_suspend, |
3202 | .resume = ioapic_resume, | |
3203 | }; | |
3204 | ||
3205 | static int __init ioapic_init_sysfs(void) | |
3206 | { | |
54168ed7 IM |
3207 | struct sys_device * dev; |
3208 | int i, size, error; | |
1da177e4 LT |
3209 | |
3210 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3211 | if (error) | |
3212 | return error; | |
3213 | ||
54168ed7 | 3214 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3215 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3216 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3217 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3218 | if (!mp_ioapic_data[i]) { |
3219 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3220 | continue; | |
3221 | } | |
1da177e4 | 3222 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3223 | dev->id = i; |
1da177e4 LT |
3224 | dev->cls = &ioapic_sysdev_class; |
3225 | error = sysdev_register(dev); | |
3226 | if (error) { | |
3227 | kfree(mp_ioapic_data[i]); | |
3228 | mp_ioapic_data[i] = NULL; | |
3229 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3230 | continue; | |
3231 | } | |
3232 | } | |
3233 | ||
3234 | return 0; | |
3235 | } | |
3236 | ||
3237 | device_initcall(ioapic_init_sysfs); | |
3238 | ||
3fc471ed | 3239 | /* |
95d77884 | 3240 | * Dynamic irq allocate and deallocation |
3fc471ed | 3241 | */ |
d047f53a | 3242 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3243 | { |
ace80ab7 | 3244 | /* Allocate an unused irq */ |
54168ed7 IM |
3245 | unsigned int irq; |
3246 | unsigned int new; | |
3fc471ed | 3247 | unsigned long flags; |
0b8f1efa | 3248 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3249 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3250 | |
3251 | irq = 0; | |
abcaa2b8 YL |
3252 | if (irq_want < nr_irqs_gsi) |
3253 | irq_want = nr_irqs_gsi; | |
3254 | ||
dade7716 | 3255 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3256 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3257 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3258 | if (!desc_new) { |
3259 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3260 | continue; |
0b8f1efa YL |
3261 | } |
3262 | cfg_new = desc_new->chip_data; | |
3263 | ||
3264 | if (cfg_new->vector != 0) | |
ace80ab7 | 3265 | continue; |
d047f53a | 3266 | |
15e957d0 | 3267 | desc_new = move_irq_desc(desc_new, node); |
37ef2a30 | 3268 | cfg_new = desc_new->chip_data; |
d047f53a | 3269 | |
fe402e1f | 3270 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3271 | irq = new; |
3272 | break; | |
3273 | } | |
dade7716 | 3274 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3275 | |
ced5b697 BP |
3276 | if (irq > 0) |
3277 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3278 | |
3fc471ed EB |
3279 | return irq; |
3280 | } | |
3281 | ||
199751d7 YL |
3282 | int create_irq(void) |
3283 | { | |
d047f53a | 3284 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3285 | unsigned int irq_want; |
54168ed7 IM |
3286 | int irq; |
3287 | ||
be5d5350 | 3288 | irq_want = nr_irqs_gsi; |
d047f53a | 3289 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3290 | |
3291 | if (irq == 0) | |
3292 | irq = -1; | |
3293 | ||
3294 | return irq; | |
199751d7 YL |
3295 | } |
3296 | ||
3fc471ed EB |
3297 | void destroy_irq(unsigned int irq) |
3298 | { | |
3299 | unsigned long flags; | |
3fc471ed | 3300 | |
ced5b697 | 3301 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3302 | |
54168ed7 | 3303 | free_irte(irq); |
dade7716 | 3304 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3305 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3306 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3307 | } |
3fc471ed | 3308 | |
2d3fcc1c | 3309 | /* |
27b46d76 | 3310 | * MSI message composition |
2d3fcc1c EB |
3311 | */ |
3312 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3313 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3314 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3315 | { |
497c9a19 YL |
3316 | struct irq_cfg *cfg; |
3317 | int err; | |
2d3fcc1c EB |
3318 | unsigned dest; |
3319 | ||
f1182638 JB |
3320 | if (disable_apic) |
3321 | return -ENXIO; | |
3322 | ||
3145e941 | 3323 | cfg = irq_cfg(irq); |
fe402e1f | 3324 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3325 | if (err) |
3326 | return err; | |
2d3fcc1c | 3327 | |
debccb3e | 3328 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3329 | |
54168ed7 IM |
3330 | if (irq_remapped(irq)) { |
3331 | struct irte irte; | |
3332 | int ir_index; | |
3333 | u16 sub_handle; | |
3334 | ||
3335 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3336 | BUG_ON(ir_index == -1); | |
3337 | ||
3338 | memset (&irte, 0, sizeof(irte)); | |
3339 | ||
3340 | irte.present = 1; | |
9b5bc8dc | 3341 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3342 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3343 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3344 | irte.vector = cfg->vector; |
3345 | irte.dest_id = IRTE_DEST(dest); | |
3346 | ||
f007e99c | 3347 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3348 | if (pdev) |
3349 | set_msi_sid(&irte, pdev); | |
3350 | else | |
3351 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3352 | |
54168ed7 IM |
3353 | modify_irte(irq, &irte); |
3354 | ||
3355 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3356 | msg->data = sub_handle; | |
3357 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3358 | MSI_ADDR_IR_SHV | | |
3359 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3360 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3361 | } else { |
9d783ba0 SS |
3362 | if (x2apic_enabled()) |
3363 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3364 | MSI_ADDR_EXT_DEST_ID(dest); | |
3365 | else | |
3366 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3367 | ||
54168ed7 IM |
3368 | msg->address_lo = |
3369 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3370 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3371 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3372 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3373 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3374 | MSI_ADDR_REDIRECTION_CPU: |
3375 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3376 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3377 | |
54168ed7 IM |
3378 | msg->data = |
3379 | MSI_DATA_TRIGGER_EDGE | | |
3380 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3381 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3382 | MSI_DATA_DELIVERY_FIXED: |
3383 | MSI_DATA_DELIVERY_LOWPRI) | | |
3384 | MSI_DATA_VECTOR(cfg->vector); | |
3385 | } | |
497c9a19 | 3386 | return err; |
2d3fcc1c EB |
3387 | } |
3388 | ||
3b7d1921 | 3389 | #ifdef CONFIG_SMP |
d5dedd45 | 3390 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3391 | { |
3145e941 | 3392 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3393 | struct irq_cfg *cfg; |
3b7d1921 EB |
3394 | struct msi_msg msg; |
3395 | unsigned int dest; | |
3b7d1921 | 3396 | |
18374d89 | 3397 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3398 | return -1; |
2d3fcc1c | 3399 | |
3145e941 | 3400 | cfg = desc->chip_data; |
2d3fcc1c | 3401 | |
30da5524 | 3402 | get_cached_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3403 | |
3404 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3405 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3406 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3407 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3408 | ||
3145e941 | 3409 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3410 | |
3411 | return 0; | |
2d3fcc1c | 3412 | } |
54168ed7 IM |
3413 | #ifdef CONFIG_INTR_REMAP |
3414 | /* | |
3415 | * Migrate the MSI irq to another cpumask. This migration is | |
3416 | * done in the process context using interrupt-remapping hardware. | |
3417 | */ | |
d5dedd45 | 3418 | static int |
e7986739 | 3419 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3420 | { |
3145e941 | 3421 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3422 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3423 | unsigned int dest; |
54168ed7 | 3424 | struct irte irte; |
54168ed7 IM |
3425 | |
3426 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3427 | return -1; |
54168ed7 | 3428 | |
18374d89 | 3429 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3430 | return -1; |
54168ed7 | 3431 | |
54168ed7 IM |
3432 | irte.vector = cfg->vector; |
3433 | irte.dest_id = IRTE_DEST(dest); | |
3434 | ||
3435 | /* | |
3436 | * atomically update the IRTE with the new destination and vector. | |
3437 | */ | |
3438 | modify_irte(irq, &irte); | |
3439 | ||
3440 | /* | |
3441 | * After this point, all the interrupts will start arriving | |
3442 | * at the new destination. So, time to cleanup the previous | |
3443 | * vector allocation. | |
3444 | */ | |
22f65d31 MT |
3445 | if (cfg->move_in_progress) |
3446 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3447 | |
3448 | return 0; | |
54168ed7 | 3449 | } |
3145e941 | 3450 | |
54168ed7 | 3451 | #endif |
3b7d1921 | 3452 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3453 | |
3b7d1921 EB |
3454 | /* |
3455 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3456 | * which implement the MSI or MSI-X Capability Structure. | |
3457 | */ | |
3458 | static struct irq_chip msi_chip = { | |
3459 | .name = "PCI-MSI", | |
3460 | .unmask = unmask_msi_irq, | |
3461 | .mask = mask_msi_irq, | |
1d025192 | 3462 | .ack = ack_apic_edge, |
3b7d1921 EB |
3463 | #ifdef CONFIG_SMP |
3464 | .set_affinity = set_msi_irq_affinity, | |
3465 | #endif | |
3466 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3467 | }; |
3468 | ||
54168ed7 IM |
3469 | static struct irq_chip msi_ir_chip = { |
3470 | .name = "IR-PCI-MSI", | |
3471 | .unmask = unmask_msi_irq, | |
3472 | .mask = mask_msi_irq, | |
a1e38ca5 | 3473 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3474 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3475 | #ifdef CONFIG_SMP |
3476 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3477 | #endif |
54168ed7 IM |
3478 | #endif |
3479 | .retrigger = ioapic_retrigger_irq, | |
3480 | }; | |
3481 | ||
3482 | /* | |
3483 | * Map the PCI dev to the corresponding remapping hardware unit | |
3484 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3485 | * in it. | |
3486 | */ | |
3487 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3488 | { | |
3489 | struct intel_iommu *iommu; | |
3490 | int index; | |
3491 | ||
3492 | iommu = map_dev_to_ir(dev); | |
3493 | if (!iommu) { | |
3494 | printk(KERN_ERR | |
3495 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3496 | return -ENOENT; | |
3497 | } | |
3498 | ||
3499 | index = alloc_irte(iommu, irq, nvec); | |
3500 | if (index < 0) { | |
3501 | printk(KERN_ERR | |
3502 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3503 | pci_name(dev)); |
54168ed7 IM |
3504 | return -ENOSPC; |
3505 | } | |
3506 | return index; | |
3507 | } | |
1d025192 | 3508 | |
3145e941 | 3509 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3510 | { |
3511 | int ret; | |
3512 | struct msi_msg msg; | |
3513 | ||
c8bc6f3c | 3514 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3515 | if (ret < 0) |
3516 | return ret; | |
3517 | ||
3145e941 | 3518 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3519 | write_msi_msg(irq, &msg); |
3520 | ||
54168ed7 IM |
3521 | if (irq_remapped(irq)) { |
3522 | struct irq_desc *desc = irq_to_desc(irq); | |
3523 | /* | |
3524 | * irq migration in process context | |
3525 | */ | |
3526 | desc->status |= IRQ_MOVE_PCNTXT; | |
3527 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3528 | } else | |
54168ed7 | 3529 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3530 | |
c81bba49 YL |
3531 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3532 | ||
1d025192 YL |
3533 | return 0; |
3534 | } | |
3535 | ||
047c8fdb YL |
3536 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3537 | { | |
54168ed7 IM |
3538 | unsigned int irq; |
3539 | int ret, sub_handle; | |
0b8f1efa | 3540 | struct msi_desc *msidesc; |
54168ed7 | 3541 | unsigned int irq_want; |
1cc18521 | 3542 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3543 | int index = 0; |
d047f53a | 3544 | int node; |
54168ed7 | 3545 | |
1c8d7b0a MW |
3546 | /* x86 doesn't support multiple MSI yet */ |
3547 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3548 | return 1; | |
3549 | ||
d047f53a | 3550 | node = dev_to_node(&dev->dev); |
be5d5350 | 3551 | irq_want = nr_irqs_gsi; |
54168ed7 | 3552 | sub_handle = 0; |
0b8f1efa | 3553 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3554 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3555 | if (irq == 0) |
3556 | return -1; | |
f1ee5548 | 3557 | irq_want = irq + 1; |
54168ed7 IM |
3558 | if (!intr_remapping_enabled) |
3559 | goto no_ir; | |
3560 | ||
3561 | if (!sub_handle) { | |
3562 | /* | |
3563 | * allocate the consecutive block of IRTE's | |
3564 | * for 'nvec' | |
3565 | */ | |
3566 | index = msi_alloc_irte(dev, irq, nvec); | |
3567 | if (index < 0) { | |
3568 | ret = index; | |
3569 | goto error; | |
3570 | } | |
3571 | } else { | |
3572 | iommu = map_dev_to_ir(dev); | |
3573 | if (!iommu) { | |
3574 | ret = -ENOENT; | |
3575 | goto error; | |
3576 | } | |
3577 | /* | |
3578 | * setup the mapping between the irq and the IRTE | |
3579 | * base index, the sub_handle pointing to the | |
3580 | * appropriate interrupt remap table entry. | |
3581 | */ | |
3582 | set_irte_irq(irq, iommu, index, sub_handle); | |
3583 | } | |
3584 | no_ir: | |
0b8f1efa | 3585 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3586 | if (ret < 0) |
3587 | goto error; | |
3588 | sub_handle++; | |
3589 | } | |
3590 | return 0; | |
047c8fdb YL |
3591 | |
3592 | error: | |
54168ed7 IM |
3593 | destroy_irq(irq); |
3594 | return ret; | |
047c8fdb YL |
3595 | } |
3596 | ||
3b7d1921 EB |
3597 | void arch_teardown_msi_irq(unsigned int irq) |
3598 | { | |
f7feaca7 | 3599 | destroy_irq(irq); |
3b7d1921 EB |
3600 | } |
3601 | ||
9d783ba0 | 3602 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3603 | #ifdef CONFIG_SMP |
d5dedd45 | 3604 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3605 | { |
3145e941 | 3606 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3607 | struct irq_cfg *cfg; |
3608 | struct msi_msg msg; | |
3609 | unsigned int dest; | |
54168ed7 | 3610 | |
18374d89 | 3611 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3612 | return -1; |
54168ed7 | 3613 | |
3145e941 | 3614 | cfg = desc->chip_data; |
54168ed7 IM |
3615 | |
3616 | dmar_msi_read(irq, &msg); | |
3617 | ||
3618 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3619 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3620 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3621 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3622 | ||
3623 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3624 | |
3625 | return 0; | |
54168ed7 | 3626 | } |
3145e941 | 3627 | |
54168ed7 IM |
3628 | #endif /* CONFIG_SMP */ |
3629 | ||
8f7007aa | 3630 | static struct irq_chip dmar_msi_type = { |
54168ed7 IM |
3631 | .name = "DMAR_MSI", |
3632 | .unmask = dmar_msi_unmask, | |
3633 | .mask = dmar_msi_mask, | |
3634 | .ack = ack_apic_edge, | |
3635 | #ifdef CONFIG_SMP | |
3636 | .set_affinity = dmar_msi_set_affinity, | |
3637 | #endif | |
3638 | .retrigger = ioapic_retrigger_irq, | |
3639 | }; | |
3640 | ||
3641 | int arch_setup_dmar_msi(unsigned int irq) | |
3642 | { | |
3643 | int ret; | |
3644 | struct msi_msg msg; | |
2d3fcc1c | 3645 | |
c8bc6f3c | 3646 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3647 | if (ret < 0) |
3648 | return ret; | |
3649 | dmar_msi_write(irq, &msg); | |
3650 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3651 | "edge"); | |
3652 | return 0; | |
3653 | } | |
3654 | #endif | |
3655 | ||
58ac1e76 | 3656 | #ifdef CONFIG_HPET_TIMER |
3657 | ||
3658 | #ifdef CONFIG_SMP | |
d5dedd45 | 3659 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3660 | { |
3145e941 | 3661 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3662 | struct irq_cfg *cfg; |
58ac1e76 | 3663 | struct msi_msg msg; |
3664 | unsigned int dest; | |
58ac1e76 | 3665 | |
18374d89 | 3666 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3667 | return -1; |
58ac1e76 | 3668 | |
3145e941 | 3669 | cfg = desc->chip_data; |
58ac1e76 | 3670 | |
3671 | hpet_msi_read(irq, &msg); | |
3672 | ||
3673 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3674 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3675 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3676 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3677 | ||
3678 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3679 | |
3680 | return 0; | |
58ac1e76 | 3681 | } |
3145e941 | 3682 | |
58ac1e76 | 3683 | #endif /* CONFIG_SMP */ |
3684 | ||
c8bc6f3c SS |
3685 | static struct irq_chip ir_hpet_msi_type = { |
3686 | .name = "IR-HPET_MSI", | |
3687 | .unmask = hpet_msi_unmask, | |
3688 | .mask = hpet_msi_mask, | |
3689 | #ifdef CONFIG_INTR_REMAP | |
3690 | .ack = ir_ack_apic_edge, | |
3691 | #ifdef CONFIG_SMP | |
3692 | .set_affinity = ir_set_msi_irq_affinity, | |
3693 | #endif | |
3694 | #endif | |
3695 | .retrigger = ioapic_retrigger_irq, | |
3696 | }; | |
3697 | ||
1cc18521 | 3698 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3699 | .name = "HPET_MSI", |
3700 | .unmask = hpet_msi_unmask, | |
3701 | .mask = hpet_msi_mask, | |
3702 | .ack = ack_apic_edge, | |
3703 | #ifdef CONFIG_SMP | |
3704 | .set_affinity = hpet_msi_set_affinity, | |
3705 | #endif | |
3706 | .retrigger = ioapic_retrigger_irq, | |
3707 | }; | |
3708 | ||
c8bc6f3c | 3709 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3710 | { |
3711 | int ret; | |
3712 | struct msi_msg msg; | |
6ec3cfec | 3713 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3714 | |
c8bc6f3c SS |
3715 | if (intr_remapping_enabled) { |
3716 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3717 | int index; | |
3718 | ||
3719 | if (!iommu) | |
3720 | return -1; | |
3721 | ||
3722 | index = alloc_irte(iommu, irq, 1); | |
3723 | if (index < 0) | |
3724 | return -1; | |
3725 | } | |
3726 | ||
3727 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3728 | if (ret < 0) |
3729 | return ret; | |
3730 | ||
3731 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3732 | desc->status |= IRQ_MOVE_PCNTXT; |
c8bc6f3c SS |
3733 | if (irq_remapped(irq)) |
3734 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3735 | handle_edge_irq, "edge"); | |
3736 | else | |
3737 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3738 | handle_edge_irq, "edge"); | |
c81bba49 | 3739 | |
58ac1e76 | 3740 | return 0; |
3741 | } | |
3742 | #endif | |
3743 | ||
54168ed7 | 3744 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3745 | /* |
3746 | * Hypertransport interrupt support | |
3747 | */ | |
3748 | #ifdef CONFIG_HT_IRQ | |
3749 | ||
3750 | #ifdef CONFIG_SMP | |
3751 | ||
497c9a19 | 3752 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3753 | { |
ec68307c EB |
3754 | struct ht_irq_msg msg; |
3755 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3756 | |
497c9a19 | 3757 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3758 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3759 | |
497c9a19 | 3760 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3761 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3762 | |
ec68307c | 3763 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3764 | } |
3765 | ||
d5dedd45 | 3766 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3767 | { |
3145e941 | 3768 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3769 | struct irq_cfg *cfg; |
8b955b0d | 3770 | unsigned int dest; |
8b955b0d | 3771 | |
18374d89 | 3772 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3773 | return -1; |
8b955b0d | 3774 | |
3145e941 | 3775 | cfg = desc->chip_data; |
8b955b0d | 3776 | |
497c9a19 | 3777 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3778 | |
3779 | return 0; | |
8b955b0d | 3780 | } |
3145e941 | 3781 | |
8b955b0d EB |
3782 | #endif |
3783 | ||
c37e108d | 3784 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3785 | .name = "PCI-HT", |
3786 | .mask = mask_ht_irq, | |
3787 | .unmask = unmask_ht_irq, | |
1d025192 | 3788 | .ack = ack_apic_edge, |
8b955b0d EB |
3789 | #ifdef CONFIG_SMP |
3790 | .set_affinity = set_ht_irq_affinity, | |
3791 | #endif | |
3792 | .retrigger = ioapic_retrigger_irq, | |
3793 | }; | |
3794 | ||
3795 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3796 | { | |
497c9a19 YL |
3797 | struct irq_cfg *cfg; |
3798 | int err; | |
8b955b0d | 3799 | |
f1182638 JB |
3800 | if (disable_apic) |
3801 | return -ENXIO; | |
3802 | ||
3145e941 | 3803 | cfg = irq_cfg(irq); |
fe402e1f | 3804 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3805 | if (!err) { |
ec68307c | 3806 | struct ht_irq_msg msg; |
8b955b0d | 3807 | unsigned dest; |
8b955b0d | 3808 | |
debccb3e IM |
3809 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3810 | apic->target_cpus()); | |
8b955b0d | 3811 | |
ec68307c | 3812 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3813 | |
ec68307c EB |
3814 | msg.address_lo = |
3815 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3816 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3817 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3818 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3819 | HT_IRQ_LOW_DM_PHYSICAL : |
3820 | HT_IRQ_LOW_DM_LOGICAL) | | |
3821 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3822 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3823 | HT_IRQ_LOW_MT_FIXED : |
3824 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3825 | HT_IRQ_LOW_IRQ_MASKED; | |
3826 | ||
ec68307c | 3827 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3828 | |
a460e745 IM |
3829 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3830 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3831 | |
3832 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3833 | } |
497c9a19 | 3834 | return err; |
8b955b0d EB |
3835 | } |
3836 | #endif /* CONFIG_HT_IRQ */ | |
3837 | ||
9d6a4d08 YL |
3838 | int __init io_apic_get_redir_entries (int ioapic) |
3839 | { | |
3840 | union IO_APIC_reg_01 reg_01; | |
3841 | unsigned long flags; | |
3842 | ||
dade7716 | 3843 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3844 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3845 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3846 | |
4b6b19a1 EB |
3847 | /* The register returns the maximum index redir index |
3848 | * supported, which is one less than the total number of redir | |
3849 | * entries. | |
3850 | */ | |
3851 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3852 | } |
3853 | ||
be5d5350 | 3854 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3855 | { |
4afc51a8 | 3856 | int nr; |
be5d5350 | 3857 | |
a4384df3 | 3858 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3859 | if (nr > nr_irqs_gsi) |
be5d5350 | 3860 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3861 | |
3862 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3863 | } |
3864 | ||
4a046d17 YL |
3865 | #ifdef CONFIG_SPARSE_IRQ |
3866 | int __init arch_probe_nr_irqs(void) | |
3867 | { | |
3868 | int nr; | |
3869 | ||
f1ee5548 YL |
3870 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3871 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3872 | |
f1ee5548 YL |
3873 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3874 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3875 | /* | |
3876 | * for MSI and HT dyn irq | |
3877 | */ | |
3878 | nr += nr_irqs_gsi * 16; | |
3879 | #endif | |
3880 | if (nr < nr_irqs) | |
4a046d17 YL |
3881 | nr_irqs = nr; |
3882 | ||
b683de2b | 3883 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3884 | } |
3885 | #endif | |
3886 | ||
e5198075 YL |
3887 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3888 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3889 | { |
3890 | struct irq_desc *desc; | |
3891 | struct irq_cfg *cfg; | |
3892 | int node; | |
e5198075 YL |
3893 | int ioapic, pin; |
3894 | int trigger, polarity; | |
5ef21837 | 3895 | |
e5198075 | 3896 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3897 | if (!IO_APIC_IRQ(irq)) { |
3898 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3899 | ioapic); | |
3900 | return -EINVAL; | |
3901 | } | |
3902 | ||
3903 | if (dev) | |
3904 | node = dev_to_node(dev); | |
3905 | else | |
3906 | node = cpu_to_node(boot_cpu_id); | |
3907 | ||
3908 | desc = irq_to_desc_alloc_node(irq, node); | |
3909 | if (!desc) { | |
3910 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3911 | return 0; | |
3912 | } | |
3913 | ||
e5198075 YL |
3914 | pin = irq_attr->ioapic_pin; |
3915 | trigger = irq_attr->trigger; | |
3916 | polarity = irq_attr->polarity; | |
3917 | ||
5ef21837 YL |
3918 | /* |
3919 | * IRQs < 16 are already in the irq_2_pin[] map | |
3920 | */ | |
b81bb373 | 3921 | if (irq >= legacy_pic->nr_legacy_irqs) { |
5ef21837 | 3922 | cfg = desc->chip_data; |
f3d1915a CG |
3923 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3924 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3925 | pin, irq); | |
3926 | return 0; | |
3927 | } | |
5ef21837 YL |
3928 | } |
3929 | ||
e5198075 | 3930 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3931 | |
3932 | return 0; | |
3933 | } | |
3934 | ||
e5198075 YL |
3935 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3936 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3937 | { |
e5198075 | 3938 | int ioapic, pin; |
5ef21837 YL |
3939 | /* |
3940 | * Avoid pin reprogramming. PRTs typically include entries | |
3941 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3942 | * we only program the IOAPIC on the first. | |
3943 | */ | |
e5198075 YL |
3944 | ioapic = irq_attr->ioapic; |
3945 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3946 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3947 | pr_debug("Pin %d-%d already programmed\n", | |
3948 | mp_ioapics[ioapic].apicid, pin); | |
3949 | return 0; | |
3950 | } | |
3951 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3952 | ||
e5198075 | 3953 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3954 | } |
3955 | ||
2a4ab640 FT |
3956 | u8 __init io_apic_unique_id(u8 id) |
3957 | { | |
3958 | #ifdef CONFIG_X86_32 | |
3959 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3960 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3961 | return io_apic_get_unique_id(nr_ioapics, id); | |
3962 | else | |
3963 | return id; | |
3964 | #else | |
3965 | int i; | |
3966 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3967 | |
2a4ab640 FT |
3968 | bitmap_zero(used, 256); |
3969 | for (i = 0; i < nr_ioapics; i++) { | |
3970 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3971 | __set_bit(ia->apicid, used); | |
3972 | } | |
3973 | if (!test_bit(id, used)) | |
3974 | return id; | |
3975 | return find_first_zero_bit(used, 256); | |
3976 | #endif | |
3977 | } | |
1da177e4 | 3978 | |
54168ed7 | 3979 | #ifdef CONFIG_X86_32 |
36062448 | 3980 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3981 | { |
3982 | union IO_APIC_reg_00 reg_00; | |
3983 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3984 | physid_mask_t tmp; | |
3985 | unsigned long flags; | |
3986 | int i = 0; | |
3987 | ||
3988 | /* | |
36062448 PC |
3989 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3990 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3991 | * supports up to 16 on one shared APIC bus. |
36062448 | 3992 | * |
1da177e4 LT |
3993 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3994 | * advantage of new APIC bus architecture. | |
3995 | */ | |
3996 | ||
3997 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3998 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3999 | |
dade7716 | 4000 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4001 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 4002 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4003 | |
4004 | if (apic_id >= get_physical_broadcast()) { | |
4005 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
4006 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
4007 | apic_id = reg_00.bits.ID; | |
4008 | } | |
4009 | ||
4010 | /* | |
36062448 | 4011 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
4012 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
4013 | */ | |
7abc0753 | 4014 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
4015 | |
4016 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 4017 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
4018 | break; |
4019 | } | |
4020 | ||
4021 | if (i == get_physical_broadcast()) | |
4022 | panic("Max apic_id exceeded!\n"); | |
4023 | ||
4024 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
4025 | "trying %d\n", ioapic, apic_id, i); | |
4026 | ||
4027 | apic_id = i; | |
36062448 | 4028 | } |
1da177e4 | 4029 | |
7abc0753 | 4030 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
4031 | physids_or(apic_id_map, apic_id_map, tmp); |
4032 | ||
4033 | if (reg_00.bits.ID != apic_id) { | |
4034 | reg_00.bits.ID = apic_id; | |
4035 | ||
dade7716 | 4036 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
4037 | io_apic_write(ioapic, 0, reg_00.raw); |
4038 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 4039 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4040 | |
4041 | /* Sanity check */ | |
6070f9ec AD |
4042 | if (reg_00.bits.ID != apic_id) { |
4043 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
4044 | return -1; | |
4045 | } | |
1da177e4 LT |
4046 | } |
4047 | ||
4048 | apic_printk(APIC_VERBOSE, KERN_INFO | |
4049 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
4050 | ||
4051 | return apic_id; | |
4052 | } | |
58f892e0 | 4053 | #endif |
1da177e4 | 4054 | |
36062448 | 4055 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4056 | { |
4057 | union IO_APIC_reg_01 reg_01; | |
4058 | unsigned long flags; | |
4059 | ||
dade7716 | 4060 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4061 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4062 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4063 | |
4064 | return reg_01.bits.version; | |
4065 | } | |
4066 | ||
9a0a91bb | 4067 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 4068 | { |
9a0a91bb | 4069 | int ioapic, pin, idx; |
61fd47e0 SL |
4070 | |
4071 | if (skip_ioapic_setup) | |
4072 | return -1; | |
4073 | ||
9a0a91bb EB |
4074 | ioapic = mp_find_ioapic(gsi); |
4075 | if (ioapic < 0) | |
61fd47e0 SL |
4076 | return -1; |
4077 | ||
9a0a91bb EB |
4078 | pin = mp_find_ioapic_pin(ioapic, gsi); |
4079 | if (pin < 0) | |
4080 | return -1; | |
4081 | ||
4082 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
4083 | if (idx < 0) | |
61fd47e0 SL |
4084 | return -1; |
4085 | ||
9a0a91bb EB |
4086 | *trigger = irq_trigger(idx); |
4087 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
4088 | return 0; |
4089 | } | |
4090 | ||
497c9a19 YL |
4091 | /* |
4092 | * This function currently is only a helper for the i386 smp boot process where | |
4093 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4094 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4095 | */ |
4096 | #ifdef CONFIG_SMP | |
4097 | void __init setup_ioapic_dest(void) | |
4098 | { | |
fad53995 | 4099 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4100 | struct irq_desc *desc; |
22f65d31 | 4101 | const struct cpumask *mask; |
497c9a19 YL |
4102 | |
4103 | if (skip_ioapic_setup == 1) | |
4104 | return; | |
4105 | ||
fad53995 | 4106 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4107 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4108 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4109 | if (irq_entry == -1) | |
4110 | continue; | |
4111 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4112 | |
fad53995 EB |
4113 | if ((ioapic > 0) && (irq > 16)) |
4114 | continue; | |
4115 | ||
b9c61b70 | 4116 | desc = irq_to_desc(irq); |
6c2e9403 | 4117 | |
b9c61b70 YL |
4118 | /* |
4119 | * Honour affinities which have been set in early boot | |
4120 | */ | |
4121 | if (desc->status & | |
4122 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4123 | mask = desc->affinity; | |
4124 | else | |
4125 | mask = apic->target_cpus(); | |
497c9a19 | 4126 | |
b9c61b70 YL |
4127 | if (intr_remapping_enabled) |
4128 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4129 | else | |
4130 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4131 | } |
b9c61b70 | 4132 | |
497c9a19 YL |
4133 | } |
4134 | #endif | |
4135 | ||
54168ed7 IM |
4136 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4137 | ||
4138 | static struct resource *ioapic_resources; | |
4139 | ||
ffc43836 | 4140 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4141 | { |
4142 | unsigned long n; | |
4143 | struct resource *res; | |
4144 | char *mem; | |
4145 | int i; | |
4146 | ||
4147 | if (nr_ioapics <= 0) | |
4148 | return NULL; | |
4149 | ||
4150 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4151 | n *= nr_ioapics; | |
4152 | ||
4153 | mem = alloc_bootmem(n); | |
4154 | res = (void *)mem; | |
4155 | ||
ffc43836 | 4156 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4157 | |
ffc43836 CG |
4158 | for (i = 0; i < nr_ioapics; i++) { |
4159 | res[i].name = mem; | |
4160 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4161 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4162 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4163 | } |
4164 | ||
4165 | ioapic_resources = res; | |
4166 | ||
4167 | return res; | |
4168 | } | |
54168ed7 | 4169 | |
f3294a33 YL |
4170 | void __init ioapic_init_mappings(void) |
4171 | { | |
4172 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4173 | struct resource *ioapic_res; |
d6c88a50 | 4174 | int i; |
f3294a33 | 4175 | |
ffc43836 | 4176 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4177 | for (i = 0; i < nr_ioapics; i++) { |
4178 | if (smp_found_config) { | |
b5ba7e6d | 4179 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4180 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4181 | if (!ioapic_phys) { |
4182 | printk(KERN_ERR | |
4183 | "WARNING: bogus zero IO-APIC " | |
4184 | "address found in MPTABLE, " | |
4185 | "disabling IO/APIC support!\n"); | |
4186 | smp_found_config = 0; | |
4187 | skip_ioapic_setup = 1; | |
4188 | goto fake_ioapic_page; | |
4189 | } | |
54168ed7 | 4190 | #endif |
f3294a33 | 4191 | } else { |
54168ed7 | 4192 | #ifdef CONFIG_X86_32 |
f3294a33 | 4193 | fake_ioapic_page: |
54168ed7 | 4194 | #endif |
e79c65a9 | 4195 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4196 | ioapic_phys = __pa(ioapic_phys); |
4197 | } | |
4198 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4199 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4200 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4201 | ioapic_phys); | |
f3294a33 | 4202 | idx++; |
54168ed7 | 4203 | |
ffc43836 | 4204 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4205 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4206 | ioapic_res++; |
f3294a33 YL |
4207 | } |
4208 | } | |
4209 | ||
857fdc53 | 4210 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4211 | { |
4212 | int i; | |
4213 | struct resource *r = ioapic_resources; | |
4214 | ||
4215 | if (!r) { | |
857fdc53 | 4216 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4217 | printk(KERN_ERR |
4218 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4219 | return; |
54168ed7 IM |
4220 | } |
4221 | ||
4222 | for (i = 0; i < nr_ioapics; i++) { | |
4223 | insert_resource(&iomem_resource, r); | |
4224 | r++; | |
4225 | } | |
54168ed7 | 4226 | } |
2a4ab640 | 4227 | |
eddb0c55 | 4228 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4229 | { |
4230 | int i = 0; | |
4231 | ||
4232 | /* Find the IOAPIC that manages this GSI. */ | |
4233 | for (i = 0; i < nr_ioapics; i++) { | |
4234 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4235 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4236 | return i; | |
4237 | } | |
54168ed7 | 4238 | |
2a4ab640 FT |
4239 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4240 | return -1; | |
4241 | } | |
4242 | ||
eddb0c55 | 4243 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4244 | { |
4245 | if (WARN_ON(ioapic == -1)) | |
4246 | return -1; | |
4247 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4248 | return -1; | |
4249 | ||
4250 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4251 | } | |
4252 | ||
4253 | static int bad_ioapic(unsigned long address) | |
4254 | { | |
4255 | if (nr_ioapics >= MAX_IO_APICS) { | |
4256 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4257 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4258 | return 1; | |
4259 | } | |
4260 | if (!address) { | |
4261 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4262 | " found in table, skipping!\n"); | |
4263 | return 1; | |
4264 | } | |
54168ed7 IM |
4265 | return 0; |
4266 | } | |
4267 | ||
2a4ab640 FT |
4268 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4269 | { | |
4270 | int idx = 0; | |
7716a5c4 | 4271 | int entries; |
2a4ab640 FT |
4272 | |
4273 | if (bad_ioapic(address)) | |
4274 | return; | |
4275 | ||
4276 | idx = nr_ioapics; | |
4277 | ||
4278 | mp_ioapics[idx].type = MP_IOAPIC; | |
4279 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4280 | mp_ioapics[idx].apicaddr = address; | |
4281 | ||
4282 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4283 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4284 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4285 | ||
4286 | /* | |
4287 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4288 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4289 | */ | |
7716a5c4 | 4290 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4291 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4292 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4293 | ||
4294 | /* | |
4295 | * The number of IO-APIC IRQ registers (== #pins): | |
4296 | */ | |
4297 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4298 | |
a4384df3 EB |
4299 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4300 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4301 | |
4302 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4303 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4304 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4305 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4306 | ||
4307 | nr_ioapics++; | |
4308 | } | |
05ddafb1 JP |
4309 | |
4310 | /* Enable IOAPIC early just for system timer */ | |
4311 | void __init pre_init_apic_IRQ0(void) | |
4312 | { | |
4313 | struct irq_cfg *cfg; | |
4314 | struct irq_desc *desc; | |
4315 | ||
4316 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4317 | #ifndef CONFIG_SMP | |
4318 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4319 | #endif | |
4320 | desc = irq_to_desc_alloc_node(0, 0); | |
4321 | ||
4322 | setup_local_APIC(); | |
4323 | ||
4324 | cfg = irq_cfg(0); | |
4325 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4326 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4327 | ||
4328 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4329 | } |