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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
d7f3d478 | 34 | #include <linux/irqdomain.h> |
7dfb7103 | 35 | #include <linux/freezer.h> |
f26d6a2b | 36 | #include <linux/kthread.h> |
54168ed7 | 37 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 38 | #include <linux/slab.h> |
d4057bdb | 39 | #include <linux/bootmem.h> |
54d5d424 | 40 | |
d4057bdb | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
6d652ea1 | 44 | #include <asm/cpu.h> |
1da177e4 | 45 | #include <asm/desc.h> |
d4057bdb YL |
46 | #include <asm/proto.h> |
47 | #include <asm/acpi.h> | |
48 | #include <asm/dma.h> | |
1da177e4 | 49 | #include <asm/timer.h> |
306e440d | 50 | #include <asm/i8259.h> |
a4dbc34d | 51 | #include <asm/setup.h> |
8a8f422d | 52 | #include <asm/irq_remapping.h> |
2c1b284e | 53 | #include <asm/hw_irq.h> |
1da177e4 | 54 | |
7b6aa335 | 55 | #include <asm/apic.h> |
1da177e4 | 56 | |
f44d1692 JL |
57 | #define for_each_ioapic(idx) \ |
58 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
59 | #define for_each_ioapic_reverse(idx) \ | |
60 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
61 | #define for_each_pin(idx, pin) \ | |
62 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
63 | #define for_each_ioapic_pin(idx, pin) \ | |
64 | for_each_ioapic((idx)) \ | |
65 | for_each_pin((idx), (pin)) | |
66 | ||
2977fb3f | 67 | #define for_each_irq_pin(entry, head) \ |
a178b87b | 68 | list_for_each_entry(entry, &head, list) |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 | 76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
d7f3d478 | 77 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 78 | static unsigned int ioapic_dynirq_base; |
b81975ea | 79 | static int ioapic_initialized; |
efa2559f | 80 | |
49c7e600 JL |
81 | struct mp_chip_data { |
82 | struct IO_APIC_route_entry entry; | |
83 | int trigger; | |
84 | int polarity; | |
96ed44b2 | 85 | u32 count; |
49c7e600 JL |
86 | bool isa_irq; |
87 | }; | |
88 | ||
15a3c7cc JL |
89 | struct mp_pin_info { |
90 | int trigger; | |
91 | int polarity; | |
92 | int node; | |
93 | int set; | |
94 | u32 count; | |
95 | }; | |
96 | ||
b69c6c3b SS |
97 | static struct ioapic { |
98 | /* | |
99 | * # of IRQ routing registers | |
100 | */ | |
101 | int nr_registers; | |
57a6f740 SS |
102 | /* |
103 | * Saved state during suspend/resume, or while enabling intr-remap. | |
104 | */ | |
105 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
106 | /* I/O APIC config */ |
107 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
108 | /* IO APIC gsi routing info */ |
109 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
110 | struct ioapic_domain_cfg irqdomain_cfg; |
111 | struct irq_domain *irqdomain; | |
15a3c7cc | 112 | struct mp_pin_info *pin_info; |
15516a3b | 113 | struct resource *iomem_res; |
b69c6c3b | 114 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 115 | |
6f50d45f | 116 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 117 | |
6f50d45f | 118 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 119 | { |
6f50d45f | 120 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
121 | } |
122 | ||
6f50d45f | 123 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 124 | { |
6f50d45f | 125 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
126 | } |
127 | ||
6f50d45f | 128 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 129 | { |
6f50d45f | 130 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 131 | } |
9f640ccb | 132 | |
18e48551 JL |
133 | static inline int mp_ioapic_pin_count(int ioapic) |
134 | { | |
135 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
136 | ||
137 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
138 | } | |
139 | ||
140 | u32 mp_pin_to_gsi(int ioapic, int pin) | |
141 | { | |
142 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
143 | } | |
144 | ||
d32932d0 JL |
145 | static inline bool mp_is_legacy_irq(int irq) |
146 | { | |
147 | return irq >= 0 && irq < nr_legacy_irqs(); | |
148 | } | |
149 | ||
95d76acc JL |
150 | /* |
151 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
152 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
153 | * may rely on non-legacy pins on the first IOAPIC. | |
154 | */ | |
18e48551 JL |
155 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
156 | { | |
95d76acc JL |
157 | if (!nr_legacy_irqs()) |
158 | return 0; | |
159 | ||
d32932d0 | 160 | return ioapic == 0 || mp_is_legacy_irq(irq); |
18e48551 JL |
161 | } |
162 | ||
15a3c7cc JL |
163 | static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin) |
164 | { | |
165 | return ioapics[ioapic_idx].pin_info + pin; | |
166 | } | |
167 | ||
d7f3d478 JL |
168 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
169 | { | |
170 | return ioapics[ioapic].irqdomain; | |
171 | } | |
172 | ||
c040aaeb | 173 | int nr_ioapics; |
2a4ab640 | 174 | |
a4384df3 EB |
175 | /* The one past the highest gsi number used */ |
176 | u32 gsi_top; | |
5777372a | 177 | |
584f734d | 178 | /* MP IRQ source entries */ |
c2c21745 | 179 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
180 | |
181 | /* # of MP IRQ source entries */ | |
182 | int mp_irq_entries; | |
183 | ||
bb8187d3 | 184 | #ifdef CONFIG_EISA |
8732fc4b AS |
185 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
186 | #endif | |
187 | ||
188 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
189 | ||
efa2559f YL |
190 | int skip_ioapic_setup; |
191 | ||
7167d08e HK |
192 | /** |
193 | * disable_ioapic_support() - disables ioapic support at runtime | |
194 | */ | |
195 | void disable_ioapic_support(void) | |
65a4e574 IM |
196 | { |
197 | #ifdef CONFIG_PCI | |
198 | noioapicquirk = 1; | |
199 | noioapicreroute = -1; | |
200 | #endif | |
201 | skip_ioapic_setup = 1; | |
202 | } | |
203 | ||
54168ed7 | 204 | static int __init parse_noapic(char *str) |
efa2559f YL |
205 | { |
206 | /* disable IO-APIC */ | |
7167d08e | 207 | disable_ioapic_support(); |
efa2559f YL |
208 | return 0; |
209 | } | |
210 | early_param("noapic", parse_noapic); | |
66759a01 | 211 | |
2d8009ba FT |
212 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
213 | void mp_save_irq(struct mpc_intsrc *m) | |
214 | { | |
215 | int i; | |
216 | ||
217 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
218 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
219 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
220 | m->srcbusirq, m->dstapic, m->dstirq); | |
221 | ||
222 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 223 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
224 | return; |
225 | } | |
226 | ||
0e3fa13f | 227 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
228 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
229 | panic("Max # of irq sources exceeded!!\n"); | |
230 | } | |
231 | ||
0b8f1efa | 232 | struct irq_pin_list { |
a178b87b | 233 | struct list_head list; |
0b8f1efa | 234 | int apic, pin; |
0b8f1efa YL |
235 | }; |
236 | ||
7e495529 | 237 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 238 | { |
d32932d0 | 239 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); |
0b8f1efa YL |
240 | } |
241 | ||
7e899419 YL |
242 | static void alloc_ioapic_saved_registers(int idx) |
243 | { | |
244 | size_t size; | |
245 | ||
246 | if (ioapics[idx].saved_registers) | |
247 | return; | |
248 | ||
249 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; | |
250 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); | |
251 | if (!ioapics[idx].saved_registers) | |
252 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); | |
253 | } | |
254 | ||
15516a3b JL |
255 | static void free_ioapic_saved_registers(int idx) |
256 | { | |
257 | kfree(ioapics[idx].saved_registers); | |
258 | ioapics[idx].saved_registers = NULL; | |
259 | } | |
260 | ||
11d686e9 | 261 | int __init arch_early_ioapic_init(void) |
8f09cd20 | 262 | { |
13315320 | 263 | int i; |
d6c88a50 | 264 | |
95d76acc | 265 | if (!nr_legacy_irqs()) |
1f91233c | 266 | io_apic_irqs = ~0UL; |
1f91233c | 267 | |
7e899419 YL |
268 | for_each_ioapic(i) |
269 | alloc_ioapic_saved_registers(i); | |
4c79185c | 270 | |
13a0c3c2 | 271 | return 0; |
0b8f1efa | 272 | } |
8f09cd20 | 273 | |
130fe05d LT |
274 | struct io_apic { |
275 | unsigned int index; | |
276 | unsigned int unused[3]; | |
277 | unsigned int data; | |
0280f7c4 SS |
278 | unsigned int unused2[11]; |
279 | unsigned int eoi; | |
130fe05d LT |
280 | }; |
281 | ||
282 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
283 | { | |
284 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 285 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
286 | } |
287 | ||
da165322 | 288 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
289 | { |
290 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
291 | writel(vector, &io_apic->eoi); | |
292 | } | |
293 | ||
4a8e2a31 | 294 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
295 | { |
296 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
297 | writel(reg, &io_apic->index); | |
298 | return readl(&io_apic->data); | |
299 | } | |
300 | ||
4a8e2a31 | 301 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
302 | { |
303 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 304 | |
130fe05d LT |
305 | writel(reg, &io_apic->index); |
306 | writel(value, &io_apic->data); | |
307 | } | |
308 | ||
309 | /* | |
310 | * Re-write a value: to be used for read-modify-write | |
311 | * cycles where the read already set up the index register. | |
312 | * | |
313 | * Older SiS APIC requires we rewrite the index register | |
314 | */ | |
4a8e2a31 | 315 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 316 | { |
54168ed7 | 317 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
318 | |
319 | if (sis_apic_bug) | |
320 | writel(reg, &io_apic->index); | |
130fe05d LT |
321 | writel(value, &io_apic->data); |
322 | } | |
323 | ||
cf4c6a2f AK |
324 | union entry_union { |
325 | struct { u32 w1, w2; }; | |
326 | struct IO_APIC_route_entry entry; | |
327 | }; | |
328 | ||
e57253a8 SS |
329 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
330 | { | |
331 | union entry_union eu; | |
332 | ||
333 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
334 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 335 | |
e57253a8 SS |
336 | return eu.entry; |
337 | } | |
338 | ||
cf4c6a2f AK |
339 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
340 | { | |
341 | union entry_union eu; | |
342 | unsigned long flags; | |
136d249e | 343 | |
dade7716 | 344 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 345 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 346 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 347 | |
cf4c6a2f AK |
348 | return eu.entry; |
349 | } | |
350 | ||
f9dadfa7 LT |
351 | /* |
352 | * When we write a new IO APIC routing entry, we need to write the high | |
353 | * word first! If the mask bit in the low word is clear, we will enable | |
354 | * the interrupt, and we need to make sure the entry is fully populated | |
355 | * before that happens. | |
356 | */ | |
136d249e | 357 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 358 | { |
50a8d4d2 F |
359 | union entry_union eu = {{0, 0}}; |
360 | ||
cf4c6a2f | 361 | eu.entry = e; |
f9dadfa7 LT |
362 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
363 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
364 | } |
365 | ||
1a8ce7ff | 366 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
367 | { |
368 | unsigned long flags; | |
136d249e | 369 | |
dade7716 | 370 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 371 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 372 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
373 | } |
374 | ||
375 | /* | |
376 | * When we mask an IO APIC routing entry, we need to write the low | |
377 | * word first, in order to set the mask bit before we change the | |
378 | * high bits! | |
379 | */ | |
380 | static void ioapic_mask_entry(int apic, int pin) | |
381 | { | |
382 | unsigned long flags; | |
383 | union entry_union eu = { .entry.mask = 1 }; | |
384 | ||
dade7716 | 385 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
386 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
387 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 388 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
389 | } |
390 | ||
1da177e4 LT |
391 | /* |
392 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
393 | * shared ISA-space IRQs, so we have to support them. We are super | |
394 | * fast in the common case, and fast for shared ISA-space IRQs. | |
395 | */ | |
136d249e | 396 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 397 | { |
a178b87b | 398 | struct irq_pin_list *entry; |
0f978f45 | 399 | |
2977fb3f | 400 | /* don't allow duplicates */ |
a178b87b | 401 | for_each_irq_pin(entry, cfg->irq_2_pin) |
0f978f45 | 402 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 403 | return 0; |
0f978f45 | 404 | |
7e495529 | 405 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 406 | if (!entry) { |
c767a54b JP |
407 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
408 | node, apic, pin); | |
f3d1915a | 409 | return -ENOMEM; |
a7428cd2 | 410 | } |
1da177e4 LT |
411 | entry->apic = apic; |
412 | entry->pin = pin; | |
875e68ec | 413 | |
a178b87b | 414 | list_add_tail(&entry->list, &cfg->irq_2_pin); |
f3d1915a CG |
415 | return 0; |
416 | } | |
417 | ||
df334bea JL |
418 | static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin) |
419 | { | |
a178b87b | 420 | struct irq_pin_list *tmp, *entry; |
df334bea | 421 | |
a178b87b | 422 | list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list) |
df334bea | 423 | if (entry->apic == apic && entry->pin == pin) { |
a178b87b | 424 | list_del(&entry->list); |
df334bea JL |
425 | kfree(entry); |
426 | return; | |
df334bea JL |
427 | } |
428 | } | |
429 | ||
f3d1915a CG |
430 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
431 | { | |
7e495529 | 432 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 433 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
434 | } |
435 | ||
436 | /* | |
437 | * Reroute an IRQ to a different pin. | |
438 | */ | |
85ac16d0 | 439 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
440 | int oldapic, int oldpin, |
441 | int newapic, int newpin) | |
1da177e4 | 442 | { |
535b6429 | 443 | struct irq_pin_list *entry; |
1da177e4 | 444 | |
2977fb3f | 445 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
446 | if (entry->apic == oldapic && entry->pin == oldpin) { |
447 | entry->apic = newapic; | |
448 | entry->pin = newpin; | |
0f978f45 | 449 | /* every one is different, right? */ |
4eea6fff | 450 | return; |
0f978f45 | 451 | } |
1da177e4 | 452 | } |
0f978f45 | 453 | |
4eea6fff JF |
454 | /* old apic/pin didn't exist, so just add new ones */ |
455 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
456 | } |
457 | ||
c29d9db3 SS |
458 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
459 | int mask_and, int mask_or, | |
460 | void (*final)(struct irq_pin_list *entry)) | |
461 | { | |
462 | unsigned int reg, pin; | |
463 | ||
464 | pin = entry->pin; | |
465 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
466 | reg &= mask_and; | |
467 | reg |= mask_or; | |
468 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
469 | if (final) | |
470 | final(entry); | |
471 | } | |
472 | ||
2f210deb JF |
473 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
474 | int mask_and, int mask_or, | |
475 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 476 | { |
87783be4 | 477 | struct irq_pin_list *entry; |
047c8fdb | 478 | |
c29d9db3 SS |
479 | for_each_irq_pin(entry, cfg->irq_2_pin) |
480 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
481 | } | |
482 | ||
7f3e632f | 483 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 484 | { |
87783be4 CG |
485 | /* |
486 | * Synchronize the IO-APIC and the CPU by doing | |
487 | * a dummy read from the IO-APIC | |
488 | */ | |
489 | struct io_apic __iomem *io_apic; | |
136d249e | 490 | |
87783be4 | 491 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 492 | readl(&io_apic->data); |
1da177e4 LT |
493 | } |
494 | ||
dd5f15e5 | 495 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 496 | { |
dd5f15e5 TG |
497 | unsigned long flags; |
498 | ||
499 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 500 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 501 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 502 | } |
1da177e4 | 503 | |
90297c5f | 504 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 505 | { |
a9786091 | 506 | mask_ioapic(irqd_cfg(data)); |
dd5f15e5 | 507 | } |
3145e941 | 508 | |
dd5f15e5 TG |
509 | static void __unmask_ioapic(struct irq_cfg *cfg) |
510 | { | |
511 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
512 | } |
513 | ||
dd5f15e5 | 514 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
515 | { |
516 | unsigned long flags; | |
517 | ||
dade7716 | 518 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 519 | __unmask_ioapic(cfg); |
dade7716 | 520 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
521 | } |
522 | ||
90297c5f | 523 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 524 | { |
a9786091 | 525 | unmask_ioapic(irqd_cfg(data)); |
3145e941 YL |
526 | } |
527 | ||
c0205701 SS |
528 | /* |
529 | * IO-APIC versions below 0x20 don't support EOI register. | |
530 | * For the record, here is the information about various versions: | |
531 | * 0Xh 82489DX | |
532 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
533 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
534 | * 30h-FFh Reserved | |
535 | * | |
536 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
537 | * version as 0x2. This is an error with documentation and these ICH chips | |
538 | * use io-apic's of version 0x20. | |
539 | * | |
540 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
541 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
542 | * mode to edge and then back to level, with RTE being masked during this. | |
543 | */ | |
da165322 | 544 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
545 | { |
546 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 547 | io_apic_eoi(apic, vector); |
c0205701 SS |
548 | } else { |
549 | struct IO_APIC_route_entry entry, entry1; | |
550 | ||
551 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
552 | ||
553 | /* | |
554 | * Mask the entry and change the trigger mode to edge. | |
555 | */ | |
556 | entry1.mask = 1; | |
557 | entry1.trigger = IOAPIC_EDGE; | |
558 | ||
559 | __ioapic_write_entry(apic, pin, entry1); | |
560 | ||
561 | /* | |
562 | * Restore the previous level triggered entry. | |
563 | */ | |
564 | __ioapic_write_entry(apic, pin, entry); | |
565 | } | |
566 | } | |
567 | ||
d32932d0 JL |
568 | void eoi_ioapic_pin(int vector, struct irq_cfg *cfg) |
569 | { | |
570 | unsigned long flags; | |
571 | struct irq_pin_list *entry; | |
572 | ||
573 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
574 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
575 | native_eoi_ioapic_pin(entry->apic, entry->pin, vector); | |
576 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
577 | } | |
578 | ||
9b1b0e42 | 579 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
c0205701 SS |
580 | { |
581 | struct irq_pin_list *entry; | |
582 | unsigned long flags; | |
583 | ||
584 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
585 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
da165322 JR |
586 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
587 | cfg->vector); | |
c0205701 SS |
588 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
589 | } | |
590 | ||
1da177e4 LT |
591 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
592 | { | |
593 | struct IO_APIC_route_entry entry; | |
36062448 | 594 | |
1da177e4 | 595 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 596 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
597 | if (entry.delivery_mode == dest_SMI) |
598 | return; | |
1e75b31d | 599 | |
1da177e4 | 600 | /* |
1e75b31d SS |
601 | * Make sure the entry is masked and re-read the contents to check |
602 | * if it is a level triggered pin and if the remote-IRR is set. | |
603 | */ | |
604 | if (!entry.mask) { | |
605 | entry.mask = 1; | |
606 | ioapic_write_entry(apic, pin, entry); | |
607 | entry = ioapic_read_entry(apic, pin); | |
608 | } | |
609 | ||
610 | if (entry.irr) { | |
c0205701 SS |
611 | unsigned long flags; |
612 | ||
1e75b31d SS |
613 | /* |
614 | * Make sure the trigger mode is set to level. Explicit EOI | |
615 | * doesn't clear the remote-IRR if the trigger mode is not | |
616 | * set to level. | |
617 | */ | |
618 | if (!entry.trigger) { | |
619 | entry.trigger = IOAPIC_LEVEL; | |
620 | ioapic_write_entry(apic, pin, entry); | |
621 | } | |
c0205701 | 622 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d32932d0 | 623 | native_eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 624 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
625 | } |
626 | ||
627 | /* | |
628 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
629 | * bit. | |
1da177e4 | 630 | */ |
f9dadfa7 | 631 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
632 | entry = ioapic_read_entry(apic, pin); |
633 | if (entry.irr) | |
c767a54b | 634 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 635 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
636 | } |
637 | ||
54168ed7 | 638 | static void clear_IO_APIC (void) |
1da177e4 LT |
639 | { |
640 | int apic, pin; | |
641 | ||
f44d1692 JL |
642 | for_each_ioapic_pin(apic, pin) |
643 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
644 | } |
645 | ||
54168ed7 | 646 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
647 | /* |
648 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
649 | * specific CPU-side IRQs. | |
650 | */ | |
651 | ||
652 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
653 | static int pirq_entries[MAX_PIRQS] = { |
654 | [0 ... MAX_PIRQS - 1] = -1 | |
655 | }; | |
1da177e4 | 656 | |
1da177e4 LT |
657 | static int __init ioapic_pirq_setup(char *str) |
658 | { | |
659 | int i, max; | |
660 | int ints[MAX_PIRQS+1]; | |
661 | ||
662 | get_options(str, ARRAY_SIZE(ints), ints); | |
663 | ||
1da177e4 LT |
664 | apic_printk(APIC_VERBOSE, KERN_INFO |
665 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
666 | max = MAX_PIRQS; | |
667 | if (ints[0] < MAX_PIRQS) | |
668 | max = ints[0]; | |
669 | ||
670 | for (i = 0; i < max; i++) { | |
671 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
672 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
673 | /* | |
674 | * PIRQs are mapped upside down, usually. | |
675 | */ | |
676 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
677 | } | |
678 | return 1; | |
679 | } | |
680 | ||
681 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
682 | #endif /* CONFIG_X86_32 */ |
683 | ||
54168ed7 | 684 | /* |
05c3dc2c | 685 | * Saves all the IO-APIC RTE's |
54168ed7 | 686 | */ |
31dce14a | 687 | int save_ioapic_entries(void) |
54168ed7 | 688 | { |
54168ed7 | 689 | int apic, pin; |
31dce14a | 690 | int err = 0; |
54168ed7 | 691 | |
f44d1692 | 692 | for_each_ioapic(apic) { |
57a6f740 | 693 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
694 | err = -ENOMEM; |
695 | continue; | |
696 | } | |
54168ed7 | 697 | |
f44d1692 | 698 | for_each_pin(apic, pin) |
57a6f740 | 699 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 700 | ioapic_read_entry(apic, pin); |
b24696bc | 701 | } |
5ffa4eb2 | 702 | |
31dce14a | 703 | return err; |
54168ed7 IM |
704 | } |
705 | ||
b24696bc FY |
706 | /* |
707 | * Mask all IO APIC entries. | |
708 | */ | |
31dce14a | 709 | void mask_ioapic_entries(void) |
05c3dc2c SS |
710 | { |
711 | int apic, pin; | |
712 | ||
f44d1692 | 713 | for_each_ioapic(apic) { |
2f344d2e | 714 | if (!ioapics[apic].saved_registers) |
31dce14a | 715 | continue; |
b24696bc | 716 | |
f44d1692 | 717 | for_each_pin(apic, pin) { |
05c3dc2c SS |
718 | struct IO_APIC_route_entry entry; |
719 | ||
57a6f740 | 720 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
721 | if (!entry.mask) { |
722 | entry.mask = 1; | |
723 | ioapic_write_entry(apic, pin, entry); | |
724 | } | |
725 | } | |
726 | } | |
727 | } | |
728 | ||
b24696bc | 729 | /* |
57a6f740 | 730 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 731 | */ |
31dce14a | 732 | int restore_ioapic_entries(void) |
54168ed7 IM |
733 | { |
734 | int apic, pin; | |
735 | ||
f44d1692 | 736 | for_each_ioapic(apic) { |
2f344d2e | 737 | if (!ioapics[apic].saved_registers) |
31dce14a | 738 | continue; |
b24696bc | 739 | |
f44d1692 | 740 | for_each_pin(apic, pin) |
54168ed7 | 741 | ioapic_write_entry(apic, pin, |
57a6f740 | 742 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 743 | } |
b24696bc | 744 | return 0; |
54168ed7 IM |
745 | } |
746 | ||
1da177e4 LT |
747 | /* |
748 | * Find the IRQ entry number of a certain pin. | |
749 | */ | |
6f50d45f | 750 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
751 | { |
752 | int i; | |
753 | ||
754 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 755 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 756 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
757 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
758 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
759 | return i; |
760 | ||
761 | return -1; | |
762 | } | |
763 | ||
764 | /* | |
765 | * Find the pin to which IRQ[irq] (ISA) is connected | |
766 | */ | |
fcfd636a | 767 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
768 | { |
769 | int i; | |
770 | ||
771 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 772 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 773 | |
d27e2b8e | 774 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
775 | (mp_irqs[i].irqtype == type) && |
776 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 777 | |
c2c21745 | 778 | return mp_irqs[i].dstirq; |
1da177e4 LT |
779 | } |
780 | return -1; | |
781 | } | |
782 | ||
fcfd636a EB |
783 | static int __init find_isa_irq_apic(int irq, int type) |
784 | { | |
785 | int i; | |
786 | ||
787 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 788 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 789 | |
73b2961b | 790 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
791 | (mp_irqs[i].irqtype == type) && |
792 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
793 | break; |
794 | } | |
6f50d45f | 795 | |
fcfd636a | 796 | if (i < mp_irq_entries) { |
6f50d45f YL |
797 | int ioapic_idx; |
798 | ||
f44d1692 | 799 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
800 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
801 | return ioapic_idx; | |
fcfd636a EB |
802 | } |
803 | ||
804 | return -1; | |
805 | } | |
806 | ||
bb8187d3 | 807 | #ifdef CONFIG_EISA |
1da177e4 LT |
808 | /* |
809 | * EISA Edge/Level control register, ELCR | |
810 | */ | |
811 | static int EISA_ELCR(unsigned int irq) | |
812 | { | |
95d76acc | 813 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
814 | unsigned int port = 0x4d0 + (irq >> 3); |
815 | return (inb(port) >> (irq & 7)) & 1; | |
816 | } | |
817 | apic_printk(APIC_VERBOSE, KERN_INFO | |
818 | "Broken MPtable reports ISA irq %d\n", irq); | |
819 | return 0; | |
820 | } | |
54168ed7 | 821 | |
c0a282c2 | 822 | #endif |
1da177e4 | 823 | |
6728801d AS |
824 | /* ISA interrupts are always polarity zero edge triggered, |
825 | * when listed as conforming in the MP table. */ | |
826 | ||
827 | #define default_ISA_trigger(idx) (0) | |
828 | #define default_ISA_polarity(idx) (0) | |
829 | ||
1da177e4 LT |
830 | /* EISA interrupts are always polarity zero and can be edge or level |
831 | * trigger depending on the ELCR value. If an interrupt is listed as | |
832 | * EISA conforming in the MP table, that means its trigger type must | |
833 | * be read in from the ELCR */ | |
834 | ||
c2c21745 | 835 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 836 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
837 | |
838 | /* PCI interrupts are always polarity one level triggered, | |
839 | * when listed as conforming in the MP table. */ | |
840 | ||
841 | #define default_PCI_trigger(idx) (1) | |
842 | #define default_PCI_polarity(idx) (1) | |
843 | ||
b77cf6a8 | 844 | static int irq_polarity(int idx) |
1da177e4 | 845 | { |
c2c21745 | 846 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
847 | int polarity; |
848 | ||
849 | /* | |
850 | * Determine IRQ line polarity (high active or low active): | |
851 | */ | |
c2c21745 | 852 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 853 | { |
54168ed7 IM |
854 | case 0: /* conforms, ie. bus-type dependent polarity */ |
855 | if (test_bit(bus, mp_bus_not_pci)) | |
856 | polarity = default_ISA_polarity(idx); | |
857 | else | |
858 | polarity = default_PCI_polarity(idx); | |
859 | break; | |
860 | case 1: /* high active */ | |
861 | { | |
862 | polarity = 0; | |
863 | break; | |
864 | } | |
865 | case 2: /* reserved */ | |
866 | { | |
c767a54b | 867 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
868 | polarity = 1; |
869 | break; | |
870 | } | |
871 | case 3: /* low active */ | |
872 | { | |
873 | polarity = 1; | |
874 | break; | |
875 | } | |
876 | default: /* invalid */ | |
877 | { | |
c767a54b | 878 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
879 | polarity = 1; |
880 | break; | |
881 | } | |
1da177e4 LT |
882 | } |
883 | return polarity; | |
884 | } | |
885 | ||
b77cf6a8 | 886 | static int irq_trigger(int idx) |
1da177e4 | 887 | { |
c2c21745 | 888 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
889 | int trigger; |
890 | ||
891 | /* | |
892 | * Determine IRQ trigger mode (edge or level sensitive): | |
893 | */ | |
c2c21745 | 894 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 895 | { |
54168ed7 IM |
896 | case 0: /* conforms, ie. bus-type dependent */ |
897 | if (test_bit(bus, mp_bus_not_pci)) | |
898 | trigger = default_ISA_trigger(idx); | |
899 | else | |
900 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 901 | #ifdef CONFIG_EISA |
54168ed7 IM |
902 | switch (mp_bus_id_to_type[bus]) { |
903 | case MP_BUS_ISA: /* ISA pin */ | |
904 | { | |
905 | /* set before the switch */ | |
906 | break; | |
907 | } | |
908 | case MP_BUS_EISA: /* EISA pin */ | |
909 | { | |
910 | trigger = default_EISA_trigger(idx); | |
911 | break; | |
912 | } | |
913 | case MP_BUS_PCI: /* PCI pin */ | |
914 | { | |
915 | /* set before the switch */ | |
916 | break; | |
917 | } | |
54168ed7 IM |
918 | default: |
919 | { | |
c767a54b | 920 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
921 | trigger = 1; |
922 | break; | |
923 | } | |
924 | } | |
925 | #endif | |
1da177e4 | 926 | break; |
54168ed7 | 927 | case 1: /* edge */ |
1da177e4 | 928 | { |
54168ed7 | 929 | trigger = 0; |
1da177e4 LT |
930 | break; |
931 | } | |
54168ed7 | 932 | case 2: /* reserved */ |
1da177e4 | 933 | { |
c767a54b | 934 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 935 | trigger = 1; |
1da177e4 LT |
936 | break; |
937 | } | |
54168ed7 | 938 | case 3: /* level */ |
1da177e4 | 939 | { |
54168ed7 | 940 | trigger = 1; |
1da177e4 LT |
941 | break; |
942 | } | |
54168ed7 | 943 | default: /* invalid */ |
1da177e4 | 944 | { |
c767a54b | 945 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 946 | trigger = 0; |
1da177e4 LT |
947 | break; |
948 | } | |
949 | } | |
950 | return trigger; | |
951 | } | |
952 | ||
c4d05a2c JL |
953 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
954 | int trigger, int polarity) | |
955 | { | |
956 | init_irq_alloc_info(info, NULL); | |
957 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
958 | info->ioapic_node = node; | |
959 | info->ioapic_trigger = trigger; | |
960 | info->ioapic_polarity = polarity; | |
961 | info->ioapic_valid = 1; | |
962 | } | |
963 | ||
96ed44b2 JL |
964 | #ifndef CONFIG_ACPI |
965 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity); | |
966 | #endif | |
967 | ||
968 | static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst, | |
969 | struct irq_alloc_info *src, | |
970 | u32 gsi, int ioapic_idx, int pin) | |
971 | { | |
972 | int trigger, polarity; | |
973 | ||
974 | copy_irq_alloc_info(dst, src); | |
975 | dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
976 | dst->ioapic_id = mpc_ioapic_id(ioapic_idx); | |
977 | dst->ioapic_pin = pin; | |
978 | dst->ioapic_valid = 1; | |
979 | if (src && src->ioapic_valid) { | |
980 | dst->ioapic_node = src->ioapic_node; | |
981 | dst->ioapic_trigger = src->ioapic_trigger; | |
982 | dst->ioapic_polarity = src->ioapic_polarity; | |
983 | } else { | |
984 | dst->ioapic_node = NUMA_NO_NODE; | |
985 | if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { | |
986 | dst->ioapic_trigger = trigger; | |
987 | dst->ioapic_polarity = polarity; | |
988 | } else { | |
989 | /* | |
990 | * PCI interrupts are always polarity one level | |
991 | * triggered. | |
992 | */ | |
993 | dst->ioapic_trigger = 1; | |
994 | dst->ioapic_polarity = 1; | |
995 | } | |
996 | } | |
997 | } | |
998 | ||
999 | static int ioapic_alloc_attr_node(struct irq_alloc_info *info) | |
1000 | { | |
1001 | return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; | |
1002 | } | |
1003 | ||
49c7e600 JL |
1004 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
1005 | { | |
1006 | irq_flow_handler_t hdl; | |
1007 | bool fasteoi; | |
1008 | ||
1009 | if (trigger) { | |
1010 | irq_set_status_flags(irq, IRQ_LEVEL); | |
1011 | fasteoi = true; | |
1012 | } else { | |
1013 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
1014 | fasteoi = false; | |
1015 | } | |
1016 | ||
1017 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; | |
1018 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); | |
1019 | } | |
1020 | ||
96ed44b2 JL |
1021 | static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) |
1022 | { | |
1023 | struct mp_chip_data *data = irq_get_chip_data(irq); | |
1024 | ||
1025 | /* | |
1026 | * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger | |
1027 | * and polarity attirbutes. So allow the first user to reprogram the | |
1028 | * pin with real trigger and polarity attributes. | |
1029 | */ | |
1030 | if (irq < nr_legacy_irqs() && data->count == 1) { | |
1031 | if (info->ioapic_trigger != data->trigger) | |
1032 | mp_register_handler(irq, data->trigger); | |
1033 | data->entry.trigger = data->trigger = info->ioapic_trigger; | |
1034 | data->entry.polarity = data->polarity = info->ioapic_polarity; | |
1035 | } | |
1036 | ||
1037 | return data->trigger == info->ioapic_trigger && | |
1038 | data->polarity == info->ioapic_polarity; | |
1039 | } | |
1040 | ||
d32932d0 | 1041 | static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, |
c4d05a2c | 1042 | struct irq_alloc_info *info) |
6b9fb708 | 1043 | { |
d32932d0 | 1044 | bool legacy = false; |
d7f3d478 | 1045 | int irq = -1; |
d7f3d478 JL |
1046 | int type = ioapics[ioapic].irqdomain_cfg.type; |
1047 | ||
1048 | switch (type) { | |
1049 | case IOAPIC_DOMAIN_LEGACY: | |
1050 | /* | |
d32932d0 JL |
1051 | * Dynamically allocate IRQ number for non-ISA IRQs in the first |
1052 | * 16 GSIs on some weird platforms. | |
d7f3d478 | 1053 | */ |
d32932d0 | 1054 | if (!ioapic_initialized || gsi >= nr_legacy_irqs()) |
d7f3d478 | 1055 | irq = gsi; |
d32932d0 | 1056 | legacy = mp_is_legacy_irq(irq); |
d7f3d478 JL |
1057 | break; |
1058 | case IOAPIC_DOMAIN_STRICT: | |
d32932d0 | 1059 | irq = gsi; |
d7f3d478 JL |
1060 | break; |
1061 | case IOAPIC_DOMAIN_DYNAMIC: | |
d7f3d478 JL |
1062 | break; |
1063 | default: | |
1064 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
d32932d0 JL |
1065 | return -1; |
1066 | } | |
1067 | ||
1068 | return __irq_domain_alloc_irqs(domain, irq, 1, | |
1069 | ioapic_alloc_attr_node(info), | |
1070 | info, legacy); | |
1071 | } | |
1072 | ||
1073 | /* | |
1074 | * Need special handling for ISA IRQs because there may be multiple IOAPIC pins | |
1075 | * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping | |
1076 | * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are | |
1077 | * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
1078 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and | |
1079 | * some BIOSes may use MP Interrupt Source records to override IRQ numbers for | |
1080 | * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be | |
1081 | * multiple pins sharing the same legacy IRQ number when ACPI is disabled. | |
1082 | */ | |
1083 | static int alloc_isa_irq_from_domain(struct irq_domain *domain, | |
1084 | int irq, int ioapic, int pin, | |
1085 | struct irq_alloc_info *info) | |
1086 | { | |
1087 | struct mp_chip_data *data; | |
1088 | struct irq_data *irq_data = irq_get_irq_data(irq); | |
1089 | int node = ioapic_alloc_attr_node(info); | |
1090 | ||
1091 | /* | |
1092 | * Legacy ISA IRQ has already been allocated, just add pin to | |
1093 | * the pin list assoicated with this IRQ and program the IOAPIC | |
1094 | * entry. The IOAPIC entry | |
1095 | */ | |
1096 | if (irq_data && irq_data->parent_data) { | |
1097 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
1098 | ||
1099 | if (!mp_check_pin_attr(irq, info)) | |
1100 | return -EBUSY; | |
1101 | if (__add_pin_to_irq_node(cfg, node, ioapic, info->ioapic_pin)) | |
1102 | return -ENOMEM; | |
1103 | } else { | |
1104 | irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true); | |
1105 | if (irq >= 0) { | |
1106 | irq_data = irq_domain_get_irq_data(domain, irq); | |
1107 | data = irq_data->chip_data; | |
1108 | data->isa_irq = true; | |
1109 | } | |
d7f3d478 JL |
1110 | } |
1111 | ||
d32932d0 | 1112 | return irq; |
d7f3d478 JL |
1113 | } |
1114 | ||
1115 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
c4d05a2c | 1116 | unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1117 | { |
1118 | int irq; | |
d32932d0 JL |
1119 | bool legacy = false; |
1120 | struct irq_alloc_info tmp; | |
1121 | struct mp_chip_data *data; | |
d7f3d478 JL |
1122 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
1123 | ||
b81975ea | 1124 | if (!domain) |
d32932d0 | 1125 | return -ENOSYS; |
16ee7b3d | 1126 | |
16ee7b3d JL |
1127 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1128 | irq = mp_irqs[idx].srcbusirq; | |
d32932d0 JL |
1129 | legacy = mp_is_legacy_irq(irq); |
1130 | } | |
16ee7b3d | 1131 | |
d32932d0 JL |
1132 | mutex_lock(&ioapic_mutex); |
1133 | if (!(flags & IOAPIC_MAP_ALLOC)) { | |
1134 | if (!legacy) { | |
1135 | irq = irq_find_mapping(domain, pin); | |
16ee7b3d | 1136 | if (irq == 0) |
d32932d0 | 1137 | irq = -ENOENT; |
16ee7b3d JL |
1138 | } |
1139 | } else { | |
d32932d0 JL |
1140 | ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); |
1141 | if (legacy) | |
1142 | irq = alloc_isa_irq_from_domain(domain, irq, | |
1143 | ioapic, pin, &tmp); | |
1144 | else if ((irq = irq_find_mapping(domain, pin)) == 0) | |
1145 | irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp); | |
1146 | else if (!mp_check_pin_attr(irq, &tmp)) | |
1147 | irq = -EBUSY; | |
1148 | if (irq >= 0) { | |
1149 | data = irq_get_chip_data(irq); | |
1150 | data->count++; | |
1151 | } | |
15a3c7cc | 1152 | } |
d7f3d478 JL |
1153 | mutex_unlock(&ioapic_mutex); |
1154 | ||
d32932d0 | 1155 | return irq; |
6b9fb708 JL |
1156 | } |
1157 | ||
d7f3d478 | 1158 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1159 | { |
d7f3d478 | 1160 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1161 | |
1162 | /* | |
1163 | * Debugging check, we are in big trouble if this message pops up! | |
1164 | */ | |
c2c21745 | 1165 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1166 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1167 | |
54168ed7 | 1168 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1169 | /* |
1170 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1171 | */ | |
1172 | if ((pin >= 16) && (pin <= 23)) { | |
1173 | if (pirq_entries[pin-16] != -1) { | |
1174 | if (!pirq_entries[pin-16]) { | |
1175 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1176 | "disabling PIRQ%d\n", pin-16); | |
1177 | } else { | |
d7f3d478 | 1178 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1179 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1180 | "using PIRQ%d -> IRQ %d\n", | |
1181 | pin-16, irq); | |
6b9fb708 | 1182 | return irq; |
1da177e4 LT |
1183 | } |
1184 | } | |
1185 | } | |
54168ed7 IM |
1186 | #endif |
1187 | ||
c4d05a2c | 1188 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
d7f3d478 | 1189 | } |
6b9fb708 | 1190 | |
c4d05a2c JL |
1191 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
1192 | struct irq_alloc_info *info) | |
d7f3d478 JL |
1193 | { |
1194 | int ioapic, pin, idx; | |
1195 | ||
1196 | ioapic = mp_find_ioapic(gsi); | |
1197 | if (ioapic < 0) | |
1198 | return -1; | |
1199 | ||
1200 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1201 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1202 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
1203 | return -1; | |
1204 | ||
c4d05a2c | 1205 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
1da177e4 LT |
1206 | } |
1207 | ||
df334bea JL |
1208 | void mp_unmap_irq(int irq) |
1209 | { | |
d32932d0 JL |
1210 | struct irq_data *irq_data = irq_get_irq_data(irq); |
1211 | struct mp_chip_data *data; | |
df334bea | 1212 | |
d32932d0 | 1213 | if (!irq_data || !irq_data->domain) |
df334bea JL |
1214 | return; |
1215 | ||
d32932d0 JL |
1216 | data = irq_data->chip_data; |
1217 | if (!data || data->isa_irq) | |
1218 | return; | |
df334bea JL |
1219 | |
1220 | mutex_lock(&ioapic_mutex); | |
d32932d0 JL |
1221 | if (--data->count == 0) |
1222 | irq_domain_free_irqs(irq, 1); | |
df334bea JL |
1223 | mutex_unlock(&ioapic_mutex); |
1224 | } | |
1225 | ||
e20c06fd YL |
1226 | /* |
1227 | * Find a specific PCI IRQ entry. | |
1228 | * Not an __init, possibly needed by modules | |
1229 | */ | |
25d0d35e | 1230 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
e20c06fd | 1231 | { |
d7f3d478 | 1232 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1233 | |
1234 | apic_printk(APIC_DEBUG, | |
1235 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1236 | bus, slot, pin); | |
1237 | if (test_bit(bus, mp_bus_not_pci)) { | |
1238 | apic_printk(APIC_VERBOSE, | |
1239 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1240 | return -1; | |
1241 | } | |
79598505 | 1242 | |
e20c06fd YL |
1243 | for (i = 0; i < mp_irq_entries; i++) { |
1244 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1245 | int ioapic_idx, found = 0; |
1246 | ||
1247 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1248 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1249 | continue; | |
e20c06fd | 1250 | |
f44d1692 | 1251 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1252 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1253 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1254 | found = 1; | |
e20c06fd | 1255 | break; |
e20c06fd | 1256 | } |
79598505 JL |
1257 | if (!found) |
1258 | continue; | |
1259 | ||
1260 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1261 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1262 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1263 | continue; |
1264 | ||
1265 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1266 | best_idx = i; |
1267 | best_ioapic = ioapic_idx; | |
1268 | goto out; | |
79598505 | 1269 | } |
d7f3d478 | 1270 | |
79598505 JL |
1271 | /* |
1272 | * Use the first all-but-pin matching entry as a | |
1273 | * best-guess fuzzy result for broken mptables. | |
1274 | */ | |
d7f3d478 JL |
1275 | if (best_idx < 0) { |
1276 | best_idx = i; | |
1277 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1278 | } |
1279 | } | |
d7f3d478 JL |
1280 | if (best_idx < 0) |
1281 | return -1; | |
1282 | ||
1283 | out: | |
25d0d35e JL |
1284 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
1285 | IOAPIC_MAP_ALLOC); | |
e20c06fd YL |
1286 | } |
1287 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1288 | ||
d32932d0 | 1289 | static struct irq_chip ioapic_chip, ioapic_ir_chip; |
1da177e4 | 1290 | |
047c8fdb | 1291 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1292 | static inline int IO_APIC_irq_trigger(int irq) |
1293 | { | |
d6c88a50 | 1294 | int apic, idx, pin; |
1d025192 | 1295 | |
f44d1692 JL |
1296 | for_each_ioapic_pin(apic, pin) { |
1297 | idx = find_irq_entry(apic, pin, mp_INT); | |
d7f3d478 | 1298 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
f44d1692 | 1299 | return irq_trigger(idx); |
d6c88a50 TG |
1300 | } |
1301 | /* | |
54168ed7 IM |
1302 | * nonexistent IRQs are edge default |
1303 | */ | |
d6c88a50 | 1304 | return 0; |
1d025192 | 1305 | } |
047c8fdb YL |
1306 | #else |
1307 | static inline int IO_APIC_irq_trigger(int irq) | |
1308 | { | |
54168ed7 | 1309 | return 1; |
047c8fdb YL |
1310 | } |
1311 | #endif | |
1d025192 | 1312 | |
1a0e62a4 TG |
1313 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1314 | unsigned long trigger) | |
1da177e4 | 1315 | { |
c60eaf25 TG |
1316 | struct irq_chip *chip = &ioapic_chip; |
1317 | irq_flow_handler_t hdl; | |
1318 | bool fasteoi; | |
199751d7 | 1319 | |
6ebcc00e | 1320 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1321 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1322 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1323 | fasteoi = true; |
1324 | } else { | |
60c69948 | 1325 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1326 | fasteoi = false; |
1327 | } | |
047c8fdb | 1328 | |
2976fd84 | 1329 | if (setup_remapped_irq(irq, cfg, chip)) |
c60eaf25 | 1330 | fasteoi = trigger != 0; |
29b61be6 | 1331 | |
c60eaf25 TG |
1332 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1333 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1334 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1335 | } |
1336 | ||
a6a25dd3 JR |
1337 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1338 | unsigned int destination, int vector, | |
1339 | struct io_apic_irq_attr *attr) | |
c5b4712c | 1340 | { |
c5b4712c YL |
1341 | memset(entry, 0, sizeof(*entry)); |
1342 | ||
1343 | entry->delivery_mode = apic->irq_delivery_mode; | |
1344 | entry->dest_mode = apic->irq_dest_mode; | |
1345 | entry->dest = destination; | |
1346 | entry->vector = vector; | |
1347 | entry->mask = 0; /* enable IRQ */ | |
1348 | entry->trigger = attr->trigger; | |
1349 | entry->polarity = attr->polarity; | |
1350 | ||
1351 | /* | |
1352 | * Mask level triggered irqs. | |
497c9a19 YL |
1353 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1354 | */ | |
c5b4712c | 1355 | if (attr->trigger) |
497c9a19 | 1356 | entry->mask = 1; |
c5b4712c | 1357 | |
497c9a19 YL |
1358 | return 0; |
1359 | } | |
1360 | ||
e4aff811 YL |
1361 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1362 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1363 | { |
1da177e4 | 1364 | struct IO_APIC_route_entry entry; |
22f65d31 | 1365 | unsigned int dest; |
497c9a19 YL |
1366 | |
1367 | if (!IO_APIC_IRQ(irq)) | |
1368 | return; | |
f1c63001 | 1369 | |
fe402e1f | 1370 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1371 | return; |
1372 | ||
ff164324 AG |
1373 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1374 | &dest)) { | |
1375 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1376 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
b794ef26 | 1377 | clear_irq_vector(irq, cfg); |
ff164324 AG |
1378 | |
1379 | return; | |
1380 | } | |
497c9a19 YL |
1381 | |
1382 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1383 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1384 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1385 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1386 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1387 | |
a6a25dd3 JR |
1388 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
1389 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
c5b4712c | 1390 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
b794ef26 | 1391 | clear_irq_vector(irq, cfg); |
c5b4712c | 1392 | |
497c9a19 YL |
1393 | return; |
1394 | } | |
1395 | ||
e4aff811 | 1396 | ioapic_register_intr(irq, cfg, attr->trigger); |
95d76acc | 1397 | if (irq < nr_legacy_irqs()) |
4305df94 | 1398 | legacy_pic->mask(irq); |
497c9a19 | 1399 | |
e4aff811 | 1400 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1401 | } |
1402 | ||
ed972ccf TG |
1403 | static void __init setup_IO_APIC_irqs(void) |
1404 | { | |
16ee7b3d JL |
1405 | unsigned int ioapic, pin; |
1406 | int idx; | |
ed972ccf TG |
1407 | |
1408 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1409 | ||
16ee7b3d JL |
1410 | for_each_ioapic_pin(ioapic, pin) { |
1411 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1412 | if (idx < 0) | |
1413 | apic_printk(APIC_VERBOSE, | |
1414 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1415 | mpc_ioapic_id(ioapic), pin); | |
1416 | else | |
1417 | pin_2_irq(idx, ioapic, pin, | |
1418 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1419 | } | |
ed972ccf TG |
1420 | } |
1421 | ||
1da177e4 | 1422 | /* |
f7633ce5 | 1423 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1424 | */ |
6f50d45f | 1425 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1426 | unsigned int pin, int vector) |
1da177e4 LT |
1427 | { |
1428 | struct IO_APIC_route_entry entry; | |
ff164324 | 1429 | unsigned int dest; |
1da177e4 | 1430 | |
36062448 | 1431 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1432 | |
1433 | /* | |
1434 | * We use logical delivery to get the timer IRQ | |
1435 | * to the first CPU. | |
1436 | */ | |
a5a39156 AG |
1437 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1438 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1439 | dest = BAD_APICID; |
1440 | ||
9b5bc8dc | 1441 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1442 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1443 | entry.dest = dest; |
9b5bc8dc | 1444 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1445 | entry.polarity = 0; |
1446 | entry.trigger = 0; | |
1447 | entry.vector = vector; | |
1448 | ||
1449 | /* | |
1450 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1451 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1452 | */ |
2c778651 TG |
1453 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1454 | "edge"); | |
1da177e4 LT |
1455 | |
1456 | /* | |
1457 | * Add it to the IO-APIC irq-routing table: | |
1458 | */ | |
6f50d45f | 1459 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1460 | } |
1461 | ||
afcc8a40 JR |
1462 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1463 | { | |
1464 | int i; | |
1465 | ||
1466 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); | |
1467 | ||
1468 | for (i = 0; i <= nr_entries; i++) { | |
1469 | struct IO_APIC_route_entry entry; | |
1470 | ||
1471 | entry = ioapic_read_entry(apic, i); | |
1472 | ||
1473 | pr_debug(" %02x %02X ", i, entry.dest); | |
1474 | pr_cont("%1d %1d %1d %1d %1d " | |
1475 | "%1d %1d %02X\n", | |
1476 | entry.mask, | |
1477 | entry.trigger, | |
1478 | entry.irr, | |
1479 | entry.polarity, | |
1480 | entry.delivery_status, | |
1481 | entry.dest_mode, | |
1482 | entry.delivery_mode, | |
1483 | entry.vector); | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | void intel_ir_io_apic_print_entries(unsigned int apic, | |
1488 | unsigned int nr_entries) | |
1da177e4 | 1489 | { |
cda417dd | 1490 | int i; |
afcc8a40 JR |
1491 | |
1492 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); | |
1493 | ||
1494 | for (i = 0; i <= nr_entries; i++) { | |
1495 | struct IR_IO_APIC_route_entry *ir_entry; | |
1496 | struct IO_APIC_route_entry entry; | |
1497 | ||
1498 | entry = ioapic_read_entry(apic, i); | |
1499 | ||
1500 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; | |
1501 | ||
1502 | pr_debug(" %02x %04X ", i, ir_entry->index); | |
1503 | pr_cont("%1d %1d %1d %1d %1d " | |
1504 | "%1d %1d %X %02X\n", | |
1505 | ir_entry->format, | |
1506 | ir_entry->mask, | |
1507 | ir_entry->trigger, | |
1508 | ir_entry->irr, | |
1509 | ir_entry->polarity, | |
1510 | ir_entry->delivery_status, | |
1511 | ir_entry->index2, | |
1512 | ir_entry->zero, | |
1513 | ir_entry->vector); | |
1514 | } | |
1515 | } | |
1516 | ||
17405453 YY |
1517 | void ioapic_zap_locks(void) |
1518 | { | |
1519 | raw_spin_lock_init(&ioapic_lock); | |
1520 | } | |
1521 | ||
a44174ee JL |
1522 | static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1523 | { | |
1524 | int i; | |
1525 | char buf[256]; | |
1526 | struct IO_APIC_route_entry entry; | |
1527 | struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry; | |
1528 | ||
1529 | printk(KERN_DEBUG "IOAPIC %d:\n", apic); | |
1530 | for (i = 0; i <= nr_entries; i++) { | |
1531 | entry = ioapic_read_entry(apic, i); | |
1532 | snprintf(buf, sizeof(buf), | |
1533 | " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", | |
1534 | i, entry.mask ? "disabled" : "enabled ", | |
1535 | entry.trigger ? "level" : "edge ", | |
1536 | entry.polarity ? "low " : "high", | |
1537 | entry.vector, entry.irr, entry.delivery_status); | |
1538 | if (ir_entry->format) | |
1539 | printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", | |
1540 | buf, (ir_entry->index << 15) | ir_entry->index, | |
1541 | ir_entry->zero); | |
1542 | else | |
1543 | printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", | |
1544 | buf, entry.dest_mode ? "logical " : "physical", | |
1545 | entry.dest, entry.delivery_mode); | |
1546 | } | |
1547 | } | |
1548 | ||
74afab7a | 1549 | static void __init print_IO_APIC(int ioapic_idx) |
afcc8a40 | 1550 | { |
1da177e4 LT |
1551 | union IO_APIC_reg_00 reg_00; |
1552 | union IO_APIC_reg_01 reg_01; | |
1553 | union IO_APIC_reg_02 reg_02; | |
1554 | union IO_APIC_reg_03 reg_03; | |
1555 | unsigned long flags; | |
1da177e4 | 1556 | |
dade7716 | 1557 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1558 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1559 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1560 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1561 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1562 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1563 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1564 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1565 | |
6f50d45f | 1566 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1567 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1568 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1569 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1570 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1571 | |
54168ed7 | 1572 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1573 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1574 | reg_01.bits.entries); | |
1da177e4 LT |
1575 | |
1576 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1577 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1578 | reg_01.bits.version); | |
1da177e4 LT |
1579 | |
1580 | /* | |
1581 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1582 | * but the value of reg_02 is read as the previous read register | |
1583 | * value, so ignore it if reg_02 == reg_01. | |
1584 | */ | |
1585 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1586 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1587 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1588 | } |
1589 | ||
1590 | /* | |
1591 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1592 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1593 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1594 | */ | |
1595 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1596 | reg_03.raw != reg_01.raw) { | |
1597 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1598 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1599 | } |
1600 | ||
1601 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
a44174ee | 1602 | io_apic_print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1603 | } |
1604 | ||
74afab7a | 1605 | void __init print_IO_APICs(void) |
cda417dd | 1606 | { |
6f50d45f | 1607 | int ioapic_idx; |
cda417dd YL |
1608 | struct irq_cfg *cfg; |
1609 | unsigned int irq; | |
6fd36ba0 | 1610 | struct irq_chip *chip; |
cda417dd YL |
1611 | |
1612 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1613 | for_each_ioapic(ioapic_idx) |
cda417dd | 1614 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1615 | mpc_ioapic_id(ioapic_idx), |
1616 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1617 | |
1618 | /* | |
1619 | * We are a bit conservative about what we expect. We have to | |
1620 | * know about every hardware change ASAP. | |
1621 | */ | |
1622 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1623 | ||
f44d1692 | 1624 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1625 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1626 | |
1da177e4 | 1627 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1628 | for_each_active_irq(irq) { |
0b8f1efa YL |
1629 | struct irq_pin_list *entry; |
1630 | ||
6fd36ba0 | 1631 | chip = irq_get_chip(irq); |
d32932d0 | 1632 | if (chip != &ioapic_chip && chip != &ioapic_ir_chip) |
6fd36ba0 MN |
1633 | continue; |
1634 | ||
32f5ef5d | 1635 | cfg = irq_cfg(irq); |
05e40760 DK |
1636 | if (!cfg) |
1637 | continue; | |
a178b87b | 1638 | if (list_empty(&cfg->irq_2_pin)) |
1da177e4 | 1639 | continue; |
8f09cd20 | 1640 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1641 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1642 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1643 | pr_cont("\n"); | |
1da177e4 LT |
1644 | } |
1645 | ||
1646 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1647 | } |
1648 | ||
efa2559f YL |
1649 | /* Where if anywhere is the i8259 connect in external int mode */ |
1650 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1651 | ||
54168ed7 | 1652 | void __init enable_IO_APIC(void) |
1da177e4 | 1653 | { |
fcfd636a | 1654 | int i8259_apic, i8259_pin; |
f44d1692 | 1655 | int apic, pin; |
bc07844a | 1656 | |
a46f5c89 TG |
1657 | if (skip_ioapic_setup) |
1658 | nr_ioapics = 0; | |
1659 | ||
1660 | if (!nr_legacy_irqs() || !nr_ioapics) | |
bc07844a TG |
1661 | return; |
1662 | ||
f44d1692 | 1663 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1664 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1665 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1666 | |
f44d1692 JL |
1667 | /* If the interrupt line is enabled and in ExtInt mode |
1668 | * I have found the pin where the i8259 is connected. | |
1669 | */ | |
1670 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1671 | ioapic_i8259.apic = apic; | |
1672 | ioapic_i8259.pin = pin; | |
1673 | goto found_i8259; | |
fcfd636a EB |
1674 | } |
1675 | } | |
1676 | found_i8259: | |
1677 | /* Look to see what if the MP table has reported the ExtINT */ | |
1678 | /* If we could not find the appropriate pin by looking at the ioapic | |
1679 | * the i8259 probably is not connected the ioapic but give the | |
1680 | * mptable a chance anyway. | |
1681 | */ | |
1682 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1683 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1684 | /* Trust the MP table if nothing is setup in the hardware */ | |
1685 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1686 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1687 | ioapic_i8259.pin = i8259_pin; | |
1688 | ioapic_i8259.apic = i8259_apic; | |
1689 | } | |
1690 | /* Complain if the MP table and the hardware disagree */ | |
1691 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1692 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1693 | { | |
1694 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1695 | } |
1696 | ||
1697 | /* | |
1698 | * Do not trust the IO-APIC being empty at bootup | |
1699 | */ | |
1700 | clear_IO_APIC(); | |
1701 | } | |
1702 | ||
1c4248ca | 1703 | void native_disable_io_apic(void) |
1da177e4 | 1704 | { |
650927ef | 1705 | /* |
0b968d23 | 1706 | * If the i8259 is routed through an IOAPIC |
650927ef | 1707 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1708 | * so legacy interrupts can be delivered. |
650927ef | 1709 | */ |
1c4248ca | 1710 | if (ioapic_i8259.pin != -1) { |
650927ef | 1711 | struct IO_APIC_route_entry entry; |
650927ef EB |
1712 | |
1713 | memset(&entry, 0, sizeof(entry)); | |
1714 | entry.mask = 0; /* Enabled */ | |
1715 | entry.trigger = 0; /* Edge */ | |
1716 | entry.irr = 0; | |
1717 | entry.polarity = 0; /* High */ | |
1718 | entry.delivery_status = 0; | |
1719 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1720 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1721 | entry.vector = 0; |
54168ed7 | 1722 | entry.dest = read_apic_id(); |
650927ef EB |
1723 | |
1724 | /* | |
1725 | * Add it to the IO-APIC irq-routing table: | |
1726 | */ | |
cf4c6a2f | 1727 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1728 | } |
54168ed7 | 1729 | |
1c4248ca JR |
1730 | if (cpu_has_apic || apic_from_smp_config()) |
1731 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1732 | ||
1733 | } | |
1734 | ||
1735 | /* | |
1736 | * Not an __init, needed by the reboot code | |
1737 | */ | |
1738 | void disable_IO_APIC(void) | |
1739 | { | |
7c6d9f97 | 1740 | /* |
1c4248ca | 1741 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1742 | */ |
1c4248ca JR |
1743 | clear_IO_APIC(); |
1744 | ||
95d76acc | 1745 | if (!nr_legacy_irqs()) |
1c4248ca JR |
1746 | return; |
1747 | ||
1748 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1749 | } |
1750 | ||
54168ed7 | 1751 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1752 | /* |
1753 | * function to set the IO-APIC physical IDs based on the | |
1754 | * values stored in the MPC table. | |
1755 | * | |
1756 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1757 | */ | |
a38c5380 | 1758 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1759 | { |
1760 | union IO_APIC_reg_00 reg_00; | |
1761 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1762 | int ioapic_idx; |
1da177e4 LT |
1763 | int i; |
1764 | unsigned char old_id; | |
1765 | unsigned long flags; | |
1766 | ||
1767 | /* | |
1768 | * This is broken; anything with a real cpu count has to | |
1769 | * circumvent this idiocy regardless. | |
1770 | */ | |
7abc0753 | 1771 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1772 | |
1773 | /* | |
1774 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1775 | */ | |
f44d1692 | 1776 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1777 | /* Read the register 0 value */ |
dade7716 | 1778 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1779 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1780 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1781 | |
6f50d45f | 1782 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1783 | |
6f50d45f | 1784 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1785 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1786 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1787 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1788 | reg_00.bits.ID); | |
6f50d45f | 1789 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1790 | } |
1791 | ||
1da177e4 LT |
1792 | /* |
1793 | * Sanity check, is the ID really free? Every APIC in a | |
1794 | * system must have a unique ID or we get lots of nice | |
1795 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1796 | */ | |
7abc0753 | 1797 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1798 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1799 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1800 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1801 | for (i = 0; i < get_physical_broadcast(); i++) |
1802 | if (!physid_isset(i, phys_id_present_map)) | |
1803 | break; | |
1804 | if (i >= get_physical_broadcast()) | |
1805 | panic("Max APIC ID exceeded!\n"); | |
1806 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1807 | i); | |
1808 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1809 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1810 | } else { |
1811 | physid_mask_t tmp; | |
6f50d45f | 1812 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1813 | &tmp); |
1da177e4 LT |
1814 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1815 | "phys_id_present_map\n", | |
6f50d45f | 1816 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1817 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1818 | } | |
1819 | ||
1da177e4 LT |
1820 | /* |
1821 | * We need to adjust the IRQ routing table | |
1822 | * if the ID changed. | |
1823 | */ | |
6f50d45f | 1824 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 1825 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1826 | if (mp_irqs[i].dstapic == old_id) |
1827 | mp_irqs[i].dstapic | |
6f50d45f | 1828 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
1829 | |
1830 | /* | |
60d79fd9 YL |
1831 | * Update the ID register according to the right value |
1832 | * from the MPC table if they are different. | |
36062448 | 1833 | */ |
6f50d45f | 1834 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
1835 | continue; |
1836 | ||
1da177e4 LT |
1837 | apic_printk(APIC_VERBOSE, KERN_INFO |
1838 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 1839 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 1840 | |
6f50d45f | 1841 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 1842 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1843 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 1844 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1845 | |
1846 | /* | |
1847 | * Sanity check | |
1848 | */ | |
dade7716 | 1849 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1850 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1851 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 1852 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 1853 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
1854 | else |
1855 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1856 | } | |
1857 | } | |
a38c5380 SAS |
1858 | |
1859 | void __init setup_ioapic_ids_from_mpc(void) | |
1860 | { | |
1861 | ||
1862 | if (acpi_ioapic) | |
1863 | return; | |
1864 | /* | |
1865 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1866 | * no meaning without the serial APIC bus. | |
1867 | */ | |
1868 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
1869 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
1870 | return; | |
1871 | setup_ioapic_ids_from_mpc_nocheck(); | |
1872 | } | |
54168ed7 | 1873 | #endif |
1da177e4 | 1874 | |
7ce0bcfd | 1875 | int no_timer_check __initdata; |
8542b200 ZA |
1876 | |
1877 | static int __init notimercheck(char *s) | |
1878 | { | |
1879 | no_timer_check = 1; | |
1880 | return 1; | |
1881 | } | |
1882 | __setup("no_timer_check", notimercheck); | |
1883 | ||
1da177e4 LT |
1884 | /* |
1885 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1886 | * about the timer IRQ. We do the following to work around the situation: | |
1887 | * | |
1888 | * - timer IRQ defaults to IO-APIC IRQ | |
1889 | * - if this function detects that timer IRQs are defunct, then we fall | |
1890 | * back to ISA timer IRQs | |
1891 | */ | |
f0a7a5c9 | 1892 | static int __init timer_irq_works(void) |
1da177e4 LT |
1893 | { |
1894 | unsigned long t1 = jiffies; | |
4aae0702 | 1895 | unsigned long flags; |
1da177e4 | 1896 | |
8542b200 ZA |
1897 | if (no_timer_check) |
1898 | return 1; | |
1899 | ||
4aae0702 | 1900 | local_save_flags(flags); |
1da177e4 LT |
1901 | local_irq_enable(); |
1902 | /* Let ten ticks pass... */ | |
1903 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1904 | local_irq_restore(flags); |
1da177e4 LT |
1905 | |
1906 | /* | |
1907 | * Expect a few ticks at least, to be sure some possible | |
1908 | * glue logic does not lock up after one or two first | |
1909 | * ticks in a non-ExtINT mode. Also the local APIC | |
1910 | * might have cached one ExtINT interrupt. Finally, at | |
1911 | * least one tick may be lost due to delays. | |
1912 | */ | |
54168ed7 IM |
1913 | |
1914 | /* jiffies wrap? */ | |
1d16b53e | 1915 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 1916 | return 1; |
1da177e4 LT |
1917 | return 0; |
1918 | } | |
1919 | ||
1920 | /* | |
1921 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1922 | * number of pending IRQ events unhandled. These cases are very rare, | |
1923 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1924 | * better to do it this way as thus we do not have to be aware of | |
1925 | * 'pending' interrupts in the IRQ path, except at this point. | |
1926 | */ | |
1927 | /* | |
1928 | * Edge triggered needs to resend any interrupt | |
1929 | * that was delayed but this is now handled in the device | |
1930 | * independent code. | |
1931 | */ | |
1932 | ||
1933 | /* | |
1934 | * Starting up a edge-triggered IO-APIC interrupt is | |
1935 | * nasty - we need to make sure that we get the edge. | |
1936 | * If it is already asserted for some reason, we need | |
1937 | * return 1 to indicate that is was pending. | |
1938 | * | |
1939 | * This is not complete - we should be able to fake | |
1940 | * an edge even if it isn't on the 8259A... | |
1941 | */ | |
54168ed7 | 1942 | |
61a38ce3 | 1943 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 1944 | { |
61a38ce3 | 1945 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
1946 | unsigned long flags; |
1947 | ||
dade7716 | 1948 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 1949 | if (irq < nr_legacy_irqs()) { |
4305df94 | 1950 | legacy_pic->mask(irq); |
b81bb373 | 1951 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
1952 | was_pending = 1; |
1953 | } | |
a9786091 | 1954 | __unmask_ioapic(irqd_cfg(data)); |
dade7716 | 1955 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1956 | |
1957 | return was_pending; | |
1958 | } | |
1959 | ||
54168ed7 IM |
1960 | /* |
1961 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1962 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1963 | * handled with the level-triggered descriptor, but that one has slightly | |
1964 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1965 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1966 | * races. | |
1967 | */ | |
497c9a19 | 1968 | |
7eb9ae07 SS |
1969 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
1970 | { | |
1971 | int apic, pin; | |
1972 | struct irq_pin_list *entry; | |
1973 | u8 vector = cfg->vector; | |
1974 | ||
1975 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
1976 | unsigned int reg; | |
1977 | ||
1978 | apic = entry->apic; | |
1979 | pin = entry->pin; | |
9f9d39e4 JR |
1980 | |
1981 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
1982 | reg = io_apic_read(apic, 0x10 + pin*2); |
1983 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
1984 | reg |= vector; | |
1985 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
1986 | } | |
1987 | } | |
1988 | ||
373dd7a2 JR |
1989 | int native_ioapic_set_affinity(struct irq_data *data, |
1990 | const struct cpumask *mask, | |
1991 | bool force) | |
7eb9ae07 SS |
1992 | { |
1993 | unsigned int dest, irq = data->irq; | |
1994 | unsigned long flags; | |
1995 | int ret; | |
1996 | ||
1997 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 1998 | return -EPERM; |
7eb9ae07 SS |
1999 | |
2000 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
cb39288c | 2001 | ret = apic_set_affinity(data, mask, &dest); |
7eb9ae07 SS |
2002 | if (!ret) { |
2003 | /* Only the high 8 bits are valid. */ | |
2004 | dest = SET_APIC_LOGICAL_ID(dest); | |
a9786091 | 2005 | __target_IO_APIC_irq(irq, dest, irqd_cfg(data)); |
7eb9ae07 SS |
2006 | ret = IRQ_SET_MASK_OK_NOCOPY; |
2007 | } | |
2008 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2009 | return ret; | |
2010 | } | |
2011 | ||
3eb2cce8 | 2012 | atomic_t irq_mis_count; |
3eb2cce8 | 2013 | |
047c8fdb | 2014 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
2015 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
2016 | { | |
2017 | struct irq_pin_list *entry; | |
2018 | unsigned long flags; | |
2019 | ||
2020 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2021 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2022 | unsigned int reg; | |
2023 | int pin; | |
2024 | ||
2025 | pin = entry->pin; | |
2026 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
2027 | /* Is the remote IRR bit set? */ | |
2028 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
2029 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2030 | return true; | |
2031 | } | |
2032 | } | |
2033 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2034 | ||
2035 | return false; | |
2036 | } | |
2037 | ||
4da7072a AG |
2038 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
2039 | { | |
54168ed7 | 2040 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2041 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 2042 | mask_ioapic(cfg); |
4da7072a | 2043 | return true; |
54168ed7 | 2044 | } |
4da7072a AG |
2045 | return false; |
2046 | } | |
2047 | ||
2048 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2049 | struct irq_cfg *cfg, bool masked) | |
2050 | { | |
2051 | if (unlikely(masked)) { | |
2052 | /* Only migrate the irq if the ack has been received. | |
2053 | * | |
2054 | * On rare occasions the broadcast level triggered ack gets | |
2055 | * delayed going to ioapics, and if we reprogram the | |
2056 | * vector while Remote IRR is still set the irq will never | |
2057 | * fire again. | |
2058 | * | |
2059 | * To prevent this scenario we read the Remote IRR bit | |
2060 | * of the ioapic. This has two effects. | |
2061 | * - On any sane system the read of the ioapic will | |
2062 | * flush writes (and acks) going to the ioapic from | |
2063 | * this cpu. | |
2064 | * - We get to see if the ACK has actually been delivered. | |
2065 | * | |
2066 | * Based on failed experiments of reprogramming the | |
2067 | * ioapic entry from outside of irq context starting | |
2068 | * with masking the ioapic entry and then polling until | |
2069 | * Remote IRR was clear before reprogramming the | |
2070 | * ioapic I don't trust the Remote IRR bit to be | |
2071 | * completey accurate. | |
2072 | * | |
2073 | * However there appears to be no other way to plug | |
2074 | * this race, so if the Remote IRR bit is not | |
2075 | * accurate and is causing problems then it is a hardware bug | |
2076 | * and you can go talk to the chipset vendor about it. | |
2077 | */ | |
2078 | if (!io_apic_level_ack_pending(cfg)) | |
2079 | irq_move_masked_irq(data); | |
2080 | unmask_ioapic(cfg); | |
2081 | } | |
2082 | } | |
2083 | #else | |
2084 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
2085 | { | |
2086 | return false; | |
2087 | } | |
2088 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2089 | struct irq_cfg *cfg, bool masked) | |
2090 | { | |
2091 | } | |
047c8fdb YL |
2092 | #endif |
2093 | ||
d32932d0 | 2094 | static void ioapic_ack_level(struct irq_data *data) |
4da7072a | 2095 | { |
a9786091 | 2096 | struct irq_cfg *cfg = irqd_cfg(data); |
4da7072a AG |
2097 | unsigned long v; |
2098 | bool masked; | |
d32932d0 | 2099 | int i; |
4da7072a AG |
2100 | |
2101 | irq_complete_move(cfg); | |
2102 | masked = ioapic_irqd_mask(data, cfg); | |
2103 | ||
3eb2cce8 | 2104 | /* |
916a0fe7 JF |
2105 | * It appears there is an erratum which affects at least version 0x11 |
2106 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2107 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2108 | * erroneously delivered as edge-triggered one but the respective IRR | |
2109 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2110 | * message but it will never arrive and further interrupts are blocked | |
2111 | * from the source. The exact reason is so far unknown, but the | |
2112 | * phenomenon was observed when two consecutive interrupt requests | |
2113 | * from a given source get delivered to the same CPU and the source is | |
2114 | * temporarily disabled in between. | |
2115 | * | |
2116 | * A workaround is to simulate an EOI message manually. We achieve it | |
2117 | * by setting the trigger mode to edge and then to level when the edge | |
2118 | * trigger mode gets detected in the TMR of a local APIC for a | |
2119 | * level-triggered interrupt. We mask the source for the time of the | |
2120 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2121 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2122 | * |
2123 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2124 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2125 | * destination that is handling the corresponding interrupt. This | |
2126 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2127 | * level-triggered io-apic interrupt will be seen as an edge | |
2128 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2129 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2130 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2131 | * supporting EOI register, we do an explicit EOI to clear the | |
2132 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2133 | * we use the above logic (mask+edge followed by unmask+level) from | |
2134 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2135 | */ |
3145e941 | 2136 | i = cfg->vector; |
3eb2cce8 | 2137 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2138 | |
54168ed7 IM |
2139 | /* |
2140 | * We must acknowledge the irq before we move it or the acknowledge will | |
2141 | * not propagate properly. | |
2142 | */ | |
2143 | ack_APIC_irq(); | |
2144 | ||
1c83995b SS |
2145 | /* |
2146 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2147 | * message via io-apic EOI register write or simulating it using | |
2148 | * mask+edge followed by unnask+level logic) manually when the | |
2149 | * level triggered interrupt is seen as the edge triggered interrupt | |
2150 | * at the cpu. | |
2151 | */ | |
ca64c47c MR |
2152 | if (!(v & (1 << (i & 0x1f)))) { |
2153 | atomic_inc(&irq_mis_count); | |
d32932d0 | 2154 | eoi_ioapic_pin(cfg->vector, cfg); |
ca64c47c MR |
2155 | } |
2156 | ||
4da7072a | 2157 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2158 | } |
1d025192 | 2159 | |
d32932d0 JL |
2160 | static void ioapic_ir_ack_level(struct irq_data *irq_data) |
2161 | { | |
2162 | struct mp_chip_data *data = irq_data->chip_data; | |
2163 | ||
2164 | /* | |
2165 | * Intr-remapping uses pin number as the virtual vector | |
2166 | * in the RTE. Actual vector is programmed in | |
2167 | * intr-remapping table entry. Hence for the io-apic | |
2168 | * EOI we use the pin number. | |
2169 | */ | |
2170 | ack_APIC_irq(); | |
2171 | eoi_ioapic_pin(data->entry.vector, irqd_cfg(irq_data)); | |
2172 | } | |
2173 | ||
2174 | static int ioapic_set_affinity(struct irq_data *irq_data, | |
2175 | const struct cpumask *mask, bool force) | |
2176 | { | |
2177 | struct irq_data *parent = irq_data->parent_data; | |
2178 | struct mp_chip_data *data = irq_data->chip_data; | |
2179 | unsigned int dest, irq = irq_data->irq; | |
2180 | struct irq_cfg *cfg; | |
2181 | unsigned long flags; | |
2182 | int ret; | |
2183 | ||
2184 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
2185 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2186 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { | |
2187 | cfg = irqd_cfg(irq_data); | |
2188 | data->entry.dest = cfg->dest_apicid; | |
2189 | data->entry.vector = cfg->vector; | |
2190 | /* Only the high 8 bits are valid. */ | |
2191 | dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid); | |
2192 | __target_IO_APIC_irq(irq, dest, cfg); | |
2193 | } | |
2194 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2195 | ||
2196 | return ret; | |
2197 | } | |
2198 | ||
f5b9ed7a | 2199 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2200 | .name = "IO-APIC", |
2201 | .irq_startup = startup_ioapic_irq, | |
2202 | .irq_mask = mask_ioapic_irq, | |
2203 | .irq_unmask = unmask_ioapic_irq, | |
d32932d0 JL |
2204 | .irq_ack = irq_chip_ack_parent, |
2205 | .irq_eoi = ioapic_ack_level, | |
2206 | .irq_set_affinity = ioapic_set_affinity, | |
2207 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
2208 | }; | |
2209 | ||
2210 | static struct irq_chip ioapic_ir_chip __read_mostly = { | |
2211 | .name = "IR-IO-APIC", | |
2212 | .irq_startup = startup_ioapic_irq, | |
2213 | .irq_mask = mask_ioapic_irq, | |
2214 | .irq_unmask = unmask_ioapic_irq, | |
2215 | .irq_ack = irq_chip_ack_parent, | |
2216 | .irq_eoi = ioapic_ir_ack_level, | |
2217 | .irq_set_affinity = ioapic_set_affinity, | |
5613570b | 2218 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
2219 | }; |
2220 | ||
1da177e4 LT |
2221 | static inline void init_IO_APIC_traps(void) |
2222 | { | |
da51a821 | 2223 | struct irq_cfg *cfg; |
ad9f4334 | 2224 | unsigned int irq; |
1da177e4 | 2225 | |
ad9f4334 | 2226 | for_each_active_irq(irq) { |
32f5ef5d | 2227 | cfg = irq_cfg(irq); |
0b8f1efa | 2228 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2229 | /* |
2230 | * Hmm.. We don't have an entry for this, | |
2231 | * so default to an old-fashioned 8259 | |
2232 | * interrupt if we can.. | |
2233 | */ | |
95d76acc | 2234 | if (irq < nr_legacy_irqs()) |
b81bb373 | 2235 | legacy_pic->make_irq(irq); |
0b8f1efa | 2236 | else |
1da177e4 | 2237 | /* Strange. Oh, well.. */ |
2c778651 | 2238 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2239 | } |
2240 | } | |
2241 | } | |
2242 | ||
f5b9ed7a IM |
2243 | /* |
2244 | * The local APIC irq-chip implementation: | |
2245 | */ | |
1da177e4 | 2246 | |
90297c5f | 2247 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2248 | { |
2249 | unsigned long v; | |
2250 | ||
2251 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2252 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2253 | } |
2254 | ||
90297c5f | 2255 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2256 | { |
f5b9ed7a | 2257 | unsigned long v; |
1da177e4 | 2258 | |
f5b9ed7a | 2259 | v = apic_read(APIC_LVT0); |
593f4a78 | 2260 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2261 | } |
1da177e4 | 2262 | |
90297c5f | 2263 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2264 | { |
2265 | ack_APIC_irq(); | |
2266 | } | |
2267 | ||
f5b9ed7a | 2268 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2269 | .name = "local-APIC", |
90297c5f TG |
2270 | .irq_mask = mask_lapic_irq, |
2271 | .irq_unmask = unmask_lapic_irq, | |
2272 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2273 | }; |
2274 | ||
60c69948 | 2275 | static void lapic_register_intr(int irq) |
c88ac1df | 2276 | { |
60c69948 | 2277 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2278 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2279 | "edge"); |
c88ac1df MR |
2280 | } |
2281 | ||
1da177e4 LT |
2282 | /* |
2283 | * This looks a bit hackish but it's about the only one way of sending | |
2284 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2285 | * not support the ExtINT mode, unfortunately. We need to send these | |
2286 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2287 | * 8259A interrupt line asserted until INTA. --macro | |
2288 | */ | |
28acf285 | 2289 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2290 | { |
fcfd636a | 2291 | int apic, pin, i; |
1da177e4 LT |
2292 | struct IO_APIC_route_entry entry0, entry1; |
2293 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2294 | |
fcfd636a | 2295 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2296 | if (pin == -1) { |
2297 | WARN_ON_ONCE(1); | |
2298 | return; | |
2299 | } | |
fcfd636a | 2300 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2301 | if (apic == -1) { |
2302 | WARN_ON_ONCE(1); | |
1da177e4 | 2303 | return; |
956fb531 | 2304 | } |
1da177e4 | 2305 | |
cf4c6a2f | 2306 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2307 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2308 | |
2309 | memset(&entry1, 0, sizeof(entry1)); | |
2310 | ||
2311 | entry1.dest_mode = 0; /* physical delivery */ | |
2312 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2313 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2314 | entry1.delivery_mode = dest_ExtINT; |
2315 | entry1.polarity = entry0.polarity; | |
2316 | entry1.trigger = 0; | |
2317 | entry1.vector = 0; | |
2318 | ||
cf4c6a2f | 2319 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2320 | |
2321 | save_control = CMOS_READ(RTC_CONTROL); | |
2322 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2323 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2324 | RTC_FREQ_SELECT); | |
2325 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2326 | ||
2327 | i = 100; | |
2328 | while (i-- > 0) { | |
2329 | mdelay(10); | |
2330 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2331 | i -= 10; | |
2332 | } | |
2333 | ||
2334 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2335 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2336 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2337 | |
cf4c6a2f | 2338 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2339 | } |
2340 | ||
efa2559f | 2341 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2342 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2343 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2344 | { |
2345 | disable_timer_pin_1 = 1; | |
2346 | return 0; | |
2347 | } | |
54168ed7 | 2348 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2349 | |
d32932d0 JL |
2350 | static int mp_alloc_timer_irq(int ioapic, int pin) |
2351 | { | |
2352 | int irq = -1; | |
2353 | struct irq_alloc_info info; | |
2354 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); | |
2355 | ||
2356 | if (domain) { | |
2357 | ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); | |
2358 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2359 | info.ioapic_pin = pin; | |
2360 | mutex_lock(&ioapic_mutex); | |
2361 | irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); | |
2362 | mutex_unlock(&ioapic_mutex); | |
2363 | } | |
2364 | ||
2365 | return irq; | |
2366 | } | |
2367 | ||
1da177e4 LT |
2368 | /* |
2369 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2370 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2371 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2372 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2373 | * |
2374 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2375 | */ |
8542b200 | 2376 | static inline void __init check_timer(void) |
1da177e4 | 2377 | { |
32f5ef5d | 2378 | struct irq_cfg *cfg = irq_cfg(0); |
f6e9456c | 2379 | int node = cpu_to_node(0); |
fcfd636a | 2380 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2381 | unsigned long flags; |
047c8fdb | 2382 | int no_pin1 = 0; |
4aae0702 IM |
2383 | |
2384 | local_irq_save(flags); | |
d4d25dec | 2385 | |
1da177e4 LT |
2386 | /* |
2387 | * get/set the timer IRQ vector: | |
2388 | */ | |
4305df94 | 2389 | legacy_pic->mask(0); |
1da177e4 LT |
2390 | |
2391 | /* | |
d11d5794 MR |
2392 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2393 | * wire has to be disabled in the local APIC. Also | |
2394 | * timer interrupts need to be acknowledged manually in | |
2395 | * the 8259A for the i82489DX when using the NMI | |
2396 | * watchdog as that APIC treats NMIs as level-triggered. | |
2397 | * The AEOI mode will finish them in the 8259A | |
2398 | * automatically. | |
1da177e4 | 2399 | */ |
593f4a78 | 2400 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2401 | legacy_pic->init(1); |
1da177e4 | 2402 | |
fcfd636a EB |
2403 | pin1 = find_isa_irq_pin(0, mp_INT); |
2404 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2405 | pin2 = ioapic_i8259.pin; | |
2406 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2407 | |
49a66a0b MR |
2408 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2409 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2410 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2411 | |
691874fa MR |
2412 | /* |
2413 | * Some BIOS writers are clueless and report the ExtINTA | |
2414 | * I/O APIC input from the cascaded 8259A as the timer | |
2415 | * interrupt input. So just in case, if only one pin | |
2416 | * was found above, try it both directly and through the | |
2417 | * 8259A. | |
2418 | */ | |
2419 | if (pin1 == -1) { | |
6a9f5de2 | 2420 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2421 | pin1 = pin2; |
2422 | apic1 = apic2; | |
2423 | no_pin1 = 1; | |
2424 | } else if (pin2 == -1) { | |
2425 | pin2 = pin1; | |
2426 | apic2 = apic1; | |
2427 | } | |
2428 | ||
1da177e4 | 2429 | if (pin1 != -1) { |
d32932d0 | 2430 | /* Ok, does IRQ0 through the IOAPIC work? */ |
691874fa | 2431 | if (no_pin1) { |
d32932d0 | 2432 | mp_alloc_timer_irq(apic1, pin1); |
f72dccac | 2433 | } else { |
d32932d0 JL |
2434 | /* |
2435 | * for edge trigger, it's already unmasked, | |
f72dccac YL |
2436 | * so only need to unmask if it is level-trigger |
2437 | * do we really have level trigger timer? | |
2438 | */ | |
2439 | int idx; | |
2440 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2441 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2442 | unmask_ioapic(cfg); |
691874fa | 2443 | } |
d32932d0 | 2444 | irq_domain_activate_irq(irq_get_irq_data(0)); |
1da177e4 | 2445 | if (timer_irq_works()) { |
66759a01 CE |
2446 | if (disable_timer_pin_1 > 0) |
2447 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2448 | goto out; |
1da177e4 | 2449 | } |
6a9f5de2 | 2450 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2451 | local_irq_disable(); |
fcfd636a | 2452 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2453 | if (!no_pin1) |
49a66a0b MR |
2454 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2455 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2456 | |
49a66a0b MR |
2457 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2458 | "(IRQ0) through the 8259A ...\n"); | |
2459 | apic_printk(APIC_QUIET, KERN_INFO | |
2460 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2461 | /* |
2462 | * legacy devices should be connected to IO APIC #0 | |
2463 | */ | |
85ac16d0 | 2464 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
d32932d0 | 2465 | irq_domain_activate_irq(irq_get_irq_data(0)); |
4305df94 | 2466 | legacy_pic->unmask(0); |
1da177e4 | 2467 | if (timer_irq_works()) { |
49a66a0b | 2468 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2469 | goto out; |
1da177e4 LT |
2470 | } |
2471 | /* | |
2472 | * Cleanup, just in case ... | |
2473 | */ | |
f72dccac | 2474 | local_irq_disable(); |
4305df94 | 2475 | legacy_pic->mask(0); |
fcfd636a | 2476 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2477 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2478 | } |
1da177e4 | 2479 | |
49a66a0b MR |
2480 | apic_printk(APIC_QUIET, KERN_INFO |
2481 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2482 | |
60c69948 | 2483 | lapic_register_intr(0); |
497c9a19 | 2484 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2485 | legacy_pic->unmask(0); |
1da177e4 LT |
2486 | |
2487 | if (timer_irq_works()) { | |
49a66a0b | 2488 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2489 | goto out; |
1da177e4 | 2490 | } |
f72dccac | 2491 | local_irq_disable(); |
4305df94 | 2492 | legacy_pic->mask(0); |
497c9a19 | 2493 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2494 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2495 | |
49a66a0b MR |
2496 | apic_printk(APIC_QUIET, KERN_INFO |
2497 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2498 | |
b81bb373 JP |
2499 | legacy_pic->init(0); |
2500 | legacy_pic->make_irq(0); | |
593f4a78 | 2501 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2502 | |
2503 | unlock_ExtINT_logic(); | |
2504 | ||
2505 | if (timer_irq_works()) { | |
49a66a0b | 2506 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2507 | goto out; |
1da177e4 | 2508 | } |
f72dccac | 2509 | local_irq_disable(); |
49a66a0b | 2510 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2ca5b404 | 2511 | if (apic_is_x2apic_enabled()) |
fb209bd8 YL |
2512 | apic_printk(APIC_QUIET, KERN_INFO |
2513 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2514 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2515 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2516 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2517 | out: |
2518 | local_irq_restore(flags); | |
1da177e4 LT |
2519 | } |
2520 | ||
2521 | /* | |
af174783 MR |
2522 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2523 | * to devices. However there may be an I/O APIC pin available for | |
2524 | * this interrupt regardless. The pin may be left unconnected, but | |
2525 | * typically it will be reused as an ExtINT cascade interrupt for | |
2526 | * the master 8259A. In the MPS case such a pin will normally be | |
2527 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2528 | * there is no provision for ExtINT interrupts, and in the absence | |
2529 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2530 | * interrupt, that is edge-triggered and unmasked by default. We | |
2531 | * used to do this, but it caused problems on some systems because | |
2532 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2533 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2534 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2535 | * the I/O APIC in all cases now. No actual device should request | |
2536 | * it anyway. --macro | |
1da177e4 | 2537 | */ |
bc07844a | 2538 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2539 | |
44767bfa JL |
2540 | static int mp_irqdomain_create(int ioapic) |
2541 | { | |
15a3c7cc | 2542 | size_t size; |
d32932d0 JL |
2543 | struct irq_alloc_info info; |
2544 | struct irq_domain *parent; | |
44767bfa JL |
2545 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2546 | struct ioapic *ip = &ioapics[ioapic]; | |
2547 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2548 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2549 | ||
15a3c7cc JL |
2550 | size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic); |
2551 | ip->pin_info = kzalloc(size, GFP_KERNEL); | |
2552 | if (!ip->pin_info) | |
2553 | return -ENOMEM; | |
2554 | ||
44767bfa JL |
2555 | if (cfg->type == IOAPIC_DOMAIN_INVALID) |
2556 | return 0; | |
2557 | ||
d32932d0 JL |
2558 | init_irq_alloc_info(&info, NULL); |
2559 | info.type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
2560 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2561 | parent = irq_remapping_get_ir_irq_domain(&info); | |
2562 | if (!parent) | |
2563 | parent = x86_vector_domain; | |
2564 | ||
44767bfa JL |
2565 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, |
2566 | (void *)(long)ioapic); | |
d32932d0 JL |
2567 | if (ip->irqdomain) { |
2568 | ip->irqdomain->parent = parent; | |
2569 | } else { | |
15a3c7cc JL |
2570 | kfree(ip->pin_info); |
2571 | ip->pin_info = NULL; | |
44767bfa | 2572 | return -ENOMEM; |
15a3c7cc | 2573 | } |
44767bfa JL |
2574 | |
2575 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2576 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2577 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2578 | gsi_cfg->gsi_end + 1); | |
2579 | ||
44767bfa JL |
2580 | return 0; |
2581 | } | |
2582 | ||
15516a3b JL |
2583 | static void ioapic_destroy_irqdomain(int idx) |
2584 | { | |
2585 | if (ioapics[idx].irqdomain) { | |
2586 | irq_domain_remove(ioapics[idx].irqdomain); | |
2587 | ioapics[idx].irqdomain = NULL; | |
2588 | } | |
2589 | kfree(ioapics[idx].pin_info); | |
2590 | ioapics[idx].pin_info = NULL; | |
2591 | } | |
2592 | ||
1da177e4 LT |
2593 | void __init setup_IO_APIC(void) |
2594 | { | |
44767bfa | 2595 | int ioapic; |
54168ed7 | 2596 | |
a46f5c89 TG |
2597 | if (skip_ioapic_setup || !nr_ioapics) |
2598 | return; | |
2599 | ||
95d76acc | 2600 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2601 | |
54168ed7 | 2602 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2603 | for_each_ioapic(ioapic) |
2604 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2605 | ||
d6c88a50 | 2606 | /* |
54168ed7 IM |
2607 | * Set up IO-APIC IRQ routing. |
2608 | */ | |
de934103 TG |
2609 | x86_init.mpparse.setup_ioapic_ids(); |
2610 | ||
1da177e4 LT |
2611 | sync_Arb_IDs(); |
2612 | setup_IO_APIC_irqs(); | |
2613 | init_IO_APIC_traps(); | |
95d76acc | 2614 | if (nr_legacy_irqs()) |
bc07844a | 2615 | check_timer(); |
b81975ea JL |
2616 | |
2617 | ioapic_initialized = 1; | |
1da177e4 LT |
2618 | } |
2619 | ||
2620 | /* | |
0d2eb44f | 2621 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2622 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2623 | */ |
36062448 | 2624 | |
1da177e4 LT |
2625 | static int __init io_apic_bug_finalize(void) |
2626 | { | |
d6c88a50 TG |
2627 | if (sis_apic_bug == -1) |
2628 | sis_apic_bug = 0; | |
2629 | return 0; | |
1da177e4 LT |
2630 | } |
2631 | ||
2632 | late_initcall(io_apic_bug_finalize); | |
2633 | ||
6f50d45f | 2634 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2635 | { |
1da177e4 LT |
2636 | unsigned long flags; |
2637 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2638 | |
dade7716 | 2639 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2640 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2641 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2642 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2643 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2644 | } |
dade7716 | 2645 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2646 | } |
1da177e4 | 2647 | |
f3c6ea1b RW |
2648 | static void ioapic_resume(void) |
2649 | { | |
6f50d45f | 2650 | int ioapic_idx; |
f3c6ea1b | 2651 | |
f44d1692 | 2652 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2653 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2654 | |
2655 | restore_ioapic_entries(); | |
1da177e4 LT |
2656 | } |
2657 | ||
f3c6ea1b | 2658 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2659 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2660 | .resume = ioapic_resume, |
2661 | }; | |
2662 | ||
f3c6ea1b | 2663 | static int __init ioapic_init_ops(void) |
1da177e4 | 2664 | { |
f3c6ea1b RW |
2665 | register_syscore_ops(&ioapic_syscore_ops); |
2666 | ||
1da177e4 LT |
2667 | return 0; |
2668 | } | |
2669 | ||
f3c6ea1b | 2670 | device_initcall(ioapic_init_ops); |
1da177e4 | 2671 | |
20443598 | 2672 | static int |
ff973d04 TG |
2673 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
2674 | { | |
2675 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
2676 | int ret; | |
2677 | ||
2678 | if (!cfg) | |
2679 | return -EINVAL; | |
2680 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
2681 | if (!ret) | |
e4aff811 | 2682 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
2683 | return ret; |
2684 | } | |
2685 | ||
67dc5e70 | 2686 | static int io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
2687 | { |
2688 | union IO_APIC_reg_01 reg_01; | |
2689 | unsigned long flags; | |
2690 | ||
dade7716 | 2691 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 2692 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2693 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 2694 | |
4b6b19a1 EB |
2695 | /* The register returns the maximum index redir index |
2696 | * supported, which is one less than the total number of redir | |
2697 | * entries. | |
2698 | */ | |
2699 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
2700 | } |
2701 | ||
62a08ae2 TG |
2702 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
2703 | { | |
b81975ea JL |
2704 | /* |
2705 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
2706 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
2707 | */ | |
2708 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
2709 | } |
2710 | ||
54168ed7 | 2711 | #ifdef CONFIG_X86_32 |
67dc5e70 | 2712 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2713 | { |
2714 | union IO_APIC_reg_00 reg_00; | |
2715 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2716 | physid_mask_t tmp; | |
2717 | unsigned long flags; | |
2718 | int i = 0; | |
2719 | ||
2720 | /* | |
36062448 PC |
2721 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2722 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2723 | * supports up to 16 on one shared APIC bus. |
36062448 | 2724 | * |
1da177e4 LT |
2725 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2726 | * advantage of new APIC bus architecture. | |
2727 | */ | |
2728 | ||
2729 | if (physids_empty(apic_id_map)) | |
7abc0753 | 2730 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 2731 | |
dade7716 | 2732 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2733 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 2734 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2735 | |
2736 | if (apic_id >= get_physical_broadcast()) { | |
2737 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2738 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2739 | apic_id = reg_00.bits.ID; | |
2740 | } | |
2741 | ||
2742 | /* | |
36062448 | 2743 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2744 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2745 | */ | |
7abc0753 | 2746 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
2747 | |
2748 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 2749 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
2750 | break; |
2751 | } | |
2752 | ||
2753 | if (i == get_physical_broadcast()) | |
2754 | panic("Max apic_id exceeded!\n"); | |
2755 | ||
2756 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2757 | "trying %d\n", ioapic, apic_id, i); | |
2758 | ||
2759 | apic_id = i; | |
36062448 | 2760 | } |
1da177e4 | 2761 | |
7abc0753 | 2762 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
2763 | physids_or(apic_id_map, apic_id_map, tmp); |
2764 | ||
2765 | if (reg_00.bits.ID != apic_id) { | |
2766 | reg_00.bits.ID = apic_id; | |
2767 | ||
dade7716 | 2768 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2769 | io_apic_write(ioapic, 0, reg_00.raw); |
2770 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 2771 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2772 | |
2773 | /* Sanity check */ | |
6070f9ec | 2774 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
2775 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
2776 | ioapic); | |
6070f9ec AD |
2777 | return -1; |
2778 | } | |
1da177e4 LT |
2779 | } |
2780 | ||
2781 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2782 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2783 | ||
2784 | return apic_id; | |
2785 | } | |
41098ffe | 2786 | |
67dc5e70 | 2787 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe TG |
2788 | { |
2789 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
2790 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
5411dc4c | 2791 | return io_apic_get_unique_id(idx, id); |
41098ffe TG |
2792 | else |
2793 | return id; | |
2794 | } | |
2795 | #else | |
67dc5e70 | 2796 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe | 2797 | { |
5411dc4c | 2798 | union IO_APIC_reg_00 reg_00; |
41098ffe | 2799 | DECLARE_BITMAP(used, 256); |
5411dc4c YL |
2800 | unsigned long flags; |
2801 | u8 new_id; | |
2802 | int i; | |
41098ffe TG |
2803 | |
2804 | bitmap_zero(used, 256); | |
f44d1692 | 2805 | for_each_ioapic(i) |
d5371430 | 2806 | __set_bit(mpc_ioapic_id(i), used); |
5411dc4c YL |
2807 | |
2808 | /* Hand out the requested id if available */ | |
41098ffe TG |
2809 | if (!test_bit(id, used)) |
2810 | return id; | |
5411dc4c YL |
2811 | |
2812 | /* | |
2813 | * Read the current id from the ioapic and keep it if | |
2814 | * available. | |
2815 | */ | |
2816 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2817 | reg_00.raw = io_apic_read(idx, 0); | |
2818 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2819 | new_id = reg_00.bits.ID; | |
2820 | if (!test_bit(new_id, used)) { | |
2821 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2822 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", | |
2823 | idx, new_id, id); | |
2824 | return new_id; | |
2825 | } | |
2826 | ||
2827 | /* | |
2828 | * Get the next free id and write it to the ioapic. | |
2829 | */ | |
2830 | new_id = find_first_zero_bit(used, 256); | |
2831 | reg_00.bits.ID = new_id; | |
2832 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2833 | io_apic_write(idx, 0, reg_00.raw); | |
2834 | reg_00.raw = io_apic_read(idx, 0); | |
2835 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2836 | /* Sanity check */ | |
2837 | BUG_ON(reg_00.bits.ID != new_id); | |
2838 | ||
2839 | return new_id; | |
41098ffe | 2840 | } |
58f892e0 | 2841 | #endif |
1da177e4 | 2842 | |
67dc5e70 | 2843 | static int io_apic_get_version(int ioapic) |
1da177e4 LT |
2844 | { |
2845 | union IO_APIC_reg_01 reg_01; | |
2846 | unsigned long flags; | |
2847 | ||
dade7716 | 2848 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2849 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2850 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2851 | |
2852 | return reg_01.bits.version; | |
2853 | } | |
2854 | ||
9a0a91bb | 2855 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 2856 | { |
9a0a91bb | 2857 | int ioapic, pin, idx; |
61fd47e0 SL |
2858 | |
2859 | if (skip_ioapic_setup) | |
2860 | return -1; | |
2861 | ||
9a0a91bb EB |
2862 | ioapic = mp_find_ioapic(gsi); |
2863 | if (ioapic < 0) | |
61fd47e0 SL |
2864 | return -1; |
2865 | ||
9a0a91bb EB |
2866 | pin = mp_find_ioapic_pin(ioapic, gsi); |
2867 | if (pin < 0) | |
2868 | return -1; | |
2869 | ||
2870 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
2871 | if (idx < 0) | |
61fd47e0 SL |
2872 | return -1; |
2873 | ||
9a0a91bb EB |
2874 | *trigger = irq_trigger(idx); |
2875 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
2876 | return 0; |
2877 | } | |
2878 | ||
497c9a19 YL |
2879 | /* |
2880 | * This function currently is only a helper for the i386 smp boot process where | |
2881 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 2882 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
2883 | */ |
2884 | #ifdef CONFIG_SMP | |
2885 | void __init setup_ioapic_dest(void) | |
2886 | { | |
fad53995 | 2887 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 2888 | const struct cpumask *mask; |
5451ddc5 | 2889 | struct irq_data *idata; |
497c9a19 YL |
2890 | |
2891 | if (skip_ioapic_setup == 1) | |
2892 | return; | |
2893 | ||
f44d1692 | 2894 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
2895 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
2896 | if (irq_entry == -1) | |
2897 | continue; | |
6c2e9403 | 2898 | |
d7f3d478 JL |
2899 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
2900 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
2901 | continue; |
2902 | ||
5451ddc5 | 2903 | idata = irq_get_irq_data(irq); |
6c2e9403 | 2904 | |
b9c61b70 YL |
2905 | /* |
2906 | * Honour affinities which have been set in early boot | |
2907 | */ | |
5451ddc5 TG |
2908 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
2909 | mask = idata->affinity; | |
b9c61b70 YL |
2910 | else |
2911 | mask = apic->target_cpus(); | |
497c9a19 | 2912 | |
373dd7a2 | 2913 | x86_io_apic_ops.set_affinity(idata, mask, false); |
497c9a19 | 2914 | } |
b9c61b70 | 2915 | |
497c9a19 YL |
2916 | } |
2917 | #endif | |
2918 | ||
54168ed7 IM |
2919 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2920 | ||
2921 | static struct resource *ioapic_resources; | |
2922 | ||
f44d1692 | 2923 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
2924 | { |
2925 | unsigned long n; | |
2926 | struct resource *res; | |
2927 | char *mem; | |
f44d1692 | 2928 | int i, num = 0; |
54168ed7 | 2929 | |
f44d1692 JL |
2930 | for_each_ioapic(i) |
2931 | num++; | |
2932 | if (num == 0) | |
54168ed7 IM |
2933 | return NULL; |
2934 | ||
2935 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 2936 | n *= num; |
54168ed7 IM |
2937 | |
2938 | mem = alloc_bootmem(n); | |
2939 | res = (void *)mem; | |
2940 | ||
f44d1692 | 2941 | mem += sizeof(struct resource) * num; |
54168ed7 | 2942 | |
f44d1692 JL |
2943 | num = 0; |
2944 | for_each_ioapic(i) { | |
2945 | res[num].name = mem; | |
2946 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 2947 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 2948 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 2949 | num++; |
15516a3b | 2950 | ioapics[i].iomem_res = res; |
54168ed7 IM |
2951 | } |
2952 | ||
2953 | ioapic_resources = res; | |
2954 | ||
2955 | return res; | |
2956 | } | |
54168ed7 | 2957 | |
4a8e2a31 | 2958 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
2959 | { |
2960 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 2961 | struct resource *ioapic_res; |
d6c88a50 | 2962 | int i; |
f3294a33 | 2963 | |
f44d1692 JL |
2964 | ioapic_res = ioapic_setup_resources(); |
2965 | for_each_ioapic(i) { | |
f3294a33 | 2966 | if (smp_found_config) { |
d5371430 | 2967 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 2968 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
2969 | if (!ioapic_phys) { |
2970 | printk(KERN_ERR | |
2971 | "WARNING: bogus zero IO-APIC " | |
2972 | "address found in MPTABLE, " | |
2973 | "disabling IO/APIC support!\n"); | |
2974 | smp_found_config = 0; | |
2975 | skip_ioapic_setup = 1; | |
2976 | goto fake_ioapic_page; | |
2977 | } | |
54168ed7 | 2978 | #endif |
f3294a33 | 2979 | } else { |
54168ed7 | 2980 | #ifdef CONFIG_X86_32 |
f3294a33 | 2981 | fake_ioapic_page: |
54168ed7 | 2982 | #endif |
e79c65a9 | 2983 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
2984 | ioapic_phys = __pa(ioapic_phys); |
2985 | } | |
2986 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
2987 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
2988 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
2989 | ioapic_phys); | |
f3294a33 | 2990 | idx++; |
54168ed7 | 2991 | |
ffc43836 | 2992 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 2993 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 2994 | ioapic_res++; |
f3294a33 YL |
2995 | } |
2996 | } | |
2997 | ||
857fdc53 | 2998 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
2999 | { |
3000 | int i; | |
3001 | struct resource *r = ioapic_resources; | |
3002 | ||
3003 | if (!r) { | |
857fdc53 | 3004 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3005 | printk(KERN_ERR |
3006 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3007 | return; |
54168ed7 IM |
3008 | } |
3009 | ||
f44d1692 | 3010 | for_each_ioapic(i) { |
54168ed7 IM |
3011 | insert_resource(&iomem_resource, r); |
3012 | r++; | |
3013 | } | |
54168ed7 | 3014 | } |
2a4ab640 | 3015 | |
eddb0c55 | 3016 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 3017 | { |
f44d1692 | 3018 | int i; |
2a4ab640 | 3019 | |
678301ec PB |
3020 | if (nr_ioapics == 0) |
3021 | return -1; | |
3022 | ||
2a4ab640 | 3023 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 3024 | for_each_ioapic(i) { |
c040aaeb | 3025 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 3026 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
3027 | return i; |
3028 | } | |
54168ed7 | 3029 | |
2a4ab640 FT |
3030 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3031 | return -1; | |
3032 | } | |
3033 | ||
eddb0c55 | 3034 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3035 | { |
c040aaeb SS |
3036 | struct mp_ioapic_gsi *gsi_cfg; |
3037 | ||
f44d1692 | 3038 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 3039 | return -1; |
c040aaeb SS |
3040 | |
3041 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3042 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3043 | return -1; |
3044 | ||
c040aaeb | 3045 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3046 | } |
3047 | ||
67dc5e70 | 3048 | static int bad_ioapic_register(int idx) |
73d63d03 SS |
3049 | { |
3050 | union IO_APIC_reg_00 reg_00; | |
3051 | union IO_APIC_reg_01 reg_01; | |
3052 | union IO_APIC_reg_02 reg_02; | |
3053 | ||
3054 | reg_00.raw = io_apic_read(idx, 0); | |
3055 | reg_01.raw = io_apic_read(idx, 1); | |
3056 | reg_02.raw = io_apic_read(idx, 2); | |
3057 | ||
3058 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3059 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3060 | mpc_ioapic_addr(idx)); | |
3061 | return 1; | |
3062 | } | |
3063 | ||
3064 | return 0; | |
3065 | } | |
3066 | ||
35ef9c94 JL |
3067 | static int find_free_ioapic_entry(void) |
3068 | { | |
7db298cb JL |
3069 | int idx; |
3070 | ||
3071 | for (idx = 0; idx < MAX_IO_APICS; idx++) | |
3072 | if (ioapics[idx].nr_registers == 0) | |
3073 | return idx; | |
3074 | ||
3075 | return MAX_IO_APICS; | |
35ef9c94 JL |
3076 | } |
3077 | ||
3078 | /** | |
3079 | * mp_register_ioapic - Register an IOAPIC device | |
3080 | * @id: hardware IOAPIC ID | |
3081 | * @address: physical address of IOAPIC register area | |
3082 | * @gsi_base: base of GSI associated with the IOAPIC | |
3083 | * @cfg: configuration information for the IOAPIC | |
3084 | */ | |
3085 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, | |
3086 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 | 3087 | { |
7db298cb | 3088 | bool hotplug = !!ioapic_initialized; |
c040aaeb | 3089 | struct mp_ioapic_gsi *gsi_cfg; |
35ef9c94 JL |
3090 | int idx, ioapic, entries; |
3091 | u32 gsi_end; | |
2a4ab640 | 3092 | |
35ef9c94 JL |
3093 | if (!address) { |
3094 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); | |
3095 | return -EINVAL; | |
3096 | } | |
3097 | for_each_ioapic(ioapic) | |
3098 | if (ioapics[ioapic].mp_config.apicaddr == address) { | |
3099 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", | |
3100 | address, ioapic); | |
3101 | return -EEXIST; | |
3102 | } | |
2a4ab640 | 3103 | |
35ef9c94 JL |
3104 | idx = find_free_ioapic_entry(); |
3105 | if (idx >= MAX_IO_APICS) { | |
3106 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", | |
3107 | MAX_IO_APICS, idx); | |
3108 | return -ENOSPC; | |
3109 | } | |
2a4ab640 | 3110 | |
d5371430 SS |
3111 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3112 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3113 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
3114 | |
3115 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
3116 | if (bad_ioapic_register(idx)) { |
3117 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
35ef9c94 | 3118 | return -ENODEV; |
73d63d03 SS |
3119 | } |
3120 | ||
5411dc4c | 3121 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
d5371430 | 3122 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
2a4ab640 FT |
3123 | |
3124 | /* | |
3125 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3126 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3127 | */ | |
7716a5c4 | 3128 | entries = io_apic_get_redir_entries(idx); |
35ef9c94 JL |
3129 | gsi_end = gsi_base + entries - 1; |
3130 | for_each_ioapic(ioapic) { | |
3131 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3132 | if ((gsi_base >= gsi_cfg->gsi_base && | |
3133 | gsi_base <= gsi_cfg->gsi_end) || | |
3134 | (gsi_end >= gsi_cfg->gsi_base && | |
3135 | gsi_end <= gsi_cfg->gsi_end)) { | |
3136 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", | |
3137 | gsi_base, gsi_end, | |
3138 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
3139 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3140 | return -ENOSPC; | |
3141 | } | |
3142 | } | |
c040aaeb SS |
3143 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3144 | gsi_cfg->gsi_base = gsi_base; | |
35ef9c94 | 3145 | gsi_cfg->gsi_end = gsi_end; |
7716a5c4 | 3146 | |
35ef9c94 JL |
3147 | ioapics[idx].irqdomain = NULL; |
3148 | ioapics[idx].irqdomain_cfg = *cfg; | |
2a4ab640 | 3149 | |
7db298cb JL |
3150 | /* |
3151 | * If mp_register_ioapic() is called during early boot stage when | |
3152 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, | |
3153 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). | |
3154 | */ | |
3155 | if (hotplug) { | |
3156 | if (mp_irqdomain_create(idx)) { | |
3157 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3158 | return -ENOMEM; | |
3159 | } | |
3160 | alloc_ioapic_saved_registers(idx); | |
3161 | } | |
3162 | ||
c040aaeb SS |
3163 | if (gsi_cfg->gsi_end >= gsi_top) |
3164 | gsi_top = gsi_cfg->gsi_end + 1; | |
35ef9c94 JL |
3165 | if (nr_ioapics <= idx) |
3166 | nr_ioapics = idx + 1; | |
3167 | ||
3168 | /* Set nr_registers to mark entry present */ | |
3169 | ioapics[idx].nr_registers = entries; | |
2a4ab640 | 3170 | |
73d63d03 SS |
3171 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
3172 | idx, mpc_ioapic_id(idx), | |
3173 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
3174 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 | 3175 | |
35ef9c94 | 3176 | return 0; |
2a4ab640 | 3177 | } |
05ddafb1 | 3178 | |
15516a3b JL |
3179 | int mp_unregister_ioapic(u32 gsi_base) |
3180 | { | |
3181 | int ioapic, pin; | |
3182 | int found = 0; | |
15516a3b JL |
3183 | |
3184 | for_each_ioapic(ioapic) | |
3185 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { | |
3186 | found = 1; | |
3187 | break; | |
3188 | } | |
3189 | if (!found) { | |
3190 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); | |
3191 | return -ENODEV; | |
3192 | } | |
3193 | ||
3194 | for_each_pin(ioapic, pin) { | |
d32932d0 JL |
3195 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
3196 | int irq = mp_map_gsi_to_irq(gsi, 0, NULL); | |
3197 | struct mp_chip_data *data; | |
3198 | ||
3199 | if (irq >= 0) { | |
3200 | data = irq_get_chip_data(irq); | |
3201 | if (data && data->count) { | |
3202 | pr_warn("pin%d on IOAPIC%d is still in use.\n", | |
3203 | pin, ioapic); | |
3204 | return -EBUSY; | |
3205 | } | |
15516a3b JL |
3206 | } |
3207 | } | |
3208 | ||
3209 | /* Mark entry not present */ | |
3210 | ioapics[ioapic].nr_registers = 0; | |
3211 | ioapic_destroy_irqdomain(ioapic); | |
3212 | free_ioapic_saved_registers(ioapic); | |
3213 | if (ioapics[ioapic].iomem_res) | |
3214 | release_resource(ioapics[ioapic].iomem_res); | |
3215 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); | |
3216 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); | |
3217 | ||
3218 | return 0; | |
3219 | } | |
3220 | ||
e89900c9 JL |
3221 | int mp_ioapic_registered(u32 gsi_base) |
3222 | { | |
3223 | int ioapic; | |
3224 | ||
3225 | for_each_ioapic(ioapic) | |
3226 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) | |
3227 | return 1; | |
3228 | ||
3229 | return 0; | |
3230 | } | |
3231 | ||
8643e28d JL |
3232 | static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr, |
3233 | int ioapic, int ioapic_pin, | |
3234 | int trigger, int polarity) | |
3235 | { | |
3236 | irq_attr->ioapic = ioapic; | |
3237 | irq_attr->ioapic_pin = ioapic_pin; | |
3238 | irq_attr->trigger = trigger; | |
3239 | irq_attr->polarity = polarity; | |
3240 | } | |
3241 | ||
15a3c7cc JL |
3242 | int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq, |
3243 | irq_hw_number_t hwirq) | |
3244 | { | |
49c7e600 | 3245 | int ioapic = mp_irqdomain_ioapic_idx(domain); |
15a3c7cc JL |
3246 | struct mp_pin_info *info = mp_pin_info(ioapic, hwirq); |
3247 | struct io_apic_irq_attr attr; | |
3248 | ||
15a3c7cc JL |
3249 | /* Get default attribute if not set by caller yet */ |
3250 | if (!info->set) { | |
3251 | u32 gsi = mp_pin_to_gsi(ioapic, hwirq); | |
3252 | ||
3253 | if (acpi_get_override_irq(gsi, &info->trigger, | |
3254 | &info->polarity) < 0) { | |
3255 | /* | |
3256 | * PCI interrupts are always polarity one level | |
3257 | * triggered. | |
3258 | */ | |
3259 | info->trigger = 1; | |
3260 | info->polarity = 1; | |
3261 | } | |
3262 | info->node = NUMA_NO_NODE; | |
f395dcae JL |
3263 | |
3264 | /* | |
3265 | * setup_IO_APIC_irqs() programs all legacy IRQs with default | |
3266 | * trigger and polarity attributes. Don't set the flag for that | |
3267 | * case so the first legacy IRQ user could reprogram the pin | |
3268 | * with real trigger and polarity attributes. | |
3269 | */ | |
3270 | if (virq >= nr_legacy_irqs() || info->count) | |
3271 | info->set = 1; | |
15a3c7cc JL |
3272 | } |
3273 | set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger, | |
3274 | info->polarity); | |
3275 | ||
3276 | return io_apic_setup_irq_pin(virq, info->node, &attr); | |
3277 | } | |
3278 | ||
df334bea JL |
3279 | void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq) |
3280 | { | |
3281 | struct irq_data *data = irq_get_irq_data(virq); | |
3282 | struct irq_cfg *cfg = irq_cfg(virq); | |
49c7e600 | 3283 | int ioapic = mp_irqdomain_ioapic_idx(domain); |
df334bea JL |
3284 | int pin = (int)data->hwirq; |
3285 | ||
df334bea JL |
3286 | ioapic_mask_entry(ioapic, pin); |
3287 | __remove_pin_from_irq(cfg, ioapic, pin); | |
a178b87b | 3288 | WARN_ON(!list_empty(&cfg->irq_2_pin)); |
df334bea JL |
3289 | arch_teardown_hwirq(virq); |
3290 | } | |
3291 | ||
49c7e600 JL |
3292 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
3293 | struct irq_alloc_info *info) | |
3294 | { | |
3295 | if (info && info->ioapic_valid) { | |
3296 | data->trigger = info->ioapic_trigger; | |
3297 | data->polarity = info->ioapic_polarity; | |
3298 | } else if (acpi_get_override_irq(gsi, &data->trigger, | |
3299 | &data->polarity) < 0) { | |
3300 | /* PCI interrupts are always polarity one level triggered. */ | |
3301 | data->trigger = 1; | |
3302 | data->polarity = 1; | |
3303 | } | |
3304 | } | |
3305 | ||
3306 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, | |
3307 | struct IO_APIC_route_entry *entry) | |
3308 | { | |
3309 | memset(entry, 0, sizeof(*entry)); | |
3310 | entry->delivery_mode = apic->irq_delivery_mode; | |
3311 | entry->dest_mode = apic->irq_dest_mode; | |
3312 | entry->dest = cfg->dest_apicid; | |
3313 | entry->vector = cfg->vector; | |
3314 | entry->mask = 0; /* enable IRQ */ | |
3315 | entry->trigger = data->trigger; | |
3316 | entry->polarity = data->polarity; | |
3317 | /* | |
3318 | * Mask level triggered irqs. | |
3319 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
3320 | */ | |
3321 | if (data->trigger) | |
3322 | entry->mask = 1; | |
3323 | } | |
3324 | ||
3325 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, | |
3326 | unsigned int nr_irqs, void *arg) | |
3327 | { | |
3328 | int ret, ioapic, pin; | |
3329 | struct irq_cfg *cfg; | |
3330 | struct irq_data *irq_data; | |
3331 | struct mp_chip_data *data; | |
3332 | struct irq_alloc_info *info = arg; | |
3333 | ||
3334 | if (!info || nr_irqs > 1) | |
3335 | return -EINVAL; | |
3336 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3337 | if (!irq_data) | |
3338 | return -EINVAL; | |
3339 | ||
3340 | ioapic = mp_irqdomain_ioapic_idx(domain); | |
3341 | pin = info->ioapic_pin; | |
3342 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) | |
3343 | return -EEXIST; | |
3344 | ||
3345 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3346 | if (!data) | |
3347 | return -ENOMEM; | |
3348 | ||
3349 | info->ioapic_entry = &data->entry; | |
3350 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); | |
3351 | if (ret < 0) { | |
3352 | kfree(data); | |
3353 | return ret; | |
3354 | } | |
3355 | ||
3356 | irq_data->hwirq = info->ioapic_pin; | |
d32932d0 JL |
3357 | irq_data->chip = (domain->parent == x86_vector_domain) ? |
3358 | &ioapic_chip : &ioapic_ir_chip; | |
49c7e600 JL |
3359 | irq_data->chip_data = data; |
3360 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); | |
3361 | ||
3362 | cfg = irqd_cfg(irq_data); | |
3363 | add_pin_to_irq_node(cfg, info->ioapic_node, ioapic, pin); | |
3364 | if (info->ioapic_entry) | |
3365 | mp_setup_entry(cfg, data, info->ioapic_entry); | |
3366 | mp_register_handler(virq, data->trigger); | |
3367 | if (virq < nr_legacy_irqs()) | |
3368 | legacy_pic->mask(virq); | |
3369 | ||
3370 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
3371 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", | |
3372 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, | |
3373 | virq, data->trigger, data->polarity, cfg->dest_apicid); | |
3374 | ||
3375 | return 0; | |
3376 | } | |
3377 | ||
3378 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, | |
3379 | unsigned int nr_irqs) | |
3380 | { | |
3381 | struct irq_cfg *cfg = irq_cfg(virq); | |
3382 | struct irq_data *irq_data; | |
3383 | ||
3384 | BUG_ON(nr_irqs != 1); | |
3385 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3386 | if (irq_data && irq_data->chip_data) { | |
3387 | __remove_pin_from_irq(cfg, mp_irqdomain_ioapic_idx(domain), | |
3388 | (int)irq_data->hwirq); | |
3389 | WARN_ON(!list_empty(&cfg->irq_2_pin)); | |
3390 | kfree(irq_data->chip_data); | |
3391 | } | |
3392 | irq_domain_free_irqs_top(domain, virq, nr_irqs); | |
3393 | } | |
3394 | ||
3395 | void mp_irqdomain_activate(struct irq_domain *domain, | |
3396 | struct irq_data *irq_data) | |
3397 | { | |
3398 | unsigned long flags; | |
3399 | struct irq_pin_list *entry; | |
3400 | struct mp_chip_data *data = irq_data->chip_data; | |
3401 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
3402 | ||
3403 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3404 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
3405 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); | |
3406 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
3407 | } | |
3408 | ||
3409 | void mp_irqdomain_deactivate(struct irq_domain *domain, | |
3410 | struct irq_data *irq_data) | |
3411 | { | |
3412 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ | |
3413 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), | |
3414 | (int)irq_data->hwirq); | |
3415 | } | |
3416 | ||
15a3c7cc JL |
3417 | int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node) |
3418 | { | |
3419 | int ret = 0; | |
3420 | int ioapic, pin; | |
3421 | struct mp_pin_info *info; | |
3422 | ||
3423 | ioapic = mp_find_ioapic(gsi); | |
3424 | if (ioapic < 0) | |
3425 | return -ENODEV; | |
3426 | ||
3427 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
3428 | info = mp_pin_info(ioapic, pin); | |
3429 | trigger = trigger ? 1 : 0; | |
3430 | polarity = polarity ? 1 : 0; | |
3431 | ||
3432 | mutex_lock(&ioapic_mutex); | |
3433 | if (!info->set) { | |
3434 | info->trigger = trigger; | |
3435 | info->polarity = polarity; | |
3436 | info->node = node; | |
3437 | info->set = 1; | |
3438 | } else if (info->trigger != trigger || info->polarity != polarity) { | |
3439 | ret = -EBUSY; | |
3440 | } | |
3441 | mutex_unlock(&ioapic_mutex); | |
3442 | ||
3443 | return ret; | |
3444 | } | |
49c7e600 JL |
3445 | |
3446 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) | |
3447 | { | |
3448 | return (int)(long)domain->host_data; | |
3449 | } |