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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #ifdef CONFIG_ACPI |
41 | #include <acpi/acpi_bus.h> | |
42 | #endif | |
43 | #include <linux/bootmem.h> | |
44 | #include <linux/dmar.h> | |
58ac1e76 | 45 | #include <linux/hpet.h> |
54d5d424 | 46 | |
d4057bdb | 47 | #include <asm/idle.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | #include <asm/smp.h> | |
6d652ea1 | 50 | #include <asm/cpu.h> |
1da177e4 | 51 | #include <asm/desc.h> |
d4057bdb YL |
52 | #include <asm/proto.h> |
53 | #include <asm/acpi.h> | |
54 | #include <asm/dma.h> | |
1da177e4 | 55 | #include <asm/timer.h> |
306e440d | 56 | #include <asm/i8259.h> |
3e4ff115 | 57 | #include <asm/nmi.h> |
2d3fcc1c | 58 | #include <asm/msidef.h> |
8b955b0d | 59 | #include <asm/hypertransport.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
d4057bdb | 61 | #include <asm/irq_remapping.h> |
58ac1e76 | 62 | #include <asm/hpet.h> |
2c1b284e | 63 | #include <asm/hw_irq.h> |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff | 67 | #define __apicdebuginit(type) static type __init |
2977fb3f CG |
68 | #define for_each_irq_pin(entry, head) \ |
69 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 70 | |
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
dade7716 TG |
77 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
78 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 79 | |
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
2a4ab640 FT |
89 | /* IO APIC gsi routing info */ |
90 | struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS]; | |
91 | ||
a4384df3 EB |
92 | /* The one past the highest gsi number used */ |
93 | u32 gsi_top; | |
5777372a | 94 | |
584f734d | 95 | /* MP IRQ source entries */ |
c2c21745 | 96 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
97 | |
98 | /* # of MP IRQ source entries */ | |
99 | int mp_irq_entries; | |
100 | ||
bc07844a TG |
101 | /* GSI interrupts */ |
102 | static int nr_irqs_gsi = NR_IRQS_LEGACY; | |
103 | ||
8732fc4b AS |
104 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
105 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
106 | #endif | |
107 | ||
108 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
109 | ||
efa2559f YL |
110 | int skip_ioapic_setup; |
111 | ||
65a4e574 IM |
112 | void arch_disable_smp_support(void) |
113 | { | |
114 | #ifdef CONFIG_PCI | |
115 | noioapicquirk = 1; | |
116 | noioapicreroute = -1; | |
117 | #endif | |
118 | skip_ioapic_setup = 1; | |
119 | } | |
120 | ||
54168ed7 | 121 | static int __init parse_noapic(char *str) |
efa2559f YL |
122 | { |
123 | /* disable IO-APIC */ | |
65a4e574 | 124 | arch_disable_smp_support(); |
efa2559f YL |
125 | return 0; |
126 | } | |
127 | early_param("noapic", parse_noapic); | |
66759a01 | 128 | |
0b8f1efa YL |
129 | struct irq_pin_list { |
130 | int apic, pin; | |
131 | struct irq_pin_list *next; | |
132 | }; | |
133 | ||
85ac16d0 | 134 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
135 | { |
136 | struct irq_pin_list *pin; | |
0b8f1efa YL |
137 | |
138 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
139 | |
140 | return pin; | |
141 | } | |
142 | ||
a1420f39 | 143 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa | 144 | #ifdef CONFIG_SPARSE_IRQ |
97943390 | 145 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
0b8f1efa | 146 | #else |
97943390 | 147 | static struct irq_cfg irq_cfgx[NR_IRQS]; |
0b8f1efa | 148 | #endif |
a1420f39 | 149 | |
13a0c3c2 | 150 | int __init arch_early_irq_init(void) |
8f09cd20 | 151 | { |
0b8f1efa YL |
152 | struct irq_cfg *cfg; |
153 | struct irq_desc *desc; | |
154 | int count; | |
dad213ae | 155 | int node; |
0b8f1efa | 156 | int i; |
d6c88a50 | 157 | |
1f91233c JP |
158 | if (!legacy_pic->nr_legacy_irqs) { |
159 | nr_irqs_gsi = 0; | |
160 | io_apic_irqs = ~0UL; | |
161 | } | |
162 | ||
0b8f1efa YL |
163 | cfg = irq_cfgx; |
164 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 165 | node = cpu_to_node(0); |
8f09cd20 | 166 | |
0b8f1efa YL |
167 | for (i = 0; i < count; i++) { |
168 | desc = irq_to_desc(i); | |
169 | desc->chip_data = &cfg[i]; | |
12274e96 YL |
170 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node); |
171 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node); | |
97943390 SS |
172 | /* |
173 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
174 | * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. | |
175 | */ | |
54b56170 | 176 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 SS |
177 | cfg[i].vector = IRQ0_VECTOR + i; |
178 | cpumask_set_cpu(0, cfg[i].domain); | |
179 | } | |
0b8f1efa | 180 | } |
13a0c3c2 YL |
181 | |
182 | return 0; | |
0b8f1efa | 183 | } |
8f09cd20 | 184 | |
0b8f1efa | 185 | #ifdef CONFIG_SPARSE_IRQ |
9338ad6f | 186 | struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 187 | { |
0b8f1efa YL |
188 | struct irq_cfg *cfg = NULL; |
189 | struct irq_desc *desc; | |
1da177e4 | 190 | |
0b8f1efa YL |
191 | desc = irq_to_desc(irq); |
192 | if (desc) | |
d4eba297 | 193 | cfg = get_irq_desc_chip_data(desc); |
0f978f45 | 194 | |
0b8f1efa | 195 | return cfg; |
8f09cd20 | 196 | } |
d6c88a50 | 197 | |
85ac16d0 | 198 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 199 | { |
0b8f1efa | 200 | struct irq_cfg *cfg; |
0f978f45 | 201 | |
0b8f1efa | 202 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 203 | if (cfg) { |
79f55997 | 204 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
205 | kfree(cfg); |
206 | cfg = NULL; | |
79f55997 | 207 | } else if (!zalloc_cpumask_var_node(&cfg->old_domain, |
80855f73 | 208 | GFP_ATOMIC, node)) { |
22f65d31 MT |
209 | free_cpumask_var(cfg->domain); |
210 | kfree(cfg); | |
211 | cfg = NULL; | |
22f65d31 MT |
212 | } |
213 | } | |
0f978f45 | 214 | |
0b8f1efa | 215 | return cfg; |
8f09cd20 YL |
216 | } |
217 | ||
85ac16d0 | 218 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 219 | { |
0b8f1efa | 220 | struct irq_cfg *cfg; |
d6c88a50 | 221 | |
d4eba297 | 222 | cfg = get_irq_desc_chip_data(desc); |
0b8f1efa | 223 | if (!cfg) { |
d4eba297 TG |
224 | cfg = get_one_free_irq_cfg(node); |
225 | desc->chip_data = cfg; | |
226 | if (!cfg) { | |
0b8f1efa YL |
227 | printk(KERN_ERR "can not alloc irq_cfg\n"); |
228 | BUG_ON(1); | |
229 | } | |
230 | } | |
1da177e4 | 231 | |
13a0c3c2 | 232 | return 0; |
0b8f1efa | 233 | } |
0f978f45 | 234 | |
fcef5911 | 235 | /* for move_irq_desc */ |
48a1b10a | 236 | static void |
85ac16d0 | 237 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 238 | { |
48a1b10a YL |
239 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
240 | ||
241 | cfg->irq_2_pin = NULL; | |
242 | old_entry = old_cfg->irq_2_pin; | |
243 | if (!old_entry) | |
244 | return; | |
0f978f45 | 245 | |
85ac16d0 | 246 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
247 | if (!entry) |
248 | return; | |
0f978f45 | 249 | |
48a1b10a YL |
250 | entry->apic = old_entry->apic; |
251 | entry->pin = old_entry->pin; | |
252 | head = entry; | |
253 | tail = entry; | |
254 | old_entry = old_entry->next; | |
255 | while (old_entry) { | |
85ac16d0 | 256 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
257 | if (!entry) { |
258 | entry = head; | |
259 | while (entry) { | |
260 | head = entry->next; | |
261 | kfree(entry); | |
262 | entry = head; | |
263 | } | |
264 | /* still use the old one */ | |
265 | return; | |
266 | } | |
267 | entry->apic = old_entry->apic; | |
268 | entry->pin = old_entry->pin; | |
269 | tail->next = entry; | |
270 | tail = entry; | |
271 | old_entry = old_entry->next; | |
272 | } | |
0f978f45 | 273 | |
48a1b10a YL |
274 | tail->next = NULL; |
275 | cfg->irq_2_pin = head; | |
0f978f45 | 276 | } |
0f978f45 | 277 | |
48a1b10a | 278 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 279 | { |
48a1b10a | 280 | struct irq_pin_list *entry, *next; |
0f978f45 | 281 | |
48a1b10a YL |
282 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
283 | return; | |
301e6190 | 284 | |
48a1b10a | 285 | entry = old_cfg->irq_2_pin; |
0f978f45 | 286 | |
48a1b10a YL |
287 | while (entry) { |
288 | next = entry->next; | |
289 | kfree(entry); | |
290 | entry = next; | |
291 | } | |
292 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 293 | } |
0f978f45 | 294 | |
48a1b10a | 295 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 296 | struct irq_desc *desc, int node) |
0f978f45 | 297 | { |
48a1b10a YL |
298 | struct irq_cfg *cfg; |
299 | struct irq_cfg *old_cfg; | |
0f978f45 | 300 | |
85ac16d0 | 301 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 302 | |
48a1b10a YL |
303 | if (!cfg) |
304 | return; | |
305 | ||
306 | desc->chip_data = cfg; | |
307 | ||
308 | old_cfg = old_desc->chip_data; | |
309 | ||
1cf180c9 TG |
310 | cfg->vector = old_cfg->vector; |
311 | cfg->move_in_progress = old_cfg->move_in_progress; | |
312 | cpumask_copy(cfg->domain, old_cfg->domain); | |
313 | cpumask_copy(cfg->old_domain, old_cfg->old_domain); | |
48a1b10a | 314 | |
85ac16d0 | 315 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 316 | } |
1da177e4 | 317 | |
1cf180c9 | 318 | static void free_irq_cfg(struct irq_cfg *cfg) |
48a1b10a | 319 | { |
1cf180c9 TG |
320 | free_cpumask_var(cfg->domain); |
321 | free_cpumask_var(cfg->old_domain); | |
322 | kfree(cfg); | |
48a1b10a YL |
323 | } |
324 | ||
325 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
326 | { | |
327 | struct irq_cfg *old_cfg, *cfg; | |
328 | ||
d4eba297 TG |
329 | old_cfg = get_irq_desc_chip_data(old_desc); |
330 | cfg = get_irq_desc_chip_data(desc); | |
48a1b10a YL |
331 | |
332 | if (old_cfg == cfg) | |
333 | return; | |
334 | ||
335 | if (old_cfg) { | |
336 | free_irq_2_pin(old_cfg, cfg); | |
337 | free_irq_cfg(old_cfg); | |
338 | old_desc->chip_data = NULL; | |
339 | } | |
340 | } | |
fcef5911 | 341 | /* end for move_irq_desc */ |
48a1b10a | 342 | |
0b8f1efa | 343 | #else |
9338ad6f | 344 | struct irq_cfg *irq_cfg(unsigned int irq) |
0b8f1efa YL |
345 | { |
346 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 347 | } |
1da177e4 | 348 | |
0b8f1efa YL |
349 | #endif |
350 | ||
130fe05d LT |
351 | struct io_apic { |
352 | unsigned int index; | |
353 | unsigned int unused[3]; | |
354 | unsigned int data; | |
0280f7c4 SS |
355 | unsigned int unused2[11]; |
356 | unsigned int eoi; | |
130fe05d LT |
357 | }; |
358 | ||
359 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
360 | { | |
361 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 362 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
363 | } |
364 | ||
0280f7c4 SS |
365 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
366 | { | |
367 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
368 | writel(vector, &io_apic->eoi); | |
369 | } | |
370 | ||
130fe05d LT |
371 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
372 | { | |
373 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
374 | writel(reg, &io_apic->index); | |
375 | return readl(&io_apic->data); | |
376 | } | |
377 | ||
378 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
379 | { | |
380 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
381 | writel(reg, &io_apic->index); | |
382 | writel(value, &io_apic->data); | |
383 | } | |
384 | ||
385 | /* | |
386 | * Re-write a value: to be used for read-modify-write | |
387 | * cycles where the read already set up the index register. | |
388 | * | |
389 | * Older SiS APIC requires we rewrite the index register | |
390 | */ | |
391 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
392 | { | |
54168ed7 | 393 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
394 | |
395 | if (sis_apic_bug) | |
396 | writel(reg, &io_apic->index); | |
130fe05d LT |
397 | writel(value, &io_apic->data); |
398 | } | |
399 | ||
3145e941 | 400 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
401 | { |
402 | struct irq_pin_list *entry; | |
403 | unsigned long flags; | |
047c8fdb | 404 | |
dade7716 | 405 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
2977fb3f | 406 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
047c8fdb YL |
407 | unsigned int reg; |
408 | int pin; | |
409 | ||
047c8fdb YL |
410 | pin = entry->pin; |
411 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
412 | /* Is the remote IRR bit set? */ | |
413 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
dade7716 | 414 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
415 | return true; |
416 | } | |
047c8fdb | 417 | } |
dade7716 | 418 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
047c8fdb YL |
419 | |
420 | return false; | |
421 | } | |
047c8fdb | 422 | |
cf4c6a2f AK |
423 | union entry_union { |
424 | struct { u32 w1, w2; }; | |
425 | struct IO_APIC_route_entry entry; | |
426 | }; | |
427 | ||
428 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
429 | { | |
430 | union entry_union eu; | |
431 | unsigned long flags; | |
dade7716 | 432 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
433 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
434 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
dade7716 | 435 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
436 | return eu.entry; |
437 | } | |
438 | ||
f9dadfa7 LT |
439 | /* |
440 | * When we write a new IO APIC routing entry, we need to write the high | |
441 | * word first! If the mask bit in the low word is clear, we will enable | |
442 | * the interrupt, and we need to make sure the entry is fully populated | |
443 | * before that happens. | |
444 | */ | |
d15512f4 AK |
445 | static void |
446 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 447 | { |
50a8d4d2 F |
448 | union entry_union eu = {{0, 0}}; |
449 | ||
cf4c6a2f | 450 | eu.entry = e; |
f9dadfa7 LT |
451 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
452 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
453 | } |
454 | ||
ca97ab90 | 455 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
456 | { |
457 | unsigned long flags; | |
dade7716 | 458 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 459 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 460 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
461 | } |
462 | ||
463 | /* | |
464 | * When we mask an IO APIC routing entry, we need to write the low | |
465 | * word first, in order to set the mask bit before we change the | |
466 | * high bits! | |
467 | */ | |
468 | static void ioapic_mask_entry(int apic, int pin) | |
469 | { | |
470 | unsigned long flags; | |
471 | union entry_union eu = { .entry.mask = 1 }; | |
472 | ||
dade7716 | 473 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
474 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
475 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 476 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
477 | } |
478 | ||
1da177e4 LT |
479 | /* |
480 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
481 | * shared ISA-space IRQs, so we have to support them. We are super | |
482 | * fast in the common case, and fast for shared ISA-space IRQs. | |
483 | */ | |
f3d1915a CG |
484 | static int |
485 | add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin) | |
1da177e4 | 486 | { |
2977fb3f | 487 | struct irq_pin_list **last, *entry; |
0f978f45 | 488 | |
2977fb3f CG |
489 | /* don't allow duplicates */ |
490 | last = &cfg->irq_2_pin; | |
491 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 492 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 493 | return 0; |
2977fb3f | 494 | last = &entry->next; |
1da177e4 | 495 | } |
0f978f45 | 496 | |
875e68ec | 497 | entry = get_one_free_irq_2_pin(node); |
a7428cd2 | 498 | if (!entry) { |
f3d1915a CG |
499 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", |
500 | node, apic, pin); | |
501 | return -ENOMEM; | |
a7428cd2 | 502 | } |
1da177e4 LT |
503 | entry->apic = apic; |
504 | entry->pin = pin; | |
875e68ec | 505 | |
2977fb3f | 506 | *last = entry; |
f3d1915a CG |
507 | return 0; |
508 | } | |
509 | ||
510 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
511 | { | |
512 | if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin)) | |
513 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); | |
1da177e4 LT |
514 | } |
515 | ||
516 | /* | |
517 | * Reroute an IRQ to a different pin. | |
518 | */ | |
85ac16d0 | 519 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
520 | int oldapic, int oldpin, |
521 | int newapic, int newpin) | |
1da177e4 | 522 | { |
535b6429 | 523 | struct irq_pin_list *entry; |
1da177e4 | 524 | |
2977fb3f | 525 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
526 | if (entry->apic == oldapic && entry->pin == oldpin) { |
527 | entry->apic = newapic; | |
528 | entry->pin = newpin; | |
0f978f45 | 529 | /* every one is different, right? */ |
4eea6fff | 530 | return; |
0f978f45 | 531 | } |
1da177e4 | 532 | } |
0f978f45 | 533 | |
4eea6fff JF |
534 | /* old apic/pin didn't exist, so just add new ones */ |
535 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
536 | } |
537 | ||
c29d9db3 SS |
538 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
539 | int mask_and, int mask_or, | |
540 | void (*final)(struct irq_pin_list *entry)) | |
541 | { | |
542 | unsigned int reg, pin; | |
543 | ||
544 | pin = entry->pin; | |
545 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
546 | reg &= mask_and; | |
547 | reg |= mask_or; | |
548 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
549 | if (final) | |
550 | final(entry); | |
551 | } | |
552 | ||
2f210deb JF |
553 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
554 | int mask_and, int mask_or, | |
555 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 556 | { |
87783be4 | 557 | struct irq_pin_list *entry; |
047c8fdb | 558 | |
c29d9db3 SS |
559 | for_each_irq_pin(entry, cfg->irq_2_pin) |
560 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
561 | } | |
562 | ||
563 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | |
564 | { | |
565 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
566 | IO_APIC_REDIR_MASKED, NULL); | |
567 | } | |
568 | ||
569 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | |
570 | { | |
571 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | |
572 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
87783be4 | 573 | } |
047c8fdb | 574 | |
7f3e632f | 575 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 576 | { |
87783be4 CG |
577 | /* |
578 | * Synchronize the IO-APIC and the CPU by doing | |
579 | * a dummy read from the IO-APIC | |
580 | */ | |
581 | struct io_apic __iomem *io_apic; | |
582 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 583 | readl(&io_apic->data); |
1da177e4 LT |
584 | } |
585 | ||
dd5f15e5 | 586 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 587 | { |
dd5f15e5 TG |
588 | unsigned long flags; |
589 | ||
590 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 591 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 592 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 593 | } |
1da177e4 | 594 | |
90297c5f | 595 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 596 | { |
90297c5f | 597 | mask_ioapic(data->chip_data); |
dd5f15e5 | 598 | } |
3145e941 | 599 | |
dd5f15e5 TG |
600 | static void __unmask_ioapic(struct irq_cfg *cfg) |
601 | { | |
602 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
603 | } |
604 | ||
dd5f15e5 | 605 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
606 | { |
607 | unsigned long flags; | |
608 | ||
dade7716 | 609 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 610 | __unmask_ioapic(cfg); |
dade7716 | 611 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
612 | } |
613 | ||
90297c5f | 614 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 615 | { |
90297c5f | 616 | unmask_ioapic(data->chip_data); |
3145e941 YL |
617 | } |
618 | ||
1da177e4 LT |
619 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
620 | { | |
621 | struct IO_APIC_route_entry entry; | |
36062448 | 622 | |
1da177e4 | 623 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 624 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
625 | if (entry.delivery_mode == dest_SMI) |
626 | return; | |
1da177e4 LT |
627 | /* |
628 | * Disable it in the IO-APIC irq-routing table: | |
629 | */ | |
f9dadfa7 | 630 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
631 | } |
632 | ||
54168ed7 | 633 | static void clear_IO_APIC (void) |
1da177e4 LT |
634 | { |
635 | int apic, pin; | |
636 | ||
637 | for (apic = 0; apic < nr_ioapics; apic++) | |
638 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
639 | clear_IO_APIC_pin(apic, pin); | |
640 | } | |
641 | ||
54168ed7 | 642 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
643 | /* |
644 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
645 | * specific CPU-side IRQs. | |
646 | */ | |
647 | ||
648 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
649 | static int pirq_entries[MAX_PIRQS] = { |
650 | [0 ... MAX_PIRQS - 1] = -1 | |
651 | }; | |
1da177e4 | 652 | |
1da177e4 LT |
653 | static int __init ioapic_pirq_setup(char *str) |
654 | { | |
655 | int i, max; | |
656 | int ints[MAX_PIRQS+1]; | |
657 | ||
658 | get_options(str, ARRAY_SIZE(ints), ints); | |
659 | ||
1da177e4 LT |
660 | apic_printk(APIC_VERBOSE, KERN_INFO |
661 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
662 | max = MAX_PIRQS; | |
663 | if (ints[0] < MAX_PIRQS) | |
664 | max = ints[0]; | |
665 | ||
666 | for (i = 0; i < max; i++) { | |
667 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
668 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
669 | /* | |
670 | * PIRQs are mapped upside down, usually. | |
671 | */ | |
672 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
673 | } | |
674 | return 1; | |
675 | } | |
676 | ||
677 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
678 | #endif /* CONFIG_X86_32 */ |
679 | ||
b24696bc FY |
680 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
681 | { | |
682 | int apic; | |
683 | struct IO_APIC_route_entry **ioapic_entries; | |
684 | ||
685 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
686 | GFP_ATOMIC); | |
687 | if (!ioapic_entries) | |
688 | return 0; | |
689 | ||
690 | for (apic = 0; apic < nr_ioapics; apic++) { | |
691 | ioapic_entries[apic] = | |
692 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
693 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
694 | if (!ioapic_entries[apic]) | |
695 | goto nomem; | |
696 | } | |
697 | ||
698 | return ioapic_entries; | |
699 | ||
700 | nomem: | |
701 | while (--apic >= 0) | |
702 | kfree(ioapic_entries[apic]); | |
703 | kfree(ioapic_entries); | |
704 | ||
705 | return 0; | |
706 | } | |
54168ed7 IM |
707 | |
708 | /* | |
05c3dc2c | 709 | * Saves all the IO-APIC RTE's |
54168ed7 | 710 | */ |
b24696bc | 711 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 712 | { |
54168ed7 IM |
713 | int apic, pin; |
714 | ||
b24696bc FY |
715 | if (!ioapic_entries) |
716 | return -ENOMEM; | |
54168ed7 IM |
717 | |
718 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
719 | if (!ioapic_entries[apic]) |
720 | return -ENOMEM; | |
54168ed7 | 721 | |
05c3dc2c | 722 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 723 | ioapic_entries[apic][pin] = |
54168ed7 | 724 | ioapic_read_entry(apic, pin); |
b24696bc | 725 | } |
5ffa4eb2 | 726 | |
54168ed7 IM |
727 | return 0; |
728 | } | |
729 | ||
b24696bc FY |
730 | /* |
731 | * Mask all IO APIC entries. | |
732 | */ | |
733 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
734 | { |
735 | int apic, pin; | |
736 | ||
b24696bc FY |
737 | if (!ioapic_entries) |
738 | return; | |
739 | ||
05c3dc2c | 740 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 741 | if (!ioapic_entries[apic]) |
05c3dc2c | 742 | break; |
b24696bc | 743 | |
05c3dc2c SS |
744 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
745 | struct IO_APIC_route_entry entry; | |
746 | ||
b24696bc | 747 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
748 | if (!entry.mask) { |
749 | entry.mask = 1; | |
750 | ioapic_write_entry(apic, pin, entry); | |
751 | } | |
752 | } | |
753 | } | |
754 | } | |
755 | ||
b24696bc FY |
756 | /* |
757 | * Restore IO APIC entries which was saved in ioapic_entries. | |
758 | */ | |
759 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
760 | { |
761 | int apic, pin; | |
762 | ||
b24696bc FY |
763 | if (!ioapic_entries) |
764 | return -ENOMEM; | |
765 | ||
5ffa4eb2 | 766 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
767 | if (!ioapic_entries[apic]) |
768 | return -ENOMEM; | |
769 | ||
54168ed7 IM |
770 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
771 | ioapic_write_entry(apic, pin, | |
b24696bc | 772 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 773 | } |
b24696bc | 774 | return 0; |
54168ed7 IM |
775 | } |
776 | ||
b24696bc FY |
777 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
778 | { | |
779 | int apic; | |
780 | ||
781 | for (apic = 0; apic < nr_ioapics; apic++) | |
782 | kfree(ioapic_entries[apic]); | |
783 | ||
784 | kfree(ioapic_entries); | |
54168ed7 | 785 | } |
1da177e4 LT |
786 | |
787 | /* | |
788 | * Find the IRQ entry number of a certain pin. | |
789 | */ | |
790 | static int find_irq_entry(int apic, int pin, int type) | |
791 | { | |
792 | int i; | |
793 | ||
794 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
795 | if (mp_irqs[i].irqtype == type && |
796 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
797 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
798 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
799 | return i; |
800 | ||
801 | return -1; | |
802 | } | |
803 | ||
804 | /* | |
805 | * Find the pin to which IRQ[irq] (ISA) is connected | |
806 | */ | |
fcfd636a | 807 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
808 | { |
809 | int i; | |
810 | ||
811 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 812 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 813 | |
d27e2b8e | 814 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
815 | (mp_irqs[i].irqtype == type) && |
816 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 817 | |
c2c21745 | 818 | return mp_irqs[i].dstirq; |
1da177e4 LT |
819 | } |
820 | return -1; | |
821 | } | |
822 | ||
fcfd636a EB |
823 | static int __init find_isa_irq_apic(int irq, int type) |
824 | { | |
825 | int i; | |
826 | ||
827 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 828 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 829 | |
73b2961b | 830 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
831 | (mp_irqs[i].irqtype == type) && |
832 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
833 | break; |
834 | } | |
835 | if (i < mp_irq_entries) { | |
836 | int apic; | |
54168ed7 | 837 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 838 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
839 | return apic; |
840 | } | |
841 | } | |
842 | ||
843 | return -1; | |
844 | } | |
845 | ||
c0a282c2 | 846 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
847 | /* |
848 | * EISA Edge/Level control register, ELCR | |
849 | */ | |
850 | static int EISA_ELCR(unsigned int irq) | |
851 | { | |
b81bb373 | 852 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
853 | unsigned int port = 0x4d0 + (irq >> 3); |
854 | return (inb(port) >> (irq & 7)) & 1; | |
855 | } | |
856 | apic_printk(APIC_VERBOSE, KERN_INFO | |
857 | "Broken MPtable reports ISA irq %d\n", irq); | |
858 | return 0; | |
859 | } | |
54168ed7 | 860 | |
c0a282c2 | 861 | #endif |
1da177e4 | 862 | |
6728801d AS |
863 | /* ISA interrupts are always polarity zero edge triggered, |
864 | * when listed as conforming in the MP table. */ | |
865 | ||
866 | #define default_ISA_trigger(idx) (0) | |
867 | #define default_ISA_polarity(idx) (0) | |
868 | ||
1da177e4 LT |
869 | /* EISA interrupts are always polarity zero and can be edge or level |
870 | * trigger depending on the ELCR value. If an interrupt is listed as | |
871 | * EISA conforming in the MP table, that means its trigger type must | |
872 | * be read in from the ELCR */ | |
873 | ||
c2c21745 | 874 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 875 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
876 | |
877 | /* PCI interrupts are always polarity one level triggered, | |
878 | * when listed as conforming in the MP table. */ | |
879 | ||
880 | #define default_PCI_trigger(idx) (1) | |
881 | #define default_PCI_polarity(idx) (1) | |
882 | ||
883 | /* MCA interrupts are always polarity zero level triggered, | |
884 | * when listed as conforming in the MP table. */ | |
885 | ||
886 | #define default_MCA_trigger(idx) (1) | |
6728801d | 887 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 888 | |
61fd47e0 | 889 | static int MPBIOS_polarity(int idx) |
1da177e4 | 890 | { |
c2c21745 | 891 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
892 | int polarity; |
893 | ||
894 | /* | |
895 | * Determine IRQ line polarity (high active or low active): | |
896 | */ | |
c2c21745 | 897 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 898 | { |
54168ed7 IM |
899 | case 0: /* conforms, ie. bus-type dependent polarity */ |
900 | if (test_bit(bus, mp_bus_not_pci)) | |
901 | polarity = default_ISA_polarity(idx); | |
902 | else | |
903 | polarity = default_PCI_polarity(idx); | |
904 | break; | |
905 | case 1: /* high active */ | |
906 | { | |
907 | polarity = 0; | |
908 | break; | |
909 | } | |
910 | case 2: /* reserved */ | |
911 | { | |
912 | printk(KERN_WARNING "broken BIOS!!\n"); | |
913 | polarity = 1; | |
914 | break; | |
915 | } | |
916 | case 3: /* low active */ | |
917 | { | |
918 | polarity = 1; | |
919 | break; | |
920 | } | |
921 | default: /* invalid */ | |
922 | { | |
923 | printk(KERN_WARNING "broken BIOS!!\n"); | |
924 | polarity = 1; | |
925 | break; | |
926 | } | |
1da177e4 LT |
927 | } |
928 | return polarity; | |
929 | } | |
930 | ||
931 | static int MPBIOS_trigger(int idx) | |
932 | { | |
c2c21745 | 933 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
934 | int trigger; |
935 | ||
936 | /* | |
937 | * Determine IRQ trigger mode (edge or level sensitive): | |
938 | */ | |
c2c21745 | 939 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 940 | { |
54168ed7 IM |
941 | case 0: /* conforms, ie. bus-type dependent */ |
942 | if (test_bit(bus, mp_bus_not_pci)) | |
943 | trigger = default_ISA_trigger(idx); | |
944 | else | |
945 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 946 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
947 | switch (mp_bus_id_to_type[bus]) { |
948 | case MP_BUS_ISA: /* ISA pin */ | |
949 | { | |
950 | /* set before the switch */ | |
951 | break; | |
952 | } | |
953 | case MP_BUS_EISA: /* EISA pin */ | |
954 | { | |
955 | trigger = default_EISA_trigger(idx); | |
956 | break; | |
957 | } | |
958 | case MP_BUS_PCI: /* PCI pin */ | |
959 | { | |
960 | /* set before the switch */ | |
961 | break; | |
962 | } | |
963 | case MP_BUS_MCA: /* MCA pin */ | |
964 | { | |
965 | trigger = default_MCA_trigger(idx); | |
966 | break; | |
967 | } | |
968 | default: | |
969 | { | |
970 | printk(KERN_WARNING "broken BIOS!!\n"); | |
971 | trigger = 1; | |
972 | break; | |
973 | } | |
974 | } | |
975 | #endif | |
1da177e4 | 976 | break; |
54168ed7 | 977 | case 1: /* edge */ |
1da177e4 | 978 | { |
54168ed7 | 979 | trigger = 0; |
1da177e4 LT |
980 | break; |
981 | } | |
54168ed7 | 982 | case 2: /* reserved */ |
1da177e4 | 983 | { |
54168ed7 IM |
984 | printk(KERN_WARNING "broken BIOS!!\n"); |
985 | trigger = 1; | |
1da177e4 LT |
986 | break; |
987 | } | |
54168ed7 | 988 | case 3: /* level */ |
1da177e4 | 989 | { |
54168ed7 | 990 | trigger = 1; |
1da177e4 LT |
991 | break; |
992 | } | |
54168ed7 | 993 | default: /* invalid */ |
1da177e4 LT |
994 | { |
995 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 996 | trigger = 0; |
1da177e4 LT |
997 | break; |
998 | } | |
999 | } | |
1000 | return trigger; | |
1001 | } | |
1002 | ||
1003 | static inline int irq_polarity(int idx) | |
1004 | { | |
1005 | return MPBIOS_polarity(idx); | |
1006 | } | |
1007 | ||
1008 | static inline int irq_trigger(int idx) | |
1009 | { | |
1010 | return MPBIOS_trigger(idx); | |
1011 | } | |
1012 | ||
1013 | static int pin_2_irq(int idx, int apic, int pin) | |
1014 | { | |
d464207c | 1015 | int irq; |
c2c21745 | 1016 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1017 | |
1018 | /* | |
1019 | * Debugging check, we are in big trouble if this message pops up! | |
1020 | */ | |
c2c21745 | 1021 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1022 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1023 | ||
54168ed7 | 1024 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1025 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1026 | } else { |
d464207c | 1027 | u32 gsi = mp_gsi_routing[apic].gsi_base + pin; |
988856ee EB |
1028 | |
1029 | if (gsi >= NR_IRQS_LEGACY) | |
1030 | irq = gsi; | |
1031 | else | |
a4384df3 | 1032 | irq = gsi_top + gsi; |
1da177e4 LT |
1033 | } |
1034 | ||
54168ed7 | 1035 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1036 | /* |
1037 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1038 | */ | |
1039 | if ((pin >= 16) && (pin <= 23)) { | |
1040 | if (pirq_entries[pin-16] != -1) { | |
1041 | if (!pirq_entries[pin-16]) { | |
1042 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1043 | "disabling PIRQ%d\n", pin-16); | |
1044 | } else { | |
1045 | irq = pirq_entries[pin-16]; | |
1046 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1047 | "using PIRQ%d -> IRQ %d\n", | |
1048 | pin-16, irq); | |
1049 | } | |
1050 | } | |
1051 | } | |
54168ed7 IM |
1052 | #endif |
1053 | ||
1da177e4 LT |
1054 | return irq; |
1055 | } | |
1056 | ||
e20c06fd YL |
1057 | /* |
1058 | * Find a specific PCI IRQ entry. | |
1059 | * Not an __init, possibly needed by modules | |
1060 | */ | |
1061 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1062 | struct io_apic_irq_attr *irq_attr) |
e20c06fd YL |
1063 | { |
1064 | int apic, i, best_guess = -1; | |
1065 | ||
1066 | apic_printk(APIC_DEBUG, | |
1067 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1068 | bus, slot, pin); | |
1069 | if (test_bit(bus, mp_bus_not_pci)) { | |
1070 | apic_printk(APIC_VERBOSE, | |
1071 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1072 | return -1; | |
1073 | } | |
1074 | for (i = 0; i < mp_irq_entries; i++) { | |
1075 | int lbus = mp_irqs[i].srcbus; | |
1076 | ||
1077 | for (apic = 0; apic < nr_ioapics; apic++) | |
1078 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || | |
1079 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1080 | break; | |
1081 | ||
1082 | if (!test_bit(lbus, mp_bus_not_pci) && | |
1083 | !mp_irqs[i].irqtype && | |
1084 | (bus == lbus) && | |
1085 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
1086 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1087 | ||
1088 | if (!(apic || IO_APIC_IRQ(irq))) | |
1089 | continue; | |
1090 | ||
1091 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
e5198075 YL |
1092 | set_io_apic_irq_attr(irq_attr, apic, |
1093 | mp_irqs[i].dstirq, | |
1094 | irq_trigger(i), | |
1095 | irq_polarity(i)); | |
e20c06fd YL |
1096 | return irq; |
1097 | } | |
1098 | /* | |
1099 | * Use the first all-but-pin matching entry as a | |
1100 | * best-guess fuzzy result for broken mptables. | |
1101 | */ | |
1102 | if (best_guess < 0) { | |
e5198075 YL |
1103 | set_io_apic_irq_attr(irq_attr, apic, |
1104 | mp_irqs[i].dstirq, | |
1105 | irq_trigger(i), | |
1106 | irq_polarity(i)); | |
e20c06fd YL |
1107 | best_guess = irq; |
1108 | } | |
1109 | } | |
1110 | } | |
1111 | return best_guess; | |
1112 | } | |
1113 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1114 | ||
497c9a19 YL |
1115 | void lock_vector_lock(void) |
1116 | { | |
1117 | /* Used to the online set of cpus does not change | |
1118 | * during assign_irq_vector. | |
1119 | */ | |
dade7716 | 1120 | raw_spin_lock(&vector_lock); |
497c9a19 | 1121 | } |
1da177e4 | 1122 | |
497c9a19 | 1123 | void unlock_vector_lock(void) |
1da177e4 | 1124 | { |
dade7716 | 1125 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1126 | } |
1da177e4 | 1127 | |
e7986739 MT |
1128 | static int |
1129 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1130 | { |
047c8fdb YL |
1131 | /* |
1132 | * NOTE! The local APIC isn't very good at handling | |
1133 | * multiple interrupts at the same interrupt level. | |
1134 | * As the interrupt level is determined by taking the | |
1135 | * vector number and shifting that right by 4, we | |
1136 | * want to spread these out a bit so that they don't | |
1137 | * all fall in the same interrupt level. | |
1138 | * | |
1139 | * Also, we've got to be careful not to trash gate | |
1140 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1141 | */ | |
6579b474 | 1142 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
ea943966 | 1143 | static int current_offset = VECTOR_OFFSET_START % 8; |
54168ed7 | 1144 | unsigned int old_vector; |
22f65d31 MT |
1145 | int cpu, err; |
1146 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1147 | |
23359a88 | 1148 | if (cfg->move_in_progress) |
54168ed7 | 1149 | return -EBUSY; |
0a1ad60d | 1150 | |
22f65d31 MT |
1151 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1152 | return -ENOMEM; | |
ace80ab7 | 1153 | |
54168ed7 IM |
1154 | old_vector = cfg->vector; |
1155 | if (old_vector) { | |
22f65d31 MT |
1156 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1157 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1158 | if (!cpumask_empty(tmp_mask)) { | |
1159 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1160 | return 0; |
22f65d31 | 1161 | } |
54168ed7 | 1162 | } |
497c9a19 | 1163 | |
e7986739 | 1164 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1165 | err = -ENOSPC; |
1166 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1167 | int new_cpu; |
1168 | int vector, offset; | |
497c9a19 | 1169 | |
e2d40b18 | 1170 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1171 | |
54168ed7 IM |
1172 | vector = current_vector; |
1173 | offset = current_offset; | |
497c9a19 | 1174 | next: |
54168ed7 IM |
1175 | vector += 8; |
1176 | if (vector >= first_system_vector) { | |
e7986739 | 1177 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 | 1178 | offset = (offset + 1) % 8; |
6579b474 | 1179 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 IM |
1180 | } |
1181 | if (unlikely(current_vector == vector)) | |
1182 | continue; | |
b77b881f YL |
1183 | |
1184 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1185 | goto next; |
b77b881f | 1186 | |
22f65d31 | 1187 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1188 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1189 | goto next; | |
1190 | /* Found one! */ | |
1191 | current_vector = vector; | |
1192 | current_offset = offset; | |
1193 | if (old_vector) { | |
1194 | cfg->move_in_progress = 1; | |
22f65d31 | 1195 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1196 | } |
22f65d31 | 1197 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1198 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1199 | cfg->vector = vector; | |
22f65d31 MT |
1200 | cpumask_copy(cfg->domain, tmp_mask); |
1201 | err = 0; | |
1202 | break; | |
54168ed7 | 1203 | } |
22f65d31 MT |
1204 | free_cpumask_var(tmp_mask); |
1205 | return err; | |
497c9a19 YL |
1206 | } |
1207 | ||
9338ad6f | 1208 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1209 | { |
1210 | int err; | |
ace80ab7 | 1211 | unsigned long flags; |
ace80ab7 | 1212 | |
dade7716 | 1213 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1214 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1215 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1216 | return err; |
1217 | } | |
1218 | ||
3145e941 | 1219 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1220 | { |
497c9a19 YL |
1221 | int cpu, vector; |
1222 | ||
497c9a19 YL |
1223 | BUG_ON(!cfg->vector); |
1224 | ||
1225 | vector = cfg->vector; | |
22f65d31 | 1226 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1227 | per_cpu(vector_irq, cpu)[vector] = -1; |
1228 | ||
1229 | cfg->vector = 0; | |
22f65d31 | 1230 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1231 | |
1232 | if (likely(!cfg->move_in_progress)) | |
1233 | return; | |
22f65d31 | 1234 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1235 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1236 | vector++) { | |
1237 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1238 | continue; | |
1239 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1240 | break; | |
1241 | } | |
1242 | } | |
1243 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1244 | } |
1245 | ||
1246 | void __setup_vector_irq(int cpu) | |
1247 | { | |
1248 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1249 | int irq, vector; |
1250 | struct irq_cfg *cfg; | |
0b8f1efa | 1251 | struct irq_desc *desc; |
497c9a19 | 1252 | |
9d133e5d SS |
1253 | /* |
1254 | * vector_lock will make sure that we don't run into irq vector | |
1255 | * assignments that might be happening on another cpu in parallel, | |
1256 | * while we setup our initial vector to irq mappings. | |
1257 | */ | |
dade7716 | 1258 | raw_spin_lock(&vector_lock); |
497c9a19 | 1259 | /* Mark the inuse vectors */ |
0b8f1efa | 1260 | for_each_irq_desc(irq, desc) { |
d4eba297 | 1261 | cfg = get_irq_desc_chip_data(desc); |
36e9e1ea SS |
1262 | |
1263 | /* | |
1264 | * If it is a legacy IRQ handled by the legacy PIC, this cpu | |
1265 | * will be part of the irq_cfg's domain. | |
1266 | */ | |
1267 | if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) | |
1268 | cpumask_set_cpu(cpu, cfg->domain); | |
1269 | ||
22f65d31 | 1270 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1271 | continue; |
1272 | vector = cfg->vector; | |
497c9a19 YL |
1273 | per_cpu(vector_irq, cpu)[vector] = irq; |
1274 | } | |
1275 | /* Mark the free vectors */ | |
1276 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1277 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1278 | if (irq < 0) | |
1279 | continue; | |
1280 | ||
1281 | cfg = irq_cfg(irq); | |
22f65d31 | 1282 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1283 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1284 | } |
dade7716 | 1285 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1286 | } |
3fde6900 | 1287 | |
f5b9ed7a | 1288 | static struct irq_chip ioapic_chip; |
54168ed7 | 1289 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1290 | |
54168ed7 IM |
1291 | #define IOAPIC_AUTO -1 |
1292 | #define IOAPIC_EDGE 0 | |
1293 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1294 | |
047c8fdb | 1295 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1296 | static inline int IO_APIC_irq_trigger(int irq) |
1297 | { | |
d6c88a50 | 1298 | int apic, idx, pin; |
1d025192 | 1299 | |
d6c88a50 TG |
1300 | for (apic = 0; apic < nr_ioapics; apic++) { |
1301 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1302 | idx = find_irq_entry(apic, pin, mp_INT); | |
1303 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1304 | return irq_trigger(idx); | |
1305 | } | |
1306 | } | |
1307 | /* | |
54168ed7 IM |
1308 | * nonexistent IRQs are edge default |
1309 | */ | |
d6c88a50 | 1310 | return 0; |
1d025192 | 1311 | } |
047c8fdb YL |
1312 | #else |
1313 | static inline int IO_APIC_irq_trigger(int irq) | |
1314 | { | |
54168ed7 | 1315 | return 1; |
047c8fdb YL |
1316 | } |
1317 | #endif | |
1d025192 | 1318 | |
3145e941 | 1319 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1320 | { |
199751d7 | 1321 | |
6ebcc00e | 1322 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1323 | trigger == IOAPIC_LEVEL) |
08678b08 | 1324 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1325 | else |
1326 | desc->status &= ~IRQ_LEVEL; | |
1327 | ||
54168ed7 IM |
1328 | if (irq_remapped(irq)) { |
1329 | desc->status |= IRQ_MOVE_PCNTXT; | |
1330 | if (trigger) | |
1331 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1332 | handle_fasteoi_irq, | |
1333 | "fasteoi"); | |
1334 | else | |
1335 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1336 | handle_edge_irq, "edge"); | |
1337 | return; | |
1338 | } | |
29b61be6 | 1339 | |
047c8fdb YL |
1340 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1341 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1342 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1343 | handle_fasteoi_irq, |
1344 | "fasteoi"); | |
047c8fdb | 1345 | else |
a460e745 | 1346 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1347 | handle_edge_irq, "edge"); |
1da177e4 LT |
1348 | } |
1349 | ||
ca97ab90 JF |
1350 | int setup_ioapic_entry(int apic_id, int irq, |
1351 | struct IO_APIC_route_entry *entry, | |
1352 | unsigned int destination, int trigger, | |
0280f7c4 | 1353 | int polarity, int vector, int pin) |
1da177e4 | 1354 | { |
497c9a19 YL |
1355 | /* |
1356 | * add it to the IO-APIC irq-routing table: | |
1357 | */ | |
1358 | memset(entry,0,sizeof(*entry)); | |
1359 | ||
54168ed7 | 1360 | if (intr_remapping_enabled) { |
c8d46cf0 | 1361 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1362 | struct irte irte; |
1363 | struct IR_IO_APIC_route_entry *ir_entry = | |
1364 | (struct IR_IO_APIC_route_entry *) entry; | |
1365 | int index; | |
1366 | ||
1367 | if (!iommu) | |
c8d46cf0 | 1368 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1369 | |
1370 | index = alloc_irte(iommu, irq, 1); | |
1371 | if (index < 0) | |
c8d46cf0 | 1372 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 | 1373 | |
62a92f4c | 1374 | prepare_irte(&irte, vector, destination); |
54168ed7 | 1375 | |
f007e99c WH |
1376 | /* Set source-id of interrupt request */ |
1377 | set_ioapic_sid(&irte, apic_id); | |
1378 | ||
54168ed7 IM |
1379 | modify_irte(irq, &irte); |
1380 | ||
1381 | ir_entry->index2 = (index >> 15) & 0x1; | |
1382 | ir_entry->zero = 0; | |
1383 | ir_entry->format = 1; | |
1384 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1385 | /* |
1386 | * IO-APIC RTE will be configured with virtual vector. | |
1387 | * irq handler will do the explicit EOI to the io-apic. | |
1388 | */ | |
1389 | ir_entry->vector = pin; | |
29b61be6 | 1390 | } else { |
9b5bc8dc IM |
1391 | entry->delivery_mode = apic->irq_delivery_mode; |
1392 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1393 | entry->dest = destination; |
0280f7c4 | 1394 | entry->vector = vector; |
54168ed7 | 1395 | } |
497c9a19 | 1396 | |
54168ed7 | 1397 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1398 | entry->trigger = trigger; |
1399 | entry->polarity = polarity; | |
497c9a19 YL |
1400 | |
1401 | /* Mask level triggered irqs. | |
1402 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1403 | */ | |
1404 | if (trigger) | |
1405 | entry->mask = 1; | |
497c9a19 YL |
1406 | return 0; |
1407 | } | |
1408 | ||
c8d46cf0 | 1409 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1410 | int trigger, int polarity) |
497c9a19 YL |
1411 | { |
1412 | struct irq_cfg *cfg; | |
1da177e4 | 1413 | struct IO_APIC_route_entry entry; |
22f65d31 | 1414 | unsigned int dest; |
497c9a19 YL |
1415 | |
1416 | if (!IO_APIC_IRQ(irq)) | |
1417 | return; | |
1418 | ||
d4eba297 | 1419 | cfg = get_irq_desc_chip_data(desc); |
497c9a19 | 1420 | |
69c89efb SS |
1421 | /* |
1422 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | |
1423 | * controllers like 8259. Now that IO-APIC can handle this irq, update | |
1424 | * the cfg->domain. | |
1425 | */ | |
28c6a0ba | 1426 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) |
69c89efb SS |
1427 | apic->vector_allocation_domain(0, cfg->domain); |
1428 | ||
fe402e1f | 1429 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1430 | return; |
1431 | ||
debccb3e | 1432 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1433 | |
1434 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1435 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1436 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1437 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1438 | irq, trigger, polarity); |
1439 | ||
1440 | ||
c8d46cf0 | 1441 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1442 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1443 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1444 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1445 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1446 | return; |
1447 | } | |
1448 | ||
3145e941 | 1449 | ioapic_register_intr(irq, desc, trigger); |
b81bb373 | 1450 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1451 | legacy_pic->mask(irq); |
497c9a19 | 1452 | |
c8d46cf0 | 1453 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1454 | } |
1455 | ||
b9c61b70 YL |
1456 | static struct { |
1457 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
1458 | } mp_ioapic_routing[MAX_IO_APICS]; | |
1459 | ||
497c9a19 YL |
1460 | static void __init setup_IO_APIC_irqs(void) |
1461 | { | |
fad53995 | 1462 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1463 | int notcon = 0; |
0b8f1efa | 1464 | struct irq_desc *desc; |
3145e941 | 1465 | struct irq_cfg *cfg; |
f6e9456c | 1466 | int node = cpu_to_node(0); |
1da177e4 LT |
1467 | |
1468 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1469 | ||
fad53995 | 1470 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) |
b9c61b70 YL |
1471 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { |
1472 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1473 | if (idx == -1) { | |
1474 | if (!notcon) { | |
1475 | notcon = 1; | |
1476 | apic_printk(APIC_VERBOSE, | |
1477 | KERN_DEBUG " %d-%d", | |
1478 | mp_ioapics[apic_id].apicid, pin); | |
1479 | } else | |
1480 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1481 | mp_ioapics[apic_id].apicid, pin); | |
1482 | continue; | |
1483 | } | |
1484 | if (notcon) { | |
1485 | apic_printk(APIC_VERBOSE, | |
1486 | " (apicid-pin) not connected\n"); | |
1487 | notcon = 0; | |
1488 | } | |
33a201fa | 1489 | |
b9c61b70 | 1490 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa | 1491 | |
fad53995 EB |
1492 | if ((apic_id > 0) && (irq > 16)) |
1493 | continue; | |
1494 | ||
b9c61b70 YL |
1495 | /* |
1496 | * Skip the timer IRQ if there's a quirk handler | |
1497 | * installed and if it returns 1: | |
1498 | */ | |
1499 | if (apic->multi_timer_check && | |
1500 | apic->multi_timer_check(apic_id, irq)) | |
1501 | continue; | |
36062448 | 1502 | |
b9c61b70 YL |
1503 | desc = irq_to_desc_alloc_node(irq, node); |
1504 | if (!desc) { | |
1505 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1506 | continue; | |
3c2cbd24 | 1507 | } |
d4eba297 | 1508 | cfg = get_irq_desc_chip_data(desc); |
b9c61b70 | 1509 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
4c6f18fc YL |
1510 | /* |
1511 | * don't mark it in pin_programmed, so later acpi could | |
1512 | * set it correctly when irq < 16 | |
1513 | */ | |
b9c61b70 YL |
1514 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
1515 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1516 | } |
1517 | ||
3c2cbd24 CG |
1518 | if (notcon) |
1519 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1520 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1521 | } |
1522 | ||
18dce6ba YL |
1523 | /* |
1524 | * for the gsit that is not in first ioapic | |
1525 | * but could not use acpi_register_gsi() | |
1526 | * like some special sci in IBM x3330 | |
1527 | */ | |
1528 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1529 | { | |
1530 | int apic_id = 0, pin, idx, irq; | |
f6e9456c | 1531 | int node = cpu_to_node(0); |
18dce6ba YL |
1532 | struct irq_desc *desc; |
1533 | struct irq_cfg *cfg; | |
1534 | ||
1535 | /* | |
1536 | * Convert 'gsi' to 'ioapic.pin'. | |
1537 | */ | |
1538 | apic_id = mp_find_ioapic(gsi); | |
1539 | if (apic_id < 0) | |
1540 | return; | |
1541 | ||
1542 | pin = mp_find_ioapic_pin(apic_id, gsi); | |
1543 | idx = find_irq_entry(apic_id, pin, mp_INT); | |
1544 | if (idx == -1) | |
1545 | return; | |
1546 | ||
1547 | irq = pin_2_irq(idx, apic_id, pin); | |
1548 | #ifdef CONFIG_SPARSE_IRQ | |
1549 | desc = irq_to_desc(irq); | |
1550 | if (desc) | |
1551 | return; | |
1552 | #endif | |
1553 | desc = irq_to_desc_alloc_node(irq, node); | |
1554 | if (!desc) { | |
1555 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1556 | return; | |
1557 | } | |
1558 | ||
d4eba297 | 1559 | cfg = get_irq_desc_chip_data(desc); |
18dce6ba YL |
1560 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
1561 | ||
1562 | if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) { | |
1563 | pr_debug("Pin %d-%d already programmed\n", | |
1564 | mp_ioapics[apic_id].apicid, pin); | |
1565 | return; | |
1566 | } | |
1567 | set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed); | |
1568 | ||
1569 | setup_IO_APIC_irq(apic_id, pin, irq, desc, | |
1570 | irq_trigger(idx), irq_polarity(idx)); | |
1571 | } | |
1572 | ||
1da177e4 | 1573 | /* |
f7633ce5 | 1574 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1575 | */ |
c8d46cf0 | 1576 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1577 | int vector) |
1da177e4 LT |
1578 | { |
1579 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1580 | |
54168ed7 IM |
1581 | if (intr_remapping_enabled) |
1582 | return; | |
54168ed7 | 1583 | |
36062448 | 1584 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1585 | |
1586 | /* | |
1587 | * We use logical delivery to get the timer IRQ | |
1588 | * to the first CPU. | |
1589 | */ | |
9b5bc8dc | 1590 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1591 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1592 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1593 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1594 | entry.polarity = 0; |
1595 | entry.trigger = 0; | |
1596 | entry.vector = vector; | |
1597 | ||
1598 | /* | |
1599 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1600 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1601 | */ |
54168ed7 | 1602 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1603 | |
1604 | /* | |
1605 | * Add it to the IO-APIC irq-routing table: | |
1606 | */ | |
c8d46cf0 | 1607 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1608 | } |
1609 | ||
32f71aff MR |
1610 | |
1611 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1612 | { |
1613 | int apic, i; | |
1614 | union IO_APIC_reg_00 reg_00; | |
1615 | union IO_APIC_reg_01 reg_01; | |
1616 | union IO_APIC_reg_02 reg_02; | |
1617 | union IO_APIC_reg_03 reg_03; | |
1618 | unsigned long flags; | |
0f978f45 | 1619 | struct irq_cfg *cfg; |
0b8f1efa | 1620 | struct irq_desc *desc; |
8f09cd20 | 1621 | unsigned int irq; |
1da177e4 | 1622 | |
36062448 | 1623 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1624 | for (i = 0; i < nr_ioapics; i++) |
1625 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1626 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1627 | |
1628 | /* | |
1629 | * We are a bit conservative about what we expect. We have to | |
1630 | * know about every hardware change ASAP. | |
1631 | */ | |
1632 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1633 | ||
1634 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1635 | ||
dade7716 | 1636 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
1637 | reg_00.raw = io_apic_read(apic, 0); |
1638 | reg_01.raw = io_apic_read(apic, 1); | |
1639 | if (reg_01.bits.version >= 0x10) | |
1640 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1641 | if (reg_01.bits.version >= 0x20) |
1642 | reg_03.raw = io_apic_read(apic, 3); | |
dade7716 | 1643 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1644 | |
54168ed7 | 1645 | printk("\n"); |
b5ba7e6d | 1646 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1647 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1648 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1649 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1650 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1651 | |
54168ed7 | 1652 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1653 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1654 | |
1655 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1656 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1657 | |
1658 | /* | |
1659 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1660 | * but the value of reg_02 is read as the previous read register | |
1661 | * value, so ignore it if reg_02 == reg_01. | |
1662 | */ | |
1663 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1664 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1665 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1666 | } |
1667 | ||
1668 | /* | |
1669 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1670 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1671 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1672 | */ | |
1673 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1674 | reg_03.raw != reg_01.raw) { | |
1675 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1676 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1677 | } |
1678 | ||
1679 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1680 | ||
d83e94ac | 1681 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
3235dc3f | 1682 | " Stat Dmod Deli Vect:\n"); |
1da177e4 LT |
1683 | |
1684 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1685 | struct IO_APIC_route_entry entry; | |
1686 | ||
cf4c6a2f | 1687 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1688 | |
54168ed7 IM |
1689 | printk(KERN_DEBUG " %02x %03X ", |
1690 | i, | |
1691 | entry.dest | |
1692 | ); | |
1da177e4 LT |
1693 | |
1694 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1695 | entry.mask, | |
1696 | entry.trigger, | |
1697 | entry.irr, | |
1698 | entry.polarity, | |
1699 | entry.delivery_status, | |
1700 | entry.dest_mode, | |
1701 | entry.delivery_mode, | |
1702 | entry.vector | |
1703 | ); | |
1704 | } | |
1705 | } | |
1da177e4 | 1706 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1707 | for_each_irq_desc(irq, desc) { |
1708 | struct irq_pin_list *entry; | |
1709 | ||
d4eba297 | 1710 | cfg = get_irq_desc_chip_data(desc); |
05e40760 DK |
1711 | if (!cfg) |
1712 | continue; | |
0b8f1efa | 1713 | entry = cfg->irq_2_pin; |
0f978f45 | 1714 | if (!entry) |
1da177e4 | 1715 | continue; |
8f09cd20 | 1716 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1717 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1da177e4 | 1718 | printk("-> %d:%d", entry->apic, entry->pin); |
1da177e4 LT |
1719 | printk("\n"); |
1720 | } | |
1721 | ||
1722 | printk(KERN_INFO ".................................... done.\n"); | |
1723 | ||
1724 | return; | |
1725 | } | |
1726 | ||
251e1e44 | 1727 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1728 | { |
251e1e44 | 1729 | int i; |
1da177e4 | 1730 | |
251e1e44 IM |
1731 | printk(KERN_DEBUG); |
1732 | ||
1733 | for (i = 0; i < 8; i++) | |
1734 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | |
1735 | ||
1736 | printk(KERN_CONT "\n"); | |
1da177e4 LT |
1737 | } |
1738 | ||
32f71aff | 1739 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1740 | { |
97a52714 | 1741 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1742 | u64 icr; |
1da177e4 | 1743 | |
251e1e44 | 1744 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1745 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1746 | v = apic_read(APIC_ID); |
54168ed7 | 1747 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1748 | v = apic_read(APIC_LVR); |
1749 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1750 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1751 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1752 | |
1753 | v = apic_read(APIC_TASKPRI); | |
1754 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1755 | ||
54168ed7 | 1756 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1757 | if (!APIC_XAPIC(ver)) { |
1758 | v = apic_read(APIC_ARBPRI); | |
1759 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1760 | v & APIC_ARBPRI_MASK); | |
1761 | } | |
1da177e4 LT |
1762 | v = apic_read(APIC_PROCPRI); |
1763 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1764 | } | |
1765 | ||
a11b5abe YL |
1766 | /* |
1767 | * Remote read supported only in the 82489DX and local APIC for | |
1768 | * Pentium processors. | |
1769 | */ | |
1770 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1771 | v = apic_read(APIC_RRR); | |
1772 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1773 | } | |
1774 | ||
1da177e4 LT |
1775 | v = apic_read(APIC_LDR); |
1776 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1777 | if (!x2apic_enabled()) { |
1778 | v = apic_read(APIC_DFR); | |
1779 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1780 | } | |
1da177e4 LT |
1781 | v = apic_read(APIC_SPIV); |
1782 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1783 | ||
1784 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1785 | print_APIC_field(APIC_ISR); |
1da177e4 | 1786 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1787 | print_APIC_field(APIC_TMR); |
1da177e4 | 1788 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1789 | print_APIC_field(APIC_IRR); |
1da177e4 | 1790 | |
54168ed7 IM |
1791 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1792 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1793 | apic_write(APIC_ESR, 0); |
54168ed7 | 1794 | |
1da177e4 LT |
1795 | v = apic_read(APIC_ESR); |
1796 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1797 | } | |
1798 | ||
7ab6af7a | 1799 | icr = apic_icr_read(); |
0c425cec IM |
1800 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1801 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1802 | |
1803 | v = apic_read(APIC_LVTT); | |
1804 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1805 | ||
1806 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1807 | v = apic_read(APIC_LVTPC); | |
1808 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1809 | } | |
1810 | v = apic_read(APIC_LVT0); | |
1811 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1812 | v = apic_read(APIC_LVT1); | |
1813 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1814 | ||
1815 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1816 | v = apic_read(APIC_LVTERR); | |
1817 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1818 | } | |
1819 | ||
1820 | v = apic_read(APIC_TMICT); | |
1821 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1822 | v = apic_read(APIC_TMCCT); | |
1823 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1824 | v = apic_read(APIC_TDCR); | |
1825 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1826 | |
1827 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1828 | v = apic_read(APIC_EFEAT); | |
1829 | maxlvt = (v >> 16) & 0xff; | |
1830 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1831 | v = apic_read(APIC_ECTRL); | |
1832 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1833 | for (i = 0; i < maxlvt; i++) { | |
1834 | v = apic_read(APIC_EILVTn(i)); | |
1835 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1836 | } | |
1837 | } | |
1da177e4 LT |
1838 | printk("\n"); |
1839 | } | |
1840 | ||
2626eb2b | 1841 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1842 | { |
ffd5aae7 YL |
1843 | int cpu; |
1844 | ||
2626eb2b CG |
1845 | if (!maxcpu) |
1846 | return; | |
1847 | ||
ffd5aae7 | 1848 | preempt_disable(); |
2626eb2b CG |
1849 | for_each_online_cpu(cpu) { |
1850 | if (cpu >= maxcpu) | |
1851 | break; | |
ffd5aae7 | 1852 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1853 | } |
ffd5aae7 | 1854 | preempt_enable(); |
1da177e4 LT |
1855 | } |
1856 | ||
32f71aff | 1857 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1858 | { |
1da177e4 LT |
1859 | unsigned int v; |
1860 | unsigned long flags; | |
1861 | ||
b81bb373 | 1862 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1863 | return; |
1864 | ||
1865 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1866 | ||
5619c280 | 1867 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1868 | |
1869 | v = inb(0xa1) << 8 | inb(0x21); | |
1870 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1871 | ||
1872 | v = inb(0xa0) << 8 | inb(0x20); | |
1873 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1874 | ||
54168ed7 IM |
1875 | outb(0x0b,0xa0); |
1876 | outb(0x0b,0x20); | |
1da177e4 | 1877 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1878 | outb(0x0a,0xa0); |
1879 | outb(0x0a,0x20); | |
1da177e4 | 1880 | |
5619c280 | 1881 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1882 | |
1883 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1884 | ||
1885 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1886 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1887 | } | |
1888 | ||
2626eb2b CG |
1889 | static int __initdata show_lapic = 1; |
1890 | static __init int setup_show_lapic(char *arg) | |
1891 | { | |
1892 | int num = -1; | |
1893 | ||
1894 | if (strcmp(arg, "all") == 0) { | |
1895 | show_lapic = CONFIG_NR_CPUS; | |
1896 | } else { | |
1897 | get_option(&arg, &num); | |
1898 | if (num >= 0) | |
1899 | show_lapic = num; | |
1900 | } | |
1901 | ||
1902 | return 1; | |
1903 | } | |
1904 | __setup("show_lapic=", setup_show_lapic); | |
1905 | ||
1906 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1907 | { |
2626eb2b CG |
1908 | if (apic_verbosity == APIC_QUIET) |
1909 | return 0; | |
1910 | ||
32f71aff | 1911 | print_PIC(); |
4797f6b0 YL |
1912 | |
1913 | /* don't print out if apic is not there */ | |
8312136f | 1914 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1915 | return 0; |
1916 | ||
2626eb2b | 1917 | print_local_APICs(show_lapic); |
32f71aff MR |
1918 | print_IO_APIC(); |
1919 | ||
1920 | return 0; | |
1921 | } | |
1922 | ||
2626eb2b | 1923 | fs_initcall(print_ICs); |
32f71aff | 1924 | |
1da177e4 | 1925 | |
efa2559f YL |
1926 | /* Where if anywhere is the i8259 connect in external int mode */ |
1927 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1928 | ||
54168ed7 | 1929 | void __init enable_IO_APIC(void) |
1da177e4 | 1930 | { |
fcfd636a | 1931 | int i8259_apic, i8259_pin; |
54168ed7 | 1932 | int apic; |
bc07844a | 1933 | |
b81bb373 | 1934 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1935 | return; |
1936 | ||
54168ed7 | 1937 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1938 | int pin; |
1939 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1940 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1941 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1942 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1943 | |
fcfd636a EB |
1944 | /* If the interrupt line is enabled and in ExtInt mode |
1945 | * I have found the pin where the i8259 is connected. | |
1946 | */ | |
1947 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1948 | ioapic_i8259.apic = apic; | |
1949 | ioapic_i8259.pin = pin; | |
1950 | goto found_i8259; | |
1951 | } | |
1952 | } | |
1953 | } | |
1954 | found_i8259: | |
1955 | /* Look to see what if the MP table has reported the ExtINT */ | |
1956 | /* If we could not find the appropriate pin by looking at the ioapic | |
1957 | * the i8259 probably is not connected the ioapic but give the | |
1958 | * mptable a chance anyway. | |
1959 | */ | |
1960 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1961 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1962 | /* Trust the MP table if nothing is setup in the hardware */ | |
1963 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1964 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1965 | ioapic_i8259.pin = i8259_pin; | |
1966 | ioapic_i8259.apic = i8259_apic; | |
1967 | } | |
1968 | /* Complain if the MP table and the hardware disagree */ | |
1969 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1970 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1971 | { | |
1972 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1973 | } |
1974 | ||
1975 | /* | |
1976 | * Do not trust the IO-APIC being empty at bootup | |
1977 | */ | |
1978 | clear_IO_APIC(); | |
1979 | } | |
1980 | ||
1981 | /* | |
1982 | * Not an __init, needed by the reboot code | |
1983 | */ | |
1984 | void disable_IO_APIC(void) | |
1985 | { | |
1986 | /* | |
1987 | * Clear the IO-APIC before rebooting: | |
1988 | */ | |
1989 | clear_IO_APIC(); | |
1990 | ||
b81bb373 | 1991 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1992 | return; |
1993 | ||
650927ef | 1994 | /* |
0b968d23 | 1995 | * If the i8259 is routed through an IOAPIC |
650927ef | 1996 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1997 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1998 | * |
1999 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
2000 | * as virtual wire B is little complex (need to configure both | |
2001 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
2002 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 2003 | */ |
7c6d9f97 | 2004 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 2005 | struct IO_APIC_route_entry entry; |
650927ef EB |
2006 | |
2007 | memset(&entry, 0, sizeof(entry)); | |
2008 | entry.mask = 0; /* Enabled */ | |
2009 | entry.trigger = 0; /* Edge */ | |
2010 | entry.irr = 0; | |
2011 | entry.polarity = 0; /* High */ | |
2012 | entry.delivery_status = 0; | |
2013 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2014 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2015 | entry.vector = 0; |
54168ed7 | 2016 | entry.dest = read_apic_id(); |
650927ef EB |
2017 | |
2018 | /* | |
2019 | * Add it to the IO-APIC irq-routing table: | |
2020 | */ | |
cf4c6a2f | 2021 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2022 | } |
54168ed7 | 2023 | |
7c6d9f97 SS |
2024 | /* |
2025 | * Use virtual wire A mode when interrupt remapping is enabled. | |
2026 | */ | |
8312136f | 2027 | if (cpu_has_apic || apic_from_smp_config()) |
3f4c3955 CG |
2028 | disconnect_bsp_APIC(!intr_remapping_enabled && |
2029 | ioapic_i8259.pin != -1); | |
1da177e4 LT |
2030 | } |
2031 | ||
54168ed7 | 2032 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2033 | /* |
2034 | * function to set the IO-APIC physical IDs based on the | |
2035 | * values stored in the MPC table. | |
2036 | * | |
2037 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2038 | */ | |
2039 | ||
de934103 | 2040 | void __init setup_ioapic_ids_from_mpc(void) |
1da177e4 LT |
2041 | { |
2042 | union IO_APIC_reg_00 reg_00; | |
2043 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2044 | int apic_id; |
1da177e4 LT |
2045 | int i; |
2046 | unsigned char old_id; | |
2047 | unsigned long flags; | |
2048 | ||
de934103 | 2049 | if (acpi_ioapic) |
d49c4288 | 2050 | return; |
ca05fea6 NP |
2051 | /* |
2052 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2053 | * no meaning without the serial APIC bus. | |
2054 | */ | |
7c5c1e42 SL |
2055 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2056 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2057 | return; |
1da177e4 LT |
2058 | /* |
2059 | * This is broken; anything with a real cpu count has to | |
2060 | * circumvent this idiocy regardless. | |
2061 | */ | |
7abc0753 | 2062 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
2063 | |
2064 | /* | |
2065 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2066 | */ | |
c8d46cf0 | 2067 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2068 | |
2069 | /* Read the register 0 value */ | |
dade7716 | 2070 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2071 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2072 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2073 | |
c8d46cf0 | 2074 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2075 | |
c8d46cf0 | 2076 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2077 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2078 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2079 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2080 | reg_00.bits.ID); | |
c8d46cf0 | 2081 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2082 | } |
2083 | ||
1da177e4 LT |
2084 | /* |
2085 | * Sanity check, is the ID really free? Every APIC in a | |
2086 | * system must have a unique ID or we get lots of nice | |
2087 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2088 | */ | |
7abc0753 | 2089 | if (apic->check_apicid_used(&phys_id_present_map, |
c8d46cf0 | 2090 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2091 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2092 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2093 | for (i = 0; i < get_physical_broadcast(); i++) |
2094 | if (!physid_isset(i, phys_id_present_map)) | |
2095 | break; | |
2096 | if (i >= get_physical_broadcast()) | |
2097 | panic("Max APIC ID exceeded!\n"); | |
2098 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2099 | i); | |
2100 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2101 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2102 | } else { |
2103 | physid_mask_t tmp; | |
7abc0753 | 2104 | apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp); |
1da177e4 LT |
2105 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2106 | "phys_id_present_map\n", | |
c8d46cf0 | 2107 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2108 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2109 | } | |
2110 | ||
2111 | ||
2112 | /* | |
2113 | * We need to adjust the IRQ routing table | |
2114 | * if the ID changed. | |
2115 | */ | |
c8d46cf0 | 2116 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2117 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2118 | if (mp_irqs[i].dstapic == old_id) |
2119 | mp_irqs[i].dstapic | |
c8d46cf0 | 2120 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2121 | |
2122 | /* | |
2123 | * Read the right value from the MPC table and | |
2124 | * write it into the ID register. | |
36062448 | 2125 | */ |
1da177e4 LT |
2126 | apic_printk(APIC_VERBOSE, KERN_INFO |
2127 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2128 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2129 | |
c8d46cf0 | 2130 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
dade7716 | 2131 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2132 | io_apic_write(apic_id, 0, reg_00.raw); |
dade7716 | 2133 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2134 | |
2135 | /* | |
2136 | * Sanity check | |
2137 | */ | |
dade7716 | 2138 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2139 | reg_00.raw = io_apic_read(apic_id, 0); |
dade7716 | 2140 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2141 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2142 | printk("could not set ID!\n"); |
2143 | else | |
2144 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2145 | } | |
2146 | } | |
54168ed7 | 2147 | #endif |
1da177e4 | 2148 | |
7ce0bcfd | 2149 | int no_timer_check __initdata; |
8542b200 ZA |
2150 | |
2151 | static int __init notimercheck(char *s) | |
2152 | { | |
2153 | no_timer_check = 1; | |
2154 | return 1; | |
2155 | } | |
2156 | __setup("no_timer_check", notimercheck); | |
2157 | ||
1da177e4 LT |
2158 | /* |
2159 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2160 | * about the timer IRQ. We do the following to work around the situation: | |
2161 | * | |
2162 | * - timer IRQ defaults to IO-APIC IRQ | |
2163 | * - if this function detects that timer IRQs are defunct, then we fall | |
2164 | * back to ISA timer IRQs | |
2165 | */ | |
f0a7a5c9 | 2166 | static int __init timer_irq_works(void) |
1da177e4 LT |
2167 | { |
2168 | unsigned long t1 = jiffies; | |
4aae0702 | 2169 | unsigned long flags; |
1da177e4 | 2170 | |
8542b200 ZA |
2171 | if (no_timer_check) |
2172 | return 1; | |
2173 | ||
4aae0702 | 2174 | local_save_flags(flags); |
1da177e4 LT |
2175 | local_irq_enable(); |
2176 | /* Let ten ticks pass... */ | |
2177 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2178 | local_irq_restore(flags); |
1da177e4 LT |
2179 | |
2180 | /* | |
2181 | * Expect a few ticks at least, to be sure some possible | |
2182 | * glue logic does not lock up after one or two first | |
2183 | * ticks in a non-ExtINT mode. Also the local APIC | |
2184 | * might have cached one ExtINT interrupt. Finally, at | |
2185 | * least one tick may be lost due to delays. | |
2186 | */ | |
54168ed7 IM |
2187 | |
2188 | /* jiffies wrap? */ | |
1d16b53e | 2189 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2190 | return 1; |
1da177e4 LT |
2191 | return 0; |
2192 | } | |
2193 | ||
2194 | /* | |
2195 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2196 | * number of pending IRQ events unhandled. These cases are very rare, | |
2197 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2198 | * better to do it this way as thus we do not have to be aware of | |
2199 | * 'pending' interrupts in the IRQ path, except at this point. | |
2200 | */ | |
2201 | /* | |
2202 | * Edge triggered needs to resend any interrupt | |
2203 | * that was delayed but this is now handled in the device | |
2204 | * independent code. | |
2205 | */ | |
2206 | ||
2207 | /* | |
2208 | * Starting up a edge-triggered IO-APIC interrupt is | |
2209 | * nasty - we need to make sure that we get the edge. | |
2210 | * If it is already asserted for some reason, we need | |
2211 | * return 1 to indicate that is was pending. | |
2212 | * | |
2213 | * This is not complete - we should be able to fake | |
2214 | * an edge even if it isn't on the 8259A... | |
2215 | */ | |
54168ed7 | 2216 | |
61a38ce3 | 2217 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2218 | { |
61a38ce3 | 2219 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2220 | unsigned long flags; |
2221 | ||
dade7716 | 2222 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2223 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2224 | legacy_pic->mask(irq); |
b81bb373 | 2225 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2226 | was_pending = 1; |
2227 | } | |
61a38ce3 | 2228 | __unmask_ioapic(data->chip_data); |
dade7716 | 2229 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2230 | |
2231 | return was_pending; | |
2232 | } | |
2233 | ||
90297c5f | 2234 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2235 | { |
90297c5f | 2236 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 IM |
2237 | unsigned long flags; |
2238 | ||
dade7716 | 2239 | raw_spin_lock_irqsave(&vector_lock, flags); |
dac5f412 | 2240 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
dade7716 | 2241 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2242 | |
2243 | return 1; | |
2244 | } | |
497c9a19 | 2245 | |
54168ed7 IM |
2246 | /* |
2247 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2248 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2249 | * handled with the level-triggered descriptor, but that one has slightly | |
2250 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2251 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2252 | * races. | |
2253 | */ | |
497c9a19 | 2254 | |
54168ed7 | 2255 | #ifdef CONFIG_SMP |
9338ad6f | 2256 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2257 | { |
2258 | cpumask_var_t cleanup_mask; | |
2259 | ||
2260 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2261 | unsigned int i; | |
e85abf8f GH |
2262 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2263 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2264 | } else { | |
2265 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2266 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2267 | free_cpumask_var(cleanup_mask); | |
2268 | } | |
2269 | cfg->move_in_progress = 0; | |
2270 | } | |
2271 | ||
4420471f | 2272 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2273 | { |
2274 | int apic, pin; | |
2275 | struct irq_pin_list *entry; | |
2276 | u8 vector = cfg->vector; | |
2277 | ||
2977fb3f | 2278 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
e85abf8f GH |
2279 | unsigned int reg; |
2280 | ||
e85abf8f GH |
2281 | apic = entry->apic; |
2282 | pin = entry->pin; | |
2283 | /* | |
2284 | * With interrupt-remapping, destination information comes | |
2285 | * from interrupt-remapping table entry. | |
2286 | */ | |
2287 | if (!irq_remapped(irq)) | |
2288 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2289 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2290 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2291 | reg |= vector; | |
2292 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
e85abf8f GH |
2293 | } |
2294 | } | |
2295 | ||
2296 | /* | |
2297 | * Either sets desc->affinity to a valid value, and returns | |
18374d89 | 2298 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
e85abf8f GH |
2299 | * leaves desc->affinity untouched. |
2300 | */ | |
9338ad6f | 2301 | unsigned int |
18374d89 SS |
2302 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask, |
2303 | unsigned int *dest_id) | |
e85abf8f GH |
2304 | { |
2305 | struct irq_cfg *cfg; | |
2306 | unsigned int irq; | |
2307 | ||
2308 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
18374d89 | 2309 | return -1; |
e85abf8f GH |
2310 | |
2311 | irq = desc->irq; | |
d4eba297 | 2312 | cfg = get_irq_desc_chip_data(desc); |
e85abf8f | 2313 | if (assign_irq_vector(irq, cfg, mask)) |
18374d89 | 2314 | return -1; |
e85abf8f | 2315 | |
e85abf8f GH |
2316 | cpumask_copy(desc->affinity, mask); |
2317 | ||
18374d89 SS |
2318 | *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); |
2319 | return 0; | |
e85abf8f GH |
2320 | } |
2321 | ||
4420471f | 2322 | static int |
e85abf8f GH |
2323 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2324 | { | |
2325 | struct irq_cfg *cfg; | |
2326 | unsigned long flags; | |
2327 | unsigned int dest; | |
2328 | unsigned int irq; | |
4420471f | 2329 | int ret = -1; |
e85abf8f GH |
2330 | |
2331 | irq = desc->irq; | |
d4eba297 | 2332 | cfg = get_irq_desc_chip_data(desc); |
e85abf8f | 2333 | |
dade7716 | 2334 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
18374d89 SS |
2335 | ret = set_desc_affinity(desc, mask, &dest); |
2336 | if (!ret) { | |
e85abf8f GH |
2337 | /* Only the high 8 bits are valid. */ |
2338 | dest = SET_APIC_LOGICAL_ID(dest); | |
2339 | __target_IO_APIC_irq(irq, dest, cfg); | |
2340 | } | |
dade7716 | 2341 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
4420471f IM |
2342 | |
2343 | return ret; | |
e85abf8f GH |
2344 | } |
2345 | ||
4420471f | 2346 | static int |
e85abf8f GH |
2347 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2348 | { | |
2349 | struct irq_desc *desc; | |
2350 | ||
2351 | desc = irq_to_desc(irq); | |
2352 | ||
4420471f | 2353 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2354 | } |
497c9a19 | 2355 | |
54168ed7 | 2356 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2357 | |
54168ed7 IM |
2358 | /* |
2359 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2360 | * | |
0280f7c4 SS |
2361 | * For both level and edge triggered, irq migration is a simple atomic |
2362 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2363 | * |
0280f7c4 SS |
2364 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2365 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2366 | * Real vector that is used for interrupting cpu will be coming from | |
2367 | * the interrupt-remapping table entry. | |
54168ed7 | 2368 | */ |
d5dedd45 | 2369 | static int |
e7986739 | 2370 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2371 | { |
54168ed7 | 2372 | struct irq_cfg *cfg; |
54168ed7 | 2373 | struct irte irte; |
54168ed7 | 2374 | unsigned int dest; |
3145e941 | 2375 | unsigned int irq; |
d5dedd45 | 2376 | int ret = -1; |
497c9a19 | 2377 | |
22f65d31 | 2378 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2379 | return ret; |
497c9a19 | 2380 | |
3145e941 | 2381 | irq = desc->irq; |
54168ed7 | 2382 | if (get_irte(irq, &irte)) |
d5dedd45 | 2383 | return ret; |
497c9a19 | 2384 | |
d4eba297 | 2385 | cfg = get_irq_desc_chip_data(desc); |
3145e941 | 2386 | if (assign_irq_vector(irq, cfg, mask)) |
d5dedd45 | 2387 | return ret; |
54168ed7 | 2388 | |
debccb3e | 2389 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2390 | |
54168ed7 IM |
2391 | irte.vector = cfg->vector; |
2392 | irte.dest_id = IRTE_DEST(dest); | |
2393 | ||
2394 | /* | |
2395 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2396 | */ | |
2397 | modify_irte(irq, &irte); | |
2398 | ||
22f65d31 MT |
2399 | if (cfg->move_in_progress) |
2400 | send_cleanup_vector(cfg); | |
54168ed7 | 2401 | |
7f7ace0c | 2402 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2403 | |
2404 | return 0; | |
54168ed7 IM |
2405 | } |
2406 | ||
54168ed7 IM |
2407 | /* |
2408 | * Migrates the IRQ destination in the process context. | |
2409 | */ | |
d5dedd45 | 2410 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2411 | const struct cpumask *mask) |
54168ed7 | 2412 | { |
d5dedd45 | 2413 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2414 | } |
d5dedd45 | 2415 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2416 | const struct cpumask *mask) |
3145e941 YL |
2417 | { |
2418 | struct irq_desc *desc = irq_to_desc(irq); | |
2419 | ||
d5dedd45 | 2420 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2421 | } |
29b61be6 | 2422 | #else |
d5dedd45 | 2423 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2424 | const struct cpumask *mask) |
2425 | { | |
d5dedd45 | 2426 | return 0; |
29b61be6 | 2427 | } |
54168ed7 IM |
2428 | #endif |
2429 | ||
2430 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2431 | { | |
2432 | unsigned vector, me; | |
8f2466f4 | 2433 | |
54168ed7 | 2434 | ack_APIC_irq(); |
54168ed7 | 2435 | exit_idle(); |
54168ed7 IM |
2436 | irq_enter(); |
2437 | ||
2438 | me = smp_processor_id(); | |
2439 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2440 | unsigned int irq; | |
68a8ca59 | 2441 | unsigned int irr; |
54168ed7 IM |
2442 | struct irq_desc *desc; |
2443 | struct irq_cfg *cfg; | |
2444 | irq = __get_cpu_var(vector_irq)[vector]; | |
2445 | ||
0b8f1efa YL |
2446 | if (irq == -1) |
2447 | continue; | |
2448 | ||
54168ed7 IM |
2449 | desc = irq_to_desc(irq); |
2450 | if (!desc) | |
2451 | continue; | |
2452 | ||
2453 | cfg = irq_cfg(irq); | |
239007b8 | 2454 | raw_spin_lock(&desc->lock); |
54168ed7 | 2455 | |
7f41c2e1 SS |
2456 | /* |
2457 | * Check if the irq migration is in progress. If so, we | |
2458 | * haven't received the cleanup request yet for this irq. | |
2459 | */ | |
2460 | if (cfg->move_in_progress) | |
2461 | goto unlock; | |
2462 | ||
22f65d31 | 2463 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2464 | goto unlock; |
2465 | ||
68a8ca59 SS |
2466 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2467 | /* | |
2468 | * Check if the vector that needs to be cleanedup is | |
2469 | * registered at the cpu's IRR. If so, then this is not | |
2470 | * the best time to clean it up. Lets clean it up in the | |
2471 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2472 | * to myself. | |
2473 | */ | |
2474 | if (irr & (1 << (vector % 32))) { | |
2475 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2476 | goto unlock; | |
2477 | } | |
54168ed7 | 2478 | __get_cpu_var(vector_irq)[vector] = -1; |
54168ed7 | 2479 | unlock: |
239007b8 | 2480 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2481 | } |
2482 | ||
2483 | irq_exit(); | |
2484 | } | |
2485 | ||
dd5f15e5 | 2486 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2487 | { |
a5e74b84 | 2488 | unsigned me; |
54168ed7 | 2489 | |
fcef5911 | 2490 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2491 | return; |
2492 | ||
54168ed7 | 2493 | me = smp_processor_id(); |
10b888d6 | 2494 | |
fcef5911 | 2495 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2496 | send_cleanup_vector(cfg); |
497c9a19 | 2497 | } |
a5e74b84 | 2498 | |
dd5f15e5 | 2499 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2500 | { |
dd5f15e5 | 2501 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2502 | } |
2503 | ||
2504 | void irq_force_complete_move(int irq) | |
2505 | { | |
dd5f15e5 | 2506 | struct irq_cfg *cfg = get_irq_chip_data(irq); |
a5e74b84 | 2507 | |
bbd391a1 PB |
2508 | if (!cfg) |
2509 | return; | |
2510 | ||
dd5f15e5 | 2511 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2512 | } |
497c9a19 | 2513 | #else |
dd5f15e5 | 2514 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2515 | #endif |
3145e941 | 2516 | |
90297c5f | 2517 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2518 | { |
90297c5f TG |
2519 | irq_complete_move(data->chip_data); |
2520 | move_native_irq(data->irq); | |
1d025192 YL |
2521 | ack_APIC_irq(); |
2522 | } | |
2523 | ||
3eb2cce8 | 2524 | atomic_t irq_mis_count; |
3eb2cce8 | 2525 | |
c29d9db3 SS |
2526 | /* |
2527 | * IO-APIC versions below 0x20 don't support EOI register. | |
2528 | * For the record, here is the information about various versions: | |
2529 | * 0Xh 82489DX | |
2530 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
2531 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
2532 | * 30h-FFh Reserved | |
2533 | * | |
2534 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
2535 | * version as 0x2. This is an error with documentation and these ICH chips | |
2536 | * use io-apic's of version 0x20. | |
2537 | * | |
2538 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
2539 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
2540 | * mode to edge and then back to level, with RTE being masked during this. | |
2541 | */ | |
dd5f15e5 | 2542 | static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
b3ec0a37 SS |
2543 | { |
2544 | struct irq_pin_list *entry; | |
dd5f15e5 | 2545 | unsigned long flags; |
b3ec0a37 | 2546 | |
dd5f15e5 | 2547 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b3ec0a37 | 2548 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
c29d9db3 SS |
2549 | if (mp_ioapics[entry->apic].apicver >= 0x20) { |
2550 | /* | |
2551 | * Intr-remapping uses pin number as the virtual vector | |
2552 | * in the RTE. Actual vector is programmed in | |
2553 | * intr-remapping table entry. Hence for the io-apic | |
2554 | * EOI we use the pin number. | |
2555 | */ | |
2556 | if (irq_remapped(irq)) | |
2557 | io_apic_eoi(entry->apic, entry->pin); | |
2558 | else | |
2559 | io_apic_eoi(entry->apic, cfg->vector); | |
2560 | } else { | |
2561 | __mask_and_edge_IO_APIC_irq(entry); | |
2562 | __unmask_and_level_IO_APIC_irq(entry); | |
2563 | } | |
b3ec0a37 | 2564 | } |
dade7716 | 2565 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
b3ec0a37 SS |
2566 | } |
2567 | ||
90297c5f | 2568 | static void ack_apic_level(struct irq_data *data) |
047c8fdb | 2569 | { |
90297c5f TG |
2570 | struct irq_cfg *cfg = data->chip_data; |
2571 | int i, do_unmask_irq = 0, irq = data->irq; | |
3145e941 | 2572 | struct irq_desc *desc = irq_to_desc(irq); |
3eb2cce8 | 2573 | unsigned long v; |
047c8fdb | 2574 | |
dd5f15e5 | 2575 | irq_complete_move(cfg); |
047c8fdb | 2576 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2577 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2578 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2579 | do_unmask_irq = 1; |
dd5f15e5 | 2580 | mask_ioapic(cfg); |
54168ed7 | 2581 | } |
047c8fdb YL |
2582 | #endif |
2583 | ||
3eb2cce8 | 2584 | /* |
916a0fe7 JF |
2585 | * It appears there is an erratum which affects at least version 0x11 |
2586 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2587 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2588 | * erroneously delivered as edge-triggered one but the respective IRR | |
2589 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2590 | * message but it will never arrive and further interrupts are blocked | |
2591 | * from the source. The exact reason is so far unknown, but the | |
2592 | * phenomenon was observed when two consecutive interrupt requests | |
2593 | * from a given source get delivered to the same CPU and the source is | |
2594 | * temporarily disabled in between. | |
2595 | * | |
2596 | * A workaround is to simulate an EOI message manually. We achieve it | |
2597 | * by setting the trigger mode to edge and then to level when the edge | |
2598 | * trigger mode gets detected in the TMR of a local APIC for a | |
2599 | * level-triggered interrupt. We mask the source for the time of the | |
2600 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2601 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2602 | * |
2603 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2604 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2605 | * destination that is handling the corresponding interrupt. This | |
2606 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2607 | * level-triggered io-apic interrupt will be seen as an edge | |
2608 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2609 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2610 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2611 | * supporting EOI register, we do an explicit EOI to clear the | |
2612 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2613 | * we use the above logic (mask+edge followed by unmask+level) from | |
2614 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2615 | */ |
3145e941 | 2616 | i = cfg->vector; |
3eb2cce8 | 2617 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2618 | |
54168ed7 IM |
2619 | /* |
2620 | * We must acknowledge the irq before we move it or the acknowledge will | |
2621 | * not propagate properly. | |
2622 | */ | |
2623 | ack_APIC_irq(); | |
2624 | ||
1c83995b SS |
2625 | /* |
2626 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2627 | * message via io-apic EOI register write or simulating it using | |
2628 | * mask+edge followed by unnask+level logic) manually when the | |
2629 | * level triggered interrupt is seen as the edge triggered interrupt | |
2630 | * at the cpu. | |
2631 | */ | |
ca64c47c MR |
2632 | if (!(v & (1 << (i & 0x1f)))) { |
2633 | atomic_inc(&irq_mis_count); | |
2634 | ||
dd5f15e5 | 2635 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2636 | } |
2637 | ||
54168ed7 IM |
2638 | /* Now we can move and renable the irq */ |
2639 | if (unlikely(do_unmask_irq)) { | |
2640 | /* Only migrate the irq if the ack has been received. | |
2641 | * | |
2642 | * On rare occasions the broadcast level triggered ack gets | |
2643 | * delayed going to ioapics, and if we reprogram the | |
2644 | * vector while Remote IRR is still set the irq will never | |
2645 | * fire again. | |
2646 | * | |
2647 | * To prevent this scenario we read the Remote IRR bit | |
2648 | * of the ioapic. This has two effects. | |
2649 | * - On any sane system the read of the ioapic will | |
2650 | * flush writes (and acks) going to the ioapic from | |
2651 | * this cpu. | |
2652 | * - We get to see if the ACK has actually been delivered. | |
2653 | * | |
2654 | * Based on failed experiments of reprogramming the | |
2655 | * ioapic entry from outside of irq context starting | |
2656 | * with masking the ioapic entry and then polling until | |
2657 | * Remote IRR was clear before reprogramming the | |
2658 | * ioapic I don't trust the Remote IRR bit to be | |
2659 | * completey accurate. | |
2660 | * | |
2661 | * However there appears to be no other way to plug | |
2662 | * this race, so if the Remote IRR bit is not | |
2663 | * accurate and is causing problems then it is a hardware bug | |
2664 | * and you can go talk to the chipset vendor about it. | |
2665 | */ | |
3145e941 | 2666 | if (!io_apic_level_ack_pending(cfg)) |
54168ed7 | 2667 | move_masked_irq(irq); |
dd5f15e5 | 2668 | unmask_ioapic(cfg); |
54168ed7 | 2669 | } |
3eb2cce8 | 2670 | } |
1d025192 | 2671 | |
d0b03bd1 | 2672 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 2673 | static void ir_ack_apic_edge(struct irq_data *data) |
d0b03bd1 | 2674 | { |
5d0ae2db | 2675 | ack_APIC_irq(); |
d0b03bd1 HW |
2676 | } |
2677 | ||
90297c5f | 2678 | static void ir_ack_apic_level(struct irq_data *data) |
d0b03bd1 | 2679 | { |
5d0ae2db | 2680 | ack_APIC_irq(); |
90297c5f | 2681 | eoi_ioapic_irq(data->irq, data->chip_data); |
d0b03bd1 HW |
2682 | } |
2683 | #endif /* CONFIG_INTR_REMAP */ | |
2684 | ||
f5b9ed7a | 2685 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 | 2686 | .name = "IO-APIC", |
61a38ce3 | 2687 | .irq_startup = startup_ioapic_irq, |
90297c5f TG |
2688 | .irq_mask = mask_ioapic_irq, |
2689 | .irq_unmask = unmask_ioapic_irq, | |
2690 | .irq_ack = ack_apic_edge, | |
2691 | .irq_eoi = ack_apic_level, | |
54d5d424 | 2692 | #ifdef CONFIG_SMP |
d6c88a50 | 2693 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2694 | #endif |
90297c5f | 2695 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2696 | }; |
2697 | ||
54168ed7 | 2698 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 | 2699 | .name = "IR-IO-APIC", |
61a38ce3 | 2700 | .irq_startup = startup_ioapic_irq, |
90297c5f TG |
2701 | .irq_mask = mask_ioapic_irq, |
2702 | .irq_unmask = unmask_ioapic_irq, | |
a1e38ca5 | 2703 | #ifdef CONFIG_INTR_REMAP |
90297c5f TG |
2704 | .irq_ack = ir_ack_apic_edge, |
2705 | .irq_eoi = ir_ack_apic_level, | |
54168ed7 | 2706 | #ifdef CONFIG_SMP |
d6c88a50 | 2707 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2708 | #endif |
54168ed7 | 2709 | #endif |
90297c5f | 2710 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 | 2711 | }; |
1da177e4 LT |
2712 | |
2713 | static inline void init_IO_APIC_traps(void) | |
2714 | { | |
2715 | int irq; | |
08678b08 | 2716 | struct irq_desc *desc; |
da51a821 | 2717 | struct irq_cfg *cfg; |
1da177e4 LT |
2718 | |
2719 | /* | |
2720 | * NOTE! The local APIC isn't very good at handling | |
2721 | * multiple interrupts at the same interrupt level. | |
2722 | * As the interrupt level is determined by taking the | |
2723 | * vector number and shifting that right by 4, we | |
2724 | * want to spread these out a bit so that they don't | |
2725 | * all fall in the same interrupt level. | |
2726 | * | |
2727 | * Also, we've got to be careful not to trash gate | |
2728 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2729 | */ | |
0b8f1efa | 2730 | for_each_irq_desc(irq, desc) { |
d4eba297 | 2731 | cfg = get_irq_desc_chip_data(desc); |
0b8f1efa | 2732 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2733 | /* |
2734 | * Hmm.. We don't have an entry for this, | |
2735 | * so default to an old-fashioned 8259 | |
2736 | * interrupt if we can.. | |
2737 | */ | |
b81bb373 JP |
2738 | if (irq < legacy_pic->nr_legacy_irqs) |
2739 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2740 | else |
1da177e4 | 2741 | /* Strange. Oh, well.. */ |
08678b08 | 2742 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2743 | } |
2744 | } | |
2745 | } | |
2746 | ||
f5b9ed7a IM |
2747 | /* |
2748 | * The local APIC irq-chip implementation: | |
2749 | */ | |
1da177e4 | 2750 | |
90297c5f | 2751 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2752 | { |
2753 | unsigned long v; | |
2754 | ||
2755 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2756 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2757 | } |
2758 | ||
90297c5f | 2759 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2760 | { |
f5b9ed7a | 2761 | unsigned long v; |
1da177e4 | 2762 | |
f5b9ed7a | 2763 | v = apic_read(APIC_LVT0); |
593f4a78 | 2764 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2765 | } |
1da177e4 | 2766 | |
90297c5f | 2767 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2768 | { |
2769 | ack_APIC_irq(); | |
2770 | } | |
2771 | ||
f5b9ed7a | 2772 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2773 | .name = "local-APIC", |
90297c5f TG |
2774 | .irq_mask = mask_lapic_irq, |
2775 | .irq_unmask = unmask_lapic_irq, | |
2776 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2777 | }; |
2778 | ||
3145e941 | 2779 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2780 | { |
08678b08 | 2781 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2782 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2783 | "edge"); | |
c88ac1df MR |
2784 | } |
2785 | ||
e9427101 | 2786 | static void __init setup_nmi(void) |
1da177e4 LT |
2787 | { |
2788 | /* | |
36062448 | 2789 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2790 | * We put the 8259A master into AEOI mode and |
2791 | * unmask on all local APICs LVT0 as NMI. | |
2792 | * | |
2793 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2794 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2795 | * the NMI handler or the timer interrupt. | |
36062448 | 2796 | */ |
1da177e4 LT |
2797 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2798 | ||
e9427101 | 2799 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2800 | |
2801 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2802 | } | |
2803 | ||
2804 | /* | |
2805 | * This looks a bit hackish but it's about the only one way of sending | |
2806 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2807 | * not support the ExtINT mode, unfortunately. We need to send these | |
2808 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2809 | * 8259A interrupt line asserted until INTA. --macro | |
2810 | */ | |
28acf285 | 2811 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2812 | { |
fcfd636a | 2813 | int apic, pin, i; |
1da177e4 LT |
2814 | struct IO_APIC_route_entry entry0, entry1; |
2815 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2816 | |
fcfd636a | 2817 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2818 | if (pin == -1) { |
2819 | WARN_ON_ONCE(1); | |
2820 | return; | |
2821 | } | |
fcfd636a | 2822 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2823 | if (apic == -1) { |
2824 | WARN_ON_ONCE(1); | |
1da177e4 | 2825 | return; |
956fb531 | 2826 | } |
1da177e4 | 2827 | |
cf4c6a2f | 2828 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2829 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2830 | |
2831 | memset(&entry1, 0, sizeof(entry1)); | |
2832 | ||
2833 | entry1.dest_mode = 0; /* physical delivery */ | |
2834 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2835 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2836 | entry1.delivery_mode = dest_ExtINT; |
2837 | entry1.polarity = entry0.polarity; | |
2838 | entry1.trigger = 0; | |
2839 | entry1.vector = 0; | |
2840 | ||
cf4c6a2f | 2841 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2842 | |
2843 | save_control = CMOS_READ(RTC_CONTROL); | |
2844 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2845 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2846 | RTC_FREQ_SELECT); | |
2847 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2848 | ||
2849 | i = 100; | |
2850 | while (i-- > 0) { | |
2851 | mdelay(10); | |
2852 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2853 | i -= 10; | |
2854 | } | |
2855 | ||
2856 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2857 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2858 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2859 | |
cf4c6a2f | 2860 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2861 | } |
2862 | ||
efa2559f | 2863 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2864 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2865 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2866 | { |
2867 | disable_timer_pin_1 = 1; | |
2868 | return 0; | |
2869 | } | |
54168ed7 | 2870 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2871 | |
2872 | int timer_through_8259 __initdata; | |
2873 | ||
1da177e4 LT |
2874 | /* |
2875 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2876 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2877 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2878 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2879 | * |
2880 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2881 | */ |
8542b200 | 2882 | static inline void __init check_timer(void) |
1da177e4 | 2883 | { |
3145e941 | 2884 | struct irq_desc *desc = irq_to_desc(0); |
d4eba297 | 2885 | struct irq_cfg *cfg = get_irq_desc_chip_data(desc); |
f6e9456c | 2886 | int node = cpu_to_node(0); |
fcfd636a | 2887 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2888 | unsigned long flags; |
047c8fdb | 2889 | int no_pin1 = 0; |
4aae0702 IM |
2890 | |
2891 | local_irq_save(flags); | |
d4d25dec | 2892 | |
1da177e4 LT |
2893 | /* |
2894 | * get/set the timer IRQ vector: | |
2895 | */ | |
4305df94 | 2896 | legacy_pic->mask(0); |
fe402e1f | 2897 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2898 | |
2899 | /* | |
d11d5794 MR |
2900 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2901 | * wire has to be disabled in the local APIC. Also | |
2902 | * timer interrupts need to be acknowledged manually in | |
2903 | * the 8259A for the i82489DX when using the NMI | |
2904 | * watchdog as that APIC treats NMIs as level-triggered. | |
2905 | * The AEOI mode will finish them in the 8259A | |
2906 | * automatically. | |
1da177e4 | 2907 | */ |
593f4a78 | 2908 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2909 | legacy_pic->init(1); |
54168ed7 | 2910 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2911 | { |
2912 | unsigned int ver; | |
2913 | ||
2914 | ver = apic_read(APIC_LVR); | |
2915 | ver = GET_APIC_VERSION(ver); | |
2916 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2917 | } | |
54168ed7 | 2918 | #endif |
1da177e4 | 2919 | |
fcfd636a EB |
2920 | pin1 = find_isa_irq_pin(0, mp_INT); |
2921 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2922 | pin2 = ioapic_i8259.pin; | |
2923 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2924 | |
49a66a0b MR |
2925 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2926 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2927 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2928 | |
691874fa MR |
2929 | /* |
2930 | * Some BIOS writers are clueless and report the ExtINTA | |
2931 | * I/O APIC input from the cascaded 8259A as the timer | |
2932 | * interrupt input. So just in case, if only one pin | |
2933 | * was found above, try it both directly and through the | |
2934 | * 8259A. | |
2935 | */ | |
2936 | if (pin1 == -1) { | |
54168ed7 IM |
2937 | if (intr_remapping_enabled) |
2938 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2939 | pin1 = pin2; |
2940 | apic1 = apic2; | |
2941 | no_pin1 = 1; | |
2942 | } else if (pin2 == -1) { | |
2943 | pin2 = pin1; | |
2944 | apic2 = apic1; | |
2945 | } | |
2946 | ||
1da177e4 LT |
2947 | if (pin1 != -1) { |
2948 | /* | |
2949 | * Ok, does IRQ0 through the IOAPIC work? | |
2950 | */ | |
691874fa | 2951 | if (no_pin1) { |
85ac16d0 | 2952 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2953 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2954 | } else { |
2955 | /* for edge trigger, setup_IO_APIC_irq already | |
2956 | * leave it unmasked. | |
2957 | * so only need to unmask if it is level-trigger | |
2958 | * do we really have level trigger timer? | |
2959 | */ | |
2960 | int idx; | |
2961 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2962 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2963 | unmask_ioapic(cfg); |
691874fa | 2964 | } |
1da177e4 LT |
2965 | if (timer_irq_works()) { |
2966 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 | 2967 | setup_nmi(); |
4305df94 | 2968 | legacy_pic->unmask(0); |
1da177e4 | 2969 | } |
66759a01 CE |
2970 | if (disable_timer_pin_1 > 0) |
2971 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2972 | goto out; |
1da177e4 | 2973 | } |
54168ed7 IM |
2974 | if (intr_remapping_enabled) |
2975 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2976 | local_irq_disable(); |
fcfd636a | 2977 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2978 | if (!no_pin1) |
49a66a0b MR |
2979 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2980 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2981 | |
49a66a0b MR |
2982 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2983 | "(IRQ0) through the 8259A ...\n"); | |
2984 | apic_printk(APIC_QUIET, KERN_INFO | |
2985 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2986 | /* |
2987 | * legacy devices should be connected to IO APIC #0 | |
2988 | */ | |
85ac16d0 | 2989 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2990 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2991 | legacy_pic->unmask(0); |
1da177e4 | 2992 | if (timer_irq_works()) { |
49a66a0b | 2993 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2994 | timer_through_8259 = 1; |
1da177e4 | 2995 | if (nmi_watchdog == NMI_IO_APIC) { |
4305df94 | 2996 | legacy_pic->mask(0); |
1da177e4 | 2997 | setup_nmi(); |
4305df94 | 2998 | legacy_pic->unmask(0); |
1da177e4 | 2999 | } |
4aae0702 | 3000 | goto out; |
1da177e4 LT |
3001 | } |
3002 | /* | |
3003 | * Cleanup, just in case ... | |
3004 | */ | |
f72dccac | 3005 | local_irq_disable(); |
4305df94 | 3006 | legacy_pic->mask(0); |
fcfd636a | 3007 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 3008 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 3009 | } |
1da177e4 LT |
3010 | |
3011 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
3012 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
3013 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 3014 | nmi_watchdog = NMI_NONE; |
1da177e4 | 3015 | } |
54168ed7 | 3016 | #ifdef CONFIG_X86_32 |
d11d5794 | 3017 | timer_ack = 0; |
54168ed7 | 3018 | #endif |
1da177e4 | 3019 | |
49a66a0b MR |
3020 | apic_printk(APIC_QUIET, KERN_INFO |
3021 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3022 | |
3145e941 | 3023 | lapic_register_intr(0, desc); |
497c9a19 | 3024 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 3025 | legacy_pic->unmask(0); |
1da177e4 LT |
3026 | |
3027 | if (timer_irq_works()) { | |
49a66a0b | 3028 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3029 | goto out; |
1da177e4 | 3030 | } |
f72dccac | 3031 | local_irq_disable(); |
4305df94 | 3032 | legacy_pic->mask(0); |
497c9a19 | 3033 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3034 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3035 | |
49a66a0b MR |
3036 | apic_printk(APIC_QUIET, KERN_INFO |
3037 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3038 | |
b81bb373 JP |
3039 | legacy_pic->init(0); |
3040 | legacy_pic->make_irq(0); | |
593f4a78 | 3041 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3042 | |
3043 | unlock_ExtINT_logic(); | |
3044 | ||
3045 | if (timer_irq_works()) { | |
49a66a0b | 3046 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3047 | goto out; |
1da177e4 | 3048 | } |
f72dccac | 3049 | local_irq_disable(); |
49a66a0b | 3050 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3051 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3052 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3053 | out: |
3054 | local_irq_restore(flags); | |
1da177e4 LT |
3055 | } |
3056 | ||
3057 | /* | |
af174783 MR |
3058 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3059 | * to devices. However there may be an I/O APIC pin available for | |
3060 | * this interrupt regardless. The pin may be left unconnected, but | |
3061 | * typically it will be reused as an ExtINT cascade interrupt for | |
3062 | * the master 8259A. In the MPS case such a pin will normally be | |
3063 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3064 | * there is no provision for ExtINT interrupts, and in the absence | |
3065 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3066 | * interrupt, that is edge-triggered and unmasked by default. We | |
3067 | * used to do this, but it caused problems on some systems because | |
3068 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3069 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3070 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3071 | * the I/O APIC in all cases now. No actual device should request | |
3072 | * it anyway. --macro | |
1da177e4 | 3073 | */ |
bc07844a | 3074 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
3075 | |
3076 | void __init setup_IO_APIC(void) | |
3077 | { | |
54168ed7 | 3078 | |
54168ed7 IM |
3079 | /* |
3080 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3081 | */ | |
b81bb373 | 3082 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 3083 | |
54168ed7 | 3084 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3085 | /* |
54168ed7 IM |
3086 | * Set up IO-APIC IRQ routing. |
3087 | */ | |
de934103 TG |
3088 | x86_init.mpparse.setup_ioapic_ids(); |
3089 | ||
1da177e4 LT |
3090 | sync_Arb_IDs(); |
3091 | setup_IO_APIC_irqs(); | |
3092 | init_IO_APIC_traps(); | |
b81bb373 | 3093 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 3094 | check_timer(); |
1da177e4 LT |
3095 | } |
3096 | ||
3097 | /* | |
54168ed7 IM |
3098 | * Called after all the initialization is done. If we didnt find any |
3099 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3100 | */ |
36062448 | 3101 | |
1da177e4 LT |
3102 | static int __init io_apic_bug_finalize(void) |
3103 | { | |
d6c88a50 TG |
3104 | if (sis_apic_bug == -1) |
3105 | sis_apic_bug = 0; | |
3106 | return 0; | |
1da177e4 LT |
3107 | } |
3108 | ||
3109 | late_initcall(io_apic_bug_finalize); | |
3110 | ||
3111 | struct sysfs_ioapic_data { | |
3112 | struct sys_device dev; | |
3113 | struct IO_APIC_route_entry entry[0]; | |
3114 | }; | |
54168ed7 | 3115 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3116 | |
438510f6 | 3117 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3118 | { |
3119 | struct IO_APIC_route_entry *entry; | |
3120 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3121 | int i; |
36062448 | 3122 | |
1da177e4 LT |
3123 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3124 | entry = data->entry; | |
54168ed7 IM |
3125 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3126 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3127 | |
3128 | return 0; | |
3129 | } | |
3130 | ||
3131 | static int ioapic_resume(struct sys_device *dev) | |
3132 | { | |
3133 | struct IO_APIC_route_entry *entry; | |
3134 | struct sysfs_ioapic_data *data; | |
3135 | unsigned long flags; | |
3136 | union IO_APIC_reg_00 reg_00; | |
3137 | int i; | |
36062448 | 3138 | |
1da177e4 LT |
3139 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3140 | entry = data->entry; | |
3141 | ||
dade7716 | 3142 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3143 | reg_00.raw = io_apic_read(dev->id, 0); |
b5ba7e6d JSR |
3144 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3145 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3146 | io_apic_write(dev->id, 0, reg_00.raw); |
3147 | } | |
dade7716 | 3148 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3149 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3150 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3151 | |
3152 | return 0; | |
3153 | } | |
3154 | ||
3155 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3156 | .name = "ioapic", |
1da177e4 LT |
3157 | .suspend = ioapic_suspend, |
3158 | .resume = ioapic_resume, | |
3159 | }; | |
3160 | ||
3161 | static int __init ioapic_init_sysfs(void) | |
3162 | { | |
54168ed7 IM |
3163 | struct sys_device * dev; |
3164 | int i, size, error; | |
1da177e4 LT |
3165 | |
3166 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3167 | if (error) | |
3168 | return error; | |
3169 | ||
54168ed7 | 3170 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3171 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3172 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3173 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3174 | if (!mp_ioapic_data[i]) { |
3175 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3176 | continue; | |
3177 | } | |
1da177e4 | 3178 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3179 | dev->id = i; |
1da177e4 LT |
3180 | dev->cls = &ioapic_sysdev_class; |
3181 | error = sysdev_register(dev); | |
3182 | if (error) { | |
3183 | kfree(mp_ioapic_data[i]); | |
3184 | mp_ioapic_data[i] = NULL; | |
3185 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3186 | continue; | |
3187 | } | |
3188 | } | |
3189 | ||
3190 | return 0; | |
3191 | } | |
3192 | ||
3193 | device_initcall(ioapic_init_sysfs); | |
3194 | ||
3fc471ed | 3195 | /* |
95d77884 | 3196 | * Dynamic irq allocate and deallocation |
3fc471ed | 3197 | */ |
d047f53a | 3198 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3199 | { |
ace80ab7 | 3200 | /* Allocate an unused irq */ |
54168ed7 IM |
3201 | unsigned int irq; |
3202 | unsigned int new; | |
3fc471ed | 3203 | unsigned long flags; |
0b8f1efa | 3204 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3205 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3206 | |
3207 | irq = 0; | |
abcaa2b8 YL |
3208 | if (irq_want < nr_irqs_gsi) |
3209 | irq_want = nr_irqs_gsi; | |
3210 | ||
dade7716 | 3211 | raw_spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3212 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3213 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3214 | if (!desc_new) { |
3215 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3216 | continue; |
0b8f1efa | 3217 | } |
d4eba297 | 3218 | cfg_new = get_irq_desc_chip_data(desc_new); |
0b8f1efa YL |
3219 | |
3220 | if (cfg_new->vector != 0) | |
ace80ab7 | 3221 | continue; |
d047f53a | 3222 | |
15e957d0 | 3223 | desc_new = move_irq_desc(desc_new, node); |
d4eba297 | 3224 | cfg_new = get_irq_desc_chip_data(desc_new); |
d047f53a | 3225 | |
fe402e1f | 3226 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3227 | irq = new; |
3228 | break; | |
3229 | } | |
dade7716 | 3230 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3231 | |
ced5b697 BP |
3232 | if (irq > 0) |
3233 | dynamic_irq_init_keep_chip_data(irq); | |
3fc471ed | 3234 | |
3fc471ed EB |
3235 | return irq; |
3236 | } | |
3237 | ||
199751d7 YL |
3238 | int create_irq(void) |
3239 | { | |
f6e9456c | 3240 | int node = cpu_to_node(0); |
be5d5350 | 3241 | unsigned int irq_want; |
54168ed7 IM |
3242 | int irq; |
3243 | ||
be5d5350 | 3244 | irq_want = nr_irqs_gsi; |
d047f53a | 3245 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3246 | |
3247 | if (irq == 0) | |
3248 | irq = -1; | |
3249 | ||
3250 | return irq; | |
199751d7 YL |
3251 | } |
3252 | ||
3fc471ed EB |
3253 | void destroy_irq(unsigned int irq) |
3254 | { | |
3255 | unsigned long flags; | |
3fc471ed | 3256 | |
ced5b697 | 3257 | dynamic_irq_cleanup_keep_chip_data(irq); |
3fc471ed | 3258 | |
54168ed7 | 3259 | free_irte(irq); |
dade7716 | 3260 | raw_spin_lock_irqsave(&vector_lock, flags); |
eb5b3794 | 3261 | __clear_irq_vector(irq, get_irq_chip_data(irq)); |
dade7716 | 3262 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
3fc471ed | 3263 | } |
3fc471ed | 3264 | |
2d3fcc1c | 3265 | /* |
27b46d76 | 3266 | * MSI message composition |
2d3fcc1c EB |
3267 | */ |
3268 | #ifdef CONFIG_PCI_MSI | |
c8bc6f3c SS |
3269 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
3270 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 3271 | { |
497c9a19 YL |
3272 | struct irq_cfg *cfg; |
3273 | int err; | |
2d3fcc1c EB |
3274 | unsigned dest; |
3275 | ||
f1182638 JB |
3276 | if (disable_apic) |
3277 | return -ENXIO; | |
3278 | ||
3145e941 | 3279 | cfg = irq_cfg(irq); |
fe402e1f | 3280 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3281 | if (err) |
3282 | return err; | |
2d3fcc1c | 3283 | |
debccb3e | 3284 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3285 | |
54168ed7 IM |
3286 | if (irq_remapped(irq)) { |
3287 | struct irte irte; | |
3288 | int ir_index; | |
3289 | u16 sub_handle; | |
3290 | ||
3291 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3292 | BUG_ON(ir_index == -1); | |
3293 | ||
62a92f4c | 3294 | prepare_irte(&irte, cfg->vector, dest); |
54168ed7 | 3295 | |
f007e99c | 3296 | /* Set source-id of interrupt request */ |
c8bc6f3c SS |
3297 | if (pdev) |
3298 | set_msi_sid(&irte, pdev); | |
3299 | else | |
3300 | set_hpet_sid(&irte, hpet_id); | |
f007e99c | 3301 | |
54168ed7 IM |
3302 | modify_irte(irq, &irte); |
3303 | ||
3304 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3305 | msg->data = sub_handle; | |
3306 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3307 | MSI_ADDR_IR_SHV | | |
3308 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3309 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3310 | } else { |
9d783ba0 SS |
3311 | if (x2apic_enabled()) |
3312 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3313 | MSI_ADDR_EXT_DEST_ID(dest); | |
3314 | else | |
3315 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3316 | ||
54168ed7 IM |
3317 | msg->address_lo = |
3318 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3319 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3320 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3321 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3322 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3323 | MSI_ADDR_REDIRECTION_CPU: |
3324 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3325 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3326 | |
54168ed7 IM |
3327 | msg->data = |
3328 | MSI_DATA_TRIGGER_EDGE | | |
3329 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3330 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3331 | MSI_DATA_DELIVERY_FIXED: |
3332 | MSI_DATA_DELIVERY_LOWPRI) | | |
3333 | MSI_DATA_VECTOR(cfg->vector); | |
3334 | } | |
497c9a19 | 3335 | return err; |
2d3fcc1c EB |
3336 | } |
3337 | ||
3b7d1921 | 3338 | #ifdef CONFIG_SMP |
d5dedd45 | 3339 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3340 | { |
3145e941 | 3341 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3342 | struct irq_cfg *cfg; |
3b7d1921 EB |
3343 | struct msi_msg msg; |
3344 | unsigned int dest; | |
3b7d1921 | 3345 | |
18374d89 | 3346 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3347 | return -1; |
2d3fcc1c | 3348 | |
d4eba297 | 3349 | cfg = get_irq_desc_chip_data(desc); |
2d3fcc1c | 3350 | |
39431acb | 3351 | __get_cached_msi_msg(desc->irq_data.msi_desc, &msg); |
3b7d1921 EB |
3352 | |
3353 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3354 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3355 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3356 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3357 | ||
39431acb | 3358 | __write_msi_msg(desc->irq_data.msi_desc, &msg); |
d5dedd45 YL |
3359 | |
3360 | return 0; | |
2d3fcc1c | 3361 | } |
54168ed7 IM |
3362 | #ifdef CONFIG_INTR_REMAP |
3363 | /* | |
3364 | * Migrate the MSI irq to another cpumask. This migration is | |
3365 | * done in the process context using interrupt-remapping hardware. | |
3366 | */ | |
d5dedd45 | 3367 | static int |
e7986739 | 3368 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3369 | { |
3145e941 | 3370 | struct irq_desc *desc = irq_to_desc(irq); |
d4eba297 | 3371 | struct irq_cfg *cfg = get_irq_desc_chip_data(desc); |
54168ed7 | 3372 | unsigned int dest; |
54168ed7 | 3373 | struct irte irte; |
54168ed7 IM |
3374 | |
3375 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3376 | return -1; |
54168ed7 | 3377 | |
18374d89 | 3378 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3379 | return -1; |
54168ed7 | 3380 | |
54168ed7 IM |
3381 | irte.vector = cfg->vector; |
3382 | irte.dest_id = IRTE_DEST(dest); | |
3383 | ||
3384 | /* | |
3385 | * atomically update the IRTE with the new destination and vector. | |
3386 | */ | |
3387 | modify_irte(irq, &irte); | |
3388 | ||
3389 | /* | |
3390 | * After this point, all the interrupts will start arriving | |
3391 | * at the new destination. So, time to cleanup the previous | |
3392 | * vector allocation. | |
3393 | */ | |
22f65d31 MT |
3394 | if (cfg->move_in_progress) |
3395 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3396 | |
3397 | return 0; | |
54168ed7 | 3398 | } |
3145e941 | 3399 | |
54168ed7 | 3400 | #endif |
3b7d1921 | 3401 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3402 | |
3b7d1921 EB |
3403 | /* |
3404 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3405 | * which implement the MSI or MSI-X Capability Structure. | |
3406 | */ | |
3407 | static struct irq_chip msi_chip = { | |
3408 | .name = "PCI-MSI", | |
1c9db525 TG |
3409 | .irq_unmask = unmask_msi_irq, |
3410 | .irq_mask = mask_msi_irq, | |
90297c5f | 3411 | .irq_ack = ack_apic_edge, |
3b7d1921 EB |
3412 | #ifdef CONFIG_SMP |
3413 | .set_affinity = set_msi_irq_affinity, | |
3414 | #endif | |
90297c5f | 3415 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3416 | }; |
3417 | ||
54168ed7 IM |
3418 | static struct irq_chip msi_ir_chip = { |
3419 | .name = "IR-PCI-MSI", | |
1c9db525 TG |
3420 | .irq_unmask = unmask_msi_irq, |
3421 | .irq_mask = mask_msi_irq, | |
a1e38ca5 | 3422 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 3423 | .irq_ack = ir_ack_apic_edge, |
54168ed7 IM |
3424 | #ifdef CONFIG_SMP |
3425 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3426 | #endif |
54168ed7 | 3427 | #endif |
90297c5f | 3428 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3429 | }; |
3430 | ||
3431 | /* | |
3432 | * Map the PCI dev to the corresponding remapping hardware unit | |
3433 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3434 | * in it. | |
3435 | */ | |
3436 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3437 | { | |
3438 | struct intel_iommu *iommu; | |
3439 | int index; | |
3440 | ||
3441 | iommu = map_dev_to_ir(dev); | |
3442 | if (!iommu) { | |
3443 | printk(KERN_ERR | |
3444 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3445 | return -ENOENT; | |
3446 | } | |
3447 | ||
3448 | index = alloc_irte(iommu, irq, nvec); | |
3449 | if (index < 0) { | |
3450 | printk(KERN_ERR | |
3451 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3452 | pci_name(dev)); |
54168ed7 IM |
3453 | return -ENOSPC; |
3454 | } | |
3455 | return index; | |
3456 | } | |
1d025192 | 3457 | |
3145e941 | 3458 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3459 | { |
3460 | int ret; | |
3461 | struct msi_msg msg; | |
3462 | ||
c8bc6f3c | 3463 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3464 | if (ret < 0) |
3465 | return ret; | |
3466 | ||
3145e941 | 3467 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3468 | write_msi_msg(irq, &msg); |
3469 | ||
54168ed7 IM |
3470 | if (irq_remapped(irq)) { |
3471 | struct irq_desc *desc = irq_to_desc(irq); | |
3472 | /* | |
3473 | * irq migration in process context | |
3474 | */ | |
3475 | desc->status |= IRQ_MOVE_PCNTXT; | |
3476 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3477 | } else | |
54168ed7 | 3478 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3479 | |
c81bba49 YL |
3480 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3481 | ||
1d025192 YL |
3482 | return 0; |
3483 | } | |
3484 | ||
047c8fdb YL |
3485 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3486 | { | |
54168ed7 IM |
3487 | unsigned int irq; |
3488 | int ret, sub_handle; | |
0b8f1efa | 3489 | struct msi_desc *msidesc; |
54168ed7 | 3490 | unsigned int irq_want; |
1cc18521 | 3491 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3492 | int index = 0; |
d047f53a | 3493 | int node; |
54168ed7 | 3494 | |
1c8d7b0a MW |
3495 | /* x86 doesn't support multiple MSI yet */ |
3496 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3497 | return 1; | |
3498 | ||
d047f53a | 3499 | node = dev_to_node(&dev->dev); |
be5d5350 | 3500 | irq_want = nr_irqs_gsi; |
54168ed7 | 3501 | sub_handle = 0; |
0b8f1efa | 3502 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3503 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3504 | if (irq == 0) |
3505 | return -1; | |
f1ee5548 | 3506 | irq_want = irq + 1; |
54168ed7 IM |
3507 | if (!intr_remapping_enabled) |
3508 | goto no_ir; | |
3509 | ||
3510 | if (!sub_handle) { | |
3511 | /* | |
3512 | * allocate the consecutive block of IRTE's | |
3513 | * for 'nvec' | |
3514 | */ | |
3515 | index = msi_alloc_irte(dev, irq, nvec); | |
3516 | if (index < 0) { | |
3517 | ret = index; | |
3518 | goto error; | |
3519 | } | |
3520 | } else { | |
3521 | iommu = map_dev_to_ir(dev); | |
3522 | if (!iommu) { | |
3523 | ret = -ENOENT; | |
3524 | goto error; | |
3525 | } | |
3526 | /* | |
3527 | * setup the mapping between the irq and the IRTE | |
3528 | * base index, the sub_handle pointing to the | |
3529 | * appropriate interrupt remap table entry. | |
3530 | */ | |
3531 | set_irte_irq(irq, iommu, index, sub_handle); | |
3532 | } | |
3533 | no_ir: | |
0b8f1efa | 3534 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3535 | if (ret < 0) |
3536 | goto error; | |
3537 | sub_handle++; | |
3538 | } | |
3539 | return 0; | |
047c8fdb YL |
3540 | |
3541 | error: | |
54168ed7 IM |
3542 | destroy_irq(irq); |
3543 | return ret; | |
047c8fdb YL |
3544 | } |
3545 | ||
3b7d1921 EB |
3546 | void arch_teardown_msi_irq(unsigned int irq) |
3547 | { | |
f7feaca7 | 3548 | destroy_irq(irq); |
3b7d1921 EB |
3549 | } |
3550 | ||
9d783ba0 | 3551 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3552 | #ifdef CONFIG_SMP |
d5dedd45 | 3553 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3554 | { |
3145e941 | 3555 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3556 | struct irq_cfg *cfg; |
3557 | struct msi_msg msg; | |
3558 | unsigned int dest; | |
54168ed7 | 3559 | |
18374d89 | 3560 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3561 | return -1; |
54168ed7 | 3562 | |
d4eba297 | 3563 | cfg = get_irq_desc_chip_data(desc); |
54168ed7 IM |
3564 | |
3565 | dmar_msi_read(irq, &msg); | |
3566 | ||
3567 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3568 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3569 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3570 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3571 | ||
3572 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3573 | |
3574 | return 0; | |
54168ed7 | 3575 | } |
3145e941 | 3576 | |
54168ed7 IM |
3577 | #endif /* CONFIG_SMP */ |
3578 | ||
8f7007aa | 3579 | static struct irq_chip dmar_msi_type = { |
54168ed7 | 3580 | .name = "DMAR_MSI", |
5c2837fb TG |
3581 | .irq_unmask = dmar_msi_unmask, |
3582 | .irq_mask = dmar_msi_mask, | |
90297c5f | 3583 | .irq_ack = ack_apic_edge, |
54168ed7 IM |
3584 | #ifdef CONFIG_SMP |
3585 | .set_affinity = dmar_msi_set_affinity, | |
3586 | #endif | |
90297c5f | 3587 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3588 | }; |
3589 | ||
3590 | int arch_setup_dmar_msi(unsigned int irq) | |
3591 | { | |
3592 | int ret; | |
3593 | struct msi_msg msg; | |
2d3fcc1c | 3594 | |
c8bc6f3c | 3595 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3596 | if (ret < 0) |
3597 | return ret; | |
3598 | dmar_msi_write(irq, &msg); | |
3599 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3600 | "edge"); | |
3601 | return 0; | |
3602 | } | |
3603 | #endif | |
3604 | ||
58ac1e76 | 3605 | #ifdef CONFIG_HPET_TIMER |
3606 | ||
3607 | #ifdef CONFIG_SMP | |
d0fbca8f TG |
3608 | static int hpet_msi_set_affinity(struct irq_data *data, |
3609 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3610 | { |
d0fbca8f TG |
3611 | struct irq_desc *desc = irq_to_desc(data->irq); |
3612 | struct irq_cfg *cfg = data->chip_data; | |
58ac1e76 | 3613 | struct msi_msg msg; |
3614 | unsigned int dest; | |
58ac1e76 | 3615 | |
18374d89 | 3616 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3617 | return -1; |
58ac1e76 | 3618 | |
d0fbca8f | 3619 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3620 | |
3621 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3622 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3623 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3624 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3625 | ||
d0fbca8f | 3626 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 YL |
3627 | |
3628 | return 0; | |
58ac1e76 | 3629 | } |
3145e941 | 3630 | |
58ac1e76 | 3631 | #endif /* CONFIG_SMP */ |
3632 | ||
c8bc6f3c SS |
3633 | static struct irq_chip ir_hpet_msi_type = { |
3634 | .name = "IR-HPET_MSI", | |
d0fbca8f TG |
3635 | .irq_unmask = hpet_msi_unmask, |
3636 | .irq_mask = hpet_msi_mask, | |
c8bc6f3c | 3637 | #ifdef CONFIG_INTR_REMAP |
90297c5f | 3638 | .irq_ack = ir_ack_apic_edge, |
c8bc6f3c SS |
3639 | #ifdef CONFIG_SMP |
3640 | .set_affinity = ir_set_msi_irq_affinity, | |
3641 | #endif | |
3642 | #endif | |
90297c5f | 3643 | .irq_retrigger = ioapic_retrigger_irq, |
c8bc6f3c SS |
3644 | }; |
3645 | ||
1cc18521 | 3646 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3647 | .name = "HPET_MSI", |
d0fbca8f TG |
3648 | .irq_unmask = hpet_msi_unmask, |
3649 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3650 | .irq_ack = ack_apic_edge, |
58ac1e76 | 3651 | #ifdef CONFIG_SMP |
d0fbca8f | 3652 | .irq_set_affinity = hpet_msi_set_affinity, |
58ac1e76 | 3653 | #endif |
90297c5f | 3654 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3655 | }; |
3656 | ||
c8bc6f3c | 3657 | int arch_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3658 | { |
58ac1e76 | 3659 | struct msi_msg msg; |
d0fbca8f | 3660 | int ret; |
58ac1e76 | 3661 | |
c8bc6f3c SS |
3662 | if (intr_remapping_enabled) { |
3663 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
3664 | int index; | |
3665 | ||
3666 | if (!iommu) | |
3667 | return -1; | |
3668 | ||
3669 | index = alloc_irte(iommu, irq, 1); | |
3670 | if (index < 0) | |
3671 | return -1; | |
3672 | } | |
3673 | ||
3674 | ret = msi_compose_msg(NULL, irq, &msg, id); | |
58ac1e76 | 3675 | if (ret < 0) |
3676 | return ret; | |
3677 | ||
d0fbca8f TG |
3678 | hpet_msi_write(get_irq_data(irq), &msg); |
3679 | irq_set_status_flags(irq,IRQ_MOVE_PCNTXT); | |
c8bc6f3c SS |
3680 | if (irq_remapped(irq)) |
3681 | set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type, | |
3682 | handle_edge_irq, "edge"); | |
3683 | else | |
3684 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, | |
3685 | handle_edge_irq, "edge"); | |
c81bba49 | 3686 | |
58ac1e76 | 3687 | return 0; |
3688 | } | |
3689 | #endif | |
3690 | ||
54168ed7 | 3691 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3692 | /* |
3693 | * Hypertransport interrupt support | |
3694 | */ | |
3695 | #ifdef CONFIG_HT_IRQ | |
3696 | ||
3697 | #ifdef CONFIG_SMP | |
3698 | ||
497c9a19 | 3699 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3700 | { |
ec68307c EB |
3701 | struct ht_irq_msg msg; |
3702 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3703 | |
497c9a19 | 3704 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3705 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3706 | |
497c9a19 | 3707 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3708 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3709 | |
ec68307c | 3710 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3711 | } |
3712 | ||
d5dedd45 | 3713 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3714 | { |
3145e941 | 3715 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3716 | struct irq_cfg *cfg; |
8b955b0d | 3717 | unsigned int dest; |
8b955b0d | 3718 | |
18374d89 | 3719 | if (set_desc_affinity(desc, mask, &dest)) |
d5dedd45 | 3720 | return -1; |
8b955b0d | 3721 | |
d4eba297 | 3722 | cfg = get_irq_desc_chip_data(desc); |
8b955b0d | 3723 | |
497c9a19 | 3724 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3725 | |
3726 | return 0; | |
8b955b0d | 3727 | } |
3145e941 | 3728 | |
8b955b0d EB |
3729 | #endif |
3730 | ||
c37e108d | 3731 | static struct irq_chip ht_irq_chip = { |
8b955b0d | 3732 | .name = "PCI-HT", |
e9f7ac66 TG |
3733 | .irq_mask = mask_ht_irq, |
3734 | .irq_unmask = unmask_ht_irq, | |
90297c5f | 3735 | .irq_ack = ack_apic_edge, |
8b955b0d EB |
3736 | #ifdef CONFIG_SMP |
3737 | .set_affinity = set_ht_irq_affinity, | |
3738 | #endif | |
90297c5f | 3739 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3740 | }; |
3741 | ||
3742 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3743 | { | |
497c9a19 YL |
3744 | struct irq_cfg *cfg; |
3745 | int err; | |
8b955b0d | 3746 | |
f1182638 JB |
3747 | if (disable_apic) |
3748 | return -ENXIO; | |
3749 | ||
3145e941 | 3750 | cfg = irq_cfg(irq); |
fe402e1f | 3751 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3752 | if (!err) { |
ec68307c | 3753 | struct ht_irq_msg msg; |
8b955b0d | 3754 | unsigned dest; |
8b955b0d | 3755 | |
debccb3e IM |
3756 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3757 | apic->target_cpus()); | |
8b955b0d | 3758 | |
ec68307c | 3759 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3760 | |
ec68307c EB |
3761 | msg.address_lo = |
3762 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3763 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3764 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3765 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3766 | HT_IRQ_LOW_DM_PHYSICAL : |
3767 | HT_IRQ_LOW_DM_LOGICAL) | | |
3768 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3769 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3770 | HT_IRQ_LOW_MT_FIXED : |
3771 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3772 | HT_IRQ_LOW_IRQ_MASKED; | |
3773 | ||
ec68307c | 3774 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3775 | |
a460e745 IM |
3776 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3777 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3778 | |
3779 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3780 | } |
497c9a19 | 3781 | return err; |
8b955b0d EB |
3782 | } |
3783 | #endif /* CONFIG_HT_IRQ */ | |
3784 | ||
9d6a4d08 YL |
3785 | int __init io_apic_get_redir_entries (int ioapic) |
3786 | { | |
3787 | union IO_APIC_reg_01 reg_01; | |
3788 | unsigned long flags; | |
3789 | ||
dade7716 | 3790 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3791 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3792 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3793 | |
4b6b19a1 EB |
3794 | /* The register returns the maximum index redir index |
3795 | * supported, which is one less than the total number of redir | |
3796 | * entries. | |
3797 | */ | |
3798 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3799 | } |
3800 | ||
be5d5350 | 3801 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3802 | { |
4afc51a8 | 3803 | int nr; |
be5d5350 | 3804 | |
a4384df3 | 3805 | nr = gsi_top + NR_IRQS_LEGACY; |
4afc51a8 | 3806 | if (nr > nr_irqs_gsi) |
be5d5350 | 3807 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3808 | |
3809 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3810 | } |
3811 | ||
4a046d17 YL |
3812 | #ifdef CONFIG_SPARSE_IRQ |
3813 | int __init arch_probe_nr_irqs(void) | |
3814 | { | |
3815 | int nr; | |
3816 | ||
f1ee5548 YL |
3817 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3818 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3819 | |
f1ee5548 YL |
3820 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3821 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3822 | /* | |
3823 | * for MSI and HT dyn irq | |
3824 | */ | |
3825 | nr += nr_irqs_gsi * 16; | |
3826 | #endif | |
3827 | if (nr < nr_irqs) | |
4a046d17 YL |
3828 | nr_irqs = nr; |
3829 | ||
b683de2b | 3830 | return NR_IRQS_LEGACY; |
4a046d17 YL |
3831 | } |
3832 | #endif | |
3833 | ||
e5198075 YL |
3834 | static int __io_apic_set_pci_routing(struct device *dev, int irq, |
3835 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 YL |
3836 | { |
3837 | struct irq_desc *desc; | |
3838 | struct irq_cfg *cfg; | |
3839 | int node; | |
e5198075 YL |
3840 | int ioapic, pin; |
3841 | int trigger, polarity; | |
5ef21837 | 3842 | |
e5198075 | 3843 | ioapic = irq_attr->ioapic; |
5ef21837 YL |
3844 | if (!IO_APIC_IRQ(irq)) { |
3845 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3846 | ioapic); | |
3847 | return -EINVAL; | |
3848 | } | |
3849 | ||
3850 | if (dev) | |
3851 | node = dev_to_node(dev); | |
3852 | else | |
f6e9456c | 3853 | node = cpu_to_node(0); |
5ef21837 YL |
3854 | |
3855 | desc = irq_to_desc_alloc_node(irq, node); | |
3856 | if (!desc) { | |
3857 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3858 | return 0; | |
3859 | } | |
3860 | ||
e5198075 YL |
3861 | pin = irq_attr->ioapic_pin; |
3862 | trigger = irq_attr->trigger; | |
3863 | polarity = irq_attr->polarity; | |
3864 | ||
5ef21837 YL |
3865 | /* |
3866 | * IRQs < 16 are already in the irq_2_pin[] map | |
3867 | */ | |
b81bb373 | 3868 | if (irq >= legacy_pic->nr_legacy_irqs) { |
d4eba297 | 3869 | cfg = get_irq_desc_chip_data(desc); |
f3d1915a CG |
3870 | if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { |
3871 | printk(KERN_INFO "can not add pin %d for irq %d\n", | |
3872 | pin, irq); | |
3873 | return 0; | |
3874 | } | |
5ef21837 YL |
3875 | } |
3876 | ||
e5198075 | 3877 | setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity); |
5ef21837 YL |
3878 | |
3879 | return 0; | |
3880 | } | |
3881 | ||
e5198075 YL |
3882 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3883 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3884 | { |
e5198075 | 3885 | int ioapic, pin; |
5ef21837 YL |
3886 | /* |
3887 | * Avoid pin reprogramming. PRTs typically include entries | |
3888 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3889 | * we only program the IOAPIC on the first. | |
3890 | */ | |
e5198075 YL |
3891 | ioapic = irq_attr->ioapic; |
3892 | pin = irq_attr->ioapic_pin; | |
5ef21837 YL |
3893 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { |
3894 | pr_debug("Pin %d-%d already programmed\n", | |
3895 | mp_ioapics[ioapic].apicid, pin); | |
3896 | return 0; | |
3897 | } | |
3898 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3899 | ||
e5198075 | 3900 | return __io_apic_set_pci_routing(dev, irq, irq_attr); |
5ef21837 YL |
3901 | } |
3902 | ||
2a4ab640 FT |
3903 | u8 __init io_apic_unique_id(u8 id) |
3904 | { | |
3905 | #ifdef CONFIG_X86_32 | |
3906 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3907 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3908 | return io_apic_get_unique_id(nr_ioapics, id); | |
3909 | else | |
3910 | return id; | |
3911 | #else | |
3912 | int i; | |
3913 | DECLARE_BITMAP(used, 256); | |
1da177e4 | 3914 | |
2a4ab640 FT |
3915 | bitmap_zero(used, 256); |
3916 | for (i = 0; i < nr_ioapics; i++) { | |
3917 | struct mpc_ioapic *ia = &mp_ioapics[i]; | |
3918 | __set_bit(ia->apicid, used); | |
3919 | } | |
3920 | if (!test_bit(id, used)) | |
3921 | return id; | |
3922 | return find_first_zero_bit(used, 256); | |
3923 | #endif | |
3924 | } | |
1da177e4 | 3925 | |
54168ed7 | 3926 | #ifdef CONFIG_X86_32 |
36062448 | 3927 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3928 | { |
3929 | union IO_APIC_reg_00 reg_00; | |
3930 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3931 | physid_mask_t tmp; | |
3932 | unsigned long flags; | |
3933 | int i = 0; | |
3934 | ||
3935 | /* | |
36062448 PC |
3936 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3937 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3938 | * supports up to 16 on one shared APIC bus. |
36062448 | 3939 | * |
1da177e4 LT |
3940 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3941 | * advantage of new APIC bus architecture. | |
3942 | */ | |
3943 | ||
3944 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3945 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3946 | |
dade7716 | 3947 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3948 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3949 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3950 | |
3951 | if (apic_id >= get_physical_broadcast()) { | |
3952 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3953 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3954 | apic_id = reg_00.bits.ID; | |
3955 | } | |
3956 | ||
3957 | /* | |
36062448 | 3958 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3959 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3960 | */ | |
7abc0753 | 3961 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3962 | |
3963 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3964 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3965 | break; |
3966 | } | |
3967 | ||
3968 | if (i == get_physical_broadcast()) | |
3969 | panic("Max apic_id exceeded!\n"); | |
3970 | ||
3971 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3972 | "trying %d\n", ioapic, apic_id, i); | |
3973 | ||
3974 | apic_id = i; | |
36062448 | 3975 | } |
1da177e4 | 3976 | |
7abc0753 | 3977 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3978 | physids_or(apic_id_map, apic_id_map, tmp); |
3979 | ||
3980 | if (reg_00.bits.ID != apic_id) { | |
3981 | reg_00.bits.ID = apic_id; | |
3982 | ||
dade7716 | 3983 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3984 | io_apic_write(ioapic, 0, reg_00.raw); |
3985 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3986 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3987 | |
3988 | /* Sanity check */ | |
6070f9ec AD |
3989 | if (reg_00.bits.ID != apic_id) { |
3990 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3991 | return -1; | |
3992 | } | |
1da177e4 LT |
3993 | } |
3994 | ||
3995 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3996 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3997 | ||
3998 | return apic_id; | |
3999 | } | |
58f892e0 | 4000 | #endif |
1da177e4 | 4001 | |
36062448 | 4002 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
4003 | { |
4004 | union IO_APIC_reg_01 reg_01; | |
4005 | unsigned long flags; | |
4006 | ||
dade7716 | 4007 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 4008 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 4009 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
4010 | |
4011 | return reg_01.bits.version; | |
4012 | } | |
4013 | ||
9a0a91bb | 4014 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 4015 | { |
9a0a91bb | 4016 | int ioapic, pin, idx; |
61fd47e0 SL |
4017 | |
4018 | if (skip_ioapic_setup) | |
4019 | return -1; | |
4020 | ||
9a0a91bb EB |
4021 | ioapic = mp_find_ioapic(gsi); |
4022 | if (ioapic < 0) | |
61fd47e0 SL |
4023 | return -1; |
4024 | ||
9a0a91bb EB |
4025 | pin = mp_find_ioapic_pin(ioapic, gsi); |
4026 | if (pin < 0) | |
4027 | return -1; | |
4028 | ||
4029 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
4030 | if (idx < 0) | |
61fd47e0 SL |
4031 | return -1; |
4032 | ||
9a0a91bb EB |
4033 | *trigger = irq_trigger(idx); |
4034 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
4035 | return 0; |
4036 | } | |
4037 | ||
497c9a19 YL |
4038 | /* |
4039 | * This function currently is only a helper for the i386 smp boot process where | |
4040 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4041 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4042 | */ |
4043 | #ifdef CONFIG_SMP | |
4044 | void __init setup_ioapic_dest(void) | |
4045 | { | |
fad53995 | 4046 | int pin, ioapic, irq, irq_entry; |
6c2e9403 | 4047 | struct irq_desc *desc; |
22f65d31 | 4048 | const struct cpumask *mask; |
497c9a19 YL |
4049 | |
4050 | if (skip_ioapic_setup == 1) | |
4051 | return; | |
4052 | ||
fad53995 | 4053 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
b9c61b70 YL |
4054 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { |
4055 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4056 | if (irq_entry == -1) | |
4057 | continue; | |
4058 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 4059 | |
fad53995 EB |
4060 | if ((ioapic > 0) && (irq > 16)) |
4061 | continue; | |
4062 | ||
b9c61b70 | 4063 | desc = irq_to_desc(irq); |
6c2e9403 | 4064 | |
b9c61b70 YL |
4065 | /* |
4066 | * Honour affinities which have been set in early boot | |
4067 | */ | |
4068 | if (desc->status & | |
4069 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4070 | mask = desc->affinity; | |
4071 | else | |
4072 | mask = apic->target_cpus(); | |
497c9a19 | 4073 | |
b9c61b70 YL |
4074 | if (intr_remapping_enabled) |
4075 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
4076 | else | |
4077 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 4078 | } |
b9c61b70 | 4079 | |
497c9a19 YL |
4080 | } |
4081 | #endif | |
4082 | ||
54168ed7 IM |
4083 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4084 | ||
4085 | static struct resource *ioapic_resources; | |
4086 | ||
ffc43836 | 4087 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
54168ed7 IM |
4088 | { |
4089 | unsigned long n; | |
4090 | struct resource *res; | |
4091 | char *mem; | |
4092 | int i; | |
4093 | ||
4094 | if (nr_ioapics <= 0) | |
4095 | return NULL; | |
4096 | ||
4097 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4098 | n *= nr_ioapics; | |
4099 | ||
4100 | mem = alloc_bootmem(n); | |
4101 | res = (void *)mem; | |
4102 | ||
ffc43836 | 4103 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 4104 | |
ffc43836 CG |
4105 | for (i = 0; i < nr_ioapics; i++) { |
4106 | res[i].name = mem; | |
4107 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 4108 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 4109 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
54168ed7 IM |
4110 | } |
4111 | ||
4112 | ioapic_resources = res; | |
4113 | ||
4114 | return res; | |
4115 | } | |
54168ed7 | 4116 | |
f3294a33 YL |
4117 | void __init ioapic_init_mappings(void) |
4118 | { | |
4119 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4120 | struct resource *ioapic_res; |
d6c88a50 | 4121 | int i; |
f3294a33 | 4122 | |
ffc43836 | 4123 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
f3294a33 YL |
4124 | for (i = 0; i < nr_ioapics; i++) { |
4125 | if (smp_found_config) { | |
b5ba7e6d | 4126 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4127 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4128 | if (!ioapic_phys) { |
4129 | printk(KERN_ERR | |
4130 | "WARNING: bogus zero IO-APIC " | |
4131 | "address found in MPTABLE, " | |
4132 | "disabling IO/APIC support!\n"); | |
4133 | smp_found_config = 0; | |
4134 | skip_ioapic_setup = 1; | |
4135 | goto fake_ioapic_page; | |
4136 | } | |
54168ed7 | 4137 | #endif |
f3294a33 | 4138 | } else { |
54168ed7 | 4139 | #ifdef CONFIG_X86_32 |
f3294a33 | 4140 | fake_ioapic_page: |
54168ed7 | 4141 | #endif |
e79c65a9 | 4142 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4143 | ioapic_phys = __pa(ioapic_phys); |
4144 | } | |
4145 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
4146 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
4147 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
4148 | ioapic_phys); | |
f3294a33 | 4149 | idx++; |
54168ed7 | 4150 | |
ffc43836 | 4151 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 4152 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 4153 | ioapic_res++; |
f3294a33 YL |
4154 | } |
4155 | } | |
4156 | ||
857fdc53 | 4157 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
4158 | { |
4159 | int i; | |
4160 | struct resource *r = ioapic_resources; | |
4161 | ||
4162 | if (!r) { | |
857fdc53 | 4163 | if (nr_ioapics > 0) |
04c93ce4 BZ |
4164 | printk(KERN_ERR |
4165 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 4166 | return; |
54168ed7 IM |
4167 | } |
4168 | ||
4169 | for (i = 0; i < nr_ioapics; i++) { | |
4170 | insert_resource(&iomem_resource, r); | |
4171 | r++; | |
4172 | } | |
54168ed7 | 4173 | } |
2a4ab640 | 4174 | |
eddb0c55 | 4175 | int mp_find_ioapic(u32 gsi) |
2a4ab640 FT |
4176 | { |
4177 | int i = 0; | |
4178 | ||
4179 | /* Find the IOAPIC that manages this GSI. */ | |
4180 | for (i = 0; i < nr_ioapics; i++) { | |
4181 | if ((gsi >= mp_gsi_routing[i].gsi_base) | |
4182 | && (gsi <= mp_gsi_routing[i].gsi_end)) | |
4183 | return i; | |
4184 | } | |
54168ed7 | 4185 | |
2a4ab640 FT |
4186 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
4187 | return -1; | |
4188 | } | |
4189 | ||
eddb0c55 | 4190 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 FT |
4191 | { |
4192 | if (WARN_ON(ioapic == -1)) | |
4193 | return -1; | |
4194 | if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end)) | |
4195 | return -1; | |
4196 | ||
4197 | return gsi - mp_gsi_routing[ioapic].gsi_base; | |
4198 | } | |
4199 | ||
4200 | static int bad_ioapic(unsigned long address) | |
4201 | { | |
4202 | if (nr_ioapics >= MAX_IO_APICS) { | |
4203 | printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded " | |
4204 | "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); | |
4205 | return 1; | |
4206 | } | |
4207 | if (!address) { | |
4208 | printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" | |
4209 | " found in table, skipping!\n"); | |
4210 | return 1; | |
4211 | } | |
54168ed7 IM |
4212 | return 0; |
4213 | } | |
4214 | ||
2a4ab640 FT |
4215 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
4216 | { | |
4217 | int idx = 0; | |
7716a5c4 | 4218 | int entries; |
2a4ab640 FT |
4219 | |
4220 | if (bad_ioapic(address)) | |
4221 | return; | |
4222 | ||
4223 | idx = nr_ioapics; | |
4224 | ||
4225 | mp_ioapics[idx].type = MP_IOAPIC; | |
4226 | mp_ioapics[idx].flags = MPC_APIC_USABLE; | |
4227 | mp_ioapics[idx].apicaddr = address; | |
4228 | ||
4229 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
4230 | mp_ioapics[idx].apicid = io_apic_unique_id(id); | |
4231 | mp_ioapics[idx].apicver = io_apic_get_version(idx); | |
4232 | ||
4233 | /* | |
4234 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
4235 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
4236 | */ | |
7716a5c4 | 4237 | entries = io_apic_get_redir_entries(idx); |
2a4ab640 | 4238 | mp_gsi_routing[idx].gsi_base = gsi_base; |
7716a5c4 EB |
4239 | mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1; |
4240 | ||
4241 | /* | |
4242 | * The number of IO-APIC IRQ registers (== #pins): | |
4243 | */ | |
4244 | nr_ioapic_registers[idx] = entries; | |
2a4ab640 | 4245 | |
a4384df3 EB |
4246 | if (mp_gsi_routing[idx].gsi_end >= gsi_top) |
4247 | gsi_top = mp_gsi_routing[idx].gsi_end + 1; | |
2a4ab640 FT |
4248 | |
4249 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " | |
4250 | "GSI %d-%d\n", idx, mp_ioapics[idx].apicid, | |
4251 | mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr, | |
4252 | mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end); | |
4253 | ||
4254 | nr_ioapics++; | |
4255 | } | |
05ddafb1 JP |
4256 | |
4257 | /* Enable IOAPIC early just for system timer */ | |
4258 | void __init pre_init_apic_IRQ0(void) | |
4259 | { | |
4260 | struct irq_cfg *cfg; | |
4261 | struct irq_desc *desc; | |
4262 | ||
4263 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
4264 | #ifndef CONFIG_SMP | |
4265 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
4266 | #endif | |
4267 | desc = irq_to_desc_alloc_node(0, 0); | |
4268 | ||
4269 | setup_local_APIC(); | |
4270 | ||
4271 | cfg = irq_cfg(0); | |
4272 | add_pin_to_irq_node(cfg, 0, 0, 0); | |
4273 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); | |
4274 | ||
4275 | setup_IO_APIC_irq(0, 0, 0, desc, 0, 0); | |
4276 | } |