[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / apic / msi.c

/*
 * Support of MSI, HPET and DMAR interrupts.
 *
 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *	Moved from arch/x86/kernel/apic/io_apic.c.
 * Jiang Liu <jiang.liu@linux.intel.com>
 *	Convert to hierarchical irqdomain
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/hpet.h>
#include <linux/msi.h>
#include <linux/irqdomain.h>
#include <asm/msidef.h>
#include <asm/hpet.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/irq_remapping.h>

static struct irq_domain *msi_default_domain;

static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct irq_cfg *cfg = irqd_cfg(data);

	msg->address_hi = MSI_ADDR_BASE_HI;

	if (x2apic_enabled())
		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);

	msg->address_lo =
		MSI_ADDR_BASE_LO |
		((apic->irq_dest_mode == 0) ?
			MSI_ADDR_DEST_MODE_PHYSICAL :
			MSI_ADDR_DEST_MODE_LOGICAL) |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_ADDR_REDIRECTION_CPU :
			MSI_ADDR_REDIRECTION_LOWPRI) |
		MSI_ADDR_DEST_ID(cfg->dest_apicid);

	msg->data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_DATA_DELIVERY_FIXED :
			MSI_DATA_DELIVERY_LOWPRI) |
		MSI_DATA_VECTOR(cfg->vector);
}

/*
 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
 * which implement the MSI or MSI-X Capability Structure.
 */
static struct irq_chip pci_msi_controller = {
	.name			= "PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= msi_domain_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	struct irq_domain *domain;
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	info.msi_dev = dev;

	domain = irq_remapping_get_irq_domain(&info);
	if (domain == NULL)
		domain = msi_default_domain;
	if (domain == NULL)
		return -ENOSYS;

	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
}

void native_teardown_msi_irq(unsigned int irq)
{
	irq_domain_free_irqs(irq, 1);
}

static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
					 msi_alloc_info_t *arg)
{
	return arg->msi_hwirq;
}

static int pci_msi_prepare(struct irq_domain *domain, struct device *dev,
			   int nvec, msi_alloc_info_t *arg)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct msi_desc *desc = first_pci_msi_entry(pdev);

	init_irq_alloc_info(arg, NULL);
	arg->msi_dev = pdev;
	if (desc->msi_attrib.is_msix) {
		arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	} else {
		arg->type = X86_IRQ_ALLOC_TYPE_MSI;
		arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	}

	return 0;
}

static void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
{
	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
}

static struct msi_domain_ops pci_msi_domain_ops = {
	.get_hwirq	= pci_msi_get_hwirq,
	.msi_prepare	= pci_msi_prepare,
	.set_desc	= pci_msi_set_desc,
};

static struct msi_domain_info pci_msi_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

void arch_init_msi_domain(struct irq_domain *parent)
{
	if (disable_apic)
		return;

	msi_default_domain = pci_msi_create_irq_domain(NULL,
					&pci_msi_domain_info, parent);
	if (!msi_default_domain)
		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
}

#ifdef CONFIG_IRQ_REMAP
static struct irq_chip pci_msi_ir_controller = {
	.name			= "IR-PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= msi_domain_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static struct msi_domain_info pci_msi_ir_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_ir_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
{
	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
}
#endif

#ifdef CONFIG_DMAR_TABLE
static int
dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
		      bool force)
{
	struct irq_data *parent = data->parent_data;
	struct msi_msg msg;
	int ret;

	ret = parent->chip->irq_set_affinity(parent, mask, force);
	if (ret >= 0) {
		irq_chip_compose_msi_msg(data, &msg);
		dmar_msi_write(data->irq, &msg);
	}

	return ret;
}

static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
{
	dmar_msi_write(data->irq, msg);
}

static struct irq_chip dmar_msi_controller = {
	.name			= "DMAR-MSI",
	.irq_unmask		= dmar_msi_unmask,
	.irq_mask		= dmar_msi_mask,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= dmar_msi_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.irq_write_msi_msg	= dmar_msi_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static int dmar_domain_alloc(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs, void *arg)
{
	struct irq_alloc_info *info = arg;
	int ret;

	if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_DMAR)
		return -EINVAL;
	if (irq_find_mapping(domain, info->dmar_id)) {
		pr_warn("IRQ for DMAR%d already exists.\n", info->dmar_id);
		return -EEXIST;
	}

	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	if (ret >= 0) {
		irq_domain_set_hwirq_and_chip(domain, virq, info->dmar_id,
					      &dmar_msi_controller, NULL);
		irq_set_handler_data(virq, info->dmar_data);
		__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	}

	return ret;
}

static void dmar_domain_free(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs)
{
	BUG_ON(nr_irqs > 1);
	irq_domain_free_irqs_top(domain, virq, nr_irqs);
}

static void dmar_domain_activate(struct irq_domain *domain,
				 struct irq_data *irq_data)
{
	struct msi_msg msg;

	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	dmar_msi_write(irq_data->irq, &msg);
}

static void dmar_domain_deactivate(struct irq_domain *domain,
				   struct irq_data *irq_data)
{
	struct msi_msg msg;

	memset(&msg, 0, sizeof(msg));
	dmar_msi_write(irq_data->irq, &msg);
}

static struct irq_domain_ops dmar_domain_ops = {
	.alloc = dmar_domain_alloc,
	.free = dmar_domain_free,
	.activate = dmar_domain_activate,
	.deactivate = dmar_domain_deactivate,
};

static struct irq_domain *dmar_get_irq_domain(void)
{
	static struct irq_domain *dmar_domain;
	static DEFINE_MUTEX(dmar_lock);

	mutex_lock(&dmar_lock);
	if (dmar_domain == NULL) {
		dmar_domain = irq_domain_add_tree(NULL, &dmar_domain_ops, NULL);
		if (dmar_domain)
			dmar_domain->parent = x86_vector_domain;
	}
	mutex_unlock(&dmar_lock);

	return dmar_domain;
}

int dmar_alloc_hwirq(int id, int node, void *arg)
{
	struct irq_domain *domain = dmar_get_irq_domain();
	struct irq_alloc_info info;

	if (!domain)
		return -1;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	info.dmar_id = id;
	info.dmar_data = arg;

	return irq_domain_alloc_irqs(domain, 1, node, &info);
}

void dmar_free_hwirq(int irq)
{
	irq_domain_free_irqs(irq, 1);
}
#endif

/*
 * MSI message composition
 */
#ifdef CONFIG_HPET_TIMER
static inline int hpet_dev_id(struct irq_domain *domain)
{
	return (int)(long)domain->host_data;
}

static int hpet_msi_set_affinity(struct irq_data *data,
				 const struct cpumask *mask, bool force)
{
	struct irq_data *parent = data->parent_data;
	struct msi_msg msg;
	int ret;

	ret = parent->chip->irq_set_affinity(parent, mask, force);
	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
		irq_chip_compose_msi_msg(data, &msg);
		hpet_msi_write(data->handler_data, &msg);
	}

	return ret;
}

static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
{
	hpet_msi_write(data->handler_data, msg);
}

static struct irq_chip hpet_msi_controller = {
	.name = "HPET-MSI",
	.irq_unmask = hpet_msi_unmask,
	.irq_mask = hpet_msi_mask,
	.irq_ack = irq_chip_ack_parent,
	.irq_set_affinity = hpet_msi_set_affinity,
	.irq_retrigger = irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg = irq_msi_compose_msg,
	.irq_write_msi_msg = hpet_msi_write_msg,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs, void *arg)
{
	struct irq_alloc_info *info = arg;
	int ret;

	if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_HPET)
		return -EINVAL;
	if (irq_find_mapping(domain, info->hpet_index)) {
		pr_warn("IRQ for HPET%d already exists.\n", info->hpet_index);
		return -EEXIST;
	}

	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	if (ret >= 0) {
		irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
		irq_domain_set_hwirq_and_chip(domain, virq, info->hpet_index,
					      &hpet_msi_controller, NULL);
		irq_set_handler_data(virq, info->hpet_data);
		__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	}

	return ret;
}

static void hpet_domain_free(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs)
{
	BUG_ON(nr_irqs > 1);
	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
	irq_domain_free_irqs_top(domain, virq, nr_irqs);
}

static void hpet_domain_activate(struct irq_domain *domain,
				struct irq_data *irq_data)
{
	struct msi_msg msg;

	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
}

static void hpet_domain_deactivate(struct irq_domain *domain,
				  struct irq_data *irq_data)
{
	struct msi_msg msg;

	memset(&msg, 0, sizeof(msg));
	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
}

static struct irq_domain_ops hpet_domain_ops = {
	.alloc = hpet_domain_alloc,
	.free = hpet_domain_free,
	.activate = hpet_domain_activate,
	.deactivate = hpet_domain_deactivate,
};

struct irq_domain *hpet_create_irq_domain(int hpet_id)
{
	struct irq_domain *parent;
	struct irq_alloc_info info;

	if (x86_vector_domain == NULL)
		return NULL;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_id = hpet_id;
	parent = irq_remapping_get_ir_irq_domain(&info);
	if (parent == NULL)
		parent = x86_vector_domain;
	else
		hpet_msi_controller.name = "IR-HPET-MSI";

	return irq_domain_add_hierarchy(parent, 0, 0, NULL, &hpet_domain_ops,
					(void *)(long)hpet_id);
}

int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
		    int dev_num)
{
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_data = dev;
	info.hpet_id = hpet_dev_id(domain);
	info.hpet_index = dev_num;

	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);
}
#endif
Commit	Line	Data
44380982 JL	1	/*
	2	* Support of MSI, HPET and DMAR interrupts.
	3	*
	4	* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
	5	* Moved from arch/x86/kernel/apic/io_apic.c.
52f518a3 JL	6	* Jiang Liu <jiang.liu@linux.intel.com>
52f518a3 JL	7	* Convert to hierarchical irqdomain
44380982 JL	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#include <linux/mm.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/pci.h>
	16	#include <linux/dmar.h>
	17	#include <linux/hpet.h>
	18	#include <linux/msi.h>
4c8f9960	19	#include <linux/irqdomain.h>
44380982 JL	20	#include <asm/msidef.h>
	21	#include <asm/hpet.h>
	22	#include <asm/hw_irq.h>
	23	#include <asm/apic.h>
	24	#include <asm/irq_remapping.h>
	25
52f518a3 JL	26	static struct irq_domain *msi_default_domain;
52f518a3 JL	27
3cb96f0c JL	28	static void irq_msi_compose_msg(struct irq_data data, struct msi_msg msg)
	29	{
	30	struct irq_cfg *cfg = irqd_cfg(data);
	31
	32	msg->address_hi = MSI_ADDR_BASE_HI;
	33
	34	if (x2apic_enabled())
	35	msg->address_hi \|= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
	36
	37	msg->address_lo =
	38	MSI_ADDR_BASE_LO \|
	39	((apic->irq_dest_mode == 0) ?
	40	MSI_ADDR_DEST_MODE_PHYSICAL :
	41	MSI_ADDR_DEST_MODE_LOGICAL) \|
	42	((apic->irq_delivery_mode != dest_LowestPrio) ?
	43	MSI_ADDR_REDIRECTION_CPU :
	44	MSI_ADDR_REDIRECTION_LOWPRI) \|
	45	MSI_ADDR_DEST_ID(cfg->dest_apicid);
	46
	47	msg->data =
	48	MSI_DATA_TRIGGER_EDGE \|
	49	MSI_DATA_LEVEL_ASSERT \|
	50	((apic->irq_delivery_mode != dest_LowestPrio) ?
	51	MSI_DATA_DELIVERY_FIXED :
	52	MSI_DATA_DELIVERY_LOWPRI) \|
	53	MSI_DATA_VECTOR(cfg->vector);
	54	}
	55
44380982 JL	56	/*
	57	* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
	58	* which implement the MSI or MSI-X Capability Structure.
	59	*/
52f518a3	60	static struct irq_chip pci_msi_controller = {
44380982 JL	61	.name = "PCI-MSI",
	62	.irq_unmask = pci_msi_unmask_irq,
	63	.irq_mask = pci_msi_mask_irq,
52f518a3 JL	64	.irq_ack = irq_chip_ack_parent,
	65	.irq_set_affinity = msi_domain_set_affinity,
	66	.irq_retrigger = irq_chip_retrigger_hierarchy,
52f518a3 JL	67	.irq_compose_msi_msg = irq_msi_compose_msg,
52f518a3 JL	68	.irq_write_msi_msg = pci_msi_domain_write_msg,
44380982 JL	69	.flags = IRQCHIP_SKIP_SET_WAKE,
	70	};
	71
52f518a3	72	int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
44380982	73	{
52f518a3 JL	74	struct irq_domain *domain;
52f518a3 JL	75	struct irq_alloc_info info;
44380982	76
52f518a3 JL	77	init_irq_alloc_info(&info, NULL);
	78	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	79	info.msi_dev = dev;
44380982	80
52f518a3 JL	81	domain = irq_remapping_get_irq_domain(&info);
	82	if (domain == NULL)
	83	domain = msi_default_domain;
	84	if (domain == NULL)
	85	return -ENOSYS;
44380982	86
52f518a3 JL	87	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
52f518a3 JL	88	}
44380982	89
52f518a3 JL	90	void native_teardown_msi_irq(unsigned int irq)
	91	{
	92	irq_domain_free_irqs(irq, 1);
	93	}
44380982	94
52f518a3 JL	95	static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
	96	msi_alloc_info_t *arg)
	97	{
	98	return arg->msi_hwirq;
	99	}
44380982	100
52f518a3 JL	101	static int pci_msi_prepare(struct irq_domain domain, struct device dev,
	102	int nvec, msi_alloc_info_t *arg)
	103	{
	104	struct pci_dev *pdev = to_pci_dev(dev);
	105	struct msi_desc *desc = first_pci_msi_entry(pdev);
	106
	107	init_irq_alloc_info(arg, NULL);
	108	arg->msi_dev = pdev;
	109	if (desc->msi_attrib.is_msix) {
	110	arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	111	} else {
	112	arg->type = X86_IRQ_ALLOC_TYPE_MSI;
	113	arg->flags \|= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	114	}
44380982 JL	115
	116	return 0;
	117	}
	118
52f518a3	119	static void pci_msi_set_desc(msi_alloc_info_t arg, struct msi_desc desc)
44380982	120	{
52f518a3 JL	121	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
52f518a3 JL	122	}
44380982	123
52f518a3 JL	124	static struct msi_domain_ops pci_msi_domain_ops = {
	125	.get_hwirq = pci_msi_get_hwirq,
	126	.msi_prepare = pci_msi_prepare,
	127	.set_desc = pci_msi_set_desc,
	128	};
44380982	129
52f518a3 JL	130	static struct msi_domain_info pci_msi_domain_info = {
52f518a3 JL	131	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
68682a26	132	MSI_FLAG_PCI_MSIX,
52f518a3 JL	133	.ops = &pci_msi_domain_ops,
	134	.chip = &pci_msi_controller,
	135	.handler = handle_edge_irq,
	136	.handler_name = "edge",
	137	};
44380982	138
52f518a3 JL	139	void arch_init_msi_domain(struct irq_domain *parent)
	140	{
	141	if (disable_apic)
	142	return;
44380982	143
52f518a3 JL	144	msi_default_domain = pci_msi_create_irq_domain(NULL,
	145	&pci_msi_domain_info, parent);
	146	if (!msi_default_domain)
	147	pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
44380982 JL	148	}
44380982 JL	149
52f518a3	150	#ifdef CONFIG_IRQ_REMAP
68682a26 JL	151	static struct irq_chip pci_msi_ir_controller = {
	152	.name = "IR-PCI-MSI",
	153	.irq_unmask = pci_msi_unmask_irq,
	154	.irq_mask = pci_msi_mask_irq,
	155	.irq_ack = irq_chip_ack_parent,
	156	.irq_set_affinity = msi_domain_set_affinity,
	157	.irq_retrigger = irq_chip_retrigger_hierarchy,
	158	.irq_write_msi_msg = pci_msi_domain_write_msg,
	159	.flags = IRQCHIP_SKIP_SET_WAKE,
	160	};
	161
	162	static struct msi_domain_info pci_msi_ir_domain_info = {
	163	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	164	MSI_FLAG_MULTI_PCI_MSI \| MSI_FLAG_PCI_MSIX,
	165	.ops = &pci_msi_domain_ops,
	166	.chip = &pci_msi_ir_controller,
	167	.handler = handle_edge_irq,
	168	.handler_name = "edge",
	169	};
	170
52f518a3	171	struct irq_domain arch_create_msi_irq_domain(struct irq_domain parent)
44380982	172	{
68682a26	173	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
44380982	174	}
52f518a3	175	#endif
44380982 JL	176
	177	#ifdef CONFIG_DMAR_TABLE
	178	static int
	179	dmar_msi_set_affinity(struct irq_data data, const struct cpumask mask,
	180	bool force)
	181	{
0921f1da	182	struct irq_data *parent = data->parent_data;
44380982 JL	183	struct msi_msg msg;
	184	int ret;
	185
0921f1da JL	186	ret = parent->chip->irq_set_affinity(parent, mask, force);
0921f1da JL	187	if (ret >= 0) {
90d84fe9	188	irq_chip_compose_msi_msg(data, &msg);
0921f1da JL	189	dmar_msi_write(data->irq, &msg);
0921f1da JL	190	}
44380982	191
0921f1da	192	return ret;
44380982 JL	193	}
44380982 JL	194
62ac1780 JL	195	static void dmar_msi_write_msg(struct irq_data data, struct msi_msg msg)
	196	{
	197	dmar_msi_write(data->irq, msg);
	198	}
	199
0921f1da	200	static struct irq_chip dmar_msi_controller = {
81dabe2e	201	.name = "DMAR-MSI",
44380982 JL	202	.irq_unmask = dmar_msi_unmask,
44380982 JL	203	.irq_mask = dmar_msi_mask,
0921f1da	204	.irq_ack = irq_chip_ack_parent,
44380982	205	.irq_set_affinity = dmar_msi_set_affinity,
0921f1da JL	206	.irq_retrigger = irq_chip_retrigger_hierarchy,
0921f1da JL	207	.irq_compose_msi_msg = irq_msi_compose_msg,
62ac1780	208	.irq_write_msi_msg = dmar_msi_write_msg,
44380982 JL	209	.flags = IRQCHIP_SKIP_SET_WAKE,
	210	};
	211
0921f1da JL	212	static int dmar_domain_alloc(struct irq_domain *domain, unsigned int virq,
	213	unsigned int nr_irqs, void *arg)
	214	{
	215	struct irq_alloc_info *info = arg;
	216	int ret;
	217
	218	if (nr_irqs > 1 \|\| !info \|\| info->type != X86_IRQ_ALLOC_TYPE_DMAR)
	219	return -EINVAL;
	220	if (irq_find_mapping(domain, info->dmar_id)) {
	221	pr_warn("IRQ for DMAR%d already exists.\n", info->dmar_id);
	222	return -EEXIST;
	223	}
	224
	225	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	226	if (ret >= 0) {
	227	irq_domain_set_hwirq_and_chip(domain, virq, info->dmar_id,
	228	&dmar_msi_controller, NULL);
	229	irq_set_handler_data(virq, info->dmar_data);
	230	__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	231	}
	232
	233	return ret;
	234	}
	235
	236	static void dmar_domain_free(struct irq_domain *domain, unsigned int virq,
	237	unsigned int nr_irqs)
	238	{
	239	BUG_ON(nr_irqs > 1);
	240	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	241	}
	242
	243	static void dmar_domain_activate(struct irq_domain *domain,
	244	struct irq_data *irq_data)
44380982	245	{
44380982 JL	246	struct msi_msg msg;
44380982 JL	247
0921f1da JL	248	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	249	dmar_msi_write(irq_data->irq, &msg);
	250	}
	251
	252	static void dmar_domain_deactivate(struct irq_domain *domain,
	253	struct irq_data *irq_data)
	254	{
	255	struct msi_msg msg;
	256
	257	memset(&msg, 0, sizeof(msg));
	258	dmar_msi_write(irq_data->irq, &msg);
	259	}
	260
	261	static struct irq_domain_ops dmar_domain_ops = {
	262	.alloc = dmar_domain_alloc,
	263	.free = dmar_domain_free,
	264	.activate = dmar_domain_activate,
	265	.deactivate = dmar_domain_deactivate,
	266	};
	267
	268	static struct irq_domain *dmar_get_irq_domain(void)
	269	{
	270	static struct irq_domain *dmar_domain;
	271	static DEFINE_MUTEX(dmar_lock);
	272
	273	mutex_lock(&dmar_lock);
	274	if (dmar_domain == NULL) {
	275	dmar_domain = irq_domain_add_tree(NULL, &dmar_domain_ops, NULL);
	276	if (dmar_domain)
	277	dmar_domain->parent = x86_vector_domain;
34742db8	278	}
0921f1da JL	279	mutex_unlock(&dmar_lock);
	280
	281	return dmar_domain;
	282	}
	283
	284	int dmar_alloc_hwirq(int id, int node, void *arg)
	285	{
	286	struct irq_domain *domain = dmar_get_irq_domain();
	287	struct irq_alloc_info info;
	288
	289	if (!domain)
	290	return -1;
	291
	292	init_irq_alloc_info(&info, NULL);
	293	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	294	info.dmar_id = id;
	295	info.dmar_data = arg;
a62b32cd	296
0921f1da	297	return irq_domain_alloc_irqs(domain, 1, node, &info);
a62b32cd JL	298	}
	299
	300	void dmar_free_hwirq(int irq)
	301	{
	302	irq_domain_free_irqs(irq, 1);
	303	}
44380982 JL	304	#endif
	305
	306	/*
	307	* MSI message composition
	308	*/
	309	#ifdef CONFIG_HPET_TIMER
3cb96f0c JL	310	static inline int hpet_dev_id(struct irq_domain *domain)
	311	{
	312	return (int)(long)domain->host_data;
	313	}
44380982 JL	314
	315	static int hpet_msi_set_affinity(struct irq_data *data,
	316	const struct cpumask *mask, bool force)
	317	{
3cb96f0c	318	struct irq_data *parent = data->parent_data;
44380982	319	struct msi_msg msg;
44380982 JL	320	int ret;
44380982 JL	321
3cb96f0c JL	322	ret = parent->chip->irq_set_affinity(parent, mask, force);
3cb96f0c JL	323	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
90d84fe9	324	irq_chip_compose_msi_msg(data, &msg);
3cb96f0c JL	325	hpet_msi_write(data->handler_data, &msg);
3cb96f0c JL	326	}
44380982	327
3cb96f0c	328	return ret;
44380982 JL	329	}
44380982 JL	330
62ac1780 JL	331	static void hpet_msi_write_msg(struct irq_data data, struct msi_msg msg)
	332	{
	333	hpet_msi_write(data->handler_data, msg);
	334	}
	335
3cb96f0c	336	static struct irq_chip hpet_msi_controller = {
81dabe2e	337	.name = "HPET-MSI",
44380982 JL	338	.irq_unmask = hpet_msi_unmask,
44380982 JL	339	.irq_mask = hpet_msi_mask,
3cb96f0c	340	.irq_ack = irq_chip_ack_parent,
44380982	341	.irq_set_affinity = hpet_msi_set_affinity,
3cb96f0c	342	.irq_retrigger = irq_chip_retrigger_hierarchy,
3cb96f0c	343	.irq_compose_msi_msg = irq_msi_compose_msg,
62ac1780	344	.irq_write_msi_msg = hpet_msi_write_msg,
44380982 JL	345	.flags = IRQCHIP_SKIP_SET_WAKE,
	346	};
	347
3cb96f0c JL	348	static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
	349	unsigned int nr_irqs, void *arg)
	350	{
	351	struct irq_alloc_info *info = arg;
	352	int ret;
	353
	354	if (nr_irqs > 1 \|\| !info \|\| info->type != X86_IRQ_ALLOC_TYPE_HPET)
	355	return -EINVAL;
	356	if (irq_find_mapping(domain, info->hpet_index)) {
	357	pr_warn("IRQ for HPET%d already exists.\n", info->hpet_index);
	358	return -EEXIST;
	359	}
	360
	361	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	362	if (ret >= 0) {
	363	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	364	irq_domain_set_hwirq_and_chip(domain, virq, info->hpet_index,
	365	&hpet_msi_controller, NULL);
	366	irq_set_handler_data(virq, info->hpet_data);
	367	__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	368	}
	369
	370	return ret;
	371	}
	372
	373	static void hpet_domain_free(struct irq_domain *domain, unsigned int virq,
	374	unsigned int nr_irqs)
	375	{
	376	BUG_ON(nr_irqs > 1);
	377	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
	378	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	379	}
	380
	381	static void hpet_domain_activate(struct irq_domain *domain,
	382	struct irq_data *irq_data)
	383	{
	384	struct msi_msg msg;
	385
	386	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	387	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
	388	}
	389
	390	static void hpet_domain_deactivate(struct irq_domain *domain,
	391	struct irq_data *irq_data)
	392	{
	393	struct msi_msg msg;
	394
	395	memset(&msg, 0, sizeof(msg));
	396	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
	397	}
	398
	399	static struct irq_domain_ops hpet_domain_ops = {
	400	.alloc = hpet_domain_alloc,
	401	.free = hpet_domain_free,
	402	.activate = hpet_domain_activate,
	403	.deactivate = hpet_domain_deactivate,
	404	};
	405
	406	struct irq_domain *hpet_create_irq_domain(int hpet_id)
	407	{
	408	struct irq_domain *parent;
	409	struct irq_alloc_info info;
	410
	411	if (x86_vector_domain == NULL)
412	return NULL;
413
414	init_irq_alloc_info(&info, NULL);
415	info.type = X86_IRQ_ALLOC_TYPE_HPET;
416	info.hpet_id = hpet_id;
417	parent = irq_remapping_get_ir_irq_domain(&info);
418	if (parent == NULL)
419	parent = x86_vector_domain;
68682a26 JL	420	else
68682a26 JL	421	hpet_msi_controller.name = "IR-HPET-MSI";
3cb96f0c JL	422
	423	return irq_domain_add_hierarchy(parent, 0, 0, NULL, &hpet_domain_ops,
	424	(void *)(long)hpet_id);
	425	}
	426
	427	int hpet_assign_irq(struct irq_domain domain, struct hpet_dev dev,
	428	int dev_num)
	429	{
	430	struct irq_alloc_info info;
	431
	432	init_irq_alloc_info(&info, NULL);
	433	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	434	info.hpet_data = dev;
	435	info.hpet_id = hpet_dev_id(domain);
	436	info.hpet_index = dev_num;
	437
	438	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);
	439	}
44380982	440	#endif