[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / apic / msi.c

/*
 * Support of MSI, HPET and DMAR interrupts.
 *
 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *	Moved from arch/x86/kernel/apic/io_apic.c.
 * Jiang Liu <jiang.liu@linux.intel.com>
 *	Convert to hierarchical irqdomain
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/hpet.h>
#include <linux/msi.h>
#include <linux/irqdomain.h>
#include <asm/msidef.h>
#include <asm/hpet.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/irq_remapping.h>

static struct irq_domain *msi_default_domain;

static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct irq_cfg *cfg = irqd_cfg(data);

	msg->address_hi = MSI_ADDR_BASE_HI;

	if (x2apic_enabled())
		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);

	msg->address_lo =
		MSI_ADDR_BASE_LO |
		((apic->irq_dest_mode == 0) ?
			MSI_ADDR_DEST_MODE_PHYSICAL :
			MSI_ADDR_DEST_MODE_LOGICAL) |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_ADDR_REDIRECTION_CPU :
			MSI_ADDR_REDIRECTION_LOWPRI) |
		MSI_ADDR_DEST_ID(cfg->dest_apicid);

	msg->data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_DATA_DELIVERY_FIXED :
			MSI_DATA_DELIVERY_LOWPRI) |
		MSI_DATA_VECTOR(cfg->vector);
}

static void msi_update_msg(struct msi_msg *msg, struct irq_data *irq_data)
{
	struct irq_cfg *cfg = irqd_cfg(irq_data);

	msg->data &= ~MSI_DATA_VECTOR_MASK;
	msg->data |= MSI_DATA_VECTOR(cfg->vector);
	msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	msg->address_lo |= MSI_ADDR_DEST_ID(cfg->dest_apicid);
	if (x2apic_enabled())
		msg->address_hi = MSI_ADDR_BASE_HI |
				  MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
}

/*
 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
 * which implement the MSI or MSI-X Capability Structure.
 */
static struct irq_chip pci_msi_controller = {
	.name			= "PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= msi_domain_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	struct irq_domain *domain;
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	info.msi_dev = dev;

	domain = irq_remapping_get_irq_domain(&info);
	if (domain == NULL)
		domain = msi_default_domain;
	if (domain == NULL)
		return -ENOSYS;

	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
}

void native_teardown_msi_irq(unsigned int irq)
{
	irq_domain_free_irqs(irq, 1);
}

static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
					 msi_alloc_info_t *arg)
{
	return arg->msi_hwirq;
}

static int pci_msi_prepare(struct irq_domain *domain, struct device *dev,
			   int nvec, msi_alloc_info_t *arg)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct msi_desc *desc = first_pci_msi_entry(pdev);

	init_irq_alloc_info(arg, NULL);
	arg->msi_dev = pdev;
	if (desc->msi_attrib.is_msix) {
		arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	} else {
		arg->type = X86_IRQ_ALLOC_TYPE_MSI;
		arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	}

	return 0;
}

static void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
{
	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
}

static struct msi_domain_ops pci_msi_domain_ops = {
	.get_hwirq	= pci_msi_get_hwirq,
	.msi_prepare	= pci_msi_prepare,
	.set_desc	= pci_msi_set_desc,
};

static struct msi_domain_info pci_msi_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

void arch_init_msi_domain(struct irq_domain *parent)
{
	if (disable_apic)
		return;

	msi_default_domain = pci_msi_create_irq_domain(NULL,
					&pci_msi_domain_info, parent);
	if (!msi_default_domain)
		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
}

#ifdef CONFIG_IRQ_REMAP
static struct irq_chip pci_msi_ir_controller = {
	.name			= "IR-PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= msi_domain_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_write_msi_msg	= pci_msi_domain_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static struct msi_domain_info pci_msi_ir_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_ir_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
{
	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
}
#endif

#ifdef CONFIG_DMAR_TABLE
static int
dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
		      bool force)
{
	struct irq_data *parent = data->parent_data;
	struct msi_msg msg;
	int ret;

	ret = parent->chip->irq_set_affinity(parent, mask, force);
	if (ret >= 0) {
		dmar_msi_read(data->irq, &msg);
		msi_update_msg(&msg, data);
		dmar_msi_write(data->irq, &msg);
	}

	return ret;
}

static struct irq_chip dmar_msi_controller = {
	.name			= "DMAR-MSI",
	.irq_unmask		= dmar_msi_unmask,
	.irq_mask		= dmar_msi_mask,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= dmar_msi_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static int dmar_domain_alloc(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs, void *arg)
{
	struct irq_alloc_info *info = arg;
	int ret;

	if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_DMAR)
		return -EINVAL;
	if (irq_find_mapping(domain, info->dmar_id)) {
		pr_warn("IRQ for DMAR%d already exists.\n", info->dmar_id);
		return -EEXIST;
	}

	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	if (ret >= 0) {
		irq_domain_set_hwirq_and_chip(domain, virq, info->dmar_id,
					      &dmar_msi_controller, NULL);
		irq_set_handler_data(virq, info->dmar_data);
		__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	}

	return ret;
}

static void dmar_domain_free(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs)
{
	BUG_ON(nr_irqs > 1);
	irq_domain_free_irqs_top(domain, virq, nr_irqs);
}

static void dmar_domain_activate(struct irq_domain *domain,
				 struct irq_data *irq_data)
{
	struct msi_msg msg;

	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	dmar_msi_write(irq_data->irq, &msg);
}

static void dmar_domain_deactivate(struct irq_domain *domain,
				   struct irq_data *irq_data)
{
	struct msi_msg msg;

	memset(&msg, 0, sizeof(msg));
	dmar_msi_write(irq_data->irq, &msg);
}

static struct irq_domain_ops dmar_domain_ops = {
	.alloc = dmar_domain_alloc,
	.free = dmar_domain_free,
	.activate = dmar_domain_activate,
	.deactivate = dmar_domain_deactivate,
};

static struct irq_domain *dmar_get_irq_domain(void)
{
	static struct irq_domain *dmar_domain;
	static DEFINE_MUTEX(dmar_lock);

	mutex_lock(&dmar_lock);
	if (dmar_domain == NULL) {
		dmar_domain = irq_domain_add_tree(NULL, &dmar_domain_ops, NULL);
		if (dmar_domain)
			dmar_domain->parent = x86_vector_domain;
	}
	mutex_unlock(&dmar_lock);

	return dmar_domain;
}

int dmar_alloc_hwirq(int id, int node, void *arg)
{
	struct irq_domain *domain = dmar_get_irq_domain();
	struct irq_alloc_info info;

	if (!domain)
		return -1;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	info.dmar_id = id;
	info.dmar_data = arg;

	return irq_domain_alloc_irqs(domain, 1, node, &info);
}

void dmar_free_hwirq(int irq)
{
	irq_domain_free_irqs(irq, 1);
}
#endif

/*
 * MSI message composition
 */
#ifdef CONFIG_HPET_TIMER
static inline int hpet_dev_id(struct irq_domain *domain)
{
	return (int)(long)domain->host_data;
}

static int hpet_msi_set_affinity(struct irq_data *data,
				 const struct cpumask *mask, bool force)
{
	struct irq_data *parent = data->parent_data;
	struct msi_msg msg;
	int ret;

	ret = parent->chip->irq_set_affinity(parent, mask, force);
	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
		hpet_msi_read(data->handler_data, &msg);
		msi_update_msg(&msg, data);
		hpet_msi_write(data->handler_data, &msg);
	}

	return ret;
}

static struct irq_chip hpet_msi_controller = {
	.name = "HPET-MSI",
	.irq_unmask = hpet_msi_unmask,
	.irq_mask = hpet_msi_mask,
	.irq_ack = irq_chip_ack_parent,
	.irq_set_affinity = hpet_msi_set_affinity,
	.irq_retrigger = irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg = irq_msi_compose_msg,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs, void *arg)
{
	struct irq_alloc_info *info = arg;
	int ret;

	if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_HPET)
		return -EINVAL;
	if (irq_find_mapping(domain, info->hpet_index)) {
		pr_warn("IRQ for HPET%d already exists.\n", info->hpet_index);
		return -EEXIST;
	}

	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	if (ret >= 0) {
		irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
		irq_domain_set_hwirq_and_chip(domain, virq, info->hpet_index,
					      &hpet_msi_controller, NULL);
		irq_set_handler_data(virq, info->hpet_data);
		__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	}

	return ret;
}

static void hpet_domain_free(struct irq_domain *domain, unsigned int virq,
			     unsigned int nr_irqs)
{
	BUG_ON(nr_irqs > 1);
	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
	irq_domain_free_irqs_top(domain, virq, nr_irqs);
}

static void hpet_domain_activate(struct irq_domain *domain,
				struct irq_data *irq_data)
{
	struct msi_msg msg;

	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
}

static void hpet_domain_deactivate(struct irq_domain *domain,
				  struct irq_data *irq_data)
{
	struct msi_msg msg;

	memset(&msg, 0, sizeof(msg));
	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
}

static struct irq_domain_ops hpet_domain_ops = {
	.alloc = hpet_domain_alloc,
	.free = hpet_domain_free,
	.activate = hpet_domain_activate,
	.deactivate = hpet_domain_deactivate,
};

struct irq_domain *hpet_create_irq_domain(int hpet_id)
{
	struct irq_domain *parent;
	struct irq_alloc_info info;

	if (x86_vector_domain == NULL)
		return NULL;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_id = hpet_id;
	parent = irq_remapping_get_ir_irq_domain(&info);
	if (parent == NULL)
		parent = x86_vector_domain;
	else
		hpet_msi_controller.name = "IR-HPET-MSI";

	return irq_domain_add_hierarchy(parent, 0, 0, NULL, &hpet_domain_ops,
					(void *)(long)hpet_id);
}

int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
		    int dev_num)
{
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_data = dev;
	info.hpet_id = hpet_dev_id(domain);
	info.hpet_index = dev_num;

	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);
}
#endif
Commit	Line	Data
44380982 JL	1	/*
	2	* Support of MSI, HPET and DMAR interrupts.
	3	*
	4	* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
	5	* Moved from arch/x86/kernel/apic/io_apic.c.
52f518a3 JL	6	* Jiang Liu <jiang.liu@linux.intel.com>
52f518a3 JL	7	* Convert to hierarchical irqdomain
44380982 JL	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#include <linux/mm.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/pci.h>
	16	#include <linux/dmar.h>
	17	#include <linux/hpet.h>
	18	#include <linux/msi.h>
4c8f9960	19	#include <linux/irqdomain.h>
44380982 JL	20	#include <asm/msidef.h>
	21	#include <asm/hpet.h>
	22	#include <asm/hw_irq.h>
	23	#include <asm/apic.h>
	24	#include <asm/irq_remapping.h>
	25
52f518a3 JL	26	static struct irq_domain *msi_default_domain;
52f518a3 JL	27
3cb96f0c JL	28	static void irq_msi_compose_msg(struct irq_data data, struct msi_msg msg)
	29	{
	30	struct irq_cfg *cfg = irqd_cfg(data);
	31
	32	msg->address_hi = MSI_ADDR_BASE_HI;
	33
	34	if (x2apic_enabled())
	35	msg->address_hi \|= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
	36
	37	msg->address_lo =
	38	MSI_ADDR_BASE_LO \|
	39	((apic->irq_dest_mode == 0) ?
	40	MSI_ADDR_DEST_MODE_PHYSICAL :
	41	MSI_ADDR_DEST_MODE_LOGICAL) \|
	42	((apic->irq_delivery_mode != dest_LowestPrio) ?
	43	MSI_ADDR_REDIRECTION_CPU :
	44	MSI_ADDR_REDIRECTION_LOWPRI) \|
	45	MSI_ADDR_DEST_ID(cfg->dest_apicid);
	46
	47	msg->data =
	48	MSI_DATA_TRIGGER_EDGE \|
	49	MSI_DATA_LEVEL_ASSERT \|
	50	((apic->irq_delivery_mode != dest_LowestPrio) ?
	51	MSI_DATA_DELIVERY_FIXED :
	52	MSI_DATA_DELIVERY_LOWPRI) \|
	53	MSI_DATA_VECTOR(cfg->vector);
	54	}
	55
	56	static void msi_update_msg(struct msi_msg msg, struct irq_data irq_data)
	57	{
	58	struct irq_cfg *cfg = irqd_cfg(irq_data);
	59
	60	msg->data &= ~MSI_DATA_VECTOR_MASK;
	61	msg->data \|= MSI_DATA_VECTOR(cfg->vector);
	62	msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
	63	msg->address_lo \|= MSI_ADDR_DEST_ID(cfg->dest_apicid);
0921f1da JL	64	if (x2apic_enabled())
	65	msg->address_hi = MSI_ADDR_BASE_HI \|
	66	MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
3cb96f0c JL	67	}
3cb96f0c JL	68
44380982 JL	69	/*
	70	* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
	71	* which implement the MSI or MSI-X Capability Structure.
	72	*/
52f518a3	73	static struct irq_chip pci_msi_controller = {
44380982 JL	74	.name = "PCI-MSI",
	75	.irq_unmask = pci_msi_unmask_irq,
	76	.irq_mask = pci_msi_mask_irq,
52f518a3 JL	77	.irq_ack = irq_chip_ack_parent,
	78	.irq_set_affinity = msi_domain_set_affinity,
	79	.irq_retrigger = irq_chip_retrigger_hierarchy,
52f518a3 JL	80	.irq_compose_msi_msg = irq_msi_compose_msg,
52f518a3 JL	81	.irq_write_msi_msg = pci_msi_domain_write_msg,
44380982 JL	82	.flags = IRQCHIP_SKIP_SET_WAKE,
	83	};
	84
52f518a3	85	int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
44380982	86	{
52f518a3 JL	87	struct irq_domain *domain;
52f518a3 JL	88	struct irq_alloc_info info;
44380982	89
52f518a3 JL	90	init_irq_alloc_info(&info, NULL);
	91	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	92	info.msi_dev = dev;
44380982	93
52f518a3 JL	94	domain = irq_remapping_get_irq_domain(&info);
	95	if (domain == NULL)
	96	domain = msi_default_domain;
	97	if (domain == NULL)
	98	return -ENOSYS;
44380982	99
52f518a3 JL	100	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
52f518a3 JL	101	}
44380982	102
52f518a3 JL	103	void native_teardown_msi_irq(unsigned int irq)
	104	{
	105	irq_domain_free_irqs(irq, 1);
	106	}
44380982	107
52f518a3 JL	108	static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
	109	msi_alloc_info_t *arg)
	110	{
	111	return arg->msi_hwirq;
	112	}
44380982	113
52f518a3 JL	114	static int pci_msi_prepare(struct irq_domain domain, struct device dev,
	115	int nvec, msi_alloc_info_t *arg)
	116	{
	117	struct pci_dev *pdev = to_pci_dev(dev);
	118	struct msi_desc *desc = first_pci_msi_entry(pdev);
	119
	120	init_irq_alloc_info(arg, NULL);
	121	arg->msi_dev = pdev;
	122	if (desc->msi_attrib.is_msix) {
	123	arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	124	} else {
	125	arg->type = X86_IRQ_ALLOC_TYPE_MSI;
	126	arg->flags \|= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	127	}
44380982 JL	128
	129	return 0;
	130	}
	131
52f518a3	132	static void pci_msi_set_desc(msi_alloc_info_t arg, struct msi_desc desc)
44380982	133	{
52f518a3 JL	134	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
52f518a3 JL	135	}
44380982	136
52f518a3 JL	137	static struct msi_domain_ops pci_msi_domain_ops = {
	138	.get_hwirq = pci_msi_get_hwirq,
	139	.msi_prepare = pci_msi_prepare,
	140	.set_desc = pci_msi_set_desc,
	141	};
44380982	142
52f518a3 JL	143	static struct msi_domain_info pci_msi_domain_info = {
52f518a3 JL	144	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
68682a26	145	MSI_FLAG_PCI_MSIX,
52f518a3 JL	146	.ops = &pci_msi_domain_ops,
	147	.chip = &pci_msi_controller,
	148	.handler = handle_edge_irq,
	149	.handler_name = "edge",
	150	};
44380982	151
52f518a3 JL	152	void arch_init_msi_domain(struct irq_domain *parent)
	153	{
	154	if (disable_apic)
	155	return;
44380982	156
52f518a3 JL	157	msi_default_domain = pci_msi_create_irq_domain(NULL,
	158	&pci_msi_domain_info, parent);
	159	if (!msi_default_domain)
	160	pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
44380982 JL	161	}
44380982 JL	162
52f518a3	163	#ifdef CONFIG_IRQ_REMAP
68682a26 JL	164	static struct irq_chip pci_msi_ir_controller = {
	165	.name = "IR-PCI-MSI",
	166	.irq_unmask = pci_msi_unmask_irq,
	167	.irq_mask = pci_msi_mask_irq,
	168	.irq_ack = irq_chip_ack_parent,
	169	.irq_set_affinity = msi_domain_set_affinity,
	170	.irq_retrigger = irq_chip_retrigger_hierarchy,
	171	.irq_write_msi_msg = pci_msi_domain_write_msg,
	172	.flags = IRQCHIP_SKIP_SET_WAKE,
	173	};
	174
	175	static struct msi_domain_info pci_msi_ir_domain_info = {
	176	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	177	MSI_FLAG_MULTI_PCI_MSI \| MSI_FLAG_PCI_MSIX,
	178	.ops = &pci_msi_domain_ops,
	179	.chip = &pci_msi_ir_controller,
	180	.handler = handle_edge_irq,
	181	.handler_name = "edge",
	182	};
	183
52f518a3	184	struct irq_domain arch_create_msi_irq_domain(struct irq_domain parent)
44380982	185	{
68682a26	186	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
44380982	187	}
52f518a3	188	#endif
44380982 JL	189
	190	#ifdef CONFIG_DMAR_TABLE
	191	static int
	192	dmar_msi_set_affinity(struct irq_data data, const struct cpumask mask,
	193	bool force)
	194	{
0921f1da	195	struct irq_data *parent = data->parent_data;
44380982 JL	196	struct msi_msg msg;
	197	int ret;
	198
0921f1da JL	199	ret = parent->chip->irq_set_affinity(parent, mask, force);
	200	if (ret >= 0) {
	201	dmar_msi_read(data->irq, &msg);
	202	msi_update_msg(&msg, data);
	203	dmar_msi_write(data->irq, &msg);
	204	}
44380982	205
0921f1da	206	return ret;
44380982 JL	207	}
44380982 JL	208
0921f1da	209	static struct irq_chip dmar_msi_controller = {
81dabe2e	210	.name = "DMAR-MSI",
44380982 JL	211	.irq_unmask = dmar_msi_unmask,
44380982 JL	212	.irq_mask = dmar_msi_mask,
0921f1da	213	.irq_ack = irq_chip_ack_parent,
44380982	214	.irq_set_affinity = dmar_msi_set_affinity,
0921f1da JL	215	.irq_retrigger = irq_chip_retrigger_hierarchy,
0921f1da JL	216	.irq_compose_msi_msg = irq_msi_compose_msg,
44380982 JL	217	.flags = IRQCHIP_SKIP_SET_WAKE,
	218	};
	219
0921f1da JL	220	static int dmar_domain_alloc(struct irq_domain *domain, unsigned int virq,
	221	unsigned int nr_irqs, void *arg)
	222	{
	223	struct irq_alloc_info *info = arg;
	224	int ret;
	225
	226	if (nr_irqs > 1 \|\| !info \|\| info->type != X86_IRQ_ALLOC_TYPE_DMAR)
	227	return -EINVAL;
	228	if (irq_find_mapping(domain, info->dmar_id)) {
	229	pr_warn("IRQ for DMAR%d already exists.\n", info->dmar_id);
	230	return -EEXIST;
	231	}
	232
	233	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	234	if (ret >= 0) {
	235	irq_domain_set_hwirq_and_chip(domain, virq, info->dmar_id,
	236	&dmar_msi_controller, NULL);
	237	irq_set_handler_data(virq, info->dmar_data);
	238	__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	239	}
	240
	241	return ret;
	242	}
	243
	244	static void dmar_domain_free(struct irq_domain *domain, unsigned int virq,
	245	unsigned int nr_irqs)
	246	{
	247	BUG_ON(nr_irqs > 1);
	248	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	249	}
	250
	251	static void dmar_domain_activate(struct irq_domain *domain,
	252	struct irq_data *irq_data)
44380982	253	{
44380982 JL	254	struct msi_msg msg;
44380982 JL	255
0921f1da JL	256	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	257	dmar_msi_write(irq_data->irq, &msg);
	258	}
	259
	260	static void dmar_domain_deactivate(struct irq_domain *domain,
	261	struct irq_data *irq_data)
	262	{
	263	struct msi_msg msg;
	264
	265	memset(&msg, 0, sizeof(msg));
	266	dmar_msi_write(irq_data->irq, &msg);
	267	}
	268
	269	static struct irq_domain_ops dmar_domain_ops = {
	270	.alloc = dmar_domain_alloc,
	271	.free = dmar_domain_free,
	272	.activate = dmar_domain_activate,
	273	.deactivate = dmar_domain_deactivate,
	274	};
	275
	276	static struct irq_domain *dmar_get_irq_domain(void)
	277	{
	278	static struct irq_domain *dmar_domain;
	279	static DEFINE_MUTEX(dmar_lock);
	280
	281	mutex_lock(&dmar_lock);
	282	if (dmar_domain == NULL) {
	283	dmar_domain = irq_domain_add_tree(NULL, &dmar_domain_ops, NULL);
	284	if (dmar_domain)
	285	dmar_domain->parent = x86_vector_domain;
34742db8	286	}
0921f1da JL	287	mutex_unlock(&dmar_lock);
	288
	289	return dmar_domain;
	290	}
	291
	292	int dmar_alloc_hwirq(int id, int node, void *arg)
	293	{
	294	struct irq_domain *domain = dmar_get_irq_domain();
	295	struct irq_alloc_info info;
	296
	297	if (!domain)
	298	return -1;
	299
	300	init_irq_alloc_info(&info, NULL);
	301	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	302	info.dmar_id = id;
	303	info.dmar_data = arg;
a62b32cd	304
0921f1da	305	return irq_domain_alloc_irqs(domain, 1, node, &info);
a62b32cd JL	306	}
	307
	308	void dmar_free_hwirq(int irq)
	309	{
	310	irq_domain_free_irqs(irq, 1);
	311	}
44380982 JL	312	#endif
	313
	314	/*
	315	* MSI message composition
	316	*/
	317	#ifdef CONFIG_HPET_TIMER
3cb96f0c JL	318	static inline int hpet_dev_id(struct irq_domain *domain)
	319	{
	320	return (int)(long)domain->host_data;
	321	}
44380982 JL	322
	323	static int hpet_msi_set_affinity(struct irq_data *data,
	324	const struct cpumask *mask, bool force)
	325	{
3cb96f0c	326	struct irq_data *parent = data->parent_data;
44380982	327	struct msi_msg msg;
44380982 JL	328	int ret;
44380982 JL	329
3cb96f0c JL	330	ret = parent->chip->irq_set_affinity(parent, mask, force);
	331	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
	332	hpet_msi_read(data->handler_data, &msg);
	333	msi_update_msg(&msg, data);
	334	hpet_msi_write(data->handler_data, &msg);
	335	}
44380982	336
3cb96f0c	337	return ret;
44380982 JL	338	}
44380982 JL	339
3cb96f0c	340	static struct irq_chip hpet_msi_controller = {
81dabe2e	341	.name = "HPET-MSI",
44380982 JL	342	.irq_unmask = hpet_msi_unmask,
44380982 JL	343	.irq_mask = hpet_msi_mask,
3cb96f0c	344	.irq_ack = irq_chip_ack_parent,
44380982	345	.irq_set_affinity = hpet_msi_set_affinity,
3cb96f0c	346	.irq_retrigger = irq_chip_retrigger_hierarchy,
3cb96f0c	347	.irq_compose_msi_msg = irq_msi_compose_msg,
44380982 JL	348	.flags = IRQCHIP_SKIP_SET_WAKE,
	349	};
	350
3cb96f0c JL	351	static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
	352	unsigned int nr_irqs, void *arg)
	353	{
	354	struct irq_alloc_info *info = arg;
	355	int ret;
	356
	357	if (nr_irqs > 1 \|\| !info \|\| info->type != X86_IRQ_ALLOC_TYPE_HPET)
	358	return -EINVAL;
	359	if (irq_find_mapping(domain, info->hpet_index)) {
	360	pr_warn("IRQ for HPET%d already exists.\n", info->hpet_index);
	361	return -EEXIST;
	362	}
	363
	364	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
	365	if (ret >= 0) {
	366	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	367	irq_domain_set_hwirq_and_chip(domain, virq, info->hpet_index,
	368	&hpet_msi_controller, NULL);
	369	irq_set_handler_data(virq, info->hpet_data);
	370	__irq_set_handler(virq, handle_edge_irq, 0, "edge");
	371	}
	372
	373	return ret;
	374	}
	375
	376	static void hpet_domain_free(struct irq_domain *domain, unsigned int virq,
	377	unsigned int nr_irqs)
	378	{
	379	BUG_ON(nr_irqs > 1);
	380	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
	381	irq_domain_free_irqs_top(domain, virq, nr_irqs);
	382	}
	383
	384	static void hpet_domain_activate(struct irq_domain *domain,
	385	struct irq_data *irq_data)
	386	{
	387	struct msi_msg msg;
	388
	389	BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
	390	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
	391	}
	392
	393	static void hpet_domain_deactivate(struct irq_domain *domain,
	394	struct irq_data *irq_data)
	395	{
	396	struct msi_msg msg;
	397
	398	memset(&msg, 0, sizeof(msg));
	399	hpet_msi_write(irq_get_handler_data(irq_data->irq), &msg);
	400	}
	401
	402	static struct irq_domain_ops hpet_domain_ops = {
	403	.alloc = hpet_domain_alloc,
	404	.free = hpet_domain_free,
	405	.activate = hpet_domain_activate,
	406	.deactivate = hpet_domain_deactivate,
	407	};
	408
	409	struct irq_domain *hpet_create_irq_domain(int hpet_id)
	410	{
	411	struct irq_domain *parent;
	412	struct irq_alloc_info info;
	413
	414	if (x86_vector_domain == NULL)
415	return NULL;
416
417	init_irq_alloc_info(&info, NULL);
418	info.type = X86_IRQ_ALLOC_TYPE_HPET;
419	info.hpet_id = hpet_id;
420	parent = irq_remapping_get_ir_irq_domain(&info);
421	if (parent == NULL)
422	parent = x86_vector_domain;
68682a26 JL	423	else
68682a26 JL	424	hpet_msi_controller.name = "IR-HPET-MSI";
3cb96f0c JL	425
	426	return irq_domain_add_hierarchy(parent, 0, 0, NULL, &hpet_domain_ops,
	427	(void *)(long)hpet_id);
	428	}
	429
	430	int hpet_assign_irq(struct irq_domain domain, struct hpet_dev dev,
	431	int dev_num)
	432	{
	433	struct irq_alloc_info info;
	434
	435	init_irq_alloc_info(&info, NULL);
	436	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	437	info.hpet_data = dev;
	438	info.hpet_id = hpet_dev_id(domain);
	439	info.hpet_index = dev_num;
	440
	441	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);
	442	}
44380982	443	#endif