[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / apic / msi.c

/*
 * Support of MSI, HPET and DMAR interrupts.
 *
 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *	Moved from arch/x86/kernel/apic/io_apic.c.
 * Jiang Liu <jiang.liu@linux.intel.com>
 *	Convert to hierarchical irqdomain
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/hpet.h>
#include <linux/msi.h>
#include <asm/irqdomain.h>
#include <asm/msidef.h>
#include <asm/hpet.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/irq_remapping.h>

static struct irq_domain *msi_default_domain;

static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct irq_cfg *cfg = irqd_cfg(data);

	msg->address_hi = MSI_ADDR_BASE_HI;

	if (x2apic_enabled())
		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);

	msg->address_lo =
		MSI_ADDR_BASE_LO |
		((apic->irq_dest_mode == 0) ?
			MSI_ADDR_DEST_MODE_PHYSICAL :
			MSI_ADDR_DEST_MODE_LOGICAL) |
		MSI_ADDR_REDIRECTION_CPU |
		MSI_ADDR_DEST_ID(cfg->dest_apicid);

	msg->data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		MSI_DATA_DELIVERY_FIXED |
		MSI_DATA_VECTOR(cfg->vector);
}

/*
 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
 * which implement the MSI or MSI-X Capability Structure.
 */
static struct irq_chip pci_msi_controller = {
	.name			= "PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	struct irq_domain *domain;
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	info.msi_dev = dev;

	domain = irq_remapping_get_irq_domain(&info);
	if (domain == NULL)
		domain = msi_default_domain;
	if (domain == NULL)
		return -ENOSYS;

	return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
}

void native_teardown_msi_irq(unsigned int irq)
{
	irq_domain_free_irqs(irq, 1);
}

static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
					 msi_alloc_info_t *arg)
{
	return arg->msi_hwirq;
}

int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
		    msi_alloc_info_t *arg)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct msi_desc *desc = first_pci_msi_entry(pdev);

	init_irq_alloc_info(arg, NULL);
	arg->msi_dev = pdev;
	if (desc->msi_attrib.is_msix) {
		arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	} else {
		arg->type = X86_IRQ_ALLOC_TYPE_MSI;
		arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(pci_msi_prepare);

void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
{
	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
}
EXPORT_SYMBOL_GPL(pci_msi_set_desc);

static struct msi_domain_ops pci_msi_domain_ops = {
	.get_hwirq	= pci_msi_get_hwirq,
	.msi_prepare	= pci_msi_prepare,
	.set_desc	= pci_msi_set_desc,
};

static struct msi_domain_info pci_msi_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

void __init arch_init_msi_domain(struct irq_domain *parent)
{
	struct fwnode_handle *fn;

	if (disable_apic)
		return;

	fn = irq_domain_alloc_named_fwnode("PCI-MSI");
	if (fn) {
		msi_default_domain =
			pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
						  parent);
		irq_domain_free_fwnode(fn);
	}
	if (!msi_default_domain)
		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
}

#ifdef CONFIG_IRQ_REMAP
static struct irq_chip pci_msi_ir_controller = {
	.name			= "IR-PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_vcpu_affinity	= irq_chip_set_vcpu_affinity_parent,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static struct msi_domain_info pci_msi_ir_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_ir_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
						    const char *name, int id)
{
	struct fwnode_handle *fn;
	struct irq_domain *d;

	fn = irq_domain_alloc_named_id_fwnode(name, id);
	if (!fn)
		return NULL;
	d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
	irq_domain_free_fwnode(fn);
	return d;
}
#endif

#ifdef CONFIG_DMAR_TABLE
static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
{
	dmar_msi_write(data->irq, msg);
}

static struct irq_chip dmar_msi_controller = {
	.name			= "DMAR-MSI",
	.irq_unmask		= dmar_msi_unmask,
	.irq_mask		= dmar_msi_mask,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= msi_domain_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.irq_write_msi_msg	= dmar_msi_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
					  msi_alloc_info_t *arg)
{
	return arg->dmar_id;
}

static int dmar_msi_init(struct irq_domain *domain,
			 struct msi_domain_info *info, unsigned int virq,
			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
{
	irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
			    handle_edge_irq, arg->dmar_data, "edge");

	return 0;
}

static struct msi_domain_ops dmar_msi_domain_ops = {
	.get_hwirq	= dmar_msi_get_hwirq,
	.msi_init	= dmar_msi_init,
};

static struct msi_domain_info dmar_msi_domain_info = {
	.ops		= &dmar_msi_domain_ops,
	.chip		= &dmar_msi_controller,
};

static struct irq_domain *dmar_get_irq_domain(void)
{
	static struct irq_domain *dmar_domain;
	static DEFINE_MUTEX(dmar_lock);
	struct fwnode_handle *fn;

	mutex_lock(&dmar_lock);
	if (dmar_domain)
		goto out;

	fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
	if (fn) {
		dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
						    x86_vector_domain);
		irq_domain_free_fwnode(fn);
	}
out:
	mutex_unlock(&dmar_lock);
	return dmar_domain;
}

int dmar_alloc_hwirq(int id, int node, void *arg)
{
	struct irq_domain *domain = dmar_get_irq_domain();
	struct irq_alloc_info info;

	if (!domain)
		return -1;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	info.dmar_id = id;
	info.dmar_data = arg;

	return irq_domain_alloc_irqs(domain, 1, node, &info);
}

void dmar_free_hwirq(int irq)
{
	irq_domain_free_irqs(irq, 1);
}
#endif

/*
 * MSI message composition
 */
#ifdef CONFIG_HPET_TIMER
static inline int hpet_dev_id(struct irq_domain *domain)
{
	struct msi_domain_info *info = msi_get_domain_info(domain);

	return (int)(long)info->data;
}

static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
{
	hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
}

static struct irq_chip hpet_msi_controller __ro_after_init = {
	.name = "HPET-MSI",
	.irq_unmask = hpet_msi_unmask,
	.irq_mask = hpet_msi_mask,
	.irq_ack = irq_chip_ack_parent,
	.irq_set_affinity = msi_domain_set_affinity,
	.irq_retrigger = irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg = irq_msi_compose_msg,
	.irq_write_msi_msg = hpet_msi_write_msg,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
					  msi_alloc_info_t *arg)
{
	return arg->hpet_index;
}

static int hpet_msi_init(struct irq_domain *domain,
			 struct msi_domain_info *info, unsigned int virq,
			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
{
	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
			    handle_edge_irq, arg->hpet_data, "edge");

	return 0;
}

static void hpet_msi_free(struct irq_domain *domain,
			  struct msi_domain_info *info, unsigned int virq)
{
	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
}

static struct msi_domain_ops hpet_msi_domain_ops = {
	.get_hwirq	= hpet_msi_get_hwirq,
	.msi_init	= hpet_msi_init,
	.msi_free	= hpet_msi_free,
};

static struct msi_domain_info hpet_msi_domain_info = {
	.ops		= &hpet_msi_domain_ops,
	.chip		= &hpet_msi_controller,
};

struct irq_domain *hpet_create_irq_domain(int hpet_id)
{
	struct msi_domain_info *domain_info;
	struct irq_domain *parent, *d;
	struct irq_alloc_info info;
	struct fwnode_handle *fn;

	if (x86_vector_domain == NULL)
		return NULL;

	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
	if (!domain_info)
		return NULL;

	*domain_info = hpet_msi_domain_info;
	domain_info->data = (void *)(long)hpet_id;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_id = hpet_id;
	parent = irq_remapping_get_ir_irq_domain(&info);
	if (parent == NULL)
		parent = x86_vector_domain;
	else
		hpet_msi_controller.name = "IR-HPET-MSI";

	fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
					      hpet_id);
	if (!fn) {
		kfree(domain_info);
		return NULL;
	}

	d = msi_create_irq_domain(fn, domain_info, parent);
	irq_domain_free_fwnode(fn);
	return d;
}

int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
		    int dev_num)
{
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_data = dev;
	info.hpet_id = hpet_dev_id(domain);
	info.hpet_index = dev_num;

	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
}
#endif
Commit	Line	Data
44380982 JL	1	/*
	2	* Support of MSI, HPET and DMAR interrupts.
	3	*
	4	* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
	5	* Moved from arch/x86/kernel/apic/io_apic.c.
52f518a3 JL	6	* Jiang Liu <jiang.liu@linux.intel.com>
52f518a3 JL	7	* Convert to hierarchical irqdomain
44380982 JL	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#include <linux/mm.h>
	14	#include <linux/interrupt.h>
f901f138	15	#include <linux/irq.h>
44380982 JL	16	#include <linux/pci.h>
	17	#include <linux/dmar.h>
	18	#include <linux/hpet.h>
	19	#include <linux/msi.h>
d746d1eb	20	#include <asm/irqdomain.h>
44380982 JL	21	#include <asm/msidef.h>
	22	#include <asm/hpet.h>
	23	#include <asm/hw_irq.h>
	24	#include <asm/apic.h>
	25	#include <asm/irq_remapping.h>
	26
52f518a3 JL	27	static struct irq_domain *msi_default_domain;
52f518a3 JL	28
3cb96f0c JL	29	static void irq_msi_compose_msg(struct irq_data data, struct msi_msg msg)
	30	{
	31	struct irq_cfg *cfg = irqd_cfg(data);
	32
	33	msg->address_hi = MSI_ADDR_BASE_HI;
	34
	35	if (x2apic_enabled())
	36	msg->address_hi \|= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
	37
	38	msg->address_lo =
	39	MSI_ADDR_BASE_LO \|
	40	((apic->irq_dest_mode == 0) ?
	41	MSI_ADDR_DEST_MODE_PHYSICAL :
	42	MSI_ADDR_DEST_MODE_LOGICAL) \|
a31e58e1	43	MSI_ADDR_REDIRECTION_CPU \|
3cb96f0c JL	44	MSI_ADDR_DEST_ID(cfg->dest_apicid);
	45
	46	msg->data =
	47	MSI_DATA_TRIGGER_EDGE \|
	48	MSI_DATA_LEVEL_ASSERT \|
a31e58e1	49	MSI_DATA_DELIVERY_FIXED \|
3cb96f0c JL	50	MSI_DATA_VECTOR(cfg->vector);
	51	}
	52
44380982 JL	53	/*
	54	* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
	55	* which implement the MSI or MSI-X Capability Structure.
	56	*/
52f518a3	57	static struct irq_chip pci_msi_controller = {
44380982 JL	58	.name = "PCI-MSI",
	59	.irq_unmask = pci_msi_unmask_irq,
	60	.irq_mask = pci_msi_mask_irq,
52f518a3	61	.irq_ack = irq_chip_ack_parent,
52f518a3	62	.irq_retrigger = irq_chip_retrigger_hierarchy,
52f518a3	63	.irq_compose_msi_msg = irq_msi_compose_msg,
44380982 JL	64	.flags = IRQCHIP_SKIP_SET_WAKE,
	65	};
	66
52f518a3	67	int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
44380982	68	{
52f518a3 JL	69	struct irq_domain *domain;
52f518a3 JL	70	struct irq_alloc_info info;
44380982	71
52f518a3 JL	72	init_irq_alloc_info(&info, NULL);
	73	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	74	info.msi_dev = dev;
44380982	75
52f518a3 JL	76	domain = irq_remapping_get_irq_domain(&info);
	77	if (domain == NULL)
	78	domain = msi_default_domain;
	79	if (domain == NULL)
	80	return -ENOSYS;
44380982	81
699c4cec	82	return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
52f518a3	83	}
44380982	84
52f518a3 JL	85	void native_teardown_msi_irq(unsigned int irq)
	86	{
	87	irq_domain_free_irqs(irq, 1);
	88	}
44380982	89
52f518a3 JL	90	static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
	91	msi_alloc_info_t *arg)
	92	{
	93	return arg->msi_hwirq;
	94	}
44380982	95
c8f3e518 JO	96	int pci_msi_prepare(struct irq_domain domain, struct device dev, int nvec,
c8f3e518 JO	97	msi_alloc_info_t *arg)
52f518a3 JL	98	{
	99	struct pci_dev *pdev = to_pci_dev(dev);
	100	struct msi_desc *desc = first_pci_msi_entry(pdev);
	101
	102	init_irq_alloc_info(arg, NULL);
	103	arg->msi_dev = pdev;
	104	if (desc->msi_attrib.is_msix) {
	105	arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	106	} else {
	107	arg->type = X86_IRQ_ALLOC_TYPE_MSI;
	108	arg->flags \|= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	109	}
44380982 JL	110
	111	return 0;
	112	}
c8f3e518	113	EXPORT_SYMBOL_GPL(pci_msi_prepare);
44380982	114
c8f3e518	115	void pci_msi_set_desc(msi_alloc_info_t arg, struct msi_desc desc)
44380982	116	{
52f518a3 JL	117	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
52f518a3 JL	118	}
c8f3e518	119	EXPORT_SYMBOL_GPL(pci_msi_set_desc);
44380982	120
52f518a3 JL	121	static struct msi_domain_ops pci_msi_domain_ops = {
	122	.get_hwirq = pci_msi_get_hwirq,
	123	.msi_prepare = pci_msi_prepare,
	124	.set_desc = pci_msi_set_desc,
	125	};
44380982	126
52f518a3 JL	127	static struct msi_domain_info pci_msi_domain_info = {
52f518a3 JL	128	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
68682a26	129	MSI_FLAG_PCI_MSIX,
52f518a3 JL	130	.ops = &pci_msi_domain_ops,
	131	.chip = &pci_msi_controller,
	132	.handler = handle_edge_irq,
	133	.handler_name = "edge",
	134	};
44380982	135
f8f37ca7	136	void __init arch_init_msi_domain(struct irq_domain *parent)
52f518a3	137	{
f8f37ca7 TG	138	struct fwnode_handle *fn;
f8f37ca7 TG	139
52f518a3 JL	140	if (disable_apic)
52f518a3 JL	141	return;
44380982	142
f8f37ca7 TG	143	fn = irq_domain_alloc_named_fwnode("PCI-MSI");
	144	if (fn) {
	145	msi_default_domain =
	146	pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
	147	parent);
	148	irq_domain_free_fwnode(fn);
	149	}
52f518a3 JL	150	if (!msi_default_domain)
52f518a3 JL	151	pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
44380982 JL	152	}
44380982 JL	153
52f518a3	154	#ifdef CONFIG_IRQ_REMAP
68682a26 JL	155	static struct irq_chip pci_msi_ir_controller = {
	156	.name = "IR-PCI-MSI",
	157	.irq_unmask = pci_msi_unmask_irq,
	158	.irq_mask = pci_msi_mask_irq,
	159	.irq_ack = irq_chip_ack_parent,
68682a26	160	.irq_retrigger = irq_chip_retrigger_hierarchy,
a2f1c8bd	161	.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
68682a26 JL	162	.flags = IRQCHIP_SKIP_SET_WAKE,
	163	};
	164
	165	static struct msi_domain_info pci_msi_ir_domain_info = {
	166	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	167	MSI_FLAG_MULTI_PCI_MSI \| MSI_FLAG_PCI_MSIX,
	168	.ops = &pci_msi_domain_ops,
	169	.chip = &pci_msi_ir_controller,
	170	.handler = handle_edge_irq,
	171	.handler_name = "edge",
	172	};
	173
667724c5 TG	174	struct irq_domain arch_create_remap_msi_irq_domain(struct irq_domain parent,
	175	const char *name, int id)
	176	{
	177	struct fwnode_handle *fn;
	178	struct irq_domain *d;
	179
	180	fn = irq_domain_alloc_named_id_fwnode(name, id);
	181	if (!fn)
	182	return NULL;
	183	d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
	184	irq_domain_free_fwnode(fn);
	185	return d;
	186	}
52f518a3	187	#endif
44380982 JL	188
44380982 JL	189	#ifdef CONFIG_DMAR_TABLE
62ac1780 JL	190	static void dmar_msi_write_msg(struct irq_data data, struct msi_msg msg)
	191	{
	192	dmar_msi_write(data->irq, msg);
	193	}
	194
0921f1da	195	static struct irq_chip dmar_msi_controller = {
81dabe2e	196	.name = "DMAR-MSI",
44380982 JL	197	.irq_unmask = dmar_msi_unmask,
44380982 JL	198	.irq_mask = dmar_msi_mask,
0921f1da	199	.irq_ack = irq_chip_ack_parent,
e390d895	200	.irq_set_affinity = msi_domain_set_affinity,
0921f1da JL	201	.irq_retrigger = irq_chip_retrigger_hierarchy,
0921f1da JL	202	.irq_compose_msi_msg = irq_msi_compose_msg,
62ac1780	203	.irq_write_msi_msg = dmar_msi_write_msg,
44380982 JL	204	.flags = IRQCHIP_SKIP_SET_WAKE,
	205	};
	206
e390d895 JL	207	static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
e390d895 JL	208	msi_alloc_info_t *arg)
0921f1da	209	{
e390d895	210	return arg->dmar_id;
0921f1da JL	211	}
0921f1da JL	212
e390d895 JL	213	static int dmar_msi_init(struct irq_domain *domain,
	214	struct msi_domain_info *info, unsigned int virq,
	215	irq_hw_number_t hwirq, msi_alloc_info_t *arg)
0921f1da	216	{
e390d895 JL	217	irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
e390d895 JL	218	handle_edge_irq, arg->dmar_data, "edge");
0921f1da	219
e390d895	220	return 0;
0921f1da JL	221	}
0921f1da JL	222
e390d895 JL	223	static struct msi_domain_ops dmar_msi_domain_ops = {
	224	.get_hwirq = dmar_msi_get_hwirq,
	225	.msi_init = dmar_msi_init,
	226	};
0921f1da	227
e390d895 JL	228	static struct msi_domain_info dmar_msi_domain_info = {
	229	.ops = &dmar_msi_domain_ops,
	230	.chip = &dmar_msi_controller,
0921f1da JL	231	};
	232
	233	static struct irq_domain *dmar_get_irq_domain(void)
	234	{
	235	static struct irq_domain *dmar_domain;
	236	static DEFINE_MUTEX(dmar_lock);
f8f37ca7	237	struct fwnode_handle *fn;
0921f1da JL	238
0921f1da JL	239	mutex_lock(&dmar_lock);
f8f37ca7 TG	240	if (dmar_domain)
	241	goto out;
	242
	243	fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
	244	if (fn) {
	245	dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
e390d895	246	x86_vector_domain);
f8f37ca7 TG	247	irq_domain_free_fwnode(fn);
	248	}
	249	out:
0921f1da	250	mutex_unlock(&dmar_lock);
0921f1da JL	251	return dmar_domain;
	252	}
	253
	254	int dmar_alloc_hwirq(int id, int node, void *arg)
	255	{
	256	struct irq_domain *domain = dmar_get_irq_domain();
	257	struct irq_alloc_info info;
	258
	259	if (!domain)
	260	return -1;
	261
	262	init_irq_alloc_info(&info, NULL);
	263	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	264	info.dmar_id = id;
	265	info.dmar_data = arg;
a62b32cd	266
0921f1da	267	return irq_domain_alloc_irqs(domain, 1, node, &info);
a62b32cd JL	268	}
	269
	270	void dmar_free_hwirq(int irq)
	271	{
	272	irq_domain_free_irqs(irq, 1);
	273	}
44380982 JL	274	#endif
	275
	276	/*
	277	* MSI message composition
	278	*/
	279	#ifdef CONFIG_HPET_TIMER
3cb96f0c JL	280	static inline int hpet_dev_id(struct irq_domain *domain)
3cb96f0c JL	281	{
e390d895	282	struct msi_domain_info *info = msi_get_domain_info(domain);
44380982	283
e390d895	284	return (int)(long)info->data;
44380982 JL	285	}
44380982 JL	286
62ac1780 JL	287	static void hpet_msi_write_msg(struct irq_data data, struct msi_msg msg)
62ac1780 JL	288	{
ff96b4d0	289	hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
62ac1780 JL	290	}
62ac1780 JL	291
404f6aac	292	static struct irq_chip hpet_msi_controller __ro_after_init = {
81dabe2e	293	.name = "HPET-MSI",
44380982 JL	294	.irq_unmask = hpet_msi_unmask,
44380982 JL	295	.irq_mask = hpet_msi_mask,
3cb96f0c	296	.irq_ack = irq_chip_ack_parent,
e390d895	297	.irq_set_affinity = msi_domain_set_affinity,
3cb96f0c	298	.irq_retrigger = irq_chip_retrigger_hierarchy,
3cb96f0c	299	.irq_compose_msi_msg = irq_msi_compose_msg,
62ac1780	300	.irq_write_msi_msg = hpet_msi_write_msg,
44380982 JL	301	.flags = IRQCHIP_SKIP_SET_WAKE,
	302	};
	303
e390d895 JL	304	static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
e390d895 JL	305	msi_alloc_info_t *arg)
3cb96f0c	306	{
e390d895	307	return arg->hpet_index;
3cb96f0c JL	308	}
3cb96f0c JL	309
e390d895 JL	310	static int hpet_msi_init(struct irq_domain *domain,
	311	struct msi_domain_info *info, unsigned int virq,
	312	irq_hw_number_t hwirq, msi_alloc_info_t *arg)
3cb96f0c	313	{
e390d895 JL	314	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	315	irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
	316	handle_edge_irq, arg->hpet_data, "edge");
3cb96f0c	317
e390d895	318	return 0;
3cb96f0c JL	319	}
3cb96f0c JL	320
e390d895 JL	321	static void hpet_msi_free(struct irq_domain *domain,
e390d895 JL	322	struct msi_domain_info *info, unsigned int virq)
3cb96f0c	323	{
e390d895	324	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
3cb96f0c JL	325	}
3cb96f0c JL	326
e390d895 JL	327	static struct msi_domain_ops hpet_msi_domain_ops = {
	328	.get_hwirq = hpet_msi_get_hwirq,
	329	.msi_init = hpet_msi_init,
	330	.msi_free = hpet_msi_free,
	331	};
	332
	333	static struct msi_domain_info hpet_msi_domain_info = {
	334	.ops = &hpet_msi_domain_ops,
	335	.chip = &hpet_msi_controller,
3cb96f0c JL	336	};
	337
	338	struct irq_domain *hpet_create_irq_domain(int hpet_id)
	339	{
e390d895	340	struct msi_domain_info *domain_info;
f8f37ca7 TG	341	struct irq_domain parent, d;
	342	struct irq_alloc_info info;
	343	struct fwnode_handle *fn;
3cb96f0c JL	344
	345	if (x86_vector_domain == NULL)
	346	return NULL;
	347
e390d895 JL	348	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
	349	if (!domain_info)
	350	return NULL;
	351
	352	*domain_info = hpet_msi_domain_info;
	353	domain_info->data = (void *)(long)hpet_id;
	354
3cb96f0c JL	355	init_irq_alloc_info(&info, NULL);
	356	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	357	info.hpet_id = hpet_id;
	358	parent = irq_remapping_get_ir_irq_domain(&info);
	359	if (parent == NULL)
	360	parent = x86_vector_domain;
68682a26 JL	361	else
68682a26 JL	362	hpet_msi_controller.name = "IR-HPET-MSI";
3cb96f0c	363
f8f37ca7 TG	364	fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
	365	hpet_id);
	366	if (!fn) {
	367	kfree(domain_info);
	368	return NULL;
	369	}
	370
	371	d = msi_create_irq_domain(fn, domain_info, parent);
	372	irq_domain_free_fwnode(fn);
	373	return d;
3cb96f0c JL	374	}
	375
	376	int hpet_assign_irq(struct irq_domain domain, struct hpet_dev dev,
	377	int dev_num)
	378	{
	379	struct irq_alloc_info info;
	380
	381	init_irq_alloc_info(&info, NULL);
	382	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	383	info.hpet_data = dev;
	384	info.hpet_id = hpet_dev_id(domain);
	385	info.hpet_index = dev_num;
	386
4a00c95d	387	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
3cb96f0c	388	}
44380982	389	#endif