[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / apic / msi.c

/*
 * Support of MSI, HPET and DMAR interrupts.
 *
 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
 *	Moved from arch/x86/kernel/apic/io_apic.c.
 * Jiang Liu <jiang.liu@linux.intel.com>
 *	Convert to hierarchical irqdomain
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/hpet.h>
#include <linux/msi.h>
#include <linux/irqdomain.h>
#include <asm/msidef.h>
#include <asm/hpet.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/irq_remapping.h>

static struct irq_domain *msi_default_domain;

static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
	struct irq_cfg *cfg = irqd_cfg(data);

	msg->address_hi = MSI_ADDR_BASE_HI;

	if (x2apic_enabled())
		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);

	msg->address_lo =
		MSI_ADDR_BASE_LO |
		((apic->irq_dest_mode == 0) ?
			MSI_ADDR_DEST_MODE_PHYSICAL :
			MSI_ADDR_DEST_MODE_LOGICAL) |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_ADDR_REDIRECTION_CPU :
			MSI_ADDR_REDIRECTION_LOWPRI) |
		MSI_ADDR_DEST_ID(cfg->dest_apicid);

	msg->data =
		MSI_DATA_TRIGGER_EDGE |
		MSI_DATA_LEVEL_ASSERT |
		((apic->irq_delivery_mode != dest_LowestPrio) ?
			MSI_DATA_DELIVERY_FIXED :
			MSI_DATA_DELIVERY_LOWPRI) |
		MSI_DATA_VECTOR(cfg->vector);
}

/*
 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
 * which implement the MSI or MSI-X Capability Structure.
 */
static struct irq_chip pci_msi_controller = {
	.name			= "PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	struct irq_domain *domain;
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	info.msi_dev = dev;

	domain = irq_remapping_get_irq_domain(&info);
	if (domain == NULL)
		domain = msi_default_domain;
	if (domain == NULL)
		return -ENOSYS;

	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
}

void native_teardown_msi_irq(unsigned int irq)
{
	irq_domain_free_irqs(irq, 1);
}

static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
					 msi_alloc_info_t *arg)
{
	return arg->msi_hwirq;
}

static int pci_msi_prepare(struct irq_domain *domain, struct device *dev,
			   int nvec, msi_alloc_info_t *arg)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct msi_desc *desc = first_pci_msi_entry(pdev);

	init_irq_alloc_info(arg, NULL);
	arg->msi_dev = pdev;
	if (desc->msi_attrib.is_msix) {
		arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	} else {
		arg->type = X86_IRQ_ALLOC_TYPE_MSI;
		arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	}

	return 0;
}

static void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
{
	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
}

static struct msi_domain_ops pci_msi_domain_ops = {
	.get_hwirq	= pci_msi_get_hwirq,
	.msi_prepare	= pci_msi_prepare,
	.set_desc	= pci_msi_set_desc,
};

static struct msi_domain_info pci_msi_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

void arch_init_msi_domain(struct irq_domain *parent)
{
	if (disable_apic)
		return;

	msi_default_domain = pci_msi_create_irq_domain(NULL,
					&pci_msi_domain_info, parent);
	if (!msi_default_domain)
		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
}

#ifdef CONFIG_IRQ_REMAP
static struct irq_chip pci_msi_ir_controller = {
	.name			= "IR-PCI-MSI",
	.irq_unmask		= pci_msi_unmask_irq,
	.irq_mask		= pci_msi_mask_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static struct msi_domain_info pci_msi_ir_domain_info = {
	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
	.ops		= &pci_msi_domain_ops,
	.chip		= &pci_msi_ir_controller,
	.handler	= handle_edge_irq,
	.handler_name	= "edge",
};

struct irq_domain *arch_create_msi_irq_domain(struct irq_domain *parent)
{
	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
}
#endif

#ifdef CONFIG_DMAR_TABLE
static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
{
	dmar_msi_write(data->irq, msg);
}

static struct irq_chip dmar_msi_controller = {
	.name			= "DMAR-MSI",
	.irq_unmask		= dmar_msi_unmask,
	.irq_mask		= dmar_msi_mask,
	.irq_ack		= irq_chip_ack_parent,
	.irq_set_affinity	= msi_domain_set_affinity,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg	= irq_msi_compose_msg,
	.irq_write_msi_msg	= dmar_msi_write_msg,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
					  msi_alloc_info_t *arg)
{
	return arg->dmar_id;
}

static int dmar_msi_init(struct irq_domain *domain,
			 struct msi_domain_info *info, unsigned int virq,
			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
{
	irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
			    handle_edge_irq, arg->dmar_data, "edge");

	return 0;
}

static struct msi_domain_ops dmar_msi_domain_ops = {
	.get_hwirq	= dmar_msi_get_hwirq,
	.msi_init	= dmar_msi_init,
};

static struct msi_domain_info dmar_msi_domain_info = {
	.ops		= &dmar_msi_domain_ops,
	.chip		= &dmar_msi_controller,
};

static struct irq_domain *dmar_get_irq_domain(void)
{
	static struct irq_domain *dmar_domain;
	static DEFINE_MUTEX(dmar_lock);

	mutex_lock(&dmar_lock);
	if (dmar_domain == NULL)
		dmar_domain = msi_create_irq_domain(NULL, &dmar_msi_domain_info,
						    x86_vector_domain);
	mutex_unlock(&dmar_lock);

	return dmar_domain;
}

int dmar_alloc_hwirq(int id, int node, void *arg)
{
	struct irq_domain *domain = dmar_get_irq_domain();
	struct irq_alloc_info info;

	if (!domain)
		return -1;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	info.dmar_id = id;
	info.dmar_data = arg;

	return irq_domain_alloc_irqs(domain, 1, node, &info);
}

void dmar_free_hwirq(int irq)
{
	irq_domain_free_irqs(irq, 1);
}
#endif

/*
 * MSI message composition
 */
#ifdef CONFIG_HPET_TIMER
static inline int hpet_dev_id(struct irq_domain *domain)
{
	struct msi_domain_info *info = msi_get_domain_info(domain);

	return (int)(long)info->data;
}

static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
{
	hpet_msi_write(data->handler_data, msg);
}

static struct irq_chip hpet_msi_controller = {
	.name = "HPET-MSI",
	.irq_unmask = hpet_msi_unmask,
	.irq_mask = hpet_msi_mask,
	.irq_ack = irq_chip_ack_parent,
	.irq_set_affinity = msi_domain_set_affinity,
	.irq_retrigger = irq_chip_retrigger_hierarchy,
	.irq_compose_msi_msg = irq_msi_compose_msg,
	.irq_write_msi_msg = hpet_msi_write_msg,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
					  msi_alloc_info_t *arg)
{
	return arg->hpet_index;
}

static int hpet_msi_init(struct irq_domain *domain,
			 struct msi_domain_info *info, unsigned int virq,
			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
{
	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
			    handle_edge_irq, arg->hpet_data, "edge");

	return 0;
}

static void hpet_msi_free(struct irq_domain *domain,
			  struct msi_domain_info *info, unsigned int virq)
{
	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
}

static struct msi_domain_ops hpet_msi_domain_ops = {
	.get_hwirq	= hpet_msi_get_hwirq,
	.msi_init	= hpet_msi_init,
	.msi_free	= hpet_msi_free,
};

static struct msi_domain_info hpet_msi_domain_info = {
	.ops		= &hpet_msi_domain_ops,
	.chip		= &hpet_msi_controller,
};

struct irq_domain *hpet_create_irq_domain(int hpet_id)
{
	struct irq_domain *parent;
	struct irq_alloc_info info;
	struct msi_domain_info *domain_info;

	if (x86_vector_domain == NULL)
		return NULL;

	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
	if (!domain_info)
		return NULL;

	*domain_info = hpet_msi_domain_info;
	domain_info->data = (void *)(long)hpet_id;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_id = hpet_id;
	parent = irq_remapping_get_ir_irq_domain(&info);
	if (parent == NULL)
		parent = x86_vector_domain;
	else
		hpet_msi_controller.name = "IR-HPET-MSI";

	return msi_create_irq_domain(NULL, domain_info, parent);
}

int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
		    int dev_num)
{
	struct irq_alloc_info info;

	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	info.hpet_data = dev;
	info.hpet_id = hpet_dev_id(domain);
	info.hpet_index = dev_num;

	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);
}
#endif
Commit	Line	Data
44380982 JL	1	/*
	2	* Support of MSI, HPET and DMAR interrupts.
	3	*
	4	* Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
	5	* Moved from arch/x86/kernel/apic/io_apic.c.
52f518a3 JL	6	* Jiang Liu <jiang.liu@linux.intel.com>
52f518a3 JL	7	* Convert to hierarchical irqdomain
44380982 JL	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#include <linux/mm.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/pci.h>
	16	#include <linux/dmar.h>
	17	#include <linux/hpet.h>
	18	#include <linux/msi.h>
4c8f9960	19	#include <linux/irqdomain.h>
44380982 JL	20	#include <asm/msidef.h>
	21	#include <asm/hpet.h>
	22	#include <asm/hw_irq.h>
	23	#include <asm/apic.h>
	24	#include <asm/irq_remapping.h>
	25
52f518a3 JL	26	static struct irq_domain *msi_default_domain;
52f518a3 JL	27
3cb96f0c JL	28	static void irq_msi_compose_msg(struct irq_data data, struct msi_msg msg)
	29	{
	30	struct irq_cfg *cfg = irqd_cfg(data);
	31
	32	msg->address_hi = MSI_ADDR_BASE_HI;
	33
	34	if (x2apic_enabled())
	35	msg->address_hi \|= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
	36
	37	msg->address_lo =
	38	MSI_ADDR_BASE_LO \|
	39	((apic->irq_dest_mode == 0) ?
	40	MSI_ADDR_DEST_MODE_PHYSICAL :
	41	MSI_ADDR_DEST_MODE_LOGICAL) \|
	42	((apic->irq_delivery_mode != dest_LowestPrio) ?
	43	MSI_ADDR_REDIRECTION_CPU :
	44	MSI_ADDR_REDIRECTION_LOWPRI) \|
	45	MSI_ADDR_DEST_ID(cfg->dest_apicid);
	46
	47	msg->data =
	48	MSI_DATA_TRIGGER_EDGE \|
	49	MSI_DATA_LEVEL_ASSERT \|
	50	((apic->irq_delivery_mode != dest_LowestPrio) ?
	51	MSI_DATA_DELIVERY_FIXED :
	52	MSI_DATA_DELIVERY_LOWPRI) \|
	53	MSI_DATA_VECTOR(cfg->vector);
	54	}
	55
44380982 JL	56	/*
	57	* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
	58	* which implement the MSI or MSI-X Capability Structure.
	59	*/
52f518a3	60	static struct irq_chip pci_msi_controller = {
44380982 JL	61	.name = "PCI-MSI",
	62	.irq_unmask = pci_msi_unmask_irq,
	63	.irq_mask = pci_msi_mask_irq,
52f518a3	64	.irq_ack = irq_chip_ack_parent,
52f518a3	65	.irq_retrigger = irq_chip_retrigger_hierarchy,
52f518a3	66	.irq_compose_msi_msg = irq_msi_compose_msg,
44380982 JL	67	.flags = IRQCHIP_SKIP_SET_WAKE,
	68	};
	69
52f518a3	70	int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
44380982	71	{
52f518a3 JL	72	struct irq_domain *domain;
52f518a3 JL	73	struct irq_alloc_info info;
44380982	74
52f518a3 JL	75	init_irq_alloc_info(&info, NULL);
	76	info.type = X86_IRQ_ALLOC_TYPE_MSI;
	77	info.msi_dev = dev;
44380982	78
52f518a3 JL	79	domain = irq_remapping_get_irq_domain(&info);
	80	if (domain == NULL)
	81	domain = msi_default_domain;
	82	if (domain == NULL)
	83	return -ENOSYS;
44380982	84
52f518a3 JL	85	return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
52f518a3 JL	86	}
44380982	87
52f518a3 JL	88	void native_teardown_msi_irq(unsigned int irq)
	89	{
	90	irq_domain_free_irqs(irq, 1);
	91	}
44380982	92
52f518a3 JL	93	static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
	94	msi_alloc_info_t *arg)
	95	{
	96	return arg->msi_hwirq;
	97	}
44380982	98
52f518a3 JL	99	static int pci_msi_prepare(struct irq_domain domain, struct device dev,
	100	int nvec, msi_alloc_info_t *arg)
	101	{
	102	struct pci_dev *pdev = to_pci_dev(dev);
	103	struct msi_desc *desc = first_pci_msi_entry(pdev);
	104
	105	init_irq_alloc_info(arg, NULL);
	106	arg->msi_dev = pdev;
	107	if (desc->msi_attrib.is_msix) {
	108	arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
	109	} else {
	110	arg->type = X86_IRQ_ALLOC_TYPE_MSI;
	111	arg->flags \|= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
	112	}
44380982 JL	113
	114	return 0;
	115	}
	116
52f518a3	117	static void pci_msi_set_desc(msi_alloc_info_t arg, struct msi_desc desc)
44380982	118	{
52f518a3 JL	119	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
52f518a3 JL	120	}
44380982	121
52f518a3 JL	122	static struct msi_domain_ops pci_msi_domain_ops = {
	123	.get_hwirq = pci_msi_get_hwirq,
	124	.msi_prepare = pci_msi_prepare,
	125	.set_desc = pci_msi_set_desc,
	126	};
44380982	127
52f518a3 JL	128	static struct msi_domain_info pci_msi_domain_info = {
52f518a3 JL	129	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
68682a26	130	MSI_FLAG_PCI_MSIX,
52f518a3 JL	131	.ops = &pci_msi_domain_ops,
	132	.chip = &pci_msi_controller,
	133	.handler = handle_edge_irq,
	134	.handler_name = "edge",
	135	};
44380982	136
52f518a3 JL	137	void arch_init_msi_domain(struct irq_domain *parent)
	138	{
	139	if (disable_apic)
	140	return;
44380982	141
52f518a3 JL	142	msi_default_domain = pci_msi_create_irq_domain(NULL,
	143	&pci_msi_domain_info, parent);
	144	if (!msi_default_domain)
	145	pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
44380982 JL	146	}
44380982 JL	147
52f518a3	148	#ifdef CONFIG_IRQ_REMAP
68682a26 JL	149	static struct irq_chip pci_msi_ir_controller = {
	150	.name = "IR-PCI-MSI",
	151	.irq_unmask = pci_msi_unmask_irq,
	152	.irq_mask = pci_msi_mask_irq,
	153	.irq_ack = irq_chip_ack_parent,
68682a26	154	.irq_retrigger = irq_chip_retrigger_hierarchy,
68682a26 JL	155	.flags = IRQCHIP_SKIP_SET_WAKE,
	156	};
	157
	158	static struct msi_domain_info pci_msi_ir_domain_info = {
	159	.flags = MSI_FLAG_USE_DEF_DOM_OPS \| MSI_FLAG_USE_DEF_CHIP_OPS \|
	160	MSI_FLAG_MULTI_PCI_MSI \| MSI_FLAG_PCI_MSIX,
	161	.ops = &pci_msi_domain_ops,
	162	.chip = &pci_msi_ir_controller,
	163	.handler = handle_edge_irq,
	164	.handler_name = "edge",
	165	};
	166
52f518a3	167	struct irq_domain arch_create_msi_irq_domain(struct irq_domain parent)
44380982	168	{
68682a26	169	return pci_msi_create_irq_domain(NULL, &pci_msi_ir_domain_info, parent);
44380982	170	}
52f518a3	171	#endif
44380982 JL	172
44380982 JL	173	#ifdef CONFIG_DMAR_TABLE
62ac1780 JL	174	static void dmar_msi_write_msg(struct irq_data data, struct msi_msg msg)
	175	{
	176	dmar_msi_write(data->irq, msg);
	177	}
	178
0921f1da	179	static struct irq_chip dmar_msi_controller = {
81dabe2e	180	.name = "DMAR-MSI",
44380982 JL	181	.irq_unmask = dmar_msi_unmask,
44380982 JL	182	.irq_mask = dmar_msi_mask,
0921f1da	183	.irq_ack = irq_chip_ack_parent,
e390d895	184	.irq_set_affinity = msi_domain_set_affinity,
0921f1da JL	185	.irq_retrigger = irq_chip_retrigger_hierarchy,
0921f1da JL	186	.irq_compose_msi_msg = irq_msi_compose_msg,
62ac1780	187	.irq_write_msi_msg = dmar_msi_write_msg,
44380982 JL	188	.flags = IRQCHIP_SKIP_SET_WAKE,
	189	};
	190
e390d895 JL	191	static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
e390d895 JL	192	msi_alloc_info_t *arg)
0921f1da	193	{
e390d895	194	return arg->dmar_id;
0921f1da JL	195	}
0921f1da JL	196
e390d895 JL	197	static int dmar_msi_init(struct irq_domain *domain,
	198	struct msi_domain_info *info, unsigned int virq,
	199	irq_hw_number_t hwirq, msi_alloc_info_t *arg)
0921f1da	200	{
e390d895 JL	201	irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
e390d895 JL	202	handle_edge_irq, arg->dmar_data, "edge");
0921f1da	203
e390d895	204	return 0;
0921f1da JL	205	}
0921f1da JL	206
e390d895 JL	207	static struct msi_domain_ops dmar_msi_domain_ops = {
	208	.get_hwirq = dmar_msi_get_hwirq,
	209	.msi_init = dmar_msi_init,
	210	};
0921f1da	211
e390d895 JL	212	static struct msi_domain_info dmar_msi_domain_info = {
	213	.ops = &dmar_msi_domain_ops,
	214	.chip = &dmar_msi_controller,
0921f1da JL	215	};
	216
	217	static struct irq_domain *dmar_get_irq_domain(void)
	218	{
	219	static struct irq_domain *dmar_domain;
	220	static DEFINE_MUTEX(dmar_lock);
	221
	222	mutex_lock(&dmar_lock);
e390d895 JL	223	if (dmar_domain == NULL)
	224	dmar_domain = msi_create_irq_domain(NULL, &dmar_msi_domain_info,
	225	x86_vector_domain);
0921f1da JL	226	mutex_unlock(&dmar_lock);
	227
	228	return dmar_domain;
	229	}
	230
	231	int dmar_alloc_hwirq(int id, int node, void *arg)
	232	{
	233	struct irq_domain *domain = dmar_get_irq_domain();
	234	struct irq_alloc_info info;
	235
	236	if (!domain)
	237	return -1;
	238
	239	init_irq_alloc_info(&info, NULL);
	240	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
	241	info.dmar_id = id;
	242	info.dmar_data = arg;
a62b32cd	243
0921f1da	244	return irq_domain_alloc_irqs(domain, 1, node, &info);
a62b32cd JL	245	}
	246
	247	void dmar_free_hwirq(int irq)
	248	{
	249	irq_domain_free_irqs(irq, 1);
	250	}
44380982 JL	251	#endif
	252
	253	/*
	254	* MSI message composition
	255	*/
	256	#ifdef CONFIG_HPET_TIMER
3cb96f0c JL	257	static inline int hpet_dev_id(struct irq_domain *domain)
3cb96f0c JL	258	{
e390d895	259	struct msi_domain_info *info = msi_get_domain_info(domain);
44380982	260
e390d895	261	return (int)(long)info->data;
44380982 JL	262	}
44380982 JL	263
62ac1780 JL	264	static void hpet_msi_write_msg(struct irq_data data, struct msi_msg msg)
	265	{
	266	hpet_msi_write(data->handler_data, msg);
	267	}
	268
3cb96f0c	269	static struct irq_chip hpet_msi_controller = {
81dabe2e	270	.name = "HPET-MSI",
44380982 JL	271	.irq_unmask = hpet_msi_unmask,
44380982 JL	272	.irq_mask = hpet_msi_mask,
3cb96f0c	273	.irq_ack = irq_chip_ack_parent,
e390d895	274	.irq_set_affinity = msi_domain_set_affinity,
3cb96f0c	275	.irq_retrigger = irq_chip_retrigger_hierarchy,
3cb96f0c	276	.irq_compose_msi_msg = irq_msi_compose_msg,
62ac1780	277	.irq_write_msi_msg = hpet_msi_write_msg,
44380982 JL	278	.flags = IRQCHIP_SKIP_SET_WAKE,
	279	};
	280
e390d895 JL	281	static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
e390d895 JL	282	msi_alloc_info_t *arg)
3cb96f0c	283	{
e390d895	284	return arg->hpet_index;
3cb96f0c JL	285	}
3cb96f0c JL	286
e390d895 JL	287	static int hpet_msi_init(struct irq_domain *domain,
	288	struct msi_domain_info *info, unsigned int virq,
	289	irq_hw_number_t hwirq, msi_alloc_info_t *arg)
3cb96f0c	290	{
e390d895 JL	291	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
	292	irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
	293	handle_edge_irq, arg->hpet_data, "edge");
3cb96f0c	294
e390d895	295	return 0;
3cb96f0c JL	296	}
3cb96f0c JL	297
e390d895 JL	298	static void hpet_msi_free(struct irq_domain *domain,
e390d895 JL	299	struct msi_domain_info *info, unsigned int virq)
3cb96f0c	300	{
e390d895	301	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
3cb96f0c JL	302	}
3cb96f0c JL	303
e390d895 JL	304	static struct msi_domain_ops hpet_msi_domain_ops = {
	305	.get_hwirq = hpet_msi_get_hwirq,
	306	.msi_init = hpet_msi_init,
	307	.msi_free = hpet_msi_free,
	308	};
	309
	310	static struct msi_domain_info hpet_msi_domain_info = {
	311	.ops = &hpet_msi_domain_ops,
	312	.chip = &hpet_msi_controller,
3cb96f0c JL	313	};
	314
	315	struct irq_domain *hpet_create_irq_domain(int hpet_id)
	316	{
	317	struct irq_domain *parent;
	318	struct irq_alloc_info info;
e390d895	319	struct msi_domain_info *domain_info;
3cb96f0c JL	320
	321	if (x86_vector_domain == NULL)
	322	return NULL;
	323
e390d895 JL	324	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
	325	if (!domain_info)
	326	return NULL;
	327
	328	*domain_info = hpet_msi_domain_info;
	329	domain_info->data = (void *)(long)hpet_id;
	330
3cb96f0c JL	331	init_irq_alloc_info(&info, NULL);
	332	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	333	info.hpet_id = hpet_id;
	334	parent = irq_remapping_get_ir_irq_domain(&info);
	335	if (parent == NULL)
	336	parent = x86_vector_domain;
68682a26 JL	337	else
68682a26 JL	338	hpet_msi_controller.name = "IR-HPET-MSI";
3cb96f0c	339
e390d895	340	return msi_create_irq_domain(NULL, domain_info, parent);
3cb96f0c JL	341	}
	342
	343	int hpet_assign_irq(struct irq_domain domain, struct hpet_dev dev,
	344	int dev_num)
	345	{
	346	struct irq_alloc_info info;
	347
	348	init_irq_alloc_info(&info, NULL);
	349	info.type = X86_IRQ_ALLOC_TYPE_HPET;
	350	info.hpet_data = dev;
	351	info.hpet_id = hpet_dev_id(domain);
	352	info.hpet_index = dev_num;
	353
	354	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, NULL);
	355	}
44380982	356	#endif