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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
029c6e1c TG |
26 | unsigned int cpu; |
27 | unsigned int prev_cpu; | |
dccfe314 | 28 | struct hlist_node clist; |
7f3262ed JL |
29 | cpumask_var_t domain; |
30 | cpumask_var_t old_domain; | |
31 | u8 move_in_progress : 1; | |
32 | }; | |
33 | ||
b5dc8e6c | 34 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 35 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 36 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 37 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 38 | static struct irq_chip lapic_controller; |
0fa115da | 39 | static struct irq_matrix *vector_matrix; |
dccfe314 TG |
40 | #ifdef CONFIG_SMP |
41 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
42 | #endif | |
74afab7a JL |
43 | |
44 | void lock_vector_lock(void) | |
45 | { | |
46 | /* Used to the online set of cpus does not change | |
47 | * during assign_irq_vector. | |
48 | */ | |
49 | raw_spin_lock(&vector_lock); | |
50 | } | |
51 | ||
52 | void unlock_vector_lock(void) | |
53 | { | |
54 | raw_spin_unlock(&vector_lock); | |
55 | } | |
56 | ||
99a1482d TG |
57 | void init_irq_alloc_info(struct irq_alloc_info *info, |
58 | const struct cpumask *mask) | |
59 | { | |
60 | memset(info, 0, sizeof(*info)); | |
61 | info->mask = mask; | |
62 | } | |
63 | ||
64 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
65 | { | |
66 | if (src) | |
67 | *dst = *src; | |
68 | else | |
69 | memset(dst, 0, sizeof(*dst)); | |
70 | } | |
71 | ||
86ba6551 | 72 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 73 | { |
86ba6551 | 74 | if (!irqd) |
b5dc8e6c JL |
75 | return NULL; |
76 | ||
86ba6551 TG |
77 | while (irqd->parent_data) |
78 | irqd = irqd->parent_data; | |
b5dc8e6c | 79 | |
86ba6551 | 80 | return irqd->chip_data; |
74afab7a JL |
81 | } |
82 | ||
86ba6551 | 83 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 84 | { |
86ba6551 | 85 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 86 | |
86ba6551 | 87 | return apicd ? &apicd->cfg : NULL; |
7f3262ed | 88 | } |
c8f3e518 | 89 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
90 | |
91 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 92 | { |
7f3262ed JL |
93 | return irqd_cfg(irq_get_irq_data(irq)); |
94 | } | |
74afab7a | 95 | |
7f3262ed JL |
96 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
97 | { | |
86ba6551 | 98 | struct apic_chip_data *apicd; |
7f3262ed | 99 | |
86ba6551 TG |
100 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
101 | if (!apicd) | |
74afab7a | 102 | return NULL; |
86ba6551 | 103 | if (!zalloc_cpumask_var_node(&apicd->domain, GFP_KERNEL, node)) |
7f3262ed | 104 | goto out_data; |
86ba6551 | 105 | if (!zalloc_cpumask_var_node(&apicd->old_domain, GFP_KERNEL, node)) |
74afab7a | 106 | goto out_domain; |
dccfe314 | 107 | INIT_HLIST_NODE(&apicd->clist); |
86ba6551 | 108 | return apicd; |
74afab7a | 109 | out_domain: |
86ba6551 | 110 | free_cpumask_var(apicd->domain); |
7f3262ed | 111 | out_data: |
86ba6551 | 112 | kfree(apicd); |
74afab7a JL |
113 | return NULL; |
114 | } | |
115 | ||
86ba6551 | 116 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 117 | { |
86ba6551 TG |
118 | if (apicd) { |
119 | free_cpumask_var(apicd->domain); | |
120 | free_cpumask_var(apicd->old_domain); | |
121 | kfree(apicd); | |
b5dc8e6c | 122 | } |
74afab7a JL |
123 | } |
124 | ||
7f3262ed | 125 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
0e24f7c9 | 126 | const struct cpumask *mask, |
86ba6551 | 127 | struct irq_data *irqd) |
74afab7a JL |
128 | { |
129 | /* | |
130 | * NOTE! The local APIC isn't very good at handling | |
131 | * multiple interrupts at the same interrupt level. | |
132 | * As the interrupt level is determined by taking the | |
133 | * vector number and shifting that right by 4, we | |
134 | * want to spread these out a bit so that they don't | |
135 | * all fall in the same interrupt level. | |
136 | * | |
137 | * Also, we've got to be careful not to trash gate | |
138 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
139 | */ | |
140 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
141 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 142 | int cpu, vector; |
74afab7a | 143 | |
98229aa3 TG |
144 | /* |
145 | * If there is still a move in progress or the previous move has not | |
146 | * been cleaned up completely, tell the caller to come back later. | |
147 | */ | |
dccfe314 | 148 | if (d->cfg.old_vector) |
74afab7a JL |
149 | return -EBUSY; |
150 | ||
74afab7a | 151 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 152 | cpumask_clear(d->old_domain); |
8a580f70 | 153 | cpumask_clear(searched_cpumask); |
74afab7a JL |
154 | cpu = cpumask_first_and(mask, cpu_online_mask); |
155 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 156 | int new_cpu, offset; |
74afab7a | 157 | |
fdba46ff | 158 | cpumask_copy(vector_cpumask, cpumask_of(cpu)); |
74afab7a | 159 | |
3716fd27 TG |
160 | /* |
161 | * Clear the offline cpus from @vector_cpumask for searching | |
162 | * and verify whether the result overlaps with @mask. If true, | |
91cd9cb7 | 163 | * then the call to apic->cpu_mask_to_apicid() will |
3716fd27 TG |
164 | * succeed as well. If not, no point in trying to find a |
165 | * vector in this mask. | |
166 | */ | |
167 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
168 | if (!cpumask_intersects(vector_searchmask, mask)) | |
169 | goto next_cpu; | |
170 | ||
f7fa7aee | 171 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 172 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 173 | goto success; |
74afab7a | 174 | /* |
ab25ac02 TG |
175 | * Mark the cpus which are not longer in the mask for |
176 | * cleanup. | |
74afab7a | 177 | */ |
ab25ac02 TG |
178 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
179 | vector = d->cfg.vector; | |
180 | goto update; | |
74afab7a JL |
181 | } |
182 | ||
183 | vector = current_vector; | |
184 | offset = current_offset; | |
185 | next: | |
186 | vector += 16; | |
05161b9c | 187 | if (vector >= FIRST_SYSTEM_VECTOR) { |
74afab7a JL |
188 | offset = (offset + 1) % 16; |
189 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
190 | } | |
191 | ||
95ffeb4b TG |
192 | /* If the search wrapped around, try the next cpu */ |
193 | if (unlikely(current_vector == vector)) | |
194 | goto next_cpu; | |
74afab7a | 195 | |
7854f822 | 196 | if (test_bit(vector, system_vectors)) |
74afab7a JL |
197 | goto next; |
198 | ||
3716fd27 | 199 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 200 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
201 | goto next; |
202 | } | |
203 | /* Found one! */ | |
204 | current_vector = vector; | |
205 | current_offset = offset; | |
ab25ac02 TG |
206 | /* Schedule the old vector for cleanup on all cpus */ |
207 | if (d->cfg.vector) | |
7f3262ed | 208 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 209 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 210 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 211 | goto update; |
95ffeb4b TG |
212 | |
213 | next_cpu: | |
214 | /* | |
215 | * We exclude the current @vector_cpumask from the requested | |
216 | * @mask and try again with the next online cpu in the | |
217 | * result. We cannot modify @mask, so we use @vector_cpumask | |
218 | * as a temporary buffer here as it will be reassigned when | |
219 | * calling apic->vector_allocation_domain() above. | |
220 | */ | |
221 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
222 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
223 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
224 | continue; | |
74afab7a | 225 | } |
433cbd57 | 226 | return -ENOSPC; |
74afab7a | 227 | |
ab25ac02 | 228 | update: |
847667ef TG |
229 | /* |
230 | * Exclude offline cpus from the cleanup mask and set the | |
231 | * move_in_progress flag when the result is not empty. | |
232 | */ | |
233 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
234 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
551adc60 | 235 | d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; |
029c6e1c | 236 | d->prev_cpu = d->cpu; |
ab25ac02 TG |
237 | d->cfg.vector = vector; |
238 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 239 | success: |
3716fd27 TG |
240 | /* |
241 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
242 | * as we already established, that mask & d->domain & cpu_online_mask | |
243 | * is not empty. | |
52b166af TG |
244 | * |
245 | * vector_searchmask is a subset of d->domain and has the offline | |
246 | * cpus masked out. | |
3716fd27 | 247 | */ |
91cd9cb7 | 248 | cpumask_and(vector_searchmask, vector_searchmask, mask); |
86ba6551 | 249 | BUG_ON(apic->cpu_mask_to_apicid(vector_searchmask, irqd, |
0e24f7c9 | 250 | &d->cfg.dest_apicid)); |
029c6e1c | 251 | d->cpu = cpumask_first(vector_searchmask); |
3716fd27 | 252 | return 0; |
74afab7a JL |
253 | } |
254 | ||
86ba6551 | 255 | static int assign_irq_vector(int irq, struct apic_chip_data *apicd, |
0e24f7c9 | 256 | const struct cpumask *mask, |
86ba6551 | 257 | struct irq_data *irqd) |
74afab7a JL |
258 | { |
259 | int err; | |
260 | unsigned long flags; | |
261 | ||
262 | raw_spin_lock_irqsave(&vector_lock, flags); | |
86ba6551 | 263 | err = __assign_irq_vector(irq, apicd, mask, irqd); |
74afab7a JL |
264 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
265 | return err; | |
266 | } | |
267 | ||
486ca539 | 268 | static int assign_irq_vector_policy(int irq, int node, |
86ba6551 | 269 | struct apic_chip_data *apicd, |
0e24f7c9 | 270 | struct irq_alloc_info *info, |
86ba6551 | 271 | struct irq_data *irqd) |
486ca539 | 272 | { |
258d86ee | 273 | if (info->mask) |
86ba6551 | 274 | return assign_irq_vector(irq, apicd, info->mask, irqd); |
486ca539 | 275 | if (node != NUMA_NO_NODE && |
86ba6551 | 276 | assign_irq_vector(irq, apicd, cpumask_of_node(node), irqd) == 0) |
486ca539 | 277 | return 0; |
86ba6551 | 278 | return assign_irq_vector(irq, apicd, cpu_online_mask, irqd); |
486ca539 JL |
279 | } |
280 | ||
86ba6551 | 281 | static void clear_irq_vector(int irq, struct apic_chip_data *apicd) |
74afab7a | 282 | { |
dccfe314 | 283 | unsigned int vector = apicd->cfg.vector; |
74afab7a | 284 | |
dccfe314 | 285 | if (!vector) |
1bdb8970 | 286 | return; |
74afab7a | 287 | |
dccfe314 | 288 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 289 | apicd->cfg.vector = 0; |
74afab7a | 290 | |
dccfe314 TG |
291 | /* Clean up move in progress */ |
292 | vector = apicd->cfg.old_vector; | |
293 | if (!vector) | |
74afab7a | 294 | return; |
74afab7a | 295 | |
dccfe314 | 296 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 297 | apicd->move_in_progress = 0; |
dccfe314 | 298 | hlist_del_init(&apicd->clist); |
74afab7a JL |
299 | } |
300 | ||
b5dc8e6c JL |
301 | static void x86_vector_free_irqs(struct irq_domain *domain, |
302 | unsigned int virq, unsigned int nr_irqs) | |
303 | { | |
86ba6551 TG |
304 | struct apic_chip_data *apicd; |
305 | struct irq_data *irqd; | |
111abeba | 306 | unsigned long flags; |
b5dc8e6c JL |
307 | int i; |
308 | ||
309 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
310 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
311 | if (irqd && irqd->chip_data) { | |
111abeba | 312 | raw_spin_lock_irqsave(&vector_lock, flags); |
86ba6551 TG |
313 | clear_irq_vector(virq + i, irqd->chip_data); |
314 | apicd = irqd->chip_data; | |
315 | irq_domain_reset_irq_data(irqd); | |
111abeba | 316 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 317 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
318 | } |
319 | } | |
320 | } | |
321 | ||
322 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
323 | unsigned int nr_irqs, void *arg) | |
324 | { | |
325 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
326 | struct apic_chip_data *apicd; |
327 | struct irq_data *irqd; | |
5f2dbbc5 | 328 | int i, err, node; |
b5dc8e6c JL |
329 | |
330 | if (disable_apic) | |
331 | return -ENXIO; | |
332 | ||
333 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
334 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
335 | return -ENOSYS; | |
336 | ||
b5dc8e6c | 337 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
338 | irqd = irq_domain_get_irq_data(domain, virq + i); |
339 | BUG_ON(!irqd); | |
340 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
341 | WARN_ON_ONCE(irqd->chip_data); |
342 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 343 | if (!apicd) { |
b5dc8e6c JL |
344 | err = -ENOMEM; |
345 | goto error; | |
346 | } | |
347 | ||
86ba6551 TG |
348 | irqd->chip = &lapic_controller; |
349 | irqd->chip_data = apicd; | |
350 | irqd->hwirq = virq + i; | |
351 | irqd_set_single_target(irqd); | |
4ef76eb6 TG |
352 | /* |
353 | * Make sure, that the legacy to IOAPIC transition stays on | |
354 | * the same vector. This is required for check_timer() to | |
355 | * work correctly as it might switch back to legacy mode. | |
356 | */ | |
357 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
358 | apicd->cfg.vector = ISA_IRQ_VECTOR(virq + i); | |
359 | apicd->cpu = 0; | |
360 | cpumask_copy(apicd->domain, cpumask_of(0)); | |
361 | } | |
362 | ||
86ba6551 TG |
363 | err = assign_irq_vector_policy(virq + i, node, apicd, info, |
364 | irqd); | |
b5dc8e6c JL |
365 | if (err) |
366 | goto error; | |
367 | } | |
368 | ||
369 | return 0; | |
370 | ||
371 | error: | |
372 | x86_vector_free_irqs(domain, virq, i + 1); | |
373 | return err; | |
374 | } | |
375 | ||
eb18cf55 TG |
376 | static const struct irq_domain_ops x86_vector_domain_ops = { |
377 | .alloc = x86_vector_alloc_irqs, | |
378 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
379 | }; |
380 | ||
11d686e9 JL |
381 | int __init arch_probe_nr_irqs(void) |
382 | { | |
383 | int nr; | |
384 | ||
385 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
386 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
387 | ||
388 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
389 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
390 | /* | |
391 | * for MSI and HT dyn irq | |
392 | */ | |
393 | if (gsi_top <= NR_IRQS_LEGACY) | |
394 | nr += 8 * nr_cpu_ids; | |
395 | else | |
396 | nr += gsi_top * 16; | |
397 | #endif | |
398 | if (nr < nr_irqs) | |
399 | nr_irqs = nr; | |
400 | ||
8c058b0b VK |
401 | /* |
402 | * We don't know if PIC is present at this point so we need to do | |
403 | * probe() to get the right number of legacy IRQs. | |
404 | */ | |
405 | return legacy_pic->probe(); | |
11d686e9 JL |
406 | } |
407 | ||
0fa115da TG |
408 | void lapic_assign_legacy_vector(unsigned int irq, bool replace) |
409 | { | |
410 | /* | |
411 | * Use assign system here so it wont get accounted as allocated | |
412 | * and moveable in the cpu hotplug check and it prevents managed | |
413 | * irq reservation from touching it. | |
414 | */ | |
415 | irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); | |
416 | } | |
417 | ||
418 | void __init lapic_assign_system_vectors(void) | |
419 | { | |
420 | unsigned int i, vector = 0; | |
421 | ||
422 | for_each_set_bit_from(vector, system_vectors, NR_VECTORS) | |
423 | irq_matrix_assign_system(vector_matrix, vector, false); | |
424 | ||
425 | if (nr_legacy_irqs() > 1) | |
426 | lapic_assign_legacy_vector(PIC_CASCADE_IR, false); | |
427 | ||
428 | /* System vectors are reserved, online it */ | |
429 | irq_matrix_online(vector_matrix); | |
430 | ||
431 | /* Mark the preallocated legacy interrupts */ | |
432 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
433 | if (i != PIC_CASCADE_IR) | |
434 | irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); | |
435 | } | |
436 | } | |
437 | ||
11d686e9 JL |
438 | int __init arch_early_irq_init(void) |
439 | { | |
9d35f859 TG |
440 | struct fwnode_handle *fn; |
441 | ||
9d35f859 TG |
442 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
443 | BUG_ON(!fn); | |
444 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
445 | NULL); | |
b5dc8e6c | 446 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 447 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
448 | irq_set_default_host(x86_vector_domain); |
449 | ||
52f518a3 | 450 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 451 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 452 | |
f7fa7aee | 453 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 454 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 455 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 456 | |
0fa115da TG |
457 | /* |
458 | * Allocate the vector matrix allocator data structure and limit the | |
459 | * search area. | |
460 | */ | |
461 | vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, | |
462 | FIRST_SYSTEM_VECTOR); | |
463 | BUG_ON(!vector_matrix); | |
464 | ||
11d686e9 JL |
465 | return arch_early_ioapic_init(); |
466 | } | |
467 | ||
f0cc6cca TG |
468 | /* Temporary hack to keep things working */ |
469 | static void vector_update_shutdown_irqs(void) | |
74afab7a | 470 | { |
a782a7e4 | 471 | struct irq_desc *desc; |
f0cc6cca | 472 | int irq; |
74afab7a | 473 | |
a782a7e4 | 474 | for_each_irq_desc(irq, desc) { |
f0cc6cca TG |
475 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
476 | struct apic_chip_data *ad = apic_chip_data(irqd); | |
74afab7a | 477 | |
dccfe314 | 478 | if (ad && ad->cfg.vector && ad->cpu == smp_processor_id()) |
f0cc6cca | 479 | this_cpu_write(vector_irq[ad->cfg.vector], desc); |
74afab7a | 480 | } |
74afab7a JL |
481 | } |
482 | ||
f0cc6cca TG |
483 | static struct irq_desc *__setup_vector_irq(int vector) |
484 | { | |
485 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
486 | ||
487 | /* Check whether the irq is in the legacy space */ | |
488 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
489 | return VECTOR_UNUSED; | |
490 | /* Check whether the irq is handled by the IOAPIC */ | |
491 | if (test_bit(isairq, &io_apic_irqs)) | |
492 | return VECTOR_UNUSED; | |
493 | return irq_to_desc(isairq); | |
494 | } | |
495 | ||
0fa115da TG |
496 | /* Online the local APIC infrastructure and initialize the vectors */ |
497 | void lapic_online(void) | |
74afab7a | 498 | { |
f0cc6cca | 499 | unsigned int vector; |
74afab7a | 500 | |
5a3f75e3 | 501 | lockdep_assert_held(&vector_lock); |
0fa115da TG |
502 | |
503 | /* Online the vector matrix array for this CPU */ | |
504 | irq_matrix_online(vector_matrix); | |
505 | ||
74afab7a | 506 | /* |
f0cc6cca TG |
507 | * The interrupt affinity logic never targets interrupts to offline |
508 | * CPUs. The exception are the legacy PIC interrupts. In general | |
509 | * they are only targeted to CPU0, but depending on the platform | |
510 | * they can be distributed to any online CPU in hardware. The | |
511 | * kernel has no influence on that. So all active legacy vectors | |
512 | * must be installed on all CPUs. All non legacy interrupts can be | |
513 | * cleared. | |
74afab7a | 514 | */ |
f0cc6cca TG |
515 | for (vector = 0; vector < NR_VECTORS; vector++) |
516 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a | 517 | |
f0cc6cca TG |
518 | /* |
519 | * Until the rewrite of the managed interrupt management is in | |
520 | * place it's necessary to walk the irq descriptors and check for | |
521 | * interrupts which are targeted at this CPU. | |
522 | */ | |
523 | vector_update_shutdown_irqs(); | |
74afab7a JL |
524 | } |
525 | ||
0fa115da TG |
526 | void lapic_offline(void) |
527 | { | |
528 | lock_vector_lock(); | |
529 | irq_matrix_offline(vector_matrix); | |
530 | unlock_vector_lock(); | |
531 | } | |
532 | ||
86ba6551 | 533 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 534 | { |
86ba6551 | 535 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 536 | unsigned long flags; |
74afab7a JL |
537 | |
538 | raw_spin_lock_irqsave(&vector_lock, flags); | |
dccfe314 | 539 | apic->send_IPI(apicd->cpu, apicd->cfg.vector); |
74afab7a JL |
540 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
541 | ||
542 | return 1; | |
543 | } | |
544 | ||
86ba6551 | 545 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 546 | { |
86ba6551 TG |
547 | irq_complete_move(irqd_cfg(irqd)); |
548 | irq_move_irq(irqd); | |
74afab7a JL |
549 | ack_APIC_irq(); |
550 | } | |
551 | ||
86ba6551 | 552 | static int apic_set_affinity(struct irq_data *irqd, |
68f9f440 | 553 | const struct cpumask *dest, bool force) |
b5dc8e6c | 554 | { |
86ba6551 TG |
555 | struct apic_chip_data *apicd = irqd->chip_data; |
556 | int err, irq = irqd->irq; | |
b5dc8e6c | 557 | |
97f2645f | 558 | if (!IS_ENABLED(CONFIG_SMP)) |
b5dc8e6c JL |
559 | return -EPERM; |
560 | ||
561 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
562 | return -EINVAL; | |
563 | ||
86ba6551 | 564 | err = assign_irq_vector(irq, apicd, dest, irqd); |
3716fd27 | 565 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
566 | } |
567 | ||
568 | static struct irq_chip lapic_controller = { | |
8947dfb2 | 569 | .name = "APIC", |
b5dc8e6c | 570 | .irq_ack = apic_ack_edge, |
68f9f440 | 571 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
572 | .irq_retrigger = apic_retrigger_irq, |
573 | }; | |
574 | ||
74afab7a | 575 | #ifdef CONFIG_SMP |
c6c2002b | 576 | |
c4158ff5 | 577 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 578 | { |
dccfe314 TG |
579 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
580 | struct apic_chip_data *apicd; | |
581 | struct hlist_node *tmp; | |
74afab7a | 582 | |
6af7faf6 | 583 | entering_ack_irq(); |
df54c493 TG |
584 | /* Prevent vectors vanishing under us */ |
585 | raw_spin_lock(&vector_lock); | |
586 | ||
dccfe314 TG |
587 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
588 | unsigned int irr, vector = apicd->cfg.old_vector; | |
74afab7a | 589 | |
74afab7a | 590 | /* |
dccfe314 TG |
591 | * Paranoia: Check if the vector that needs to be cleaned |
592 | * up is registered at the APICs IRR. If so, then this is | |
593 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 594 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
595 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
596 | * priority external vector, so on return from this | |
597 | * interrupt the device interrupt will happen first. | |
74afab7a | 598 | */ |
dccfe314 TG |
599 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
600 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 601 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 602 | continue; |
74afab7a | 603 | } |
dccfe314 | 604 | hlist_del_init(&apicd->clist); |
7276c6a2 | 605 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
dccfe314 | 606 | apicd->cfg.old_vector = 0; |
74afab7a JL |
607 | } |
608 | ||
df54c493 | 609 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 610 | exiting_irq(); |
74afab7a JL |
611 | } |
612 | ||
dccfe314 TG |
613 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
614 | { | |
615 | unsigned int cpu; | |
616 | ||
617 | raw_spin_lock(&vector_lock); | |
618 | apicd->move_in_progress = 0; | |
619 | cpu = apicd->prev_cpu; | |
620 | if (cpu_online(cpu)) { | |
621 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
622 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
623 | } else { | |
624 | apicd->cfg.old_vector = 0; | |
625 | } | |
626 | raw_spin_unlock(&vector_lock); | |
627 | } | |
628 | ||
629 | void send_cleanup_vector(struct irq_cfg *cfg) | |
630 | { | |
631 | struct apic_chip_data *apicd; | |
632 | ||
633 | apicd = container_of(cfg, struct apic_chip_data, cfg); | |
634 | if (apicd->move_in_progress) | |
635 | __send_cleanup_vector(apicd); | |
636 | } | |
637 | ||
74afab7a JL |
638 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
639 | { | |
86ba6551 | 640 | struct apic_chip_data *apicd; |
74afab7a | 641 | |
86ba6551 TG |
642 | apicd = container_of(cfg, struct apic_chip_data, cfg); |
643 | if (likely(!apicd->move_in_progress)) | |
74afab7a JL |
644 | return; |
645 | ||
dccfe314 | 646 | if (vector == apicd->cfg.vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 647 | __send_cleanup_vector(apicd); |
74afab7a JL |
648 | } |
649 | ||
650 | void irq_complete_move(struct irq_cfg *cfg) | |
651 | { | |
652 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
653 | } | |
654 | ||
90a2282e | 655 | /* |
551adc60 | 656 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
657 | */ |
658 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 659 | { |
86ba6551 | 660 | struct apic_chip_data *apicd; |
dccfe314 TG |
661 | struct irq_data *irqd; |
662 | unsigned int vector; | |
56d7d2f4 | 663 | |
db91aa79 MW |
664 | /* |
665 | * The function is called for all descriptors regardless of which | |
666 | * irqdomain they belong to. For example if an IRQ is provided by | |
667 | * an irq_chip as part of a GPIO driver, the chip data for that | |
668 | * descriptor is specific to the irq_chip in question. | |
669 | * | |
670 | * Check first that the chip_data is what we expect | |
671 | * (apic_chip_data) before touching it any further. | |
672 | */ | |
86ba6551 | 673 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 674 | irq_desc_get_irq(desc)); |
86ba6551 | 675 | if (!irqd) |
db91aa79 MW |
676 | return; |
677 | ||
dccfe314 | 678 | raw_spin_lock(&vector_lock); |
86ba6551 | 679 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
680 | if (!apicd) |
681 | goto unlock; | |
db91aa79 | 682 | |
dccfe314 TG |
683 | /* |
684 | * If old_vector is empty, no action required. | |
685 | */ | |
686 | vector = apicd->cfg.old_vector; | |
687 | if (!vector) | |
688 | goto unlock; | |
74afab7a | 689 | |
56d7d2f4 | 690 | /* |
dccfe314 | 691 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
692 | * done yet, then the following setaffinity call will fail with |
693 | * -EBUSY. This can leave the interrupt in a stale state. | |
694 | * | |
551adc60 TG |
695 | * All CPUs are stuck in stop machine with interrupts disabled so |
696 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 697 | * |
551adc60 TG |
698 | * 1) The interrupt is in move_in_progress state. That means that we |
699 | * have not seen an interrupt since the io_apic was reprogrammed to | |
700 | * the new vector. | |
701 | * | |
702 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
703 | * have not been processed yet. | |
704 | */ | |
86ba6551 | 705 | if (apicd->move_in_progress) { |
98229aa3 | 706 | /* |
551adc60 TG |
707 | * In theory there is a race: |
708 | * | |
709 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
710 | * is effective, i.e. it's raised on | |
711 | * the old vector. | |
712 | * | |
713 | * So if the target cpu cannot handle that interrupt before | |
714 | * the old vector is cleaned up, we get a spurious interrupt | |
715 | * and in the worst case the ioapic irq line becomes stale. | |
716 | * | |
717 | * But in case of cpu hotplug this should be a non issue | |
718 | * because if the affinity update happens right before all | |
719 | * cpus rendevouz in stop machine, there is no way that the | |
720 | * interrupt can be blocked on the target cpu because all cpus | |
721 | * loops first with interrupts enabled in stop machine, so the | |
722 | * old vector is not yet cleaned up when the interrupt fires. | |
723 | * | |
724 | * So the only way to run into this issue is if the delivery | |
725 | * of the interrupt on the apic/system bus would be delayed | |
726 | * beyond the point where the target cpu disables interrupts | |
727 | * in stop machine. I doubt that it can happen, but at least | |
728 | * there is a theroretical chance. Virtualization might be | |
729 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
730 | * as stupid as the real hardware. | |
731 | * | |
732 | * Anyway, there is nothing we can do about that at this point | |
733 | * w/o refactoring the whole fixup_irq() business completely. | |
734 | * We print at least the irq number and the old vector number, | |
735 | * so we have the necessary information when a problem in that | |
736 | * area arises. | |
98229aa3 | 737 | */ |
551adc60 | 738 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 739 | irqd->irq, vector); |
98229aa3 | 740 | } |
dccfe314 | 741 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
551adc60 | 742 | /* Cleanup the left overs of the (half finished) move */ |
86ba6551 | 743 | cpumask_clear(apicd->old_domain); |
dccfe314 | 744 | apicd->cfg.old_vector = 0; |
86ba6551 | 745 | apicd->move_in_progress = 0; |
dccfe314 TG |
746 | hlist_del_init(&apicd->clist); |
747 | unlock: | |
56d7d2f4 | 748 | raw_spin_unlock(&vector_lock); |
74afab7a | 749 | } |
74afab7a JL |
750 | #endif |
751 | ||
74afab7a JL |
752 | static void __init print_APIC_field(int base) |
753 | { | |
754 | int i; | |
755 | ||
756 | printk(KERN_DEBUG); | |
757 | ||
758 | for (i = 0; i < 8; i++) | |
759 | pr_cont("%08x", apic_read(base + i*0x10)); | |
760 | ||
761 | pr_cont("\n"); | |
762 | } | |
763 | ||
764 | static void __init print_local_APIC(void *dummy) | |
765 | { | |
766 | unsigned int i, v, ver, maxlvt; | |
767 | u64 icr; | |
768 | ||
849d3569 JL |
769 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
770 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 771 | v = apic_read(APIC_ID); |
849d3569 | 772 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 773 | v = apic_read(APIC_LVR); |
849d3569 | 774 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
775 | ver = GET_APIC_VERSION(v); |
776 | maxlvt = lapic_get_maxlvt(); | |
777 | ||
778 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 779 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
780 | |
781 | /* !82489DX */ | |
782 | if (APIC_INTEGRATED(ver)) { | |
783 | if (!APIC_XAPIC(ver)) { | |
784 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
785 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
786 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
787 | } |
788 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 789 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
790 | } |
791 | ||
792 | /* | |
793 | * Remote read supported only in the 82489DX and local APIC for | |
794 | * Pentium processors. | |
795 | */ | |
796 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
797 | v = apic_read(APIC_RRR); | |
849d3569 | 798 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
799 | } |
800 | ||
801 | v = apic_read(APIC_LDR); | |
849d3569 | 802 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
803 | if (!x2apic_enabled()) { |
804 | v = apic_read(APIC_DFR); | |
849d3569 | 805 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
806 | } |
807 | v = apic_read(APIC_SPIV); | |
849d3569 | 808 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 809 | |
849d3569 | 810 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 811 | print_APIC_field(APIC_ISR); |
849d3569 | 812 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 813 | print_APIC_field(APIC_TMR); |
849d3569 | 814 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
815 | print_APIC_field(APIC_IRR); |
816 | ||
817 | /* !82489DX */ | |
818 | if (APIC_INTEGRATED(ver)) { | |
819 | /* Due to the Pentium erratum 3AP. */ | |
820 | if (maxlvt > 3) | |
821 | apic_write(APIC_ESR, 0); | |
822 | ||
823 | v = apic_read(APIC_ESR); | |
849d3569 | 824 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
825 | } |
826 | ||
827 | icr = apic_icr_read(); | |
849d3569 JL |
828 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
829 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
830 | |
831 | v = apic_read(APIC_LVTT); | |
849d3569 | 832 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
833 | |
834 | if (maxlvt > 3) { | |
835 | /* PC is LVT#4. */ | |
836 | v = apic_read(APIC_LVTPC); | |
849d3569 | 837 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
838 | } |
839 | v = apic_read(APIC_LVT0); | |
849d3569 | 840 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 841 | v = apic_read(APIC_LVT1); |
849d3569 | 842 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
843 | |
844 | if (maxlvt > 2) { | |
845 | /* ERR is LVT#3. */ | |
846 | v = apic_read(APIC_LVTERR); | |
849d3569 | 847 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
848 | } |
849 | ||
850 | v = apic_read(APIC_TMICT); | |
849d3569 | 851 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 852 | v = apic_read(APIC_TMCCT); |
849d3569 | 853 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 854 | v = apic_read(APIC_TDCR); |
849d3569 | 855 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
856 | |
857 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
858 | v = apic_read(APIC_EFEAT); | |
859 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 860 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 861 | v = apic_read(APIC_ECTRL); |
849d3569 | 862 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
863 | for (i = 0; i < maxlvt; i++) { |
864 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 865 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
866 | } |
867 | } | |
868 | pr_cont("\n"); | |
869 | } | |
870 | ||
871 | static void __init print_local_APICs(int maxcpu) | |
872 | { | |
873 | int cpu; | |
874 | ||
875 | if (!maxcpu) | |
876 | return; | |
877 | ||
878 | preempt_disable(); | |
879 | for_each_online_cpu(cpu) { | |
880 | if (cpu >= maxcpu) | |
881 | break; | |
882 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
883 | } | |
884 | preempt_enable(); | |
885 | } | |
886 | ||
887 | static void __init print_PIC(void) | |
888 | { | |
889 | unsigned int v; | |
890 | unsigned long flags; | |
891 | ||
892 | if (!nr_legacy_irqs()) | |
893 | return; | |
894 | ||
849d3569 | 895 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
896 | |
897 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
898 | ||
899 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 900 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
901 | |
902 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 903 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
904 | |
905 | outb(0x0b, 0xa0); | |
906 | outb(0x0b, 0x20); | |
907 | v = inb(0xa0) << 8 | inb(0x20); | |
908 | outb(0x0a, 0xa0); | |
909 | outb(0x0a, 0x20); | |
910 | ||
911 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
912 | ||
849d3569 | 913 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
914 | |
915 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 916 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
917 | } |
918 | ||
919 | static int show_lapic __initdata = 1; | |
920 | static __init int setup_show_lapic(char *arg) | |
921 | { | |
922 | int num = -1; | |
923 | ||
924 | if (strcmp(arg, "all") == 0) { | |
925 | show_lapic = CONFIG_NR_CPUS; | |
926 | } else { | |
927 | get_option(&arg, &num); | |
928 | if (num >= 0) | |
929 | show_lapic = num; | |
930 | } | |
931 | ||
932 | return 1; | |
933 | } | |
934 | __setup("show_lapic=", setup_show_lapic); | |
935 | ||
936 | static int __init print_ICs(void) | |
937 | { | |
938 | if (apic_verbosity == APIC_QUIET) | |
939 | return 0; | |
940 | ||
941 | print_PIC(); | |
942 | ||
943 | /* don't print out if apic is not there */ | |
93984fbd | 944 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
945 | return 0; |
946 | ||
947 | print_local_APICs(show_lapic); | |
948 | print_IO_APICs(); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | late_initcall(print_ICs); |