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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
74afab7a | 32 | static DEFINE_RAW_SPINLOCK(vector_lock); |
f7fa7aee | 33 | static cpumask_var_t vector_cpumask; |
b5dc8e6c | 34 | static struct irq_chip lapic_controller; |
13315320 | 35 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 36 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 37 | #endif |
74afab7a JL |
38 | |
39 | void lock_vector_lock(void) | |
40 | { | |
41 | /* Used to the online set of cpus does not change | |
42 | * during assign_irq_vector. | |
43 | */ | |
44 | raw_spin_lock(&vector_lock); | |
45 | } | |
46 | ||
47 | void unlock_vector_lock(void) | |
48 | { | |
49 | raw_spin_unlock(&vector_lock); | |
50 | } | |
51 | ||
7f3262ed | 52 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 53 | { |
b5dc8e6c JL |
54 | if (!irq_data) |
55 | return NULL; | |
56 | ||
57 | while (irq_data->parent_data) | |
58 | irq_data = irq_data->parent_data; | |
59 | ||
74afab7a JL |
60 | return irq_data->chip_data; |
61 | } | |
62 | ||
7f3262ed JL |
63 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
64 | { | |
65 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
66 | ||
67 | return data ? &data->cfg : NULL; | |
68 | } | |
69 | ||
70 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 71 | { |
7f3262ed JL |
72 | return irqd_cfg(irq_get_irq_data(irq)); |
73 | } | |
74afab7a | 74 | |
7f3262ed JL |
75 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
76 | { | |
77 | struct apic_chip_data *data; | |
78 | ||
79 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
80 | if (!data) | |
74afab7a | 81 | return NULL; |
7f3262ed JL |
82 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
83 | goto out_data; | |
84 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 85 | goto out_domain; |
7f3262ed | 86 | return data; |
74afab7a | 87 | out_domain: |
7f3262ed JL |
88 | free_cpumask_var(data->domain); |
89 | out_data: | |
90 | kfree(data); | |
74afab7a JL |
91 | return NULL; |
92 | } | |
93 | ||
7f3262ed | 94 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 95 | { |
7f3262ed JL |
96 | if (data) { |
97 | free_cpumask_var(data->domain); | |
98 | free_cpumask_var(data->old_domain); | |
99 | kfree(data); | |
b5dc8e6c | 100 | } |
74afab7a JL |
101 | } |
102 | ||
7f3262ed JL |
103 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
104 | const struct cpumask *mask) | |
74afab7a JL |
105 | { |
106 | /* | |
107 | * NOTE! The local APIC isn't very good at handling | |
108 | * multiple interrupts at the same interrupt level. | |
109 | * As the interrupt level is determined by taking the | |
110 | * vector number and shifting that right by 4, we | |
111 | * want to spread these out a bit so that they don't | |
112 | * all fall in the same interrupt level. | |
113 | * | |
114 | * Also, we've got to be careful not to trash gate | |
115 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
116 | */ | |
117 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
118 | static int current_offset = VECTOR_OFFSET_START % 16; | |
119 | int cpu, err; | |
74afab7a | 120 | |
7f3262ed | 121 | if (d->move_in_progress) |
74afab7a JL |
122 | return -EBUSY; |
123 | ||
74afab7a JL |
124 | /* Only try and allocate irqs on cpus that are present */ |
125 | err = -ENOSPC; | |
7f3262ed | 126 | cpumask_clear(d->old_domain); |
74afab7a JL |
127 | cpu = cpumask_first_and(mask, cpu_online_mask); |
128 | while (cpu < nr_cpu_ids) { | |
129 | int new_cpu, vector, offset; | |
130 | ||
f7fa7aee | 131 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 132 | |
f7fa7aee | 133 | if (cpumask_subset(vector_cpumask, d->domain)) { |
74afab7a | 134 | err = 0; |
f7fa7aee | 135 | if (cpumask_equal(vector_cpumask, d->domain)) |
74afab7a JL |
136 | break; |
137 | /* | |
138 | * New cpumask using the vector is a proper subset of | |
139 | * the current in use mask. So cleanup the vector | |
140 | * allocation for the members that are not used anymore. | |
141 | */ | |
f7fa7aee JL |
142 | cpumask_andnot(d->old_domain, d->domain, |
143 | vector_cpumask); | |
7f3262ed JL |
144 | d->move_in_progress = |
145 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
f7fa7aee | 146 | cpumask_and(d->domain, d->domain, vector_cpumask); |
74afab7a JL |
147 | break; |
148 | } | |
149 | ||
150 | vector = current_vector; | |
151 | offset = current_offset; | |
152 | next: | |
153 | vector += 16; | |
154 | if (vector >= first_system_vector) { | |
155 | offset = (offset + 1) % 16; | |
156 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
157 | } | |
158 | ||
159 | if (unlikely(current_vector == vector)) { | |
f7fa7aee JL |
160 | cpumask_or(d->old_domain, d->old_domain, |
161 | vector_cpumask); | |
162 | cpumask_andnot(vector_cpumask, mask, d->old_domain); | |
163 | cpu = cpumask_first_and(vector_cpumask, | |
164 | cpu_online_mask); | |
74afab7a JL |
165 | continue; |
166 | } | |
167 | ||
168 | if (test_bit(vector, used_vectors)) | |
169 | goto next; | |
170 | ||
f7fa7aee | 171 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { |
a782a7e4 | 172 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
173 | goto next; |
174 | } | |
175 | /* Found one! */ | |
176 | current_vector = vector; | |
177 | current_offset = offset; | |
7f3262ed JL |
178 | if (d->cfg.vector) { |
179 | cpumask_copy(d->old_domain, d->domain); | |
180 | d->move_in_progress = | |
181 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
74afab7a | 182 | } |
f7fa7aee | 183 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) |
a782a7e4 | 184 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
7f3262ed | 185 | d->cfg.vector = vector; |
f7fa7aee | 186 | cpumask_copy(d->domain, vector_cpumask); |
74afab7a JL |
187 | err = 0; |
188 | break; | |
189 | } | |
74afab7a | 190 | |
5f0052f9 JL |
191 | if (!err) { |
192 | /* cache destination APIC IDs into cfg->dest_apicid */ | |
7f3262ed JL |
193 | err = apic->cpu_mask_to_apicid_and(mask, d->domain, |
194 | &d->cfg.dest_apicid); | |
5f0052f9 JL |
195 | } |
196 | ||
74afab7a JL |
197 | return err; |
198 | } | |
199 | ||
7f3262ed | 200 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 201 | const struct cpumask *mask) |
74afab7a JL |
202 | { |
203 | int err; | |
204 | unsigned long flags; | |
205 | ||
206 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 207 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
208 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
209 | return err; | |
210 | } | |
211 | ||
486ca539 JL |
212 | static int assign_irq_vector_policy(int irq, int node, |
213 | struct apic_chip_data *data, | |
214 | struct irq_alloc_info *info) | |
215 | { | |
216 | if (info && info->mask) | |
217 | return assign_irq_vector(irq, data, info->mask); | |
218 | if (node != NUMA_NO_NODE && | |
219 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
220 | return 0; | |
221 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
222 | } | |
223 | ||
7f3262ed | 224 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a | 225 | { |
a782a7e4 | 226 | struct irq_desc *desc; |
74afab7a | 227 | unsigned long flags; |
a782a7e4 | 228 | int cpu, vector; |
74afab7a JL |
229 | |
230 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 231 | BUG_ON(!data->cfg.vector); |
74afab7a | 232 | |
7f3262ed JL |
233 | vector = data->cfg.vector; |
234 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 235 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 236 | |
7f3262ed JL |
237 | data->cfg.vector = 0; |
238 | cpumask_clear(data->domain); | |
74afab7a | 239 | |
7f3262ed | 240 | if (likely(!data->move_in_progress)) { |
74afab7a JL |
241 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
242 | return; | |
243 | } | |
244 | ||
a782a7e4 | 245 | desc = irq_to_desc(irq); |
7f3262ed | 246 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
247 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
248 | vector++) { | |
a782a7e4 | 249 | if (per_cpu(vector_irq, cpu)[vector] != desc) |
74afab7a | 250 | continue; |
7276c6a2 | 251 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
252 | break; |
253 | } | |
254 | } | |
7f3262ed | 255 | data->move_in_progress = 0; |
74afab7a JL |
256 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
257 | } | |
258 | ||
b5dc8e6c JL |
259 | void init_irq_alloc_info(struct irq_alloc_info *info, |
260 | const struct cpumask *mask) | |
261 | { | |
262 | memset(info, 0, sizeof(*info)); | |
263 | info->mask = mask; | |
264 | } | |
265 | ||
266 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
267 | { | |
268 | if (src) | |
269 | *dst = *src; | |
270 | else | |
271 | memset(dst, 0, sizeof(*dst)); | |
272 | } | |
273 | ||
b5dc8e6c JL |
274 | static void x86_vector_free_irqs(struct irq_domain *domain, |
275 | unsigned int virq, unsigned int nr_irqs) | |
276 | { | |
277 | struct irq_data *irq_data; | |
278 | int i; | |
279 | ||
280 | for (i = 0; i < nr_irqs; i++) { | |
281 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
282 | if (irq_data && irq_data->chip_data) { | |
b5dc8e6c | 283 | clear_irq_vector(virq + i, irq_data->chip_data); |
7f3262ed | 284 | free_apic_chip_data(irq_data->chip_data); |
13315320 JL |
285 | #ifdef CONFIG_X86_IO_APIC |
286 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 287 | legacy_irq_data[virq + i] = NULL; |
13315320 | 288 | #endif |
b5dc8e6c JL |
289 | irq_domain_reset_irq_data(irq_data); |
290 | } | |
291 | } | |
292 | } | |
293 | ||
294 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
295 | unsigned int nr_irqs, void *arg) | |
296 | { | |
297 | struct irq_alloc_info *info = arg; | |
7f3262ed | 298 | struct apic_chip_data *data; |
b5dc8e6c | 299 | struct irq_data *irq_data; |
5f2dbbc5 | 300 | int i, err, node; |
b5dc8e6c JL |
301 | |
302 | if (disable_apic) | |
303 | return -ENXIO; | |
304 | ||
305 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
306 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
307 | return -ENOSYS; | |
308 | ||
b5dc8e6c JL |
309 | for (i = 0; i < nr_irqs; i++) { |
310 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
311 | BUG_ON(!irq_data); | |
5f2dbbc5 | 312 | node = irq_data_get_node(irq_data); |
13315320 | 313 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
314 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
315 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
316 | else |
317 | #endif | |
5f2dbbc5 | 318 | data = alloc_apic_chip_data(node); |
7f3262ed | 319 | if (!data) { |
b5dc8e6c JL |
320 | err = -ENOMEM; |
321 | goto error; | |
322 | } | |
323 | ||
324 | irq_data->chip = &lapic_controller; | |
7f3262ed | 325 | irq_data->chip_data = data; |
b5dc8e6c | 326 | irq_data->hwirq = virq + i; |
43af9872 | 327 | err = assign_irq_vector_policy(virq + i, node, data, info); |
b5dc8e6c JL |
328 | if (err) |
329 | goto error; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | ||
334 | error: | |
335 | x86_vector_free_irqs(domain, virq, i + 1); | |
336 | return err; | |
337 | } | |
338 | ||
eb18cf55 TG |
339 | static const struct irq_domain_ops x86_vector_domain_ops = { |
340 | .alloc = x86_vector_alloc_irqs, | |
341 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
342 | }; |
343 | ||
11d686e9 JL |
344 | int __init arch_probe_nr_irqs(void) |
345 | { | |
346 | int nr; | |
347 | ||
348 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
349 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
350 | ||
351 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
352 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
353 | /* | |
354 | * for MSI and HT dyn irq | |
355 | */ | |
356 | if (gsi_top <= NR_IRQS_LEGACY) | |
357 | nr += 8 * nr_cpu_ids; | |
358 | else | |
359 | nr += gsi_top * 16; | |
360 | #endif | |
361 | if (nr < nr_irqs) | |
362 | nr_irqs = nr; | |
363 | ||
364 | return nr_legacy_irqs(); | |
365 | } | |
366 | ||
13315320 JL |
367 | #ifdef CONFIG_X86_IO_APIC |
368 | static void init_legacy_irqs(void) | |
369 | { | |
370 | int i, node = cpu_to_node(0); | |
7f3262ed | 371 | struct apic_chip_data *data; |
13315320 JL |
372 | |
373 | /* | |
374 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 375 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
376 | */ |
377 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
378 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
379 | BUG_ON(!data); | |
191a6635 IM |
380 | |
381 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
382 | cpumask_setall(data->domain); |
383 | irq_set_chip_data(i, data); | |
13315320 JL |
384 | } |
385 | } | |
386 | #else | |
387 | static void init_legacy_irqs(void) { } | |
388 | #endif | |
389 | ||
11d686e9 JL |
390 | int __init arch_early_irq_init(void) |
391 | { | |
13315320 JL |
392 | init_legacy_irqs(); |
393 | ||
b5dc8e6c JL |
394 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
395 | NULL); | |
396 | BUG_ON(x86_vector_domain == NULL); | |
397 | irq_set_default_host(x86_vector_domain); | |
398 | ||
52f518a3 | 399 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 400 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 401 | |
f7fa7aee JL |
402 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
403 | ||
11d686e9 JL |
404 | return arch_early_ioapic_init(); |
405 | } | |
406 | ||
a782a7e4 | 407 | /* Initialize vector_irq on a new cpu */ |
74afab7a JL |
408 | static void __setup_vector_irq(int cpu) |
409 | { | |
7f3262ed | 410 | struct apic_chip_data *data; |
a782a7e4 TG |
411 | struct irq_desc *desc; |
412 | int irq, vector; | |
74afab7a | 413 | |
74afab7a | 414 | /* Mark the inuse vectors */ |
a782a7e4 TG |
415 | for_each_irq_desc(irq, desc) { |
416 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
74afab7a | 417 | |
a782a7e4 TG |
418 | data = apic_chip_data(idata); |
419 | if (!data || !cpumask_test_cpu(cpu, data->domain)) | |
74afab7a | 420 | continue; |
7f3262ed | 421 | vector = data->cfg.vector; |
a782a7e4 | 422 | per_cpu(vector_irq, cpu)[vector] = desc; |
74afab7a JL |
423 | } |
424 | /* Mark the free vectors */ | |
425 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
a782a7e4 TG |
426 | desc = per_cpu(vector_irq, cpu)[vector]; |
427 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
428 | continue; |
429 | ||
a782a7e4 | 430 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 431 | if (!cpumask_test_cpu(cpu, data->domain)) |
7276c6a2 | 432 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 433 | } |
74afab7a JL |
434 | } |
435 | ||
436 | /* | |
5a3f75e3 | 437 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
438 | */ |
439 | void setup_vector_irq(int cpu) | |
440 | { | |
441 | int irq; | |
442 | ||
5a3f75e3 | 443 | lockdep_assert_held(&vector_lock); |
74afab7a JL |
444 | /* |
445 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
446 | * boot cpu. But there are certain platforms where PIC interrupts are | |
447 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
448 | * legacy PIC, for the new cpu that is coming online, setup the static | |
449 | * legacy vector to irq mapping: | |
450 | */ | |
451 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
a782a7e4 | 452 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); |
74afab7a JL |
453 | |
454 | __setup_vector_irq(cpu); | |
455 | } | |
456 | ||
7f3262ed | 457 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 458 | { |
7f3262ed | 459 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
460 | unsigned long flags; |
461 | int cpu; | |
462 | ||
463 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
464 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
465 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
466 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
467 | ||
468 | return 1; | |
469 | } | |
470 | ||
471 | void apic_ack_edge(struct irq_data *data) | |
472 | { | |
a9786091 | 473 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
474 | irq_move_irq(data); |
475 | ack_APIC_irq(); | |
476 | } | |
477 | ||
68f9f440 JL |
478 | static int apic_set_affinity(struct irq_data *irq_data, |
479 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 480 | { |
7f3262ed | 481 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
482 | int err, irq = irq_data->irq; |
483 | ||
484 | if (!config_enabled(CONFIG_SMP)) | |
485 | return -EPERM; | |
486 | ||
487 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
488 | return -EINVAL; | |
489 | ||
7f3262ed | 490 | err = assign_irq_vector(irq, data, dest); |
b5dc8e6c | 491 | if (err) { |
c149e4cd | 492 | if (assign_irq_vector(irq, data, |
9df872fa | 493 | irq_data_get_affinity_mask(irq_data))) |
b5dc8e6c JL |
494 | pr_err("Failed to recover vector for irq %d\n", irq); |
495 | return err; | |
496 | } | |
497 | ||
498 | return IRQ_SET_MASK_OK; | |
499 | } | |
500 | ||
501 | static struct irq_chip lapic_controller = { | |
502 | .irq_ack = apic_ack_edge, | |
68f9f440 | 503 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
504 | .irq_retrigger = apic_retrigger_irq, |
505 | }; | |
506 | ||
74afab7a | 507 | #ifdef CONFIG_SMP |
7f3262ed | 508 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a JL |
509 | { |
510 | cpumask_var_t cleanup_mask; | |
511 | ||
512 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
513 | unsigned int i; | |
514 | ||
7f3262ed | 515 | for_each_cpu_and(i, data->old_domain, cpu_online_mask) |
74afab7a JL |
516 | apic->send_IPI_mask(cpumask_of(i), |
517 | IRQ_MOVE_CLEANUP_VECTOR); | |
518 | } else { | |
7f3262ed | 519 | cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); |
74afab7a JL |
520 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
521 | free_cpumask_var(cleanup_mask); | |
522 | } | |
7f3262ed | 523 | data->move_in_progress = 0; |
74afab7a JL |
524 | } |
525 | ||
c6c2002b JL |
526 | void send_cleanup_vector(struct irq_cfg *cfg) |
527 | { | |
7f3262ed JL |
528 | struct apic_chip_data *data; |
529 | ||
530 | data = container_of(cfg, struct apic_chip_data, cfg); | |
531 | if (data->move_in_progress) | |
532 | __send_cleanup_vector(data); | |
c6c2002b JL |
533 | } |
534 | ||
74afab7a JL |
535 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
536 | { | |
537 | unsigned vector, me; | |
538 | ||
6af7faf6 | 539 | entering_ack_irq(); |
74afab7a | 540 | |
df54c493 TG |
541 | /* Prevent vectors vanishing under us */ |
542 | raw_spin_lock(&vector_lock); | |
543 | ||
74afab7a JL |
544 | me = smp_processor_id(); |
545 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
7f3262ed | 546 | struct apic_chip_data *data; |
a782a7e4 TG |
547 | struct irq_desc *desc; |
548 | unsigned int irr; | |
74afab7a | 549 | |
df54c493 | 550 | retry: |
a782a7e4 TG |
551 | desc = __this_cpu_read(vector_irq[vector]); |
552 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
553 | continue; |
554 | ||
df54c493 TG |
555 | if (!raw_spin_trylock(&desc->lock)) { |
556 | raw_spin_unlock(&vector_lock); | |
557 | cpu_relax(); | |
558 | raw_spin_lock(&vector_lock); | |
559 | goto retry; | |
560 | } | |
74afab7a | 561 | |
a782a7e4 | 562 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 563 | if (!data) |
df54c493 | 564 | goto unlock; |
74afab7a JL |
565 | |
566 | /* | |
567 | * Check if the irq migration is in progress. If so, we | |
568 | * haven't received the cleanup request yet for this irq. | |
569 | */ | |
7f3262ed | 570 | if (data->move_in_progress) |
74afab7a JL |
571 | goto unlock; |
572 | ||
7f3262ed JL |
573 | if (vector == data->cfg.vector && |
574 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
575 | goto unlock; |
576 | ||
577 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
578 | /* | |
579 | * Check if the vector that needs to be cleanedup is | |
580 | * registered at the cpu's IRR. If so, then this is not | |
581 | * the best time to clean it up. Lets clean it up in the | |
582 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
583 | * to myself. | |
584 | */ | |
585 | if (irr & (1 << (vector % 32))) { | |
586 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
587 | goto unlock; | |
588 | } | |
7276c6a2 | 589 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
74afab7a JL |
590 | unlock: |
591 | raw_spin_unlock(&desc->lock); | |
592 | } | |
593 | ||
df54c493 TG |
594 | raw_spin_unlock(&vector_lock); |
595 | ||
6af7faf6 | 596 | exiting_irq(); |
74afab7a JL |
597 | } |
598 | ||
599 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
600 | { | |
601 | unsigned me; | |
7f3262ed | 602 | struct apic_chip_data *data; |
74afab7a | 603 | |
7f3262ed JL |
604 | data = container_of(cfg, struct apic_chip_data, cfg); |
605 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
606 | return; |
607 | ||
608 | me = smp_processor_id(); | |
7f3262ed JL |
609 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
610 | __send_cleanup_vector(data); | |
74afab7a JL |
611 | } |
612 | ||
613 | void irq_complete_move(struct irq_cfg *cfg) | |
614 | { | |
615 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
616 | } | |
617 | ||
618 | void irq_force_complete_move(int irq) | |
619 | { | |
620 | struct irq_cfg *cfg = irq_cfg(irq); | |
621 | ||
7f3262ed JL |
622 | if (cfg) |
623 | __irq_complete_move(cfg, cfg->vector); | |
74afab7a | 624 | } |
74afab7a JL |
625 | #endif |
626 | ||
74afab7a JL |
627 | static void __init print_APIC_field(int base) |
628 | { | |
629 | int i; | |
630 | ||
631 | printk(KERN_DEBUG); | |
632 | ||
633 | for (i = 0; i < 8; i++) | |
634 | pr_cont("%08x", apic_read(base + i*0x10)); | |
635 | ||
636 | pr_cont("\n"); | |
637 | } | |
638 | ||
639 | static void __init print_local_APIC(void *dummy) | |
640 | { | |
641 | unsigned int i, v, ver, maxlvt; | |
642 | u64 icr; | |
643 | ||
849d3569 JL |
644 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
645 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 646 | v = apic_read(APIC_ID); |
849d3569 | 647 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 648 | v = apic_read(APIC_LVR); |
849d3569 | 649 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
650 | ver = GET_APIC_VERSION(v); |
651 | maxlvt = lapic_get_maxlvt(); | |
652 | ||
653 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 654 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
655 | |
656 | /* !82489DX */ | |
657 | if (APIC_INTEGRATED(ver)) { | |
658 | if (!APIC_XAPIC(ver)) { | |
659 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
660 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
661 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
662 | } |
663 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 664 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
665 | } |
666 | ||
667 | /* | |
668 | * Remote read supported only in the 82489DX and local APIC for | |
669 | * Pentium processors. | |
670 | */ | |
671 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
672 | v = apic_read(APIC_RRR); | |
849d3569 | 673 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
674 | } |
675 | ||
676 | v = apic_read(APIC_LDR); | |
849d3569 | 677 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
678 | if (!x2apic_enabled()) { |
679 | v = apic_read(APIC_DFR); | |
849d3569 | 680 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
681 | } |
682 | v = apic_read(APIC_SPIV); | |
849d3569 | 683 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 684 | |
849d3569 | 685 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 686 | print_APIC_field(APIC_ISR); |
849d3569 | 687 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 688 | print_APIC_field(APIC_TMR); |
849d3569 | 689 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
690 | print_APIC_field(APIC_IRR); |
691 | ||
692 | /* !82489DX */ | |
693 | if (APIC_INTEGRATED(ver)) { | |
694 | /* Due to the Pentium erratum 3AP. */ | |
695 | if (maxlvt > 3) | |
696 | apic_write(APIC_ESR, 0); | |
697 | ||
698 | v = apic_read(APIC_ESR); | |
849d3569 | 699 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
700 | } |
701 | ||
702 | icr = apic_icr_read(); | |
849d3569 JL |
703 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
704 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
705 | |
706 | v = apic_read(APIC_LVTT); | |
849d3569 | 707 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
708 | |
709 | if (maxlvt > 3) { | |
710 | /* PC is LVT#4. */ | |
711 | v = apic_read(APIC_LVTPC); | |
849d3569 | 712 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
713 | } |
714 | v = apic_read(APIC_LVT0); | |
849d3569 | 715 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 716 | v = apic_read(APIC_LVT1); |
849d3569 | 717 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
718 | |
719 | if (maxlvt > 2) { | |
720 | /* ERR is LVT#3. */ | |
721 | v = apic_read(APIC_LVTERR); | |
849d3569 | 722 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
723 | } |
724 | ||
725 | v = apic_read(APIC_TMICT); | |
849d3569 | 726 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 727 | v = apic_read(APIC_TMCCT); |
849d3569 | 728 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 729 | v = apic_read(APIC_TDCR); |
849d3569 | 730 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
731 | |
732 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
733 | v = apic_read(APIC_EFEAT); | |
734 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 735 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 736 | v = apic_read(APIC_ECTRL); |
849d3569 | 737 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
738 | for (i = 0; i < maxlvt; i++) { |
739 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 740 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
741 | } |
742 | } | |
743 | pr_cont("\n"); | |
744 | } | |
745 | ||
746 | static void __init print_local_APICs(int maxcpu) | |
747 | { | |
748 | int cpu; | |
749 | ||
750 | if (!maxcpu) | |
751 | return; | |
752 | ||
753 | preempt_disable(); | |
754 | for_each_online_cpu(cpu) { | |
755 | if (cpu >= maxcpu) | |
756 | break; | |
757 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
758 | } | |
759 | preempt_enable(); | |
760 | } | |
761 | ||
762 | static void __init print_PIC(void) | |
763 | { | |
764 | unsigned int v; | |
765 | unsigned long flags; | |
766 | ||
767 | if (!nr_legacy_irqs()) | |
768 | return; | |
769 | ||
849d3569 | 770 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
771 | |
772 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
773 | ||
774 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 775 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
776 | |
777 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 778 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
779 | |
780 | outb(0x0b, 0xa0); | |
781 | outb(0x0b, 0x20); | |
782 | v = inb(0xa0) << 8 | inb(0x20); | |
783 | outb(0x0a, 0xa0); | |
784 | outb(0x0a, 0x20); | |
785 | ||
786 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
787 | ||
849d3569 | 788 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
789 | |
790 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 791 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
792 | } |
793 | ||
794 | static int show_lapic __initdata = 1; | |
795 | static __init int setup_show_lapic(char *arg) | |
796 | { | |
797 | int num = -1; | |
798 | ||
799 | if (strcmp(arg, "all") == 0) { | |
800 | show_lapic = CONFIG_NR_CPUS; | |
801 | } else { | |
802 | get_option(&arg, &num); | |
803 | if (num >= 0) | |
804 | show_lapic = num; | |
805 | } | |
806 | ||
807 | return 1; | |
808 | } | |
809 | __setup("show_lapic=", setup_show_lapic); | |
810 | ||
811 | static int __init print_ICs(void) | |
812 | { | |
813 | if (apic_verbosity == APIC_QUIET) | |
814 | return 0; | |
815 | ||
816 | print_PIC(); | |
817 | ||
818 | /* don't print out if apic is not there */ | |
819 | if (!cpu_has_apic && !apic_from_smp_config()) | |
820 | return 0; | |
821 | ||
822 | print_local_APICs(show_lapic); | |
823 | print_IO_APICs(); | |
824 | ||
825 | return 0; | |
826 | } | |
827 | ||
828 | late_initcall(print_ICs); |