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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
029c6e1c TG |
26 | unsigned int cpu; |
27 | unsigned int prev_cpu; | |
dccfe314 | 28 | struct hlist_node clist; |
7f3262ed JL |
29 | cpumask_var_t domain; |
30 | cpumask_var_t old_domain; | |
31 | u8 move_in_progress : 1; | |
32 | }; | |
33 | ||
b5dc8e6c | 34 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 35 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 36 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 37 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 38 | static struct irq_chip lapic_controller; |
13315320 | 39 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 40 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 41 | #endif |
dccfe314 TG |
42 | #ifdef CONFIG_SMP |
43 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
44 | #endif | |
74afab7a JL |
45 | |
46 | void lock_vector_lock(void) | |
47 | { | |
48 | /* Used to the online set of cpus does not change | |
49 | * during assign_irq_vector. | |
50 | */ | |
51 | raw_spin_lock(&vector_lock); | |
52 | } | |
53 | ||
54 | void unlock_vector_lock(void) | |
55 | { | |
56 | raw_spin_unlock(&vector_lock); | |
57 | } | |
58 | ||
86ba6551 | 59 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 60 | { |
86ba6551 | 61 | if (!irqd) |
b5dc8e6c JL |
62 | return NULL; |
63 | ||
86ba6551 TG |
64 | while (irqd->parent_data) |
65 | irqd = irqd->parent_data; | |
b5dc8e6c | 66 | |
86ba6551 | 67 | return irqd->chip_data; |
74afab7a JL |
68 | } |
69 | ||
86ba6551 | 70 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 71 | { |
86ba6551 | 72 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 73 | |
86ba6551 | 74 | return apicd ? &apicd->cfg : NULL; |
7f3262ed | 75 | } |
c8f3e518 | 76 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
77 | |
78 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 79 | { |
7f3262ed JL |
80 | return irqd_cfg(irq_get_irq_data(irq)); |
81 | } | |
74afab7a | 82 | |
7f3262ed JL |
83 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
84 | { | |
86ba6551 | 85 | struct apic_chip_data *apicd; |
7f3262ed | 86 | |
86ba6551 TG |
87 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
88 | if (!apicd) | |
74afab7a | 89 | return NULL; |
86ba6551 | 90 | if (!zalloc_cpumask_var_node(&apicd->domain, GFP_KERNEL, node)) |
7f3262ed | 91 | goto out_data; |
86ba6551 | 92 | if (!zalloc_cpumask_var_node(&apicd->old_domain, GFP_KERNEL, node)) |
74afab7a | 93 | goto out_domain; |
dccfe314 | 94 | INIT_HLIST_NODE(&apicd->clist); |
86ba6551 | 95 | return apicd; |
74afab7a | 96 | out_domain: |
86ba6551 | 97 | free_cpumask_var(apicd->domain); |
7f3262ed | 98 | out_data: |
86ba6551 | 99 | kfree(apicd); |
74afab7a JL |
100 | return NULL; |
101 | } | |
102 | ||
86ba6551 | 103 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 104 | { |
86ba6551 TG |
105 | if (apicd) { |
106 | free_cpumask_var(apicd->domain); | |
107 | free_cpumask_var(apicd->old_domain); | |
108 | kfree(apicd); | |
b5dc8e6c | 109 | } |
74afab7a JL |
110 | } |
111 | ||
7f3262ed | 112 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
0e24f7c9 | 113 | const struct cpumask *mask, |
86ba6551 | 114 | struct irq_data *irqd) |
74afab7a JL |
115 | { |
116 | /* | |
117 | * NOTE! The local APIC isn't very good at handling | |
118 | * multiple interrupts at the same interrupt level. | |
119 | * As the interrupt level is determined by taking the | |
120 | * vector number and shifting that right by 4, we | |
121 | * want to spread these out a bit so that they don't | |
122 | * all fall in the same interrupt level. | |
123 | * | |
124 | * Also, we've got to be careful not to trash gate | |
125 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
126 | */ | |
127 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
128 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 129 | int cpu, vector; |
74afab7a | 130 | |
98229aa3 TG |
131 | /* |
132 | * If there is still a move in progress or the previous move has not | |
133 | * been cleaned up completely, tell the caller to come back later. | |
134 | */ | |
dccfe314 | 135 | if (d->cfg.old_vector) |
74afab7a JL |
136 | return -EBUSY; |
137 | ||
74afab7a | 138 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 139 | cpumask_clear(d->old_domain); |
8a580f70 | 140 | cpumask_clear(searched_cpumask); |
74afab7a JL |
141 | cpu = cpumask_first_and(mask, cpu_online_mask); |
142 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 143 | int new_cpu, offset; |
74afab7a | 144 | |
fdba46ff | 145 | cpumask_copy(vector_cpumask, cpumask_of(cpu)); |
74afab7a | 146 | |
3716fd27 TG |
147 | /* |
148 | * Clear the offline cpus from @vector_cpumask for searching | |
149 | * and verify whether the result overlaps with @mask. If true, | |
91cd9cb7 | 150 | * then the call to apic->cpu_mask_to_apicid() will |
3716fd27 TG |
151 | * succeed as well. If not, no point in trying to find a |
152 | * vector in this mask. | |
153 | */ | |
154 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
155 | if (!cpumask_intersects(vector_searchmask, mask)) | |
156 | goto next_cpu; | |
157 | ||
f7fa7aee | 158 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 159 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 160 | goto success; |
74afab7a | 161 | /* |
ab25ac02 TG |
162 | * Mark the cpus which are not longer in the mask for |
163 | * cleanup. | |
74afab7a | 164 | */ |
ab25ac02 TG |
165 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
166 | vector = d->cfg.vector; | |
167 | goto update; | |
74afab7a JL |
168 | } |
169 | ||
170 | vector = current_vector; | |
171 | offset = current_offset; | |
172 | next: | |
173 | vector += 16; | |
05161b9c | 174 | if (vector >= FIRST_SYSTEM_VECTOR) { |
74afab7a JL |
175 | offset = (offset + 1) % 16; |
176 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
177 | } | |
178 | ||
95ffeb4b TG |
179 | /* If the search wrapped around, try the next cpu */ |
180 | if (unlikely(current_vector == vector)) | |
181 | goto next_cpu; | |
74afab7a | 182 | |
7854f822 | 183 | if (test_bit(vector, system_vectors)) |
74afab7a JL |
184 | goto next; |
185 | ||
3716fd27 | 186 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 187 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
188 | goto next; |
189 | } | |
190 | /* Found one! */ | |
191 | current_vector = vector; | |
192 | current_offset = offset; | |
ab25ac02 TG |
193 | /* Schedule the old vector for cleanup on all cpus */ |
194 | if (d->cfg.vector) | |
7f3262ed | 195 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 196 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 197 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 198 | goto update; |
95ffeb4b TG |
199 | |
200 | next_cpu: | |
201 | /* | |
202 | * We exclude the current @vector_cpumask from the requested | |
203 | * @mask and try again with the next online cpu in the | |
204 | * result. We cannot modify @mask, so we use @vector_cpumask | |
205 | * as a temporary buffer here as it will be reassigned when | |
206 | * calling apic->vector_allocation_domain() above. | |
207 | */ | |
208 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
209 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
210 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
211 | continue; | |
74afab7a | 212 | } |
433cbd57 | 213 | return -ENOSPC; |
74afab7a | 214 | |
ab25ac02 | 215 | update: |
847667ef TG |
216 | /* |
217 | * Exclude offline cpus from the cleanup mask and set the | |
218 | * move_in_progress flag when the result is not empty. | |
219 | */ | |
220 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
221 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
551adc60 | 222 | d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; |
029c6e1c | 223 | d->prev_cpu = d->cpu; |
ab25ac02 TG |
224 | d->cfg.vector = vector; |
225 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 226 | success: |
3716fd27 TG |
227 | /* |
228 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
229 | * as we already established, that mask & d->domain & cpu_online_mask | |
230 | * is not empty. | |
52b166af TG |
231 | * |
232 | * vector_searchmask is a subset of d->domain and has the offline | |
233 | * cpus masked out. | |
3716fd27 | 234 | */ |
91cd9cb7 | 235 | cpumask_and(vector_searchmask, vector_searchmask, mask); |
86ba6551 | 236 | BUG_ON(apic->cpu_mask_to_apicid(vector_searchmask, irqd, |
0e24f7c9 | 237 | &d->cfg.dest_apicid)); |
029c6e1c | 238 | d->cpu = cpumask_first(vector_searchmask); |
3716fd27 | 239 | return 0; |
74afab7a JL |
240 | } |
241 | ||
86ba6551 | 242 | static int assign_irq_vector(int irq, struct apic_chip_data *apicd, |
0e24f7c9 | 243 | const struct cpumask *mask, |
86ba6551 | 244 | struct irq_data *irqd) |
74afab7a JL |
245 | { |
246 | int err; | |
247 | unsigned long flags; | |
248 | ||
249 | raw_spin_lock_irqsave(&vector_lock, flags); | |
86ba6551 | 250 | err = __assign_irq_vector(irq, apicd, mask, irqd); |
74afab7a JL |
251 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
252 | return err; | |
253 | } | |
254 | ||
486ca539 | 255 | static int assign_irq_vector_policy(int irq, int node, |
86ba6551 | 256 | struct apic_chip_data *apicd, |
0e24f7c9 | 257 | struct irq_alloc_info *info, |
86ba6551 | 258 | struct irq_data *irqd) |
486ca539 JL |
259 | { |
260 | if (info && info->mask) | |
86ba6551 | 261 | return assign_irq_vector(irq, apicd, info->mask, irqd); |
486ca539 | 262 | if (node != NUMA_NO_NODE && |
86ba6551 | 263 | assign_irq_vector(irq, apicd, cpumask_of_node(node), irqd) == 0) |
486ca539 | 264 | return 0; |
86ba6551 | 265 | return assign_irq_vector(irq, apicd, cpu_online_mask, irqd); |
486ca539 JL |
266 | } |
267 | ||
86ba6551 | 268 | static void clear_irq_vector(int irq, struct apic_chip_data *apicd) |
74afab7a | 269 | { |
dccfe314 | 270 | unsigned int vector = apicd->cfg.vector; |
74afab7a | 271 | |
dccfe314 | 272 | if (!vector) |
1bdb8970 | 273 | return; |
74afab7a | 274 | |
dccfe314 | 275 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 276 | apicd->cfg.vector = 0; |
74afab7a | 277 | |
dccfe314 TG |
278 | /* Clean up move in progress */ |
279 | vector = apicd->cfg.old_vector; | |
280 | if (!vector) | |
74afab7a | 281 | return; |
74afab7a | 282 | |
dccfe314 | 283 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 284 | apicd->move_in_progress = 0; |
dccfe314 | 285 | hlist_del_init(&apicd->clist); |
74afab7a JL |
286 | } |
287 | ||
b5dc8e6c JL |
288 | void init_irq_alloc_info(struct irq_alloc_info *info, |
289 | const struct cpumask *mask) | |
290 | { | |
291 | memset(info, 0, sizeof(*info)); | |
292 | info->mask = mask; | |
293 | } | |
294 | ||
295 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
296 | { | |
297 | if (src) | |
298 | *dst = *src; | |
299 | else | |
300 | memset(dst, 0, sizeof(*dst)); | |
301 | } | |
302 | ||
b5dc8e6c JL |
303 | static void x86_vector_free_irqs(struct irq_domain *domain, |
304 | unsigned int virq, unsigned int nr_irqs) | |
305 | { | |
86ba6551 TG |
306 | struct apic_chip_data *apicd; |
307 | struct irq_data *irqd; | |
111abeba | 308 | unsigned long flags; |
b5dc8e6c JL |
309 | int i; |
310 | ||
311 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
312 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
313 | if (irqd && irqd->chip_data) { | |
111abeba | 314 | raw_spin_lock_irqsave(&vector_lock, flags); |
86ba6551 TG |
315 | clear_irq_vector(virq + i, irqd->chip_data); |
316 | apicd = irqd->chip_data; | |
317 | irq_domain_reset_irq_data(irqd); | |
111abeba | 318 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 319 | free_apic_chip_data(apicd); |
13315320 JL |
320 | #ifdef CONFIG_X86_IO_APIC |
321 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 322 | legacy_irq_data[virq + i] = NULL; |
13315320 | 323 | #endif |
b5dc8e6c JL |
324 | } |
325 | } | |
326 | } | |
327 | ||
328 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
329 | unsigned int nr_irqs, void *arg) | |
330 | { | |
331 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
332 | struct apic_chip_data *apicd; |
333 | struct irq_data *irqd; | |
5f2dbbc5 | 334 | int i, err, node; |
b5dc8e6c JL |
335 | |
336 | if (disable_apic) | |
337 | return -ENXIO; | |
338 | ||
339 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
340 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
341 | return -ENOSYS; | |
342 | ||
b5dc8e6c | 343 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
344 | irqd = irq_domain_get_irq_data(domain, virq + i); |
345 | BUG_ON(!irqd); | |
346 | node = irq_data_get_node(irqd); | |
13315320 | 347 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 348 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
86ba6551 | 349 | apicd = legacy_irq_data[virq + i]; |
13315320 JL |
350 | else |
351 | #endif | |
86ba6551 TG |
352 | apicd = alloc_apic_chip_data(node); |
353 | if (!apicd) { | |
b5dc8e6c JL |
354 | err = -ENOMEM; |
355 | goto error; | |
356 | } | |
357 | ||
86ba6551 TG |
358 | irqd->chip = &lapic_controller; |
359 | irqd->chip_data = apicd; | |
360 | irqd->hwirq = virq + i; | |
361 | irqd_set_single_target(irqd); | |
362 | err = assign_irq_vector_policy(virq + i, node, apicd, info, | |
363 | irqd); | |
b5dc8e6c JL |
364 | if (err) |
365 | goto error; | |
366 | } | |
367 | ||
368 | return 0; | |
369 | ||
370 | error: | |
371 | x86_vector_free_irqs(domain, virq, i + 1); | |
372 | return err; | |
373 | } | |
374 | ||
eb18cf55 TG |
375 | static const struct irq_domain_ops x86_vector_domain_ops = { |
376 | .alloc = x86_vector_alloc_irqs, | |
377 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
378 | }; |
379 | ||
11d686e9 JL |
380 | int __init arch_probe_nr_irqs(void) |
381 | { | |
382 | int nr; | |
383 | ||
384 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
385 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
386 | ||
387 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
388 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
389 | /* | |
390 | * for MSI and HT dyn irq | |
391 | */ | |
392 | if (gsi_top <= NR_IRQS_LEGACY) | |
393 | nr += 8 * nr_cpu_ids; | |
394 | else | |
395 | nr += gsi_top * 16; | |
396 | #endif | |
397 | if (nr < nr_irqs) | |
398 | nr_irqs = nr; | |
399 | ||
8c058b0b VK |
400 | /* |
401 | * We don't know if PIC is present at this point so we need to do | |
402 | * probe() to get the right number of legacy IRQs. | |
403 | */ | |
404 | return legacy_pic->probe(); | |
11d686e9 JL |
405 | } |
406 | ||
13315320 | 407 | #ifdef CONFIG_X86_IO_APIC |
a884d25f | 408 | static void __init init_legacy_irqs(void) |
13315320 JL |
409 | { |
410 | int i, node = cpu_to_node(0); | |
86ba6551 | 411 | struct apic_chip_data *apicd; |
13315320 JL |
412 | |
413 | /* | |
414 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 415 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
416 | */ |
417 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
86ba6551 TG |
418 | apicd = legacy_irq_data[i] = alloc_apic_chip_data(node); |
419 | BUG_ON(!apicd); | |
191a6635 | 420 | |
86ba6551 TG |
421 | apicd->cfg.vector = ISA_IRQ_VECTOR(i); |
422 | cpumask_copy(apicd->domain, cpumask_of(0)); | |
029c6e1c | 423 | apicd->cpu = 0; |
86ba6551 | 424 | irq_set_chip_data(i, apicd); |
13315320 JL |
425 | } |
426 | } | |
427 | #else | |
a884d25f | 428 | static inline void init_legacy_irqs(void) { } |
13315320 JL |
429 | #endif |
430 | ||
11d686e9 JL |
431 | int __init arch_early_irq_init(void) |
432 | { | |
9d35f859 TG |
433 | struct fwnode_handle *fn; |
434 | ||
13315320 JL |
435 | init_legacy_irqs(); |
436 | ||
9d35f859 TG |
437 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
438 | BUG_ON(!fn); | |
439 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
440 | NULL); | |
b5dc8e6c | 441 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 442 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
443 | irq_set_default_host(x86_vector_domain); |
444 | ||
52f518a3 | 445 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 446 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 447 | |
f7fa7aee | 448 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 449 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 450 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 451 | |
11d686e9 JL |
452 | return arch_early_ioapic_init(); |
453 | } | |
454 | ||
f0cc6cca TG |
455 | /* Temporary hack to keep things working */ |
456 | static void vector_update_shutdown_irqs(void) | |
74afab7a | 457 | { |
a782a7e4 | 458 | struct irq_desc *desc; |
f0cc6cca | 459 | int irq; |
74afab7a | 460 | |
a782a7e4 | 461 | for_each_irq_desc(irq, desc) { |
f0cc6cca TG |
462 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
463 | struct apic_chip_data *ad = apic_chip_data(irqd); | |
74afab7a | 464 | |
dccfe314 | 465 | if (ad && ad->cfg.vector && ad->cpu == smp_processor_id()) |
f0cc6cca | 466 | this_cpu_write(vector_irq[ad->cfg.vector], desc); |
74afab7a | 467 | } |
74afab7a JL |
468 | } |
469 | ||
f0cc6cca TG |
470 | static struct irq_desc *__setup_vector_irq(int vector) |
471 | { | |
472 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
473 | ||
474 | /* Check whether the irq is in the legacy space */ | |
475 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
476 | return VECTOR_UNUSED; | |
477 | /* Check whether the irq is handled by the IOAPIC */ | |
478 | if (test_bit(isairq, &io_apic_irqs)) | |
479 | return VECTOR_UNUSED; | |
480 | return irq_to_desc(isairq); | |
481 | } | |
482 | ||
74afab7a | 483 | /* |
5a3f75e3 | 484 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
485 | */ |
486 | void setup_vector_irq(int cpu) | |
487 | { | |
f0cc6cca | 488 | unsigned int vector; |
74afab7a | 489 | |
5a3f75e3 | 490 | lockdep_assert_held(&vector_lock); |
74afab7a | 491 | /* |
f0cc6cca TG |
492 | * The interrupt affinity logic never targets interrupts to offline |
493 | * CPUs. The exception are the legacy PIC interrupts. In general | |
494 | * they are only targeted to CPU0, but depending on the platform | |
495 | * they can be distributed to any online CPU in hardware. The | |
496 | * kernel has no influence on that. So all active legacy vectors | |
497 | * must be installed on all CPUs. All non legacy interrupts can be | |
498 | * cleared. | |
74afab7a | 499 | */ |
f0cc6cca TG |
500 | for (vector = 0; vector < NR_VECTORS; vector++) |
501 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a | 502 | |
f0cc6cca TG |
503 | /* |
504 | * Until the rewrite of the managed interrupt management is in | |
505 | * place it's necessary to walk the irq descriptors and check for | |
506 | * interrupts which are targeted at this CPU. | |
507 | */ | |
508 | vector_update_shutdown_irqs(); | |
74afab7a JL |
509 | } |
510 | ||
86ba6551 | 511 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 512 | { |
86ba6551 | 513 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 514 | unsigned long flags; |
74afab7a JL |
515 | |
516 | raw_spin_lock_irqsave(&vector_lock, flags); | |
dccfe314 | 517 | apic->send_IPI(apicd->cpu, apicd->cfg.vector); |
74afab7a JL |
518 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
519 | ||
520 | return 1; | |
521 | } | |
522 | ||
86ba6551 | 523 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 524 | { |
86ba6551 TG |
525 | irq_complete_move(irqd_cfg(irqd)); |
526 | irq_move_irq(irqd); | |
74afab7a JL |
527 | ack_APIC_irq(); |
528 | } | |
529 | ||
86ba6551 | 530 | static int apic_set_affinity(struct irq_data *irqd, |
68f9f440 | 531 | const struct cpumask *dest, bool force) |
b5dc8e6c | 532 | { |
86ba6551 TG |
533 | struct apic_chip_data *apicd = irqd->chip_data; |
534 | int err, irq = irqd->irq; | |
b5dc8e6c | 535 | |
97f2645f | 536 | if (!IS_ENABLED(CONFIG_SMP)) |
b5dc8e6c JL |
537 | return -EPERM; |
538 | ||
539 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
540 | return -EINVAL; | |
541 | ||
86ba6551 | 542 | err = assign_irq_vector(irq, apicd, dest, irqd); |
3716fd27 | 543 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
544 | } |
545 | ||
546 | static struct irq_chip lapic_controller = { | |
8947dfb2 | 547 | .name = "APIC", |
b5dc8e6c | 548 | .irq_ack = apic_ack_edge, |
68f9f440 | 549 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
550 | .irq_retrigger = apic_retrigger_irq, |
551 | }; | |
552 | ||
74afab7a | 553 | #ifdef CONFIG_SMP |
c6c2002b | 554 | |
c4158ff5 | 555 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 556 | { |
dccfe314 TG |
557 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
558 | struct apic_chip_data *apicd; | |
559 | struct hlist_node *tmp; | |
74afab7a | 560 | |
6af7faf6 | 561 | entering_ack_irq(); |
df54c493 TG |
562 | /* Prevent vectors vanishing under us */ |
563 | raw_spin_lock(&vector_lock); | |
564 | ||
dccfe314 TG |
565 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
566 | unsigned int irr, vector = apicd->cfg.old_vector; | |
74afab7a | 567 | |
74afab7a | 568 | /* |
dccfe314 TG |
569 | * Paranoia: Check if the vector that needs to be cleaned |
570 | * up is registered at the APICs IRR. If so, then this is | |
571 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 572 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
573 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
574 | * priority external vector, so on return from this | |
575 | * interrupt the device interrupt will happen first. | |
74afab7a | 576 | */ |
dccfe314 TG |
577 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
578 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 579 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 580 | continue; |
74afab7a | 581 | } |
dccfe314 | 582 | hlist_del_init(&apicd->clist); |
7276c6a2 | 583 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
dccfe314 | 584 | apicd->cfg.old_vector = 0; |
74afab7a JL |
585 | } |
586 | ||
df54c493 | 587 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 588 | exiting_irq(); |
74afab7a JL |
589 | } |
590 | ||
dccfe314 TG |
591 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
592 | { | |
593 | unsigned int cpu; | |
594 | ||
595 | raw_spin_lock(&vector_lock); | |
596 | apicd->move_in_progress = 0; | |
597 | cpu = apicd->prev_cpu; | |
598 | if (cpu_online(cpu)) { | |
599 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
600 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
601 | } else { | |
602 | apicd->cfg.old_vector = 0; | |
603 | } | |
604 | raw_spin_unlock(&vector_lock); | |
605 | } | |
606 | ||
607 | void send_cleanup_vector(struct irq_cfg *cfg) | |
608 | { | |
609 | struct apic_chip_data *apicd; | |
610 | ||
611 | apicd = container_of(cfg, struct apic_chip_data, cfg); | |
612 | if (apicd->move_in_progress) | |
613 | __send_cleanup_vector(apicd); | |
614 | } | |
615 | ||
74afab7a JL |
616 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
617 | { | |
86ba6551 | 618 | struct apic_chip_data *apicd; |
74afab7a | 619 | |
86ba6551 TG |
620 | apicd = container_of(cfg, struct apic_chip_data, cfg); |
621 | if (likely(!apicd->move_in_progress)) | |
74afab7a JL |
622 | return; |
623 | ||
dccfe314 | 624 | if (vector == apicd->cfg.vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 625 | __send_cleanup_vector(apicd); |
74afab7a JL |
626 | } |
627 | ||
628 | void irq_complete_move(struct irq_cfg *cfg) | |
629 | { | |
630 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
631 | } | |
632 | ||
90a2282e | 633 | /* |
551adc60 | 634 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
635 | */ |
636 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 637 | { |
86ba6551 | 638 | struct apic_chip_data *apicd; |
dccfe314 TG |
639 | struct irq_data *irqd; |
640 | unsigned int vector; | |
56d7d2f4 | 641 | |
db91aa79 MW |
642 | /* |
643 | * The function is called for all descriptors regardless of which | |
644 | * irqdomain they belong to. For example if an IRQ is provided by | |
645 | * an irq_chip as part of a GPIO driver, the chip data for that | |
646 | * descriptor is specific to the irq_chip in question. | |
647 | * | |
648 | * Check first that the chip_data is what we expect | |
649 | * (apic_chip_data) before touching it any further. | |
650 | */ | |
86ba6551 | 651 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 652 | irq_desc_get_irq(desc)); |
86ba6551 | 653 | if (!irqd) |
db91aa79 MW |
654 | return; |
655 | ||
dccfe314 | 656 | raw_spin_lock(&vector_lock); |
86ba6551 | 657 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
658 | if (!apicd) |
659 | goto unlock; | |
db91aa79 | 660 | |
dccfe314 TG |
661 | /* |
662 | * If old_vector is empty, no action required. | |
663 | */ | |
664 | vector = apicd->cfg.old_vector; | |
665 | if (!vector) | |
666 | goto unlock; | |
74afab7a | 667 | |
56d7d2f4 | 668 | /* |
dccfe314 | 669 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
670 | * done yet, then the following setaffinity call will fail with |
671 | * -EBUSY. This can leave the interrupt in a stale state. | |
672 | * | |
551adc60 TG |
673 | * All CPUs are stuck in stop machine with interrupts disabled so |
674 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 675 | * |
551adc60 TG |
676 | * 1) The interrupt is in move_in_progress state. That means that we |
677 | * have not seen an interrupt since the io_apic was reprogrammed to | |
678 | * the new vector. | |
679 | * | |
680 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
681 | * have not been processed yet. | |
682 | */ | |
86ba6551 | 683 | if (apicd->move_in_progress) { |
98229aa3 | 684 | /* |
551adc60 TG |
685 | * In theory there is a race: |
686 | * | |
687 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
688 | * is effective, i.e. it's raised on | |
689 | * the old vector. | |
690 | * | |
691 | * So if the target cpu cannot handle that interrupt before | |
692 | * the old vector is cleaned up, we get a spurious interrupt | |
693 | * and in the worst case the ioapic irq line becomes stale. | |
694 | * | |
695 | * But in case of cpu hotplug this should be a non issue | |
696 | * because if the affinity update happens right before all | |
697 | * cpus rendevouz in stop machine, there is no way that the | |
698 | * interrupt can be blocked on the target cpu because all cpus | |
699 | * loops first with interrupts enabled in stop machine, so the | |
700 | * old vector is not yet cleaned up when the interrupt fires. | |
701 | * | |
702 | * So the only way to run into this issue is if the delivery | |
703 | * of the interrupt on the apic/system bus would be delayed | |
704 | * beyond the point where the target cpu disables interrupts | |
705 | * in stop machine. I doubt that it can happen, but at least | |
706 | * there is a theroretical chance. Virtualization might be | |
707 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
708 | * as stupid as the real hardware. | |
709 | * | |
710 | * Anyway, there is nothing we can do about that at this point | |
711 | * w/o refactoring the whole fixup_irq() business completely. | |
712 | * We print at least the irq number and the old vector number, | |
713 | * so we have the necessary information when a problem in that | |
714 | * area arises. | |
98229aa3 | 715 | */ |
551adc60 | 716 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 717 | irqd->irq, vector); |
98229aa3 | 718 | } |
dccfe314 | 719 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
551adc60 | 720 | /* Cleanup the left overs of the (half finished) move */ |
86ba6551 | 721 | cpumask_clear(apicd->old_domain); |
dccfe314 | 722 | apicd->cfg.old_vector = 0; |
86ba6551 | 723 | apicd->move_in_progress = 0; |
dccfe314 TG |
724 | hlist_del_init(&apicd->clist); |
725 | unlock: | |
56d7d2f4 | 726 | raw_spin_unlock(&vector_lock); |
74afab7a | 727 | } |
74afab7a JL |
728 | #endif |
729 | ||
74afab7a JL |
730 | static void __init print_APIC_field(int base) |
731 | { | |
732 | int i; | |
733 | ||
734 | printk(KERN_DEBUG); | |
735 | ||
736 | for (i = 0; i < 8; i++) | |
737 | pr_cont("%08x", apic_read(base + i*0x10)); | |
738 | ||
739 | pr_cont("\n"); | |
740 | } | |
741 | ||
742 | static void __init print_local_APIC(void *dummy) | |
743 | { | |
744 | unsigned int i, v, ver, maxlvt; | |
745 | u64 icr; | |
746 | ||
849d3569 JL |
747 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
748 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 749 | v = apic_read(APIC_ID); |
849d3569 | 750 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 751 | v = apic_read(APIC_LVR); |
849d3569 | 752 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
753 | ver = GET_APIC_VERSION(v); |
754 | maxlvt = lapic_get_maxlvt(); | |
755 | ||
756 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 757 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
758 | |
759 | /* !82489DX */ | |
760 | if (APIC_INTEGRATED(ver)) { | |
761 | if (!APIC_XAPIC(ver)) { | |
762 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
763 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
764 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
765 | } |
766 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 767 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
768 | } |
769 | ||
770 | /* | |
771 | * Remote read supported only in the 82489DX and local APIC for | |
772 | * Pentium processors. | |
773 | */ | |
774 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
775 | v = apic_read(APIC_RRR); | |
849d3569 | 776 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
777 | } |
778 | ||
779 | v = apic_read(APIC_LDR); | |
849d3569 | 780 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
781 | if (!x2apic_enabled()) { |
782 | v = apic_read(APIC_DFR); | |
849d3569 | 783 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
784 | } |
785 | v = apic_read(APIC_SPIV); | |
849d3569 | 786 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 787 | |
849d3569 | 788 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 789 | print_APIC_field(APIC_ISR); |
849d3569 | 790 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 791 | print_APIC_field(APIC_TMR); |
849d3569 | 792 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
793 | print_APIC_field(APIC_IRR); |
794 | ||
795 | /* !82489DX */ | |
796 | if (APIC_INTEGRATED(ver)) { | |
797 | /* Due to the Pentium erratum 3AP. */ | |
798 | if (maxlvt > 3) | |
799 | apic_write(APIC_ESR, 0); | |
800 | ||
801 | v = apic_read(APIC_ESR); | |
849d3569 | 802 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
803 | } |
804 | ||
805 | icr = apic_icr_read(); | |
849d3569 JL |
806 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
807 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
808 | |
809 | v = apic_read(APIC_LVTT); | |
849d3569 | 810 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
811 | |
812 | if (maxlvt > 3) { | |
813 | /* PC is LVT#4. */ | |
814 | v = apic_read(APIC_LVTPC); | |
849d3569 | 815 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
816 | } |
817 | v = apic_read(APIC_LVT0); | |
849d3569 | 818 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 819 | v = apic_read(APIC_LVT1); |
849d3569 | 820 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
821 | |
822 | if (maxlvt > 2) { | |
823 | /* ERR is LVT#3. */ | |
824 | v = apic_read(APIC_LVTERR); | |
849d3569 | 825 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
826 | } |
827 | ||
828 | v = apic_read(APIC_TMICT); | |
849d3569 | 829 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 830 | v = apic_read(APIC_TMCCT); |
849d3569 | 831 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 832 | v = apic_read(APIC_TDCR); |
849d3569 | 833 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
834 | |
835 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
836 | v = apic_read(APIC_EFEAT); | |
837 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 838 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 839 | v = apic_read(APIC_ECTRL); |
849d3569 | 840 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
841 | for (i = 0; i < maxlvt; i++) { |
842 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 843 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
844 | } |
845 | } | |
846 | pr_cont("\n"); | |
847 | } | |
848 | ||
849 | static void __init print_local_APICs(int maxcpu) | |
850 | { | |
851 | int cpu; | |
852 | ||
853 | if (!maxcpu) | |
854 | return; | |
855 | ||
856 | preempt_disable(); | |
857 | for_each_online_cpu(cpu) { | |
858 | if (cpu >= maxcpu) | |
859 | break; | |
860 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
861 | } | |
862 | preempt_enable(); | |
863 | } | |
864 | ||
865 | static void __init print_PIC(void) | |
866 | { | |
867 | unsigned int v; | |
868 | unsigned long flags; | |
869 | ||
870 | if (!nr_legacy_irqs()) | |
871 | return; | |
872 | ||
849d3569 | 873 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
874 | |
875 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
876 | ||
877 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 878 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
879 | |
880 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 881 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
882 | |
883 | outb(0x0b, 0xa0); | |
884 | outb(0x0b, 0x20); | |
885 | v = inb(0xa0) << 8 | inb(0x20); | |
886 | outb(0x0a, 0xa0); | |
887 | outb(0x0a, 0x20); | |
888 | ||
889 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
890 | ||
849d3569 | 891 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
892 | |
893 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 894 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
895 | } |
896 | ||
897 | static int show_lapic __initdata = 1; | |
898 | static __init int setup_show_lapic(char *arg) | |
899 | { | |
900 | int num = -1; | |
901 | ||
902 | if (strcmp(arg, "all") == 0) { | |
903 | show_lapic = CONFIG_NR_CPUS; | |
904 | } else { | |
905 | get_option(&arg, &num); | |
906 | if (num >= 0) | |
907 | show_lapic = num; | |
908 | } | |
909 | ||
910 | return 1; | |
911 | } | |
912 | __setup("show_lapic=", setup_show_lapic); | |
913 | ||
914 | static int __init print_ICs(void) | |
915 | { | |
916 | if (apic_verbosity == APIC_QUIET) | |
917 | return 0; | |
918 | ||
919 | print_PIC(); | |
920 | ||
921 | /* don't print out if apic is not there */ | |
93984fbd | 922 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
923 | return 0; |
924 | ||
925 | print_local_APICs(show_lapic); | |
926 | print_IO_APICs(); | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
931 | late_initcall(print_ICs); |