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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
65d7ed57 | 14 | #include <linux/seq_file.h> |
74afab7a JL |
15 | #include <linux/init.h> |
16 | #include <linux/compiler.h> | |
74afab7a | 17 | #include <linux/slab.h> |
d746d1eb | 18 | #include <asm/irqdomain.h> |
74afab7a JL |
19 | #include <asm/hw_irq.h> |
20 | #include <asm/apic.h> | |
21 | #include <asm/i8259.h> | |
22 | #include <asm/desc.h> | |
23 | #include <asm/irq_remapping.h> | |
24 | ||
8d1e3dca TG |
25 | #include <asm/trace/irq_vectors.h> |
26 | ||
7f3262ed | 27 | struct apic_chip_data { |
ba224fea TG |
28 | struct irq_cfg hw_irq_cfg; |
29 | unsigned int vector; | |
30 | unsigned int prev_vector; | |
029c6e1c TG |
31 | unsigned int cpu; |
32 | unsigned int prev_cpu; | |
69cde000 | 33 | unsigned int irq; |
dccfe314 | 34 | struct hlist_node clist; |
2db1f959 | 35 | unsigned int move_in_progress : 1, |
4900be83 TG |
36 | is_managed : 1, |
37 | can_reserve : 1, | |
38 | has_reserved : 1; | |
7f3262ed JL |
39 | }; |
40 | ||
b5dc8e6c | 41 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 42 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 43 | static DEFINE_RAW_SPINLOCK(vector_lock); |
69cde000 | 44 | static cpumask_var_t vector_searchmask; |
b5dc8e6c | 45 | static struct irq_chip lapic_controller; |
0fa115da | 46 | static struct irq_matrix *vector_matrix; |
dccfe314 TG |
47 | #ifdef CONFIG_SMP |
48 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
49 | #endif | |
74afab7a JL |
50 | |
51 | void lock_vector_lock(void) | |
52 | { | |
53 | /* Used to the online set of cpus does not change | |
54 | * during assign_irq_vector. | |
55 | */ | |
56 | raw_spin_lock(&vector_lock); | |
57 | } | |
58 | ||
59 | void unlock_vector_lock(void) | |
60 | { | |
61 | raw_spin_unlock(&vector_lock); | |
62 | } | |
63 | ||
99a1482d TG |
64 | void init_irq_alloc_info(struct irq_alloc_info *info, |
65 | const struct cpumask *mask) | |
66 | { | |
67 | memset(info, 0, sizeof(*info)); | |
68 | info->mask = mask; | |
69 | } | |
70 | ||
71 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
72 | { | |
73 | if (src) | |
74 | *dst = *src; | |
75 | else | |
76 | memset(dst, 0, sizeof(*dst)); | |
77 | } | |
78 | ||
86ba6551 | 79 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 80 | { |
86ba6551 | 81 | if (!irqd) |
b5dc8e6c JL |
82 | return NULL; |
83 | ||
86ba6551 TG |
84 | while (irqd->parent_data) |
85 | irqd = irqd->parent_data; | |
b5dc8e6c | 86 | |
86ba6551 | 87 | return irqd->chip_data; |
74afab7a JL |
88 | } |
89 | ||
86ba6551 | 90 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 91 | { |
86ba6551 | 92 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 93 | |
ba224fea | 94 | return apicd ? &apicd->hw_irq_cfg : NULL; |
7f3262ed | 95 | } |
c8f3e518 | 96 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
97 | |
98 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 99 | { |
7f3262ed JL |
100 | return irqd_cfg(irq_get_irq_data(irq)); |
101 | } | |
74afab7a | 102 | |
7f3262ed JL |
103 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
104 | { | |
86ba6551 | 105 | struct apic_chip_data *apicd; |
7f3262ed | 106 | |
86ba6551 | 107 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
69cde000 TG |
108 | if (apicd) |
109 | INIT_HLIST_NODE(&apicd->clist); | |
86ba6551 | 110 | return apicd; |
74afab7a JL |
111 | } |
112 | ||
86ba6551 | 113 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 114 | { |
69cde000 | 115 | kfree(apicd); |
74afab7a JL |
116 | } |
117 | ||
ba224fea TG |
118 | static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector, |
119 | unsigned int cpu) | |
74afab7a | 120 | { |
69cde000 | 121 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 122 | |
69cde000 | 123 | lockdep_assert_held(&vector_lock); |
74afab7a | 124 | |
ba224fea TG |
125 | apicd->hw_irq_cfg.vector = vector; |
126 | apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); | |
127 | irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); | |
128 | trace_vector_config(irqd->irq, vector, cpu, | |
129 | apicd->hw_irq_cfg.dest_apicid); | |
69cde000 | 130 | } |
74afab7a | 131 | |
69cde000 TG |
132 | static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, |
133 | unsigned int newcpu) | |
134 | { | |
135 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
136 | struct irq_desc *desc = irq_data_to_desc(irqd); | |
74afab7a | 137 | |
69cde000 | 138 | lockdep_assert_held(&vector_lock); |
74afab7a | 139 | |
ba224fea | 140 | trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector, |
69cde000 | 141 | apicd->cpu); |
74afab7a | 142 | |
69cde000 | 143 | /* Setup the vector move, if required */ |
ba224fea | 144 | if (apicd->vector && cpu_online(apicd->cpu)) { |
69cde000 | 145 | apicd->move_in_progress = true; |
ba224fea | 146 | apicd->prev_vector = apicd->vector; |
69cde000 TG |
147 | apicd->prev_cpu = apicd->cpu; |
148 | } else { | |
ba224fea | 149 | apicd->prev_vector = 0; |
69cde000 | 150 | } |
74afab7a | 151 | |
ba224fea | 152 | apicd->vector = newvec; |
69cde000 TG |
153 | apicd->cpu = newcpu; |
154 | BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec])); | |
155 | per_cpu(vector_irq, newcpu)[newvec] = desc; | |
156 | } | |
74afab7a | 157 | |
2db1f959 TG |
158 | static void vector_assign_managed_shutdown(struct irq_data *irqd) |
159 | { | |
160 | unsigned int cpu = cpumask_first(cpu_online_mask); | |
161 | ||
162 | apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu); | |
163 | } | |
164 | ||
165 | static int reserve_managed_vector(struct irq_data *irqd) | |
166 | { | |
167 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
168 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
169 | unsigned long flags; | |
170 | int ret; | |
171 | ||
172 | raw_spin_lock_irqsave(&vector_lock, flags); | |
173 | apicd->is_managed = true; | |
174 | ret = irq_matrix_reserve_managed(vector_matrix, affmsk); | |
175 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
176 | trace_vector_reserve_managed(irqd->irq, ret); | |
177 | return ret; | |
178 | } | |
179 | ||
4900be83 TG |
180 | static void reserve_irq_vector_locked(struct irq_data *irqd) |
181 | { | |
182 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
183 | ||
184 | irq_matrix_reserve(vector_matrix); | |
185 | apicd->can_reserve = true; | |
186 | apicd->has_reserved = true; | |
187 | trace_vector_reserve(irqd->irq, 0); | |
188 | vector_assign_managed_shutdown(irqd); | |
189 | } | |
190 | ||
191 | static int reserve_irq_vector(struct irq_data *irqd) | |
192 | { | |
193 | unsigned long flags; | |
194 | ||
195 | raw_spin_lock_irqsave(&vector_lock, flags); | |
196 | reserve_irq_vector_locked(irqd); | |
197 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
198 | return 0; | |
199 | } | |
200 | ||
69cde000 TG |
201 | static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest) |
202 | { | |
203 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
4900be83 | 204 | bool resvd = apicd->has_reserved; |
69cde000 | 205 | unsigned int cpu = apicd->cpu; |
ba224fea TG |
206 | int vector = apicd->vector; |
207 | ||
208 | lockdep_assert_held(&vector_lock); | |
74afab7a | 209 | |
3716fd27 | 210 | /* |
69cde000 TG |
211 | * If the current target CPU is online and in the new requested |
212 | * affinity mask, there is no point in moving the interrupt from | |
213 | * one CPU to another. | |
3716fd27 | 214 | */ |
69cde000 TG |
215 | if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest)) |
216 | return 0; | |
217 | ||
4900be83 | 218 | vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu); |
69cde000 TG |
219 | if (vector > 0) |
220 | apic_update_vector(irqd, vector, cpu); | |
4900be83 | 221 | trace_vector_alloc(irqd->irq, vector, resvd, vector); |
69cde000 TG |
222 | return vector; |
223 | } | |
224 | ||
225 | static int assign_vector_locked(struct irq_data *irqd, | |
226 | const struct cpumask *dest) | |
227 | { | |
ba224fea | 228 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
69cde000 TG |
229 | int vector = allocate_vector(irqd, dest); |
230 | ||
231 | if (vector < 0) | |
232 | return vector; | |
233 | ||
ba224fea | 234 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); |
3716fd27 | 235 | return 0; |
74afab7a JL |
236 | } |
237 | ||
69cde000 | 238 | static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest) |
74afab7a | 239 | { |
74afab7a | 240 | unsigned long flags; |
69cde000 | 241 | int ret; |
74afab7a JL |
242 | |
243 | raw_spin_lock_irqsave(&vector_lock, flags); | |
69cde000 TG |
244 | cpumask_and(vector_searchmask, dest, cpu_online_mask); |
245 | ret = assign_vector_locked(irqd, vector_searchmask); | |
74afab7a | 246 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
69cde000 | 247 | return ret; |
74afab7a JL |
248 | } |
249 | ||
2db1f959 TG |
250 | static int assign_irq_vector_any_locked(struct irq_data *irqd) |
251 | { | |
252 | int node = irq_data_get_node(irqd); | |
253 | ||
254 | if (node != NUMA_NO_NODE) { | |
255 | if (!assign_vector_locked(irqd, cpumask_of_node(node))) | |
256 | return 0; | |
257 | } | |
258 | return assign_vector_locked(irqd, cpu_online_mask); | |
259 | } | |
260 | ||
2db1f959 TG |
261 | static int |
262 | assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info) | |
486ca539 | 263 | { |
2db1f959 TG |
264 | if (irqd_affinity_is_managed(irqd)) |
265 | return reserve_managed_vector(irqd); | |
258d86ee | 266 | if (info->mask) |
69cde000 | 267 | return assign_irq_vector(irqd, info->mask); |
464d1230 TG |
268 | /* |
269 | * Make only a global reservation with no guarantee. A real vector | |
270 | * is associated at activation time. | |
271 | */ | |
4900be83 | 272 | return reserve_irq_vector(irqd); |
2db1f959 TG |
273 | } |
274 | ||
275 | static int | |
276 | assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest) | |
277 | { | |
278 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
279 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
280 | int vector, cpu; | |
281 | ||
282 | cpumask_and(vector_searchmask, vector_searchmask, affmsk); | |
283 | cpu = cpumask_first(vector_searchmask); | |
284 | if (cpu >= nr_cpu_ids) | |
285 | return -EINVAL; | |
286 | /* set_affinity might call here for nothing */ | |
287 | if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask)) | |
486ca539 | 288 | return 0; |
2db1f959 TG |
289 | vector = irq_matrix_alloc_managed(vector_matrix, cpu); |
290 | trace_vector_alloc_managed(irqd->irq, vector, vector); | |
291 | if (vector < 0) | |
292 | return vector; | |
293 | apic_update_vector(irqd, vector, cpu); | |
294 | apic_update_irq_cfg(irqd, vector, cpu); | |
295 | return 0; | |
486ca539 JL |
296 | } |
297 | ||
69cde000 | 298 | static void clear_irq_vector(struct irq_data *irqd) |
74afab7a | 299 | { |
69cde000 | 300 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
2db1f959 | 301 | bool managed = irqd_affinity_is_managed(irqd); |
ba224fea | 302 | unsigned int vector = apicd->vector; |
74afab7a | 303 | |
69cde000 | 304 | lockdep_assert_held(&vector_lock); |
ba224fea | 305 | |
dccfe314 | 306 | if (!vector) |
1bdb8970 | 307 | return; |
74afab7a | 308 | |
ba224fea | 309 | trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector, |
69cde000 TG |
310 | apicd->prev_cpu); |
311 | ||
dccfe314 | 312 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
2db1f959 | 313 | irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); |
ba224fea | 314 | apicd->vector = 0; |
74afab7a | 315 | |
dccfe314 | 316 | /* Clean up move in progress */ |
ba224fea | 317 | vector = apicd->prev_vector; |
dccfe314 | 318 | if (!vector) |
74afab7a | 319 | return; |
74afab7a | 320 | |
dccfe314 | 321 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
2db1f959 | 322 | irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); |
ba224fea | 323 | apicd->prev_vector = 0; |
86ba6551 | 324 | apicd->move_in_progress = 0; |
dccfe314 | 325 | hlist_del_init(&apicd->clist); |
74afab7a JL |
326 | } |
327 | ||
2db1f959 TG |
328 | static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd) |
329 | { | |
330 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
331 | unsigned long flags; | |
332 | ||
333 | trace_vector_deactivate(irqd->irq, apicd->is_managed, | |
4900be83 | 334 | apicd->can_reserve, false); |
2db1f959 | 335 | |
4900be83 TG |
336 | /* Regular fixed assigned interrupt */ |
337 | if (!apicd->is_managed && !apicd->can_reserve) | |
338 | return; | |
339 | /* If the interrupt has a global reservation, nothing to do */ | |
340 | if (apicd->has_reserved) | |
2db1f959 TG |
341 | return; |
342 | ||
343 | raw_spin_lock_irqsave(&vector_lock, flags); | |
344 | clear_irq_vector(irqd); | |
4900be83 TG |
345 | if (apicd->can_reserve) |
346 | reserve_irq_vector_locked(irqd); | |
347 | else | |
348 | vector_assign_managed_shutdown(irqd); | |
2db1f959 TG |
349 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
350 | } | |
351 | ||
4900be83 TG |
352 | static int activate_reserved(struct irq_data *irqd) |
353 | { | |
354 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
355 | int ret; | |
356 | ||
357 | ret = assign_irq_vector_any_locked(irqd); | |
358 | if (!ret) | |
359 | apicd->has_reserved = false; | |
360 | return ret; | |
361 | } | |
362 | ||
2db1f959 TG |
363 | static int activate_managed(struct irq_data *irqd) |
364 | { | |
365 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
366 | int ret; | |
367 | ||
368 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
369 | if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) { | |
370 | /* Something in the core code broke! Survive gracefully */ | |
371 | pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq); | |
372 | return EINVAL; | |
373 | } | |
374 | ||
375 | ret = assign_managed_vector(irqd, vector_searchmask); | |
376 | /* | |
377 | * This should not happen. The vector reservation got buggered. Handle | |
378 | * it gracefully. | |
379 | */ | |
380 | if (WARN_ON_ONCE(ret < 0)) { | |
381 | pr_err("Managed startup irq %u, no vector available\n", | |
382 | irqd->irq); | |
383 | } | |
384 | return ret; | |
385 | } | |
386 | ||
387 | static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, | |
388 | bool early) | |
389 | { | |
390 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
391 | unsigned long flags; | |
392 | int ret = 0; | |
393 | ||
394 | trace_vector_activate(irqd->irq, apicd->is_managed, | |
4900be83 | 395 | apicd->can_reserve, early); |
2db1f959 | 396 | |
4900be83 TG |
397 | /* Nothing to do for fixed assigned vectors */ |
398 | if (!apicd->can_reserve && !apicd->is_managed) | |
2db1f959 TG |
399 | return 0; |
400 | ||
401 | raw_spin_lock_irqsave(&vector_lock, flags); | |
402 | if (early || irqd_is_managed_and_shutdown(irqd)) | |
403 | vector_assign_managed_shutdown(irqd); | |
4900be83 | 404 | else if (apicd->is_managed) |
2db1f959 | 405 | ret = activate_managed(irqd); |
4900be83 TG |
406 | else if (apicd->has_reserved) |
407 | ret = activate_reserved(irqd); | |
2db1f959 TG |
408 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
409 | return ret; | |
410 | } | |
411 | ||
412 | static void vector_free_reserved_and_managed(struct irq_data *irqd) | |
413 | { | |
414 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
415 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
416 | ||
4900be83 TG |
417 | trace_vector_teardown(irqd->irq, apicd->is_managed, |
418 | apicd->has_reserved); | |
2db1f959 | 419 | |
4900be83 TG |
420 | if (apicd->has_reserved) |
421 | irq_matrix_remove_reserved(vector_matrix); | |
2db1f959 TG |
422 | if (apicd->is_managed) |
423 | irq_matrix_remove_managed(vector_matrix, dest); | |
424 | } | |
425 | ||
b5dc8e6c JL |
426 | static void x86_vector_free_irqs(struct irq_domain *domain, |
427 | unsigned int virq, unsigned int nr_irqs) | |
428 | { | |
86ba6551 TG |
429 | struct apic_chip_data *apicd; |
430 | struct irq_data *irqd; | |
111abeba | 431 | unsigned long flags; |
b5dc8e6c JL |
432 | int i; |
433 | ||
434 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
435 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
436 | if (irqd && irqd->chip_data) { | |
111abeba | 437 | raw_spin_lock_irqsave(&vector_lock, flags); |
69cde000 | 438 | clear_irq_vector(irqd); |
2db1f959 | 439 | vector_free_reserved_and_managed(irqd); |
86ba6551 TG |
440 | apicd = irqd->chip_data; |
441 | irq_domain_reset_irq_data(irqd); | |
111abeba | 442 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 443 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
444 | } |
445 | } | |
446 | } | |
447 | ||
464d1230 TG |
448 | static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd, |
449 | struct apic_chip_data *apicd) | |
450 | { | |
451 | unsigned long flags; | |
452 | bool realloc = false; | |
453 | ||
454 | apicd->vector = ISA_IRQ_VECTOR(virq); | |
455 | apicd->cpu = 0; | |
456 | ||
457 | raw_spin_lock_irqsave(&vector_lock, flags); | |
458 | /* | |
459 | * If the interrupt is activated, then it must stay at this vector | |
460 | * position. That's usually the timer interrupt (0). | |
461 | */ | |
462 | if (irqd_is_activated(irqd)) { | |
463 | trace_vector_setup(virq, true, 0); | |
464 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); | |
465 | } else { | |
466 | /* Release the vector */ | |
467 | apicd->can_reserve = true; | |
468 | clear_irq_vector(irqd); | |
469 | realloc = true; | |
470 | } | |
471 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
472 | return realloc; | |
473 | } | |
474 | ||
b5dc8e6c JL |
475 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, |
476 | unsigned int nr_irqs, void *arg) | |
477 | { | |
478 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
479 | struct apic_chip_data *apicd; |
480 | struct irq_data *irqd; | |
5f2dbbc5 | 481 | int i, err, node; |
b5dc8e6c JL |
482 | |
483 | if (disable_apic) | |
484 | return -ENXIO; | |
485 | ||
486 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
487 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
488 | return -ENOSYS; | |
489 | ||
b5dc8e6c | 490 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
491 | irqd = irq_domain_get_irq_data(domain, virq + i); |
492 | BUG_ON(!irqd); | |
493 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
494 | WARN_ON_ONCE(irqd->chip_data); |
495 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 496 | if (!apicd) { |
b5dc8e6c JL |
497 | err = -ENOMEM; |
498 | goto error; | |
499 | } | |
500 | ||
69cde000 | 501 | apicd->irq = virq + i; |
86ba6551 TG |
502 | irqd->chip = &lapic_controller; |
503 | irqd->chip_data = apicd; | |
504 | irqd->hwirq = virq + i; | |
505 | irqd_set_single_target(irqd); | |
4ef76eb6 | 506 | /* |
69cde000 TG |
507 | * Legacy vectors are already assigned when the IOAPIC |
508 | * takes them over. They stay on the same vector. This is | |
509 | * required for check_timer() to work correctly as it might | |
510 | * switch back to legacy mode. Only update the hardware | |
511 | * config. | |
4ef76eb6 TG |
512 | */ |
513 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
464d1230 TG |
514 | if (!vector_configure_legacy(virq + i, irqd, apicd)) |
515 | continue; | |
4ef76eb6 TG |
516 | } |
517 | ||
2db1f959 | 518 | err = assign_irq_vector_policy(irqd, info); |
69cde000 | 519 | trace_vector_setup(virq + i, false, err); |
b5dc8e6c JL |
520 | if (err) |
521 | goto error; | |
522 | } | |
523 | ||
524 | return 0; | |
525 | ||
526 | error: | |
527 | x86_vector_free_irqs(domain, virq, i + 1); | |
528 | return err; | |
529 | } | |
530 | ||
65d7ed57 TG |
531 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
532 | void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, | |
533 | struct irq_data *irqd, int ind) | |
534 | { | |
ba224fea | 535 | unsigned int cpu, vector, prev_cpu, prev_vector; |
65d7ed57 TG |
536 | struct apic_chip_data *apicd; |
537 | unsigned long flags; | |
538 | int irq; | |
539 | ||
540 | if (!irqd) { | |
541 | irq_matrix_debug_show(m, vector_matrix, ind); | |
542 | return; | |
543 | } | |
544 | ||
545 | irq = irqd->irq; | |
546 | if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { | |
547 | seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); | |
548 | seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); | |
549 | return; | |
550 | } | |
551 | ||
552 | apicd = irqd->chip_data; | |
553 | if (!apicd) { | |
554 | seq_printf(m, "%*sVector: Not assigned\n", ind, ""); | |
555 | return; | |
556 | } | |
557 | ||
558 | raw_spin_lock_irqsave(&vector_lock, flags); | |
559 | cpu = apicd->cpu; | |
ba224fea | 560 | vector = apicd->vector; |
65d7ed57 | 561 | prev_cpu = apicd->prev_cpu; |
ba224fea | 562 | prev_vector = apicd->prev_vector; |
65d7ed57 | 563 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
ba224fea | 564 | seq_printf(m, "%*sVector: %5u\n", ind, "", vector); |
65d7ed57 | 565 | seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu); |
ba224fea TG |
566 | if (prev_vector) { |
567 | seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vector); | |
65d7ed57 TG |
568 | seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu); |
569 | } | |
570 | } | |
571 | #endif | |
572 | ||
eb18cf55 | 573 | static const struct irq_domain_ops x86_vector_domain_ops = { |
65d7ed57 TG |
574 | .alloc = x86_vector_alloc_irqs, |
575 | .free = x86_vector_free_irqs, | |
2db1f959 TG |
576 | .activate = x86_vector_activate, |
577 | .deactivate = x86_vector_deactivate, | |
65d7ed57 TG |
578 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
579 | .debug_show = x86_vector_debug_show, | |
580 | #endif | |
b5dc8e6c JL |
581 | }; |
582 | ||
11d686e9 JL |
583 | int __init arch_probe_nr_irqs(void) |
584 | { | |
585 | int nr; | |
586 | ||
587 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
588 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
589 | ||
590 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
591 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
592 | /* | |
593 | * for MSI and HT dyn irq | |
594 | */ | |
595 | if (gsi_top <= NR_IRQS_LEGACY) | |
596 | nr += 8 * nr_cpu_ids; | |
597 | else | |
598 | nr += gsi_top * 16; | |
599 | #endif | |
600 | if (nr < nr_irqs) | |
601 | nr_irqs = nr; | |
602 | ||
8c058b0b VK |
603 | /* |
604 | * We don't know if PIC is present at this point so we need to do | |
605 | * probe() to get the right number of legacy IRQs. | |
606 | */ | |
607 | return legacy_pic->probe(); | |
11d686e9 JL |
608 | } |
609 | ||
0fa115da TG |
610 | void lapic_assign_legacy_vector(unsigned int irq, bool replace) |
611 | { | |
612 | /* | |
613 | * Use assign system here so it wont get accounted as allocated | |
614 | * and moveable in the cpu hotplug check and it prevents managed | |
615 | * irq reservation from touching it. | |
616 | */ | |
617 | irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); | |
618 | } | |
619 | ||
620 | void __init lapic_assign_system_vectors(void) | |
621 | { | |
622 | unsigned int i, vector = 0; | |
623 | ||
624 | for_each_set_bit_from(vector, system_vectors, NR_VECTORS) | |
625 | irq_matrix_assign_system(vector_matrix, vector, false); | |
626 | ||
627 | if (nr_legacy_irqs() > 1) | |
628 | lapic_assign_legacy_vector(PIC_CASCADE_IR, false); | |
629 | ||
630 | /* System vectors are reserved, online it */ | |
631 | irq_matrix_online(vector_matrix); | |
632 | ||
633 | /* Mark the preallocated legacy interrupts */ | |
634 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
635 | if (i != PIC_CASCADE_IR) | |
636 | irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); | |
637 | } | |
638 | } | |
639 | ||
11d686e9 JL |
640 | int __init arch_early_irq_init(void) |
641 | { | |
9d35f859 TG |
642 | struct fwnode_handle *fn; |
643 | ||
9d35f859 TG |
644 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
645 | BUG_ON(!fn); | |
646 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
647 | NULL); | |
b5dc8e6c | 648 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 649 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
650 | irq_set_default_host(x86_vector_domain); |
651 | ||
52f518a3 | 652 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 653 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 654 | |
3716fd27 | 655 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
f7fa7aee | 656 | |
0fa115da TG |
657 | /* |
658 | * Allocate the vector matrix allocator data structure and limit the | |
659 | * search area. | |
660 | */ | |
661 | vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, | |
662 | FIRST_SYSTEM_VECTOR); | |
663 | BUG_ON(!vector_matrix); | |
664 | ||
11d686e9 JL |
665 | return arch_early_ioapic_init(); |
666 | } | |
667 | ||
ba801640 | 668 | #ifdef CONFIG_SMP |
74afab7a | 669 | |
f0cc6cca TG |
670 | static struct irq_desc *__setup_vector_irq(int vector) |
671 | { | |
672 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
673 | ||
674 | /* Check whether the irq is in the legacy space */ | |
675 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
676 | return VECTOR_UNUSED; | |
677 | /* Check whether the irq is handled by the IOAPIC */ | |
678 | if (test_bit(isairq, &io_apic_irqs)) | |
679 | return VECTOR_UNUSED; | |
680 | return irq_to_desc(isairq); | |
681 | } | |
682 | ||
0fa115da TG |
683 | /* Online the local APIC infrastructure and initialize the vectors */ |
684 | void lapic_online(void) | |
74afab7a | 685 | { |
f0cc6cca | 686 | unsigned int vector; |
74afab7a | 687 | |
5a3f75e3 | 688 | lockdep_assert_held(&vector_lock); |
0fa115da TG |
689 | |
690 | /* Online the vector matrix array for this CPU */ | |
691 | irq_matrix_online(vector_matrix); | |
692 | ||
74afab7a | 693 | /* |
f0cc6cca TG |
694 | * The interrupt affinity logic never targets interrupts to offline |
695 | * CPUs. The exception are the legacy PIC interrupts. In general | |
696 | * they are only targeted to CPU0, but depending on the platform | |
697 | * they can be distributed to any online CPU in hardware. The | |
698 | * kernel has no influence on that. So all active legacy vectors | |
699 | * must be installed on all CPUs. All non legacy interrupts can be | |
700 | * cleared. | |
74afab7a | 701 | */ |
f0cc6cca TG |
702 | for (vector = 0; vector < NR_VECTORS; vector++) |
703 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a JL |
704 | } |
705 | ||
0fa115da TG |
706 | void lapic_offline(void) |
707 | { | |
708 | lock_vector_lock(); | |
709 | irq_matrix_offline(vector_matrix); | |
710 | unlock_vector_lock(); | |
711 | } | |
712 | ||
ba801640 TG |
713 | static int apic_set_affinity(struct irq_data *irqd, |
714 | const struct cpumask *dest, bool force) | |
715 | { | |
716 | int err; | |
717 | ||
2db1f959 TG |
718 | raw_spin_lock(&vector_lock); |
719 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
720 | if (irqd_affinity_is_managed(irqd)) | |
721 | err = assign_managed_vector(irqd, vector_searchmask); | |
722 | else | |
723 | err = assign_vector_locked(irqd, vector_searchmask); | |
724 | raw_spin_unlock(&vector_lock); | |
ba801640 TG |
725 | return err ? err : IRQ_SET_MASK_OK; |
726 | } | |
727 | ||
728 | #else | |
729 | # define apic_set_affinity NULL | |
730 | #endif | |
731 | ||
86ba6551 | 732 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 733 | { |
86ba6551 | 734 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 735 | unsigned long flags; |
74afab7a JL |
736 | |
737 | raw_spin_lock_irqsave(&vector_lock, flags); | |
ba224fea | 738 | apic->send_IPI(apicd->cpu, apicd->vector); |
74afab7a JL |
739 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
740 | ||
741 | return 1; | |
742 | } | |
743 | ||
86ba6551 | 744 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 745 | { |
86ba6551 TG |
746 | irq_complete_move(irqd_cfg(irqd)); |
747 | irq_move_irq(irqd); | |
74afab7a JL |
748 | ack_APIC_irq(); |
749 | } | |
750 | ||
b5dc8e6c | 751 | static struct irq_chip lapic_controller = { |
8947dfb2 | 752 | .name = "APIC", |
b5dc8e6c | 753 | .irq_ack = apic_ack_edge, |
68f9f440 | 754 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
755 | .irq_retrigger = apic_retrigger_irq, |
756 | }; | |
757 | ||
74afab7a | 758 | #ifdef CONFIG_SMP |
c6c2002b | 759 | |
69cde000 TG |
760 | static void free_moved_vector(struct apic_chip_data *apicd) |
761 | { | |
ba224fea | 762 | unsigned int vector = apicd->prev_vector; |
69cde000 | 763 | unsigned int cpu = apicd->prev_cpu; |
2db1f959 TG |
764 | bool managed = apicd->is_managed; |
765 | ||
766 | /* | |
767 | * This should never happen. Managed interrupts are not | |
768 | * migrated except on CPU down, which does not involve the | |
769 | * cleanup vector. But try to keep the accounting correct | |
770 | * nevertheless. | |
771 | */ | |
772 | WARN_ON_ONCE(managed); | |
69cde000 | 773 | |
2db1f959 TG |
774 | trace_vector_free_moved(apicd->irq, vector, managed); |
775 | irq_matrix_free(vector_matrix, cpu, vector, managed); | |
69cde000 TG |
776 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
777 | hlist_del_init(&apicd->clist); | |
ba224fea | 778 | apicd->prev_vector = 0; |
69cde000 TG |
779 | apicd->move_in_progress = 0; |
780 | } | |
781 | ||
c4158ff5 | 782 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 783 | { |
dccfe314 TG |
784 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
785 | struct apic_chip_data *apicd; | |
786 | struct hlist_node *tmp; | |
74afab7a | 787 | |
6af7faf6 | 788 | entering_ack_irq(); |
df54c493 TG |
789 | /* Prevent vectors vanishing under us */ |
790 | raw_spin_lock(&vector_lock); | |
791 | ||
dccfe314 | 792 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
ba224fea | 793 | unsigned int irr, vector = apicd->prev_vector; |
74afab7a | 794 | |
74afab7a | 795 | /* |
dccfe314 TG |
796 | * Paranoia: Check if the vector that needs to be cleaned |
797 | * up is registered at the APICs IRR. If so, then this is | |
798 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 799 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
800 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
801 | * priority external vector, so on return from this | |
802 | * interrupt the device interrupt will happen first. | |
74afab7a | 803 | */ |
dccfe314 TG |
804 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
805 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 806 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 807 | continue; |
74afab7a | 808 | } |
69cde000 | 809 | free_moved_vector(apicd); |
74afab7a JL |
810 | } |
811 | ||
df54c493 | 812 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 813 | exiting_irq(); |
74afab7a JL |
814 | } |
815 | ||
dccfe314 TG |
816 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
817 | { | |
818 | unsigned int cpu; | |
819 | ||
820 | raw_spin_lock(&vector_lock); | |
821 | apicd->move_in_progress = 0; | |
822 | cpu = apicd->prev_cpu; | |
823 | if (cpu_online(cpu)) { | |
824 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
825 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
826 | } else { | |
ba224fea | 827 | apicd->prev_vector = 0; |
dccfe314 TG |
828 | } |
829 | raw_spin_unlock(&vector_lock); | |
830 | } | |
831 | ||
832 | void send_cleanup_vector(struct irq_cfg *cfg) | |
833 | { | |
834 | struct apic_chip_data *apicd; | |
835 | ||
ba224fea | 836 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
dccfe314 TG |
837 | if (apicd->move_in_progress) |
838 | __send_cleanup_vector(apicd); | |
839 | } | |
840 | ||
74afab7a JL |
841 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
842 | { | |
86ba6551 | 843 | struct apic_chip_data *apicd; |
74afab7a | 844 | |
ba224fea | 845 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
86ba6551 | 846 | if (likely(!apicd->move_in_progress)) |
74afab7a JL |
847 | return; |
848 | ||
ba224fea | 849 | if (vector == apicd->vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 850 | __send_cleanup_vector(apicd); |
74afab7a JL |
851 | } |
852 | ||
853 | void irq_complete_move(struct irq_cfg *cfg) | |
854 | { | |
855 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
856 | } | |
857 | ||
90a2282e | 858 | /* |
551adc60 | 859 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
860 | */ |
861 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 862 | { |
86ba6551 | 863 | struct apic_chip_data *apicd; |
dccfe314 TG |
864 | struct irq_data *irqd; |
865 | unsigned int vector; | |
56d7d2f4 | 866 | |
db91aa79 MW |
867 | /* |
868 | * The function is called for all descriptors regardless of which | |
869 | * irqdomain they belong to. For example if an IRQ is provided by | |
870 | * an irq_chip as part of a GPIO driver, the chip data for that | |
871 | * descriptor is specific to the irq_chip in question. | |
872 | * | |
873 | * Check first that the chip_data is what we expect | |
874 | * (apic_chip_data) before touching it any further. | |
875 | */ | |
86ba6551 | 876 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 877 | irq_desc_get_irq(desc)); |
86ba6551 | 878 | if (!irqd) |
db91aa79 MW |
879 | return; |
880 | ||
dccfe314 | 881 | raw_spin_lock(&vector_lock); |
86ba6551 | 882 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
883 | if (!apicd) |
884 | goto unlock; | |
db91aa79 | 885 | |
dccfe314 | 886 | /* |
ba224fea | 887 | * If prev_vector is empty, no action required. |
dccfe314 | 888 | */ |
ba224fea | 889 | vector = apicd->prev_vector; |
dccfe314 TG |
890 | if (!vector) |
891 | goto unlock; | |
74afab7a | 892 | |
56d7d2f4 | 893 | /* |
dccfe314 | 894 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
895 | * done yet, then the following setaffinity call will fail with |
896 | * -EBUSY. This can leave the interrupt in a stale state. | |
897 | * | |
551adc60 TG |
898 | * All CPUs are stuck in stop machine with interrupts disabled so |
899 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 900 | * |
551adc60 TG |
901 | * 1) The interrupt is in move_in_progress state. That means that we |
902 | * have not seen an interrupt since the io_apic was reprogrammed to | |
903 | * the new vector. | |
904 | * | |
905 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
906 | * have not been processed yet. | |
907 | */ | |
86ba6551 | 908 | if (apicd->move_in_progress) { |
98229aa3 | 909 | /* |
551adc60 TG |
910 | * In theory there is a race: |
911 | * | |
912 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
913 | * is effective, i.e. it's raised on | |
914 | * the old vector. | |
915 | * | |
916 | * So if the target cpu cannot handle that interrupt before | |
917 | * the old vector is cleaned up, we get a spurious interrupt | |
918 | * and in the worst case the ioapic irq line becomes stale. | |
919 | * | |
920 | * But in case of cpu hotplug this should be a non issue | |
921 | * because if the affinity update happens right before all | |
922 | * cpus rendevouz in stop machine, there is no way that the | |
923 | * interrupt can be blocked on the target cpu because all cpus | |
924 | * loops first with interrupts enabled in stop machine, so the | |
925 | * old vector is not yet cleaned up when the interrupt fires. | |
926 | * | |
927 | * So the only way to run into this issue is if the delivery | |
928 | * of the interrupt on the apic/system bus would be delayed | |
929 | * beyond the point where the target cpu disables interrupts | |
930 | * in stop machine. I doubt that it can happen, but at least | |
931 | * there is a theroretical chance. Virtualization might be | |
932 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
933 | * as stupid as the real hardware. | |
934 | * | |
935 | * Anyway, there is nothing we can do about that at this point | |
936 | * w/o refactoring the whole fixup_irq() business completely. | |
937 | * We print at least the irq number and the old vector number, | |
938 | * so we have the necessary information when a problem in that | |
939 | * area arises. | |
98229aa3 | 940 | */ |
551adc60 | 941 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 942 | irqd->irq, vector); |
98229aa3 | 943 | } |
69cde000 | 944 | free_moved_vector(apicd); |
dccfe314 | 945 | unlock: |
56d7d2f4 | 946 | raw_spin_unlock(&vector_lock); |
74afab7a | 947 | } |
74afab7a JL |
948 | #endif |
949 | ||
74afab7a JL |
950 | static void __init print_APIC_field(int base) |
951 | { | |
952 | int i; | |
953 | ||
954 | printk(KERN_DEBUG); | |
955 | ||
956 | for (i = 0; i < 8; i++) | |
957 | pr_cont("%08x", apic_read(base + i*0x10)); | |
958 | ||
959 | pr_cont("\n"); | |
960 | } | |
961 | ||
962 | static void __init print_local_APIC(void *dummy) | |
963 | { | |
964 | unsigned int i, v, ver, maxlvt; | |
965 | u64 icr; | |
966 | ||
849d3569 JL |
967 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
968 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 969 | v = apic_read(APIC_ID); |
849d3569 | 970 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 971 | v = apic_read(APIC_LVR); |
849d3569 | 972 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
973 | ver = GET_APIC_VERSION(v); |
974 | maxlvt = lapic_get_maxlvt(); | |
975 | ||
976 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 977 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
978 | |
979 | /* !82489DX */ | |
980 | if (APIC_INTEGRATED(ver)) { | |
981 | if (!APIC_XAPIC(ver)) { | |
982 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
983 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
984 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
985 | } |
986 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 987 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
988 | } |
989 | ||
990 | /* | |
991 | * Remote read supported only in the 82489DX and local APIC for | |
992 | * Pentium processors. | |
993 | */ | |
994 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
995 | v = apic_read(APIC_RRR); | |
849d3569 | 996 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
997 | } |
998 | ||
999 | v = apic_read(APIC_LDR); | |
849d3569 | 1000 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
1001 | if (!x2apic_enabled()) { |
1002 | v = apic_read(APIC_DFR); | |
849d3569 | 1003 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
1004 | } |
1005 | v = apic_read(APIC_SPIV); | |
849d3569 | 1006 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 1007 | |
849d3569 | 1008 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 1009 | print_APIC_field(APIC_ISR); |
849d3569 | 1010 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 1011 | print_APIC_field(APIC_TMR); |
849d3569 | 1012 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
1013 | print_APIC_field(APIC_IRR); |
1014 | ||
1015 | /* !82489DX */ | |
1016 | if (APIC_INTEGRATED(ver)) { | |
1017 | /* Due to the Pentium erratum 3AP. */ | |
1018 | if (maxlvt > 3) | |
1019 | apic_write(APIC_ESR, 0); | |
1020 | ||
1021 | v = apic_read(APIC_ESR); | |
849d3569 | 1022 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
1023 | } |
1024 | ||
1025 | icr = apic_icr_read(); | |
849d3569 JL |
1026 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
1027 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
1028 | |
1029 | v = apic_read(APIC_LVTT); | |
849d3569 | 1030 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
1031 | |
1032 | if (maxlvt > 3) { | |
1033 | /* PC is LVT#4. */ | |
1034 | v = apic_read(APIC_LVTPC); | |
849d3569 | 1035 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
1036 | } |
1037 | v = apic_read(APIC_LVT0); | |
849d3569 | 1038 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 1039 | v = apic_read(APIC_LVT1); |
849d3569 | 1040 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
1041 | |
1042 | if (maxlvt > 2) { | |
1043 | /* ERR is LVT#3. */ | |
1044 | v = apic_read(APIC_LVTERR); | |
849d3569 | 1045 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
1046 | } |
1047 | ||
1048 | v = apic_read(APIC_TMICT); | |
849d3569 | 1049 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 1050 | v = apic_read(APIC_TMCCT); |
849d3569 | 1051 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 1052 | v = apic_read(APIC_TDCR); |
849d3569 | 1053 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
1054 | |
1055 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1056 | v = apic_read(APIC_EFEAT); | |
1057 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 1058 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 1059 | v = apic_read(APIC_ECTRL); |
849d3569 | 1060 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
1061 | for (i = 0; i < maxlvt; i++) { |
1062 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 1063 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
1064 | } |
1065 | } | |
1066 | pr_cont("\n"); | |
1067 | } | |
1068 | ||
1069 | static void __init print_local_APICs(int maxcpu) | |
1070 | { | |
1071 | int cpu; | |
1072 | ||
1073 | if (!maxcpu) | |
1074 | return; | |
1075 | ||
1076 | preempt_disable(); | |
1077 | for_each_online_cpu(cpu) { | |
1078 | if (cpu >= maxcpu) | |
1079 | break; | |
1080 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1081 | } | |
1082 | preempt_enable(); | |
1083 | } | |
1084 | ||
1085 | static void __init print_PIC(void) | |
1086 | { | |
1087 | unsigned int v; | |
1088 | unsigned long flags; | |
1089 | ||
1090 | if (!nr_legacy_irqs()) | |
1091 | return; | |
1092 | ||
849d3569 | 1093 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
1094 | |
1095 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
1096 | ||
1097 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 1098 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
1099 | |
1100 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 1101 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
1102 | |
1103 | outb(0x0b, 0xa0); | |
1104 | outb(0x0b, 0x20); | |
1105 | v = inb(0xa0) << 8 | inb(0x20); | |
1106 | outb(0x0a, 0xa0); | |
1107 | outb(0x0a, 0x20); | |
1108 | ||
1109 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
1110 | ||
849d3569 | 1111 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
1112 | |
1113 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 1114 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
1115 | } |
1116 | ||
1117 | static int show_lapic __initdata = 1; | |
1118 | static __init int setup_show_lapic(char *arg) | |
1119 | { | |
1120 | int num = -1; | |
1121 | ||
1122 | if (strcmp(arg, "all") == 0) { | |
1123 | show_lapic = CONFIG_NR_CPUS; | |
1124 | } else { | |
1125 | get_option(&arg, &num); | |
1126 | if (num >= 0) | |
1127 | show_lapic = num; | |
1128 | } | |
1129 | ||
1130 | return 1; | |
1131 | } | |
1132 | __setup("show_lapic=", setup_show_lapic); | |
1133 | ||
1134 | static int __init print_ICs(void) | |
1135 | { | |
1136 | if (apic_verbosity == APIC_QUIET) | |
1137 | return 0; | |
1138 | ||
1139 | print_PIC(); | |
1140 | ||
1141 | /* don't print out if apic is not there */ | |
93984fbd | 1142 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
1143 | return 0; |
1144 | ||
1145 | print_local_APICs(show_lapic); | |
1146 | print_IO_APICs(); | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | late_initcall(print_ICs); |