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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
74afab7a | 32 | static DEFINE_RAW_SPINLOCK(vector_lock); |
f7fa7aee | 33 | static cpumask_var_t vector_cpumask; |
b5dc8e6c | 34 | static struct irq_chip lapic_controller; |
13315320 | 35 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 36 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 37 | #endif |
74afab7a JL |
38 | |
39 | void lock_vector_lock(void) | |
40 | { | |
41 | /* Used to the online set of cpus does not change | |
42 | * during assign_irq_vector. | |
43 | */ | |
44 | raw_spin_lock(&vector_lock); | |
45 | } | |
46 | ||
47 | void unlock_vector_lock(void) | |
48 | { | |
49 | raw_spin_unlock(&vector_lock); | |
50 | } | |
51 | ||
7f3262ed | 52 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 53 | { |
b5dc8e6c JL |
54 | if (!irq_data) |
55 | return NULL; | |
56 | ||
57 | while (irq_data->parent_data) | |
58 | irq_data = irq_data->parent_data; | |
59 | ||
74afab7a JL |
60 | return irq_data->chip_data; |
61 | } | |
62 | ||
7f3262ed JL |
63 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
64 | { | |
65 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
66 | ||
67 | return data ? &data->cfg : NULL; | |
68 | } | |
69 | ||
70 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 71 | { |
7f3262ed JL |
72 | return irqd_cfg(irq_get_irq_data(irq)); |
73 | } | |
74afab7a | 74 | |
7f3262ed JL |
75 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
76 | { | |
77 | struct apic_chip_data *data; | |
78 | ||
79 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
80 | if (!data) | |
74afab7a | 81 | return NULL; |
7f3262ed JL |
82 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
83 | goto out_data; | |
84 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 85 | goto out_domain; |
7f3262ed | 86 | return data; |
74afab7a | 87 | out_domain: |
7f3262ed JL |
88 | free_cpumask_var(data->domain); |
89 | out_data: | |
90 | kfree(data); | |
74afab7a JL |
91 | return NULL; |
92 | } | |
93 | ||
7f3262ed | 94 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 95 | { |
7f3262ed JL |
96 | if (data) { |
97 | free_cpumask_var(data->domain); | |
98 | free_cpumask_var(data->old_domain); | |
99 | kfree(data); | |
b5dc8e6c | 100 | } |
74afab7a JL |
101 | } |
102 | ||
7f3262ed JL |
103 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
104 | const struct cpumask *mask) | |
74afab7a JL |
105 | { |
106 | /* | |
107 | * NOTE! The local APIC isn't very good at handling | |
108 | * multiple interrupts at the same interrupt level. | |
109 | * As the interrupt level is determined by taking the | |
110 | * vector number and shifting that right by 4, we | |
111 | * want to spread these out a bit so that they don't | |
112 | * all fall in the same interrupt level. | |
113 | * | |
114 | * Also, we've got to be careful not to trash gate | |
115 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
116 | */ | |
117 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
118 | static int current_offset = VECTOR_OFFSET_START % 16; | |
119 | int cpu, err; | |
74afab7a | 120 | |
7f3262ed | 121 | if (d->move_in_progress) |
74afab7a JL |
122 | return -EBUSY; |
123 | ||
74afab7a JL |
124 | /* Only try and allocate irqs on cpus that are present */ |
125 | err = -ENOSPC; | |
7f3262ed | 126 | cpumask_clear(d->old_domain); |
74afab7a JL |
127 | cpu = cpumask_first_and(mask, cpu_online_mask); |
128 | while (cpu < nr_cpu_ids) { | |
129 | int new_cpu, vector, offset; | |
130 | ||
f7fa7aee | 131 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 132 | |
f7fa7aee | 133 | if (cpumask_subset(vector_cpumask, d->domain)) { |
74afab7a | 134 | err = 0; |
f7fa7aee | 135 | if (cpumask_equal(vector_cpumask, d->domain)) |
74afab7a JL |
136 | break; |
137 | /* | |
138 | * New cpumask using the vector is a proper subset of | |
139 | * the current in use mask. So cleanup the vector | |
140 | * allocation for the members that are not used anymore. | |
141 | */ | |
f7fa7aee JL |
142 | cpumask_andnot(d->old_domain, d->domain, |
143 | vector_cpumask); | |
7f3262ed JL |
144 | d->move_in_progress = |
145 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
f7fa7aee | 146 | cpumask_and(d->domain, d->domain, vector_cpumask); |
74afab7a JL |
147 | break; |
148 | } | |
149 | ||
150 | vector = current_vector; | |
151 | offset = current_offset; | |
152 | next: | |
153 | vector += 16; | |
154 | if (vector >= first_system_vector) { | |
155 | offset = (offset + 1) % 16; | |
156 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
157 | } | |
158 | ||
159 | if (unlikely(current_vector == vector)) { | |
f7fa7aee JL |
160 | cpumask_or(d->old_domain, d->old_domain, |
161 | vector_cpumask); | |
162 | cpumask_andnot(vector_cpumask, mask, d->old_domain); | |
163 | cpu = cpumask_first_and(vector_cpumask, | |
164 | cpu_online_mask); | |
74afab7a JL |
165 | continue; |
166 | } | |
167 | ||
168 | if (test_bit(vector, used_vectors)) | |
169 | goto next; | |
170 | ||
f7fa7aee | 171 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { |
74afab7a JL |
172 | if (per_cpu(vector_irq, new_cpu)[vector] > |
173 | VECTOR_UNDEFINED) | |
174 | goto next; | |
175 | } | |
176 | /* Found one! */ | |
177 | current_vector = vector; | |
178 | current_offset = offset; | |
7f3262ed JL |
179 | if (d->cfg.vector) { |
180 | cpumask_copy(d->old_domain, d->domain); | |
181 | d->move_in_progress = | |
182 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
74afab7a | 183 | } |
f7fa7aee | 184 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) |
74afab7a | 185 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
7f3262ed | 186 | d->cfg.vector = vector; |
f7fa7aee | 187 | cpumask_copy(d->domain, vector_cpumask); |
74afab7a JL |
188 | err = 0; |
189 | break; | |
190 | } | |
74afab7a | 191 | |
5f0052f9 JL |
192 | if (!err) { |
193 | /* cache destination APIC IDs into cfg->dest_apicid */ | |
7f3262ed JL |
194 | err = apic->cpu_mask_to_apicid_and(mask, d->domain, |
195 | &d->cfg.dest_apicid); | |
5f0052f9 JL |
196 | } |
197 | ||
74afab7a JL |
198 | return err; |
199 | } | |
200 | ||
7f3262ed | 201 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 202 | const struct cpumask *mask) |
74afab7a JL |
203 | { |
204 | int err; | |
205 | unsigned long flags; | |
206 | ||
207 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 208 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
209 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
210 | return err; | |
211 | } | |
212 | ||
486ca539 JL |
213 | static int assign_irq_vector_policy(int irq, int node, |
214 | struct apic_chip_data *data, | |
215 | struct irq_alloc_info *info) | |
216 | { | |
217 | if (info && info->mask) | |
218 | return assign_irq_vector(irq, data, info->mask); | |
219 | if (node != NUMA_NO_NODE && | |
220 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
221 | return 0; | |
222 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
223 | } | |
224 | ||
7f3262ed | 225 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a JL |
226 | { |
227 | int cpu, vector; | |
228 | unsigned long flags; | |
229 | ||
230 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 231 | BUG_ON(!data->cfg.vector); |
74afab7a | 232 | |
7f3262ed JL |
233 | vector = data->cfg.vector; |
234 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
74afab7a JL |
235 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
236 | ||
7f3262ed JL |
237 | data->cfg.vector = 0; |
238 | cpumask_clear(data->domain); | |
74afab7a | 239 | |
7f3262ed | 240 | if (likely(!data->move_in_progress)) { |
74afab7a JL |
241 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
242 | return; | |
243 | } | |
244 | ||
7f3262ed | 245 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
246 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
247 | vector++) { | |
248 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
249 | continue; | |
250 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; | |
251 | break; | |
252 | } | |
253 | } | |
7f3262ed | 254 | data->move_in_progress = 0; |
74afab7a JL |
255 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
256 | } | |
257 | ||
b5dc8e6c JL |
258 | void init_irq_alloc_info(struct irq_alloc_info *info, |
259 | const struct cpumask *mask) | |
260 | { | |
261 | memset(info, 0, sizeof(*info)); | |
262 | info->mask = mask; | |
263 | } | |
264 | ||
265 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
266 | { | |
267 | if (src) | |
268 | *dst = *src; | |
269 | else | |
270 | memset(dst, 0, sizeof(*dst)); | |
271 | } | |
272 | ||
b5dc8e6c JL |
273 | static void x86_vector_free_irqs(struct irq_domain *domain, |
274 | unsigned int virq, unsigned int nr_irqs) | |
275 | { | |
276 | struct irq_data *irq_data; | |
277 | int i; | |
278 | ||
279 | for (i = 0; i < nr_irqs; i++) { | |
280 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
281 | if (irq_data && irq_data->chip_data) { | |
b5dc8e6c | 282 | clear_irq_vector(virq + i, irq_data->chip_data); |
7f3262ed | 283 | free_apic_chip_data(irq_data->chip_data); |
13315320 JL |
284 | #ifdef CONFIG_X86_IO_APIC |
285 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 286 | legacy_irq_data[virq + i] = NULL; |
13315320 | 287 | #endif |
b5dc8e6c JL |
288 | irq_domain_reset_irq_data(irq_data); |
289 | } | |
290 | } | |
291 | } | |
292 | ||
293 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
294 | unsigned int nr_irqs, void *arg) | |
295 | { | |
296 | struct irq_alloc_info *info = arg; | |
7f3262ed | 297 | struct apic_chip_data *data; |
b5dc8e6c | 298 | struct irq_data *irq_data; |
b5dc8e6c JL |
299 | int i, err; |
300 | ||
301 | if (disable_apic) | |
302 | return -ENXIO; | |
303 | ||
304 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
305 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
306 | return -ENOSYS; | |
307 | ||
b5dc8e6c JL |
308 | for (i = 0; i < nr_irqs; i++) { |
309 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
310 | BUG_ON(!irq_data); | |
13315320 | 311 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
312 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
313 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
314 | else |
315 | #endif | |
7f3262ed JL |
316 | data = alloc_apic_chip_data(irq_data->node); |
317 | if (!data) { | |
b5dc8e6c JL |
318 | err = -ENOMEM; |
319 | goto error; | |
320 | } | |
321 | ||
322 | irq_data->chip = &lapic_controller; | |
7f3262ed | 323 | irq_data->chip_data = data; |
b5dc8e6c | 324 | irq_data->hwirq = virq + i; |
486ca539 JL |
325 | err = assign_irq_vector_policy(virq, irq_data->node, data, |
326 | info); | |
b5dc8e6c JL |
327 | if (err) |
328 | goto error; | |
329 | } | |
330 | ||
331 | return 0; | |
332 | ||
333 | error: | |
334 | x86_vector_free_irqs(domain, virq, i + 1); | |
335 | return err; | |
336 | } | |
337 | ||
eb18cf55 TG |
338 | static const struct irq_domain_ops x86_vector_domain_ops = { |
339 | .alloc = x86_vector_alloc_irqs, | |
340 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
341 | }; |
342 | ||
11d686e9 JL |
343 | int __init arch_probe_nr_irqs(void) |
344 | { | |
345 | int nr; | |
346 | ||
347 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
348 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
349 | ||
350 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
351 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
352 | /* | |
353 | * for MSI and HT dyn irq | |
354 | */ | |
355 | if (gsi_top <= NR_IRQS_LEGACY) | |
356 | nr += 8 * nr_cpu_ids; | |
357 | else | |
358 | nr += gsi_top * 16; | |
359 | #endif | |
360 | if (nr < nr_irqs) | |
361 | nr_irqs = nr; | |
362 | ||
363 | return nr_legacy_irqs(); | |
364 | } | |
365 | ||
13315320 JL |
366 | #ifdef CONFIG_X86_IO_APIC |
367 | static void init_legacy_irqs(void) | |
368 | { | |
369 | int i, node = cpu_to_node(0); | |
7f3262ed | 370 | struct apic_chip_data *data; |
13315320 JL |
371 | |
372 | /* | |
373 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 374 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
375 | */ |
376 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
377 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
378 | BUG_ON(!data); | |
191a6635 IM |
379 | |
380 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
381 | cpumask_setall(data->domain); |
382 | irq_set_chip_data(i, data); | |
13315320 JL |
383 | } |
384 | } | |
385 | #else | |
386 | static void init_legacy_irqs(void) { } | |
387 | #endif | |
388 | ||
11d686e9 JL |
389 | int __init arch_early_irq_init(void) |
390 | { | |
13315320 JL |
391 | init_legacy_irqs(); |
392 | ||
b5dc8e6c JL |
393 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
394 | NULL); | |
395 | BUG_ON(x86_vector_domain == NULL); | |
396 | irq_set_default_host(x86_vector_domain); | |
397 | ||
52f518a3 | 398 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 399 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 400 | |
f7fa7aee JL |
401 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
402 | ||
11d686e9 JL |
403 | return arch_early_ioapic_init(); |
404 | } | |
405 | ||
74afab7a JL |
406 | static void __setup_vector_irq(int cpu) |
407 | { | |
408 | /* Initialize vector_irq on a new cpu */ | |
409 | int irq, vector; | |
7f3262ed | 410 | struct apic_chip_data *data; |
74afab7a JL |
411 | |
412 | /* | |
413 | * vector_lock will make sure that we don't run into irq vector | |
414 | * assignments that might be happening on another cpu in parallel, | |
415 | * while we setup our initial vector to irq mappings. | |
416 | */ | |
417 | raw_spin_lock(&vector_lock); | |
418 | /* Mark the inuse vectors */ | |
419 | for_each_active_irq(irq) { | |
7f3262ed JL |
420 | data = apic_chip_data(irq_get_irq_data(irq)); |
421 | if (!data) | |
74afab7a JL |
422 | continue; |
423 | ||
7f3262ed | 424 | if (!cpumask_test_cpu(cpu, data->domain)) |
74afab7a | 425 | continue; |
7f3262ed | 426 | vector = data->cfg.vector; |
74afab7a JL |
427 | per_cpu(vector_irq, cpu)[vector] = irq; |
428 | } | |
429 | /* Mark the free vectors */ | |
430 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
431 | irq = per_cpu(vector_irq, cpu)[vector]; | |
432 | if (irq <= VECTOR_UNDEFINED) | |
433 | continue; | |
434 | ||
7f3262ed JL |
435 | data = apic_chip_data(irq_get_irq_data(irq)); |
436 | if (!cpumask_test_cpu(cpu, data->domain)) | |
74afab7a JL |
437 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
438 | } | |
439 | raw_spin_unlock(&vector_lock); | |
440 | } | |
441 | ||
442 | /* | |
443 | * Setup the vector to irq mappings. | |
444 | */ | |
445 | void setup_vector_irq(int cpu) | |
446 | { | |
447 | int irq; | |
448 | ||
449 | /* | |
450 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
451 | * boot cpu. But there are certain platforms where PIC interrupts are | |
452 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
453 | * legacy PIC, for the new cpu that is coming online, setup the static | |
454 | * legacy vector to irq mapping: | |
455 | */ | |
456 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
8b455e65 | 457 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq; |
74afab7a JL |
458 | |
459 | __setup_vector_irq(cpu); | |
460 | } | |
461 | ||
7f3262ed | 462 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 463 | { |
7f3262ed | 464 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
465 | unsigned long flags; |
466 | int cpu; | |
467 | ||
468 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
469 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
470 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
471 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
472 | ||
473 | return 1; | |
474 | } | |
475 | ||
476 | void apic_ack_edge(struct irq_data *data) | |
477 | { | |
a9786091 | 478 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
479 | irq_move_irq(data); |
480 | ack_APIC_irq(); | |
481 | } | |
482 | ||
68f9f440 JL |
483 | static int apic_set_affinity(struct irq_data *irq_data, |
484 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 485 | { |
7f3262ed | 486 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
487 | int err, irq = irq_data->irq; |
488 | ||
489 | if (!config_enabled(CONFIG_SMP)) | |
490 | return -EPERM; | |
491 | ||
492 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
493 | return -EINVAL; | |
494 | ||
7f3262ed | 495 | err = assign_irq_vector(irq, data, dest); |
b5dc8e6c JL |
496 | if (err) { |
497 | struct irq_data *top = irq_get_irq_data(irq); | |
498 | ||
7f3262ed | 499 | if (assign_irq_vector(irq, data, top->affinity)) |
b5dc8e6c JL |
500 | pr_err("Failed to recover vector for irq %d\n", irq); |
501 | return err; | |
502 | } | |
503 | ||
504 | return IRQ_SET_MASK_OK; | |
505 | } | |
506 | ||
507 | static struct irq_chip lapic_controller = { | |
508 | .irq_ack = apic_ack_edge, | |
68f9f440 | 509 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
510 | .irq_retrigger = apic_retrigger_irq, |
511 | }; | |
512 | ||
74afab7a | 513 | #ifdef CONFIG_SMP |
7f3262ed | 514 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a JL |
515 | { |
516 | cpumask_var_t cleanup_mask; | |
517 | ||
518 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
519 | unsigned int i; | |
520 | ||
7f3262ed | 521 | for_each_cpu_and(i, data->old_domain, cpu_online_mask) |
74afab7a JL |
522 | apic->send_IPI_mask(cpumask_of(i), |
523 | IRQ_MOVE_CLEANUP_VECTOR); | |
524 | } else { | |
7f3262ed | 525 | cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); |
74afab7a JL |
526 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
527 | free_cpumask_var(cleanup_mask); | |
528 | } | |
7f3262ed | 529 | data->move_in_progress = 0; |
74afab7a JL |
530 | } |
531 | ||
c6c2002b JL |
532 | void send_cleanup_vector(struct irq_cfg *cfg) |
533 | { | |
7f3262ed JL |
534 | struct apic_chip_data *data; |
535 | ||
536 | data = container_of(cfg, struct apic_chip_data, cfg); | |
537 | if (data->move_in_progress) | |
538 | __send_cleanup_vector(data); | |
c6c2002b JL |
539 | } |
540 | ||
74afab7a JL |
541 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
542 | { | |
543 | unsigned vector, me; | |
544 | ||
545 | ack_APIC_irq(); | |
546 | irq_enter(); | |
547 | exit_idle(); | |
548 | ||
549 | me = smp_processor_id(); | |
550 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
551 | int irq; | |
552 | unsigned int irr; | |
553 | struct irq_desc *desc; | |
7f3262ed | 554 | struct apic_chip_data *data; |
74afab7a JL |
555 | |
556 | irq = __this_cpu_read(vector_irq[vector]); | |
557 | ||
558 | if (irq <= VECTOR_UNDEFINED) | |
559 | continue; | |
560 | ||
561 | desc = irq_to_desc(irq); | |
562 | if (!desc) | |
563 | continue; | |
564 | ||
7f3262ed JL |
565 | data = apic_chip_data(&desc->irq_data); |
566 | if (!data) | |
74afab7a JL |
567 | continue; |
568 | ||
569 | raw_spin_lock(&desc->lock); | |
570 | ||
571 | /* | |
572 | * Check if the irq migration is in progress. If so, we | |
573 | * haven't received the cleanup request yet for this irq. | |
574 | */ | |
7f3262ed | 575 | if (data->move_in_progress) |
74afab7a JL |
576 | goto unlock; |
577 | ||
7f3262ed JL |
578 | if (vector == data->cfg.vector && |
579 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
580 | goto unlock; |
581 | ||
582 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
583 | /* | |
584 | * Check if the vector that needs to be cleanedup is | |
585 | * registered at the cpu's IRR. If so, then this is not | |
586 | * the best time to clean it up. Lets clean it up in the | |
587 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
588 | * to myself. | |
589 | */ | |
590 | if (irr & (1 << (vector % 32))) { | |
591 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
592 | goto unlock; | |
593 | } | |
594 | __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); | |
595 | unlock: | |
596 | raw_spin_unlock(&desc->lock); | |
597 | } | |
598 | ||
599 | irq_exit(); | |
600 | } | |
601 | ||
602 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
603 | { | |
604 | unsigned me; | |
7f3262ed | 605 | struct apic_chip_data *data; |
74afab7a | 606 | |
7f3262ed JL |
607 | data = container_of(cfg, struct apic_chip_data, cfg); |
608 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
609 | return; |
610 | ||
611 | me = smp_processor_id(); | |
7f3262ed JL |
612 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
613 | __send_cleanup_vector(data); | |
74afab7a JL |
614 | } |
615 | ||
616 | void irq_complete_move(struct irq_cfg *cfg) | |
617 | { | |
618 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
619 | } | |
620 | ||
621 | void irq_force_complete_move(int irq) | |
622 | { | |
623 | struct irq_cfg *cfg = irq_cfg(irq); | |
624 | ||
7f3262ed JL |
625 | if (cfg) |
626 | __irq_complete_move(cfg, cfg->vector); | |
74afab7a | 627 | } |
74afab7a JL |
628 | #endif |
629 | ||
74afab7a JL |
630 | static void __init print_APIC_field(int base) |
631 | { | |
632 | int i; | |
633 | ||
634 | printk(KERN_DEBUG); | |
635 | ||
636 | for (i = 0; i < 8; i++) | |
637 | pr_cont("%08x", apic_read(base + i*0x10)); | |
638 | ||
639 | pr_cont("\n"); | |
640 | } | |
641 | ||
642 | static void __init print_local_APIC(void *dummy) | |
643 | { | |
644 | unsigned int i, v, ver, maxlvt; | |
645 | u64 icr; | |
646 | ||
849d3569 JL |
647 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
648 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 649 | v = apic_read(APIC_ID); |
849d3569 | 650 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 651 | v = apic_read(APIC_LVR); |
849d3569 | 652 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
653 | ver = GET_APIC_VERSION(v); |
654 | maxlvt = lapic_get_maxlvt(); | |
655 | ||
656 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 657 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
658 | |
659 | /* !82489DX */ | |
660 | if (APIC_INTEGRATED(ver)) { | |
661 | if (!APIC_XAPIC(ver)) { | |
662 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
663 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
664 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
665 | } |
666 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 667 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
668 | } |
669 | ||
670 | /* | |
671 | * Remote read supported only in the 82489DX and local APIC for | |
672 | * Pentium processors. | |
673 | */ | |
674 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
675 | v = apic_read(APIC_RRR); | |
849d3569 | 676 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
677 | } |
678 | ||
679 | v = apic_read(APIC_LDR); | |
849d3569 | 680 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
681 | if (!x2apic_enabled()) { |
682 | v = apic_read(APIC_DFR); | |
849d3569 | 683 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
684 | } |
685 | v = apic_read(APIC_SPIV); | |
849d3569 | 686 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 687 | |
849d3569 | 688 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 689 | print_APIC_field(APIC_ISR); |
849d3569 | 690 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 691 | print_APIC_field(APIC_TMR); |
849d3569 | 692 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
693 | print_APIC_field(APIC_IRR); |
694 | ||
695 | /* !82489DX */ | |
696 | if (APIC_INTEGRATED(ver)) { | |
697 | /* Due to the Pentium erratum 3AP. */ | |
698 | if (maxlvt > 3) | |
699 | apic_write(APIC_ESR, 0); | |
700 | ||
701 | v = apic_read(APIC_ESR); | |
849d3569 | 702 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
703 | } |
704 | ||
705 | icr = apic_icr_read(); | |
849d3569 JL |
706 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
707 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
708 | |
709 | v = apic_read(APIC_LVTT); | |
849d3569 | 710 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
711 | |
712 | if (maxlvt > 3) { | |
713 | /* PC is LVT#4. */ | |
714 | v = apic_read(APIC_LVTPC); | |
849d3569 | 715 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
716 | } |
717 | v = apic_read(APIC_LVT0); | |
849d3569 | 718 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 719 | v = apic_read(APIC_LVT1); |
849d3569 | 720 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
721 | |
722 | if (maxlvt > 2) { | |
723 | /* ERR is LVT#3. */ | |
724 | v = apic_read(APIC_LVTERR); | |
849d3569 | 725 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
726 | } |
727 | ||
728 | v = apic_read(APIC_TMICT); | |
849d3569 | 729 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 730 | v = apic_read(APIC_TMCCT); |
849d3569 | 731 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 732 | v = apic_read(APIC_TDCR); |
849d3569 | 733 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
734 | |
735 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
736 | v = apic_read(APIC_EFEAT); | |
737 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 738 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 739 | v = apic_read(APIC_ECTRL); |
849d3569 | 740 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
741 | for (i = 0; i < maxlvt; i++) { |
742 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 743 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
744 | } |
745 | } | |
746 | pr_cont("\n"); | |
747 | } | |
748 | ||
749 | static void __init print_local_APICs(int maxcpu) | |
750 | { | |
751 | int cpu; | |
752 | ||
753 | if (!maxcpu) | |
754 | return; | |
755 | ||
756 | preempt_disable(); | |
757 | for_each_online_cpu(cpu) { | |
758 | if (cpu >= maxcpu) | |
759 | break; | |
760 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
761 | } | |
762 | preempt_enable(); | |
763 | } | |
764 | ||
765 | static void __init print_PIC(void) | |
766 | { | |
767 | unsigned int v; | |
768 | unsigned long flags; | |
769 | ||
770 | if (!nr_legacy_irqs()) | |
771 | return; | |
772 | ||
849d3569 | 773 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
774 | |
775 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
776 | ||
777 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 778 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
779 | |
780 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 781 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
782 | |
783 | outb(0x0b, 0xa0); | |
784 | outb(0x0b, 0x20); | |
785 | v = inb(0xa0) << 8 | inb(0x20); | |
786 | outb(0x0a, 0xa0); | |
787 | outb(0x0a, 0x20); | |
788 | ||
789 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
790 | ||
849d3569 | 791 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
792 | |
793 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 794 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
795 | } |
796 | ||
797 | static int show_lapic __initdata = 1; | |
798 | static __init int setup_show_lapic(char *arg) | |
799 | { | |
800 | int num = -1; | |
801 | ||
802 | if (strcmp(arg, "all") == 0) { | |
803 | show_lapic = CONFIG_NR_CPUS; | |
804 | } else { | |
805 | get_option(&arg, &num); | |
806 | if (num >= 0) | |
807 | show_lapic = num; | |
808 | } | |
809 | ||
810 | return 1; | |
811 | } | |
812 | __setup("show_lapic=", setup_show_lapic); | |
813 | ||
814 | static int __init print_ICs(void) | |
815 | { | |
816 | if (apic_verbosity == APIC_QUIET) | |
817 | return 0; | |
818 | ||
819 | print_PIC(); | |
820 | ||
821 | /* don't print out if apic is not there */ | |
822 | if (!cpu_has_apic && !apic_from_smp_config()) | |
823 | return 0; | |
824 | ||
825 | print_local_APICs(show_lapic); | |
826 | print_IO_APICs(); | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
831 | late_initcall(print_ICs); |