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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
65d7ed57 | 14 | #include <linux/seq_file.h> |
74afab7a JL |
15 | #include <linux/init.h> |
16 | #include <linux/compiler.h> | |
74afab7a | 17 | #include <linux/slab.h> |
d746d1eb | 18 | #include <asm/irqdomain.h> |
74afab7a JL |
19 | #include <asm/hw_irq.h> |
20 | #include <asm/apic.h> | |
21 | #include <asm/i8259.h> | |
22 | #include <asm/desc.h> | |
23 | #include <asm/irq_remapping.h> | |
24 | ||
7f3262ed JL |
25 | struct apic_chip_data { |
26 | struct irq_cfg cfg; | |
029c6e1c TG |
27 | unsigned int cpu; |
28 | unsigned int prev_cpu; | |
dccfe314 | 29 | struct hlist_node clist; |
7f3262ed JL |
30 | cpumask_var_t domain; |
31 | cpumask_var_t old_domain; | |
32 | u8 move_in_progress : 1; | |
33 | }; | |
34 | ||
b5dc8e6c | 35 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 36 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 37 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 38 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 39 | static struct irq_chip lapic_controller; |
0fa115da | 40 | static struct irq_matrix *vector_matrix; |
dccfe314 TG |
41 | #ifdef CONFIG_SMP |
42 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
43 | #endif | |
74afab7a JL |
44 | |
45 | void lock_vector_lock(void) | |
46 | { | |
47 | /* Used to the online set of cpus does not change | |
48 | * during assign_irq_vector. | |
49 | */ | |
50 | raw_spin_lock(&vector_lock); | |
51 | } | |
52 | ||
53 | void unlock_vector_lock(void) | |
54 | { | |
55 | raw_spin_unlock(&vector_lock); | |
56 | } | |
57 | ||
99a1482d TG |
58 | void init_irq_alloc_info(struct irq_alloc_info *info, |
59 | const struct cpumask *mask) | |
60 | { | |
61 | memset(info, 0, sizeof(*info)); | |
62 | info->mask = mask; | |
63 | } | |
64 | ||
65 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
66 | { | |
67 | if (src) | |
68 | *dst = *src; | |
69 | else | |
70 | memset(dst, 0, sizeof(*dst)); | |
71 | } | |
72 | ||
86ba6551 | 73 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 74 | { |
86ba6551 | 75 | if (!irqd) |
b5dc8e6c JL |
76 | return NULL; |
77 | ||
86ba6551 TG |
78 | while (irqd->parent_data) |
79 | irqd = irqd->parent_data; | |
b5dc8e6c | 80 | |
86ba6551 | 81 | return irqd->chip_data; |
74afab7a JL |
82 | } |
83 | ||
86ba6551 | 84 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 85 | { |
86ba6551 | 86 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 87 | |
86ba6551 | 88 | return apicd ? &apicd->cfg : NULL; |
7f3262ed | 89 | } |
c8f3e518 | 90 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
91 | |
92 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 93 | { |
7f3262ed JL |
94 | return irqd_cfg(irq_get_irq_data(irq)); |
95 | } | |
74afab7a | 96 | |
7f3262ed JL |
97 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
98 | { | |
86ba6551 | 99 | struct apic_chip_data *apicd; |
7f3262ed | 100 | |
86ba6551 TG |
101 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
102 | if (!apicd) | |
74afab7a | 103 | return NULL; |
86ba6551 | 104 | if (!zalloc_cpumask_var_node(&apicd->domain, GFP_KERNEL, node)) |
7f3262ed | 105 | goto out_data; |
86ba6551 | 106 | if (!zalloc_cpumask_var_node(&apicd->old_domain, GFP_KERNEL, node)) |
74afab7a | 107 | goto out_domain; |
dccfe314 | 108 | INIT_HLIST_NODE(&apicd->clist); |
86ba6551 | 109 | return apicd; |
74afab7a | 110 | out_domain: |
86ba6551 | 111 | free_cpumask_var(apicd->domain); |
7f3262ed | 112 | out_data: |
86ba6551 | 113 | kfree(apicd); |
74afab7a JL |
114 | return NULL; |
115 | } | |
116 | ||
86ba6551 | 117 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 118 | { |
86ba6551 TG |
119 | if (apicd) { |
120 | free_cpumask_var(apicd->domain); | |
121 | free_cpumask_var(apicd->old_domain); | |
122 | kfree(apicd); | |
b5dc8e6c | 123 | } |
74afab7a JL |
124 | } |
125 | ||
7f3262ed | 126 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
0e24f7c9 | 127 | const struct cpumask *mask, |
86ba6551 | 128 | struct irq_data *irqd) |
74afab7a JL |
129 | { |
130 | /* | |
131 | * NOTE! The local APIC isn't very good at handling | |
132 | * multiple interrupts at the same interrupt level. | |
133 | * As the interrupt level is determined by taking the | |
134 | * vector number and shifting that right by 4, we | |
135 | * want to spread these out a bit so that they don't | |
136 | * all fall in the same interrupt level. | |
137 | * | |
138 | * Also, we've got to be careful not to trash gate | |
139 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
140 | */ | |
141 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
142 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 143 | int cpu, vector; |
74afab7a | 144 | |
98229aa3 TG |
145 | /* |
146 | * If there is still a move in progress or the previous move has not | |
147 | * been cleaned up completely, tell the caller to come back later. | |
148 | */ | |
dccfe314 | 149 | if (d->cfg.old_vector) |
74afab7a JL |
150 | return -EBUSY; |
151 | ||
74afab7a | 152 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 153 | cpumask_clear(d->old_domain); |
8a580f70 | 154 | cpumask_clear(searched_cpumask); |
74afab7a JL |
155 | cpu = cpumask_first_and(mask, cpu_online_mask); |
156 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 157 | int new_cpu, offset; |
74afab7a | 158 | |
fdba46ff | 159 | cpumask_copy(vector_cpumask, cpumask_of(cpu)); |
74afab7a | 160 | |
3716fd27 TG |
161 | /* |
162 | * Clear the offline cpus from @vector_cpumask for searching | |
163 | * and verify whether the result overlaps with @mask. If true, | |
91cd9cb7 | 164 | * then the call to apic->cpu_mask_to_apicid() will |
3716fd27 TG |
165 | * succeed as well. If not, no point in trying to find a |
166 | * vector in this mask. | |
167 | */ | |
168 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
169 | if (!cpumask_intersects(vector_searchmask, mask)) | |
170 | goto next_cpu; | |
171 | ||
f7fa7aee | 172 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 173 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 174 | goto success; |
74afab7a | 175 | /* |
ab25ac02 TG |
176 | * Mark the cpus which are not longer in the mask for |
177 | * cleanup. | |
74afab7a | 178 | */ |
ab25ac02 TG |
179 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
180 | vector = d->cfg.vector; | |
181 | goto update; | |
74afab7a JL |
182 | } |
183 | ||
184 | vector = current_vector; | |
185 | offset = current_offset; | |
186 | next: | |
187 | vector += 16; | |
05161b9c | 188 | if (vector >= FIRST_SYSTEM_VECTOR) { |
74afab7a JL |
189 | offset = (offset + 1) % 16; |
190 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
191 | } | |
192 | ||
95ffeb4b TG |
193 | /* If the search wrapped around, try the next cpu */ |
194 | if (unlikely(current_vector == vector)) | |
195 | goto next_cpu; | |
74afab7a | 196 | |
7854f822 | 197 | if (test_bit(vector, system_vectors)) |
74afab7a JL |
198 | goto next; |
199 | ||
3716fd27 | 200 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 201 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
202 | goto next; |
203 | } | |
204 | /* Found one! */ | |
205 | current_vector = vector; | |
206 | current_offset = offset; | |
ab25ac02 TG |
207 | /* Schedule the old vector for cleanup on all cpus */ |
208 | if (d->cfg.vector) | |
7f3262ed | 209 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 210 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 211 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 212 | goto update; |
95ffeb4b TG |
213 | |
214 | next_cpu: | |
215 | /* | |
216 | * We exclude the current @vector_cpumask from the requested | |
217 | * @mask and try again with the next online cpu in the | |
218 | * result. We cannot modify @mask, so we use @vector_cpumask | |
219 | * as a temporary buffer here as it will be reassigned when | |
220 | * calling apic->vector_allocation_domain() above. | |
221 | */ | |
222 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
223 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
224 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
225 | continue; | |
74afab7a | 226 | } |
433cbd57 | 227 | return -ENOSPC; |
74afab7a | 228 | |
ab25ac02 | 229 | update: |
847667ef TG |
230 | /* |
231 | * Exclude offline cpus from the cleanup mask and set the | |
232 | * move_in_progress flag when the result is not empty. | |
233 | */ | |
234 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
235 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
551adc60 | 236 | d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; |
029c6e1c | 237 | d->prev_cpu = d->cpu; |
ab25ac02 TG |
238 | d->cfg.vector = vector; |
239 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 240 | success: |
3716fd27 TG |
241 | /* |
242 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
243 | * as we already established, that mask & d->domain & cpu_online_mask | |
244 | * is not empty. | |
52b166af TG |
245 | * |
246 | * vector_searchmask is a subset of d->domain and has the offline | |
247 | * cpus masked out. | |
3716fd27 | 248 | */ |
91cd9cb7 | 249 | cpumask_and(vector_searchmask, vector_searchmask, mask); |
86ba6551 | 250 | BUG_ON(apic->cpu_mask_to_apicid(vector_searchmask, irqd, |
0e24f7c9 | 251 | &d->cfg.dest_apicid)); |
029c6e1c | 252 | d->cpu = cpumask_first(vector_searchmask); |
3716fd27 | 253 | return 0; |
74afab7a JL |
254 | } |
255 | ||
86ba6551 | 256 | static int assign_irq_vector(int irq, struct apic_chip_data *apicd, |
0e24f7c9 | 257 | const struct cpumask *mask, |
86ba6551 | 258 | struct irq_data *irqd) |
74afab7a JL |
259 | { |
260 | int err; | |
261 | unsigned long flags; | |
262 | ||
263 | raw_spin_lock_irqsave(&vector_lock, flags); | |
86ba6551 | 264 | err = __assign_irq_vector(irq, apicd, mask, irqd); |
74afab7a JL |
265 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
266 | return err; | |
267 | } | |
268 | ||
486ca539 | 269 | static int assign_irq_vector_policy(int irq, int node, |
86ba6551 | 270 | struct apic_chip_data *apicd, |
0e24f7c9 | 271 | struct irq_alloc_info *info, |
86ba6551 | 272 | struct irq_data *irqd) |
486ca539 | 273 | { |
258d86ee | 274 | if (info->mask) |
86ba6551 | 275 | return assign_irq_vector(irq, apicd, info->mask, irqd); |
486ca539 | 276 | if (node != NUMA_NO_NODE && |
86ba6551 | 277 | assign_irq_vector(irq, apicd, cpumask_of_node(node), irqd) == 0) |
486ca539 | 278 | return 0; |
86ba6551 | 279 | return assign_irq_vector(irq, apicd, cpu_online_mask, irqd); |
486ca539 JL |
280 | } |
281 | ||
86ba6551 | 282 | static void clear_irq_vector(int irq, struct apic_chip_data *apicd) |
74afab7a | 283 | { |
dccfe314 | 284 | unsigned int vector = apicd->cfg.vector; |
74afab7a | 285 | |
dccfe314 | 286 | if (!vector) |
1bdb8970 | 287 | return; |
74afab7a | 288 | |
dccfe314 | 289 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 290 | apicd->cfg.vector = 0; |
74afab7a | 291 | |
dccfe314 TG |
292 | /* Clean up move in progress */ |
293 | vector = apicd->cfg.old_vector; | |
294 | if (!vector) | |
74afab7a | 295 | return; |
74afab7a | 296 | |
dccfe314 | 297 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 298 | apicd->move_in_progress = 0; |
dccfe314 | 299 | hlist_del_init(&apicd->clist); |
74afab7a JL |
300 | } |
301 | ||
b5dc8e6c JL |
302 | static void x86_vector_free_irqs(struct irq_domain *domain, |
303 | unsigned int virq, unsigned int nr_irqs) | |
304 | { | |
86ba6551 TG |
305 | struct apic_chip_data *apicd; |
306 | struct irq_data *irqd; | |
111abeba | 307 | unsigned long flags; |
b5dc8e6c JL |
308 | int i; |
309 | ||
310 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
311 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
312 | if (irqd && irqd->chip_data) { | |
111abeba | 313 | raw_spin_lock_irqsave(&vector_lock, flags); |
86ba6551 TG |
314 | clear_irq_vector(virq + i, irqd->chip_data); |
315 | apicd = irqd->chip_data; | |
316 | irq_domain_reset_irq_data(irqd); | |
111abeba | 317 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 318 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
319 | } |
320 | } | |
321 | } | |
322 | ||
323 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
324 | unsigned int nr_irqs, void *arg) | |
325 | { | |
326 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
327 | struct apic_chip_data *apicd; |
328 | struct irq_data *irqd; | |
5f2dbbc5 | 329 | int i, err, node; |
b5dc8e6c JL |
330 | |
331 | if (disable_apic) | |
332 | return -ENXIO; | |
333 | ||
334 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
335 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
336 | return -ENOSYS; | |
337 | ||
b5dc8e6c | 338 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
339 | irqd = irq_domain_get_irq_data(domain, virq + i); |
340 | BUG_ON(!irqd); | |
341 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
342 | WARN_ON_ONCE(irqd->chip_data); |
343 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 344 | if (!apicd) { |
b5dc8e6c JL |
345 | err = -ENOMEM; |
346 | goto error; | |
347 | } | |
348 | ||
86ba6551 TG |
349 | irqd->chip = &lapic_controller; |
350 | irqd->chip_data = apicd; | |
351 | irqd->hwirq = virq + i; | |
352 | irqd_set_single_target(irqd); | |
4ef76eb6 TG |
353 | /* |
354 | * Make sure, that the legacy to IOAPIC transition stays on | |
355 | * the same vector. This is required for check_timer() to | |
356 | * work correctly as it might switch back to legacy mode. | |
357 | */ | |
358 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
359 | apicd->cfg.vector = ISA_IRQ_VECTOR(virq + i); | |
360 | apicd->cpu = 0; | |
361 | cpumask_copy(apicd->domain, cpumask_of(0)); | |
362 | } | |
363 | ||
86ba6551 TG |
364 | err = assign_irq_vector_policy(virq + i, node, apicd, info, |
365 | irqd); | |
b5dc8e6c JL |
366 | if (err) |
367 | goto error; | |
368 | } | |
369 | ||
370 | return 0; | |
371 | ||
372 | error: | |
373 | x86_vector_free_irqs(domain, virq, i + 1); | |
374 | return err; | |
375 | } | |
376 | ||
65d7ed57 TG |
377 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
378 | void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, | |
379 | struct irq_data *irqd, int ind) | |
380 | { | |
381 | unsigned int cpu, vec, prev_cpu, prev_vec; | |
382 | struct apic_chip_data *apicd; | |
383 | unsigned long flags; | |
384 | int irq; | |
385 | ||
386 | if (!irqd) { | |
387 | irq_matrix_debug_show(m, vector_matrix, ind); | |
388 | return; | |
389 | } | |
390 | ||
391 | irq = irqd->irq; | |
392 | if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { | |
393 | seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); | |
394 | seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); | |
395 | return; | |
396 | } | |
397 | ||
398 | apicd = irqd->chip_data; | |
399 | if (!apicd) { | |
400 | seq_printf(m, "%*sVector: Not assigned\n", ind, ""); | |
401 | return; | |
402 | } | |
403 | ||
404 | raw_spin_lock_irqsave(&vector_lock, flags); | |
405 | cpu = apicd->cpu; | |
406 | vec = apicd->cfg.vector; | |
407 | prev_cpu = apicd->prev_cpu; | |
408 | prev_vec = apicd->cfg.old_vector; | |
409 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
410 | seq_printf(m, "%*sVector: %5u\n", ind, "", vec); | |
411 | seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu); | |
412 | if (prev_vec) { | |
413 | seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vec); | |
414 | seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu); | |
415 | } | |
416 | } | |
417 | #endif | |
418 | ||
eb18cf55 | 419 | static const struct irq_domain_ops x86_vector_domain_ops = { |
65d7ed57 TG |
420 | .alloc = x86_vector_alloc_irqs, |
421 | .free = x86_vector_free_irqs, | |
422 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS | |
423 | .debug_show = x86_vector_debug_show, | |
424 | #endif | |
b5dc8e6c JL |
425 | }; |
426 | ||
11d686e9 JL |
427 | int __init arch_probe_nr_irqs(void) |
428 | { | |
429 | int nr; | |
430 | ||
431 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
432 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
433 | ||
434 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
435 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
436 | /* | |
437 | * for MSI and HT dyn irq | |
438 | */ | |
439 | if (gsi_top <= NR_IRQS_LEGACY) | |
440 | nr += 8 * nr_cpu_ids; | |
441 | else | |
442 | nr += gsi_top * 16; | |
443 | #endif | |
444 | if (nr < nr_irqs) | |
445 | nr_irqs = nr; | |
446 | ||
8c058b0b VK |
447 | /* |
448 | * We don't know if PIC is present at this point so we need to do | |
449 | * probe() to get the right number of legacy IRQs. | |
450 | */ | |
451 | return legacy_pic->probe(); | |
11d686e9 JL |
452 | } |
453 | ||
0fa115da TG |
454 | void lapic_assign_legacy_vector(unsigned int irq, bool replace) |
455 | { | |
456 | /* | |
457 | * Use assign system here so it wont get accounted as allocated | |
458 | * and moveable in the cpu hotplug check and it prevents managed | |
459 | * irq reservation from touching it. | |
460 | */ | |
461 | irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); | |
462 | } | |
463 | ||
464 | void __init lapic_assign_system_vectors(void) | |
465 | { | |
466 | unsigned int i, vector = 0; | |
467 | ||
468 | for_each_set_bit_from(vector, system_vectors, NR_VECTORS) | |
469 | irq_matrix_assign_system(vector_matrix, vector, false); | |
470 | ||
471 | if (nr_legacy_irqs() > 1) | |
472 | lapic_assign_legacy_vector(PIC_CASCADE_IR, false); | |
473 | ||
474 | /* System vectors are reserved, online it */ | |
475 | irq_matrix_online(vector_matrix); | |
476 | ||
477 | /* Mark the preallocated legacy interrupts */ | |
478 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
479 | if (i != PIC_CASCADE_IR) | |
480 | irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); | |
481 | } | |
482 | } | |
483 | ||
11d686e9 JL |
484 | int __init arch_early_irq_init(void) |
485 | { | |
9d35f859 TG |
486 | struct fwnode_handle *fn; |
487 | ||
9d35f859 TG |
488 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
489 | BUG_ON(!fn); | |
490 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
491 | NULL); | |
b5dc8e6c | 492 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 493 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
494 | irq_set_default_host(x86_vector_domain); |
495 | ||
52f518a3 | 496 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 497 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 498 | |
f7fa7aee | 499 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 500 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 501 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 502 | |
0fa115da TG |
503 | /* |
504 | * Allocate the vector matrix allocator data structure and limit the | |
505 | * search area. | |
506 | */ | |
507 | vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, | |
508 | FIRST_SYSTEM_VECTOR); | |
509 | BUG_ON(!vector_matrix); | |
510 | ||
11d686e9 JL |
511 | return arch_early_ioapic_init(); |
512 | } | |
513 | ||
f0cc6cca TG |
514 | /* Temporary hack to keep things working */ |
515 | static void vector_update_shutdown_irqs(void) | |
74afab7a | 516 | { |
a782a7e4 | 517 | struct irq_desc *desc; |
f0cc6cca | 518 | int irq; |
74afab7a | 519 | |
a782a7e4 | 520 | for_each_irq_desc(irq, desc) { |
f0cc6cca TG |
521 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
522 | struct apic_chip_data *ad = apic_chip_data(irqd); | |
74afab7a | 523 | |
dccfe314 | 524 | if (ad && ad->cfg.vector && ad->cpu == smp_processor_id()) |
f0cc6cca | 525 | this_cpu_write(vector_irq[ad->cfg.vector], desc); |
74afab7a | 526 | } |
74afab7a JL |
527 | } |
528 | ||
f0cc6cca TG |
529 | static struct irq_desc *__setup_vector_irq(int vector) |
530 | { | |
531 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
532 | ||
533 | /* Check whether the irq is in the legacy space */ | |
534 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
535 | return VECTOR_UNUSED; | |
536 | /* Check whether the irq is handled by the IOAPIC */ | |
537 | if (test_bit(isairq, &io_apic_irqs)) | |
538 | return VECTOR_UNUSED; | |
539 | return irq_to_desc(isairq); | |
540 | } | |
541 | ||
0fa115da TG |
542 | /* Online the local APIC infrastructure and initialize the vectors */ |
543 | void lapic_online(void) | |
74afab7a | 544 | { |
f0cc6cca | 545 | unsigned int vector; |
74afab7a | 546 | |
5a3f75e3 | 547 | lockdep_assert_held(&vector_lock); |
0fa115da TG |
548 | |
549 | /* Online the vector matrix array for this CPU */ | |
550 | irq_matrix_online(vector_matrix); | |
551 | ||
74afab7a | 552 | /* |
f0cc6cca TG |
553 | * The interrupt affinity logic never targets interrupts to offline |
554 | * CPUs. The exception are the legacy PIC interrupts. In general | |
555 | * they are only targeted to CPU0, but depending on the platform | |
556 | * they can be distributed to any online CPU in hardware. The | |
557 | * kernel has no influence on that. So all active legacy vectors | |
558 | * must be installed on all CPUs. All non legacy interrupts can be | |
559 | * cleared. | |
74afab7a | 560 | */ |
f0cc6cca TG |
561 | for (vector = 0; vector < NR_VECTORS; vector++) |
562 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a | 563 | |
f0cc6cca TG |
564 | /* |
565 | * Until the rewrite of the managed interrupt management is in | |
566 | * place it's necessary to walk the irq descriptors and check for | |
567 | * interrupts which are targeted at this CPU. | |
568 | */ | |
569 | vector_update_shutdown_irqs(); | |
74afab7a JL |
570 | } |
571 | ||
0fa115da TG |
572 | void lapic_offline(void) |
573 | { | |
574 | lock_vector_lock(); | |
575 | irq_matrix_offline(vector_matrix); | |
576 | unlock_vector_lock(); | |
577 | } | |
578 | ||
86ba6551 | 579 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 580 | { |
86ba6551 | 581 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 582 | unsigned long flags; |
74afab7a JL |
583 | |
584 | raw_spin_lock_irqsave(&vector_lock, flags); | |
dccfe314 | 585 | apic->send_IPI(apicd->cpu, apicd->cfg.vector); |
74afab7a JL |
586 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
587 | ||
588 | return 1; | |
589 | } | |
590 | ||
86ba6551 | 591 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 592 | { |
86ba6551 TG |
593 | irq_complete_move(irqd_cfg(irqd)); |
594 | irq_move_irq(irqd); | |
74afab7a JL |
595 | ack_APIC_irq(); |
596 | } | |
597 | ||
86ba6551 | 598 | static int apic_set_affinity(struct irq_data *irqd, |
68f9f440 | 599 | const struct cpumask *dest, bool force) |
b5dc8e6c | 600 | { |
86ba6551 TG |
601 | struct apic_chip_data *apicd = irqd->chip_data; |
602 | int err, irq = irqd->irq; | |
b5dc8e6c | 603 | |
97f2645f | 604 | if (!IS_ENABLED(CONFIG_SMP)) |
b5dc8e6c JL |
605 | return -EPERM; |
606 | ||
607 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
608 | return -EINVAL; | |
609 | ||
86ba6551 | 610 | err = assign_irq_vector(irq, apicd, dest, irqd); |
3716fd27 | 611 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
612 | } |
613 | ||
614 | static struct irq_chip lapic_controller = { | |
8947dfb2 | 615 | .name = "APIC", |
b5dc8e6c | 616 | .irq_ack = apic_ack_edge, |
68f9f440 | 617 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
618 | .irq_retrigger = apic_retrigger_irq, |
619 | }; | |
620 | ||
74afab7a | 621 | #ifdef CONFIG_SMP |
c6c2002b | 622 | |
c4158ff5 | 623 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 624 | { |
dccfe314 TG |
625 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
626 | struct apic_chip_data *apicd; | |
627 | struct hlist_node *tmp; | |
74afab7a | 628 | |
6af7faf6 | 629 | entering_ack_irq(); |
df54c493 TG |
630 | /* Prevent vectors vanishing under us */ |
631 | raw_spin_lock(&vector_lock); | |
632 | ||
dccfe314 TG |
633 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
634 | unsigned int irr, vector = apicd->cfg.old_vector; | |
74afab7a | 635 | |
74afab7a | 636 | /* |
dccfe314 TG |
637 | * Paranoia: Check if the vector that needs to be cleaned |
638 | * up is registered at the APICs IRR. If so, then this is | |
639 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 640 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
641 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
642 | * priority external vector, so on return from this | |
643 | * interrupt the device interrupt will happen first. | |
74afab7a | 644 | */ |
dccfe314 TG |
645 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
646 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 647 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 648 | continue; |
74afab7a | 649 | } |
dccfe314 | 650 | hlist_del_init(&apicd->clist); |
7276c6a2 | 651 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
dccfe314 | 652 | apicd->cfg.old_vector = 0; |
74afab7a JL |
653 | } |
654 | ||
df54c493 | 655 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 656 | exiting_irq(); |
74afab7a JL |
657 | } |
658 | ||
dccfe314 TG |
659 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
660 | { | |
661 | unsigned int cpu; | |
662 | ||
663 | raw_spin_lock(&vector_lock); | |
664 | apicd->move_in_progress = 0; | |
665 | cpu = apicd->prev_cpu; | |
666 | if (cpu_online(cpu)) { | |
667 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
668 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
669 | } else { | |
670 | apicd->cfg.old_vector = 0; | |
671 | } | |
672 | raw_spin_unlock(&vector_lock); | |
673 | } | |
674 | ||
675 | void send_cleanup_vector(struct irq_cfg *cfg) | |
676 | { | |
677 | struct apic_chip_data *apicd; | |
678 | ||
679 | apicd = container_of(cfg, struct apic_chip_data, cfg); | |
680 | if (apicd->move_in_progress) | |
681 | __send_cleanup_vector(apicd); | |
682 | } | |
683 | ||
74afab7a JL |
684 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
685 | { | |
86ba6551 | 686 | struct apic_chip_data *apicd; |
74afab7a | 687 | |
86ba6551 TG |
688 | apicd = container_of(cfg, struct apic_chip_data, cfg); |
689 | if (likely(!apicd->move_in_progress)) | |
74afab7a JL |
690 | return; |
691 | ||
dccfe314 | 692 | if (vector == apicd->cfg.vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 693 | __send_cleanup_vector(apicd); |
74afab7a JL |
694 | } |
695 | ||
696 | void irq_complete_move(struct irq_cfg *cfg) | |
697 | { | |
698 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
699 | } | |
700 | ||
90a2282e | 701 | /* |
551adc60 | 702 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
703 | */ |
704 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 705 | { |
86ba6551 | 706 | struct apic_chip_data *apicd; |
dccfe314 TG |
707 | struct irq_data *irqd; |
708 | unsigned int vector; | |
56d7d2f4 | 709 | |
db91aa79 MW |
710 | /* |
711 | * The function is called for all descriptors regardless of which | |
712 | * irqdomain they belong to. For example if an IRQ is provided by | |
713 | * an irq_chip as part of a GPIO driver, the chip data for that | |
714 | * descriptor is specific to the irq_chip in question. | |
715 | * | |
716 | * Check first that the chip_data is what we expect | |
717 | * (apic_chip_data) before touching it any further. | |
718 | */ | |
86ba6551 | 719 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 720 | irq_desc_get_irq(desc)); |
86ba6551 | 721 | if (!irqd) |
db91aa79 MW |
722 | return; |
723 | ||
dccfe314 | 724 | raw_spin_lock(&vector_lock); |
86ba6551 | 725 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
726 | if (!apicd) |
727 | goto unlock; | |
db91aa79 | 728 | |
dccfe314 TG |
729 | /* |
730 | * If old_vector is empty, no action required. | |
731 | */ | |
732 | vector = apicd->cfg.old_vector; | |
733 | if (!vector) | |
734 | goto unlock; | |
74afab7a | 735 | |
56d7d2f4 | 736 | /* |
dccfe314 | 737 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
738 | * done yet, then the following setaffinity call will fail with |
739 | * -EBUSY. This can leave the interrupt in a stale state. | |
740 | * | |
551adc60 TG |
741 | * All CPUs are stuck in stop machine with interrupts disabled so |
742 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 743 | * |
551adc60 TG |
744 | * 1) The interrupt is in move_in_progress state. That means that we |
745 | * have not seen an interrupt since the io_apic was reprogrammed to | |
746 | * the new vector. | |
747 | * | |
748 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
749 | * have not been processed yet. | |
750 | */ | |
86ba6551 | 751 | if (apicd->move_in_progress) { |
98229aa3 | 752 | /* |
551adc60 TG |
753 | * In theory there is a race: |
754 | * | |
755 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
756 | * is effective, i.e. it's raised on | |
757 | * the old vector. | |
758 | * | |
759 | * So if the target cpu cannot handle that interrupt before | |
760 | * the old vector is cleaned up, we get a spurious interrupt | |
761 | * and in the worst case the ioapic irq line becomes stale. | |
762 | * | |
763 | * But in case of cpu hotplug this should be a non issue | |
764 | * because if the affinity update happens right before all | |
765 | * cpus rendevouz in stop machine, there is no way that the | |
766 | * interrupt can be blocked on the target cpu because all cpus | |
767 | * loops first with interrupts enabled in stop machine, so the | |
768 | * old vector is not yet cleaned up when the interrupt fires. | |
769 | * | |
770 | * So the only way to run into this issue is if the delivery | |
771 | * of the interrupt on the apic/system bus would be delayed | |
772 | * beyond the point where the target cpu disables interrupts | |
773 | * in stop machine. I doubt that it can happen, but at least | |
774 | * there is a theroretical chance. Virtualization might be | |
775 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
776 | * as stupid as the real hardware. | |
777 | * | |
778 | * Anyway, there is nothing we can do about that at this point | |
779 | * w/o refactoring the whole fixup_irq() business completely. | |
780 | * We print at least the irq number and the old vector number, | |
781 | * so we have the necessary information when a problem in that | |
782 | * area arises. | |
98229aa3 | 783 | */ |
551adc60 | 784 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 785 | irqd->irq, vector); |
98229aa3 | 786 | } |
dccfe314 | 787 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
551adc60 | 788 | /* Cleanup the left overs of the (half finished) move */ |
86ba6551 | 789 | cpumask_clear(apicd->old_domain); |
dccfe314 | 790 | apicd->cfg.old_vector = 0; |
86ba6551 | 791 | apicd->move_in_progress = 0; |
dccfe314 TG |
792 | hlist_del_init(&apicd->clist); |
793 | unlock: | |
56d7d2f4 | 794 | raw_spin_unlock(&vector_lock); |
74afab7a | 795 | } |
74afab7a JL |
796 | #endif |
797 | ||
74afab7a JL |
798 | static void __init print_APIC_field(int base) |
799 | { | |
800 | int i; | |
801 | ||
802 | printk(KERN_DEBUG); | |
803 | ||
804 | for (i = 0; i < 8; i++) | |
805 | pr_cont("%08x", apic_read(base + i*0x10)); | |
806 | ||
807 | pr_cont("\n"); | |
808 | } | |
809 | ||
810 | static void __init print_local_APIC(void *dummy) | |
811 | { | |
812 | unsigned int i, v, ver, maxlvt; | |
813 | u64 icr; | |
814 | ||
849d3569 JL |
815 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
816 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 817 | v = apic_read(APIC_ID); |
849d3569 | 818 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 819 | v = apic_read(APIC_LVR); |
849d3569 | 820 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
821 | ver = GET_APIC_VERSION(v); |
822 | maxlvt = lapic_get_maxlvt(); | |
823 | ||
824 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 825 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
826 | |
827 | /* !82489DX */ | |
828 | if (APIC_INTEGRATED(ver)) { | |
829 | if (!APIC_XAPIC(ver)) { | |
830 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
831 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
832 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
833 | } |
834 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 835 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
836 | } |
837 | ||
838 | /* | |
839 | * Remote read supported only in the 82489DX and local APIC for | |
840 | * Pentium processors. | |
841 | */ | |
842 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
843 | v = apic_read(APIC_RRR); | |
849d3569 | 844 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
845 | } |
846 | ||
847 | v = apic_read(APIC_LDR); | |
849d3569 | 848 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
849 | if (!x2apic_enabled()) { |
850 | v = apic_read(APIC_DFR); | |
849d3569 | 851 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
852 | } |
853 | v = apic_read(APIC_SPIV); | |
849d3569 | 854 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 855 | |
849d3569 | 856 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 857 | print_APIC_field(APIC_ISR); |
849d3569 | 858 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 859 | print_APIC_field(APIC_TMR); |
849d3569 | 860 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
861 | print_APIC_field(APIC_IRR); |
862 | ||
863 | /* !82489DX */ | |
864 | if (APIC_INTEGRATED(ver)) { | |
865 | /* Due to the Pentium erratum 3AP. */ | |
866 | if (maxlvt > 3) | |
867 | apic_write(APIC_ESR, 0); | |
868 | ||
869 | v = apic_read(APIC_ESR); | |
849d3569 | 870 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
871 | } |
872 | ||
873 | icr = apic_icr_read(); | |
849d3569 JL |
874 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
875 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
876 | |
877 | v = apic_read(APIC_LVTT); | |
849d3569 | 878 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
879 | |
880 | if (maxlvt > 3) { | |
881 | /* PC is LVT#4. */ | |
882 | v = apic_read(APIC_LVTPC); | |
849d3569 | 883 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
884 | } |
885 | v = apic_read(APIC_LVT0); | |
849d3569 | 886 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 887 | v = apic_read(APIC_LVT1); |
849d3569 | 888 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
889 | |
890 | if (maxlvt > 2) { | |
891 | /* ERR is LVT#3. */ | |
892 | v = apic_read(APIC_LVTERR); | |
849d3569 | 893 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
894 | } |
895 | ||
896 | v = apic_read(APIC_TMICT); | |
849d3569 | 897 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 898 | v = apic_read(APIC_TMCCT); |
849d3569 | 899 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 900 | v = apic_read(APIC_TDCR); |
849d3569 | 901 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
902 | |
903 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
904 | v = apic_read(APIC_EFEAT); | |
905 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 906 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 907 | v = apic_read(APIC_ECTRL); |
849d3569 | 908 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
909 | for (i = 0; i < maxlvt; i++) { |
910 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 911 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
912 | } |
913 | } | |
914 | pr_cont("\n"); | |
915 | } | |
916 | ||
917 | static void __init print_local_APICs(int maxcpu) | |
918 | { | |
919 | int cpu; | |
920 | ||
921 | if (!maxcpu) | |
922 | return; | |
923 | ||
924 | preempt_disable(); | |
925 | for_each_online_cpu(cpu) { | |
926 | if (cpu >= maxcpu) | |
927 | break; | |
928 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
929 | } | |
930 | preempt_enable(); | |
931 | } | |
932 | ||
933 | static void __init print_PIC(void) | |
934 | { | |
935 | unsigned int v; | |
936 | unsigned long flags; | |
937 | ||
938 | if (!nr_legacy_irqs()) | |
939 | return; | |
940 | ||
849d3569 | 941 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
942 | |
943 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
944 | ||
945 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 946 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
947 | |
948 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 949 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
950 | |
951 | outb(0x0b, 0xa0); | |
952 | outb(0x0b, 0x20); | |
953 | v = inb(0xa0) << 8 | inb(0x20); | |
954 | outb(0x0a, 0xa0); | |
955 | outb(0x0a, 0x20); | |
956 | ||
957 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
958 | ||
849d3569 | 959 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
960 | |
961 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 962 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
963 | } |
964 | ||
965 | static int show_lapic __initdata = 1; | |
966 | static __init int setup_show_lapic(char *arg) | |
967 | { | |
968 | int num = -1; | |
969 | ||
970 | if (strcmp(arg, "all") == 0) { | |
971 | show_lapic = CONFIG_NR_CPUS; | |
972 | } else { | |
973 | get_option(&arg, &num); | |
974 | if (num >= 0) | |
975 | show_lapic = num; | |
976 | } | |
977 | ||
978 | return 1; | |
979 | } | |
980 | __setup("show_lapic=", setup_show_lapic); | |
981 | ||
982 | static int __init print_ICs(void) | |
983 | { | |
984 | if (apic_verbosity == APIC_QUIET) | |
985 | return 0; | |
986 | ||
987 | print_PIC(); | |
988 | ||
989 | /* don't print out if apic is not there */ | |
93984fbd | 990 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
991 | return 0; |
992 | ||
993 | print_local_APICs(show_lapic); | |
994 | print_IO_APICs(); | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
999 | late_initcall(print_ICs); |