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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
029c6e1c TG |
26 | unsigned int cpu; |
27 | unsigned int prev_cpu; | |
dccfe314 | 28 | struct hlist_node clist; |
7f3262ed JL |
29 | cpumask_var_t domain; |
30 | cpumask_var_t old_domain; | |
31 | u8 move_in_progress : 1; | |
32 | }; | |
33 | ||
b5dc8e6c | 34 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 35 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 36 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 37 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 38 | static struct irq_chip lapic_controller; |
dccfe314 TG |
39 | #ifdef CONFIG_SMP |
40 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
41 | #endif | |
74afab7a JL |
42 | |
43 | void lock_vector_lock(void) | |
44 | { | |
45 | /* Used to the online set of cpus does not change | |
46 | * during assign_irq_vector. | |
47 | */ | |
48 | raw_spin_lock(&vector_lock); | |
49 | } | |
50 | ||
51 | void unlock_vector_lock(void) | |
52 | { | |
53 | raw_spin_unlock(&vector_lock); | |
54 | } | |
55 | ||
99a1482d TG |
56 | void init_irq_alloc_info(struct irq_alloc_info *info, |
57 | const struct cpumask *mask) | |
58 | { | |
59 | memset(info, 0, sizeof(*info)); | |
60 | info->mask = mask; | |
61 | } | |
62 | ||
63 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
64 | { | |
65 | if (src) | |
66 | *dst = *src; | |
67 | else | |
68 | memset(dst, 0, sizeof(*dst)); | |
69 | } | |
70 | ||
86ba6551 | 71 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 72 | { |
86ba6551 | 73 | if (!irqd) |
b5dc8e6c JL |
74 | return NULL; |
75 | ||
86ba6551 TG |
76 | while (irqd->parent_data) |
77 | irqd = irqd->parent_data; | |
b5dc8e6c | 78 | |
86ba6551 | 79 | return irqd->chip_data; |
74afab7a JL |
80 | } |
81 | ||
86ba6551 | 82 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 83 | { |
86ba6551 | 84 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 85 | |
86ba6551 | 86 | return apicd ? &apicd->cfg : NULL; |
7f3262ed | 87 | } |
c8f3e518 | 88 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
89 | |
90 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 91 | { |
7f3262ed JL |
92 | return irqd_cfg(irq_get_irq_data(irq)); |
93 | } | |
74afab7a | 94 | |
7f3262ed JL |
95 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
96 | { | |
86ba6551 | 97 | struct apic_chip_data *apicd; |
7f3262ed | 98 | |
86ba6551 TG |
99 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
100 | if (!apicd) | |
74afab7a | 101 | return NULL; |
86ba6551 | 102 | if (!zalloc_cpumask_var_node(&apicd->domain, GFP_KERNEL, node)) |
7f3262ed | 103 | goto out_data; |
86ba6551 | 104 | if (!zalloc_cpumask_var_node(&apicd->old_domain, GFP_KERNEL, node)) |
74afab7a | 105 | goto out_domain; |
dccfe314 | 106 | INIT_HLIST_NODE(&apicd->clist); |
86ba6551 | 107 | return apicd; |
74afab7a | 108 | out_domain: |
86ba6551 | 109 | free_cpumask_var(apicd->domain); |
7f3262ed | 110 | out_data: |
86ba6551 | 111 | kfree(apicd); |
74afab7a JL |
112 | return NULL; |
113 | } | |
114 | ||
86ba6551 | 115 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 116 | { |
86ba6551 TG |
117 | if (apicd) { |
118 | free_cpumask_var(apicd->domain); | |
119 | free_cpumask_var(apicd->old_domain); | |
120 | kfree(apicd); | |
b5dc8e6c | 121 | } |
74afab7a JL |
122 | } |
123 | ||
7f3262ed | 124 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
0e24f7c9 | 125 | const struct cpumask *mask, |
86ba6551 | 126 | struct irq_data *irqd) |
74afab7a JL |
127 | { |
128 | /* | |
129 | * NOTE! The local APIC isn't very good at handling | |
130 | * multiple interrupts at the same interrupt level. | |
131 | * As the interrupt level is determined by taking the | |
132 | * vector number and shifting that right by 4, we | |
133 | * want to spread these out a bit so that they don't | |
134 | * all fall in the same interrupt level. | |
135 | * | |
136 | * Also, we've got to be careful not to trash gate | |
137 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
138 | */ | |
139 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
140 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 141 | int cpu, vector; |
74afab7a | 142 | |
98229aa3 TG |
143 | /* |
144 | * If there is still a move in progress or the previous move has not | |
145 | * been cleaned up completely, tell the caller to come back later. | |
146 | */ | |
dccfe314 | 147 | if (d->cfg.old_vector) |
74afab7a JL |
148 | return -EBUSY; |
149 | ||
74afab7a | 150 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 151 | cpumask_clear(d->old_domain); |
8a580f70 | 152 | cpumask_clear(searched_cpumask); |
74afab7a JL |
153 | cpu = cpumask_first_and(mask, cpu_online_mask); |
154 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 155 | int new_cpu, offset; |
74afab7a | 156 | |
fdba46ff | 157 | cpumask_copy(vector_cpumask, cpumask_of(cpu)); |
74afab7a | 158 | |
3716fd27 TG |
159 | /* |
160 | * Clear the offline cpus from @vector_cpumask for searching | |
161 | * and verify whether the result overlaps with @mask. If true, | |
91cd9cb7 | 162 | * then the call to apic->cpu_mask_to_apicid() will |
3716fd27 TG |
163 | * succeed as well. If not, no point in trying to find a |
164 | * vector in this mask. | |
165 | */ | |
166 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
167 | if (!cpumask_intersects(vector_searchmask, mask)) | |
168 | goto next_cpu; | |
169 | ||
f7fa7aee | 170 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 171 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 172 | goto success; |
74afab7a | 173 | /* |
ab25ac02 TG |
174 | * Mark the cpus which are not longer in the mask for |
175 | * cleanup. | |
74afab7a | 176 | */ |
ab25ac02 TG |
177 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
178 | vector = d->cfg.vector; | |
179 | goto update; | |
74afab7a JL |
180 | } |
181 | ||
182 | vector = current_vector; | |
183 | offset = current_offset; | |
184 | next: | |
185 | vector += 16; | |
05161b9c | 186 | if (vector >= FIRST_SYSTEM_VECTOR) { |
74afab7a JL |
187 | offset = (offset + 1) % 16; |
188 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
189 | } | |
190 | ||
95ffeb4b TG |
191 | /* If the search wrapped around, try the next cpu */ |
192 | if (unlikely(current_vector == vector)) | |
193 | goto next_cpu; | |
74afab7a | 194 | |
7854f822 | 195 | if (test_bit(vector, system_vectors)) |
74afab7a JL |
196 | goto next; |
197 | ||
3716fd27 | 198 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 199 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
200 | goto next; |
201 | } | |
202 | /* Found one! */ | |
203 | current_vector = vector; | |
204 | current_offset = offset; | |
ab25ac02 TG |
205 | /* Schedule the old vector for cleanup on all cpus */ |
206 | if (d->cfg.vector) | |
7f3262ed | 207 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 208 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 209 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 210 | goto update; |
95ffeb4b TG |
211 | |
212 | next_cpu: | |
213 | /* | |
214 | * We exclude the current @vector_cpumask from the requested | |
215 | * @mask and try again with the next online cpu in the | |
216 | * result. We cannot modify @mask, so we use @vector_cpumask | |
217 | * as a temporary buffer here as it will be reassigned when | |
218 | * calling apic->vector_allocation_domain() above. | |
219 | */ | |
220 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
221 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
222 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
223 | continue; | |
74afab7a | 224 | } |
433cbd57 | 225 | return -ENOSPC; |
74afab7a | 226 | |
ab25ac02 | 227 | update: |
847667ef TG |
228 | /* |
229 | * Exclude offline cpus from the cleanup mask and set the | |
230 | * move_in_progress flag when the result is not empty. | |
231 | */ | |
232 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
233 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
551adc60 | 234 | d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; |
029c6e1c | 235 | d->prev_cpu = d->cpu; |
ab25ac02 TG |
236 | d->cfg.vector = vector; |
237 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 238 | success: |
3716fd27 TG |
239 | /* |
240 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
241 | * as we already established, that mask & d->domain & cpu_online_mask | |
242 | * is not empty. | |
52b166af TG |
243 | * |
244 | * vector_searchmask is a subset of d->domain and has the offline | |
245 | * cpus masked out. | |
3716fd27 | 246 | */ |
91cd9cb7 | 247 | cpumask_and(vector_searchmask, vector_searchmask, mask); |
86ba6551 | 248 | BUG_ON(apic->cpu_mask_to_apicid(vector_searchmask, irqd, |
0e24f7c9 | 249 | &d->cfg.dest_apicid)); |
029c6e1c | 250 | d->cpu = cpumask_first(vector_searchmask); |
3716fd27 | 251 | return 0; |
74afab7a JL |
252 | } |
253 | ||
86ba6551 | 254 | static int assign_irq_vector(int irq, struct apic_chip_data *apicd, |
0e24f7c9 | 255 | const struct cpumask *mask, |
86ba6551 | 256 | struct irq_data *irqd) |
74afab7a JL |
257 | { |
258 | int err; | |
259 | unsigned long flags; | |
260 | ||
261 | raw_spin_lock_irqsave(&vector_lock, flags); | |
86ba6551 | 262 | err = __assign_irq_vector(irq, apicd, mask, irqd); |
74afab7a JL |
263 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
264 | return err; | |
265 | } | |
266 | ||
486ca539 | 267 | static int assign_irq_vector_policy(int irq, int node, |
86ba6551 | 268 | struct apic_chip_data *apicd, |
0e24f7c9 | 269 | struct irq_alloc_info *info, |
86ba6551 | 270 | struct irq_data *irqd) |
486ca539 | 271 | { |
258d86ee | 272 | if (info->mask) |
86ba6551 | 273 | return assign_irq_vector(irq, apicd, info->mask, irqd); |
486ca539 | 274 | if (node != NUMA_NO_NODE && |
86ba6551 | 275 | assign_irq_vector(irq, apicd, cpumask_of_node(node), irqd) == 0) |
486ca539 | 276 | return 0; |
86ba6551 | 277 | return assign_irq_vector(irq, apicd, cpu_online_mask, irqd); |
486ca539 JL |
278 | } |
279 | ||
86ba6551 | 280 | static void clear_irq_vector(int irq, struct apic_chip_data *apicd) |
74afab7a | 281 | { |
dccfe314 | 282 | unsigned int vector = apicd->cfg.vector; |
74afab7a | 283 | |
dccfe314 | 284 | if (!vector) |
1bdb8970 | 285 | return; |
74afab7a | 286 | |
dccfe314 | 287 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 288 | apicd->cfg.vector = 0; |
74afab7a | 289 | |
dccfe314 TG |
290 | /* Clean up move in progress */ |
291 | vector = apicd->cfg.old_vector; | |
292 | if (!vector) | |
74afab7a | 293 | return; |
74afab7a | 294 | |
dccfe314 | 295 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
86ba6551 | 296 | apicd->move_in_progress = 0; |
dccfe314 | 297 | hlist_del_init(&apicd->clist); |
74afab7a JL |
298 | } |
299 | ||
b5dc8e6c JL |
300 | static void x86_vector_free_irqs(struct irq_domain *domain, |
301 | unsigned int virq, unsigned int nr_irqs) | |
302 | { | |
86ba6551 TG |
303 | struct apic_chip_data *apicd; |
304 | struct irq_data *irqd; | |
111abeba | 305 | unsigned long flags; |
b5dc8e6c JL |
306 | int i; |
307 | ||
308 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
309 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
310 | if (irqd && irqd->chip_data) { | |
111abeba | 311 | raw_spin_lock_irqsave(&vector_lock, flags); |
86ba6551 TG |
312 | clear_irq_vector(virq + i, irqd->chip_data); |
313 | apicd = irqd->chip_data; | |
314 | irq_domain_reset_irq_data(irqd); | |
111abeba | 315 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 316 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
317 | } |
318 | } | |
319 | } | |
320 | ||
321 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
322 | unsigned int nr_irqs, void *arg) | |
323 | { | |
324 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
325 | struct apic_chip_data *apicd; |
326 | struct irq_data *irqd; | |
5f2dbbc5 | 327 | int i, err, node; |
b5dc8e6c JL |
328 | |
329 | if (disable_apic) | |
330 | return -ENXIO; | |
331 | ||
332 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
333 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
334 | return -ENOSYS; | |
335 | ||
b5dc8e6c | 336 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
337 | irqd = irq_domain_get_irq_data(domain, virq + i); |
338 | BUG_ON(!irqd); | |
339 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
340 | WARN_ON_ONCE(irqd->chip_data); |
341 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 342 | if (!apicd) { |
b5dc8e6c JL |
343 | err = -ENOMEM; |
344 | goto error; | |
345 | } | |
346 | ||
86ba6551 TG |
347 | irqd->chip = &lapic_controller; |
348 | irqd->chip_data = apicd; | |
349 | irqd->hwirq = virq + i; | |
350 | irqd_set_single_target(irqd); | |
4ef76eb6 TG |
351 | /* |
352 | * Make sure, that the legacy to IOAPIC transition stays on | |
353 | * the same vector. This is required for check_timer() to | |
354 | * work correctly as it might switch back to legacy mode. | |
355 | */ | |
356 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
357 | apicd->cfg.vector = ISA_IRQ_VECTOR(virq + i); | |
358 | apicd->cpu = 0; | |
359 | cpumask_copy(apicd->domain, cpumask_of(0)); | |
360 | } | |
361 | ||
86ba6551 TG |
362 | err = assign_irq_vector_policy(virq + i, node, apicd, info, |
363 | irqd); | |
b5dc8e6c JL |
364 | if (err) |
365 | goto error; | |
366 | } | |
367 | ||
368 | return 0; | |
369 | ||
370 | error: | |
371 | x86_vector_free_irqs(domain, virq, i + 1); | |
372 | return err; | |
373 | } | |
374 | ||
eb18cf55 TG |
375 | static const struct irq_domain_ops x86_vector_domain_ops = { |
376 | .alloc = x86_vector_alloc_irqs, | |
377 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
378 | }; |
379 | ||
11d686e9 JL |
380 | int __init arch_probe_nr_irqs(void) |
381 | { | |
382 | int nr; | |
383 | ||
384 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
385 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
386 | ||
387 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
388 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
389 | /* | |
390 | * for MSI and HT dyn irq | |
391 | */ | |
392 | if (gsi_top <= NR_IRQS_LEGACY) | |
393 | nr += 8 * nr_cpu_ids; | |
394 | else | |
395 | nr += gsi_top * 16; | |
396 | #endif | |
397 | if (nr < nr_irqs) | |
398 | nr_irqs = nr; | |
399 | ||
8c058b0b VK |
400 | /* |
401 | * We don't know if PIC is present at this point so we need to do | |
402 | * probe() to get the right number of legacy IRQs. | |
403 | */ | |
404 | return legacy_pic->probe(); | |
11d686e9 JL |
405 | } |
406 | ||
407 | int __init arch_early_irq_init(void) | |
408 | { | |
9d35f859 TG |
409 | struct fwnode_handle *fn; |
410 | ||
9d35f859 TG |
411 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
412 | BUG_ON(!fn); | |
413 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
414 | NULL); | |
b5dc8e6c | 415 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 416 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
417 | irq_set_default_host(x86_vector_domain); |
418 | ||
52f518a3 | 419 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 420 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 421 | |
f7fa7aee | 422 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 423 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 424 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 425 | |
11d686e9 JL |
426 | return arch_early_ioapic_init(); |
427 | } | |
428 | ||
f0cc6cca TG |
429 | /* Temporary hack to keep things working */ |
430 | static void vector_update_shutdown_irqs(void) | |
74afab7a | 431 | { |
a782a7e4 | 432 | struct irq_desc *desc; |
f0cc6cca | 433 | int irq; |
74afab7a | 434 | |
a782a7e4 | 435 | for_each_irq_desc(irq, desc) { |
f0cc6cca TG |
436 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
437 | struct apic_chip_data *ad = apic_chip_data(irqd); | |
74afab7a | 438 | |
dccfe314 | 439 | if (ad && ad->cfg.vector && ad->cpu == smp_processor_id()) |
f0cc6cca | 440 | this_cpu_write(vector_irq[ad->cfg.vector], desc); |
74afab7a | 441 | } |
74afab7a JL |
442 | } |
443 | ||
f0cc6cca TG |
444 | static struct irq_desc *__setup_vector_irq(int vector) |
445 | { | |
446 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
447 | ||
448 | /* Check whether the irq is in the legacy space */ | |
449 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
450 | return VECTOR_UNUSED; | |
451 | /* Check whether the irq is handled by the IOAPIC */ | |
452 | if (test_bit(isairq, &io_apic_irqs)) | |
453 | return VECTOR_UNUSED; | |
454 | return irq_to_desc(isairq); | |
455 | } | |
456 | ||
74afab7a | 457 | /* |
5a3f75e3 | 458 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
459 | */ |
460 | void setup_vector_irq(int cpu) | |
461 | { | |
f0cc6cca | 462 | unsigned int vector; |
74afab7a | 463 | |
5a3f75e3 | 464 | lockdep_assert_held(&vector_lock); |
74afab7a | 465 | /* |
f0cc6cca TG |
466 | * The interrupt affinity logic never targets interrupts to offline |
467 | * CPUs. The exception are the legacy PIC interrupts. In general | |
468 | * they are only targeted to CPU0, but depending on the platform | |
469 | * they can be distributed to any online CPU in hardware. The | |
470 | * kernel has no influence on that. So all active legacy vectors | |
471 | * must be installed on all CPUs. All non legacy interrupts can be | |
472 | * cleared. | |
74afab7a | 473 | */ |
f0cc6cca TG |
474 | for (vector = 0; vector < NR_VECTORS; vector++) |
475 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a | 476 | |
f0cc6cca TG |
477 | /* |
478 | * Until the rewrite of the managed interrupt management is in | |
479 | * place it's necessary to walk the irq descriptors and check for | |
480 | * interrupts which are targeted at this CPU. | |
481 | */ | |
482 | vector_update_shutdown_irqs(); | |
74afab7a JL |
483 | } |
484 | ||
86ba6551 | 485 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 486 | { |
86ba6551 | 487 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 488 | unsigned long flags; |
74afab7a JL |
489 | |
490 | raw_spin_lock_irqsave(&vector_lock, flags); | |
dccfe314 | 491 | apic->send_IPI(apicd->cpu, apicd->cfg.vector); |
74afab7a JL |
492 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
493 | ||
494 | return 1; | |
495 | } | |
496 | ||
86ba6551 | 497 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 498 | { |
86ba6551 TG |
499 | irq_complete_move(irqd_cfg(irqd)); |
500 | irq_move_irq(irqd); | |
74afab7a JL |
501 | ack_APIC_irq(); |
502 | } | |
503 | ||
86ba6551 | 504 | static int apic_set_affinity(struct irq_data *irqd, |
68f9f440 | 505 | const struct cpumask *dest, bool force) |
b5dc8e6c | 506 | { |
86ba6551 TG |
507 | struct apic_chip_data *apicd = irqd->chip_data; |
508 | int err, irq = irqd->irq; | |
b5dc8e6c | 509 | |
97f2645f | 510 | if (!IS_ENABLED(CONFIG_SMP)) |
b5dc8e6c JL |
511 | return -EPERM; |
512 | ||
513 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
514 | return -EINVAL; | |
515 | ||
86ba6551 | 516 | err = assign_irq_vector(irq, apicd, dest, irqd); |
3716fd27 | 517 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
518 | } |
519 | ||
520 | static struct irq_chip lapic_controller = { | |
8947dfb2 | 521 | .name = "APIC", |
b5dc8e6c | 522 | .irq_ack = apic_ack_edge, |
68f9f440 | 523 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
524 | .irq_retrigger = apic_retrigger_irq, |
525 | }; | |
526 | ||
74afab7a | 527 | #ifdef CONFIG_SMP |
c6c2002b | 528 | |
c4158ff5 | 529 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 530 | { |
dccfe314 TG |
531 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
532 | struct apic_chip_data *apicd; | |
533 | struct hlist_node *tmp; | |
74afab7a | 534 | |
6af7faf6 | 535 | entering_ack_irq(); |
df54c493 TG |
536 | /* Prevent vectors vanishing under us */ |
537 | raw_spin_lock(&vector_lock); | |
538 | ||
dccfe314 TG |
539 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
540 | unsigned int irr, vector = apicd->cfg.old_vector; | |
74afab7a | 541 | |
74afab7a | 542 | /* |
dccfe314 TG |
543 | * Paranoia: Check if the vector that needs to be cleaned |
544 | * up is registered at the APICs IRR. If so, then this is | |
545 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 546 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
547 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
548 | * priority external vector, so on return from this | |
549 | * interrupt the device interrupt will happen first. | |
74afab7a | 550 | */ |
dccfe314 TG |
551 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
552 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 553 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 554 | continue; |
74afab7a | 555 | } |
dccfe314 | 556 | hlist_del_init(&apicd->clist); |
7276c6a2 | 557 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
dccfe314 | 558 | apicd->cfg.old_vector = 0; |
74afab7a JL |
559 | } |
560 | ||
df54c493 | 561 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 562 | exiting_irq(); |
74afab7a JL |
563 | } |
564 | ||
dccfe314 TG |
565 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
566 | { | |
567 | unsigned int cpu; | |
568 | ||
569 | raw_spin_lock(&vector_lock); | |
570 | apicd->move_in_progress = 0; | |
571 | cpu = apicd->prev_cpu; | |
572 | if (cpu_online(cpu)) { | |
573 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
574 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
575 | } else { | |
576 | apicd->cfg.old_vector = 0; | |
577 | } | |
578 | raw_spin_unlock(&vector_lock); | |
579 | } | |
580 | ||
581 | void send_cleanup_vector(struct irq_cfg *cfg) | |
582 | { | |
583 | struct apic_chip_data *apicd; | |
584 | ||
585 | apicd = container_of(cfg, struct apic_chip_data, cfg); | |
586 | if (apicd->move_in_progress) | |
587 | __send_cleanup_vector(apicd); | |
588 | } | |
589 | ||
74afab7a JL |
590 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
591 | { | |
86ba6551 | 592 | struct apic_chip_data *apicd; |
74afab7a | 593 | |
86ba6551 TG |
594 | apicd = container_of(cfg, struct apic_chip_data, cfg); |
595 | if (likely(!apicd->move_in_progress)) | |
74afab7a JL |
596 | return; |
597 | ||
dccfe314 | 598 | if (vector == apicd->cfg.vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 599 | __send_cleanup_vector(apicd); |
74afab7a JL |
600 | } |
601 | ||
602 | void irq_complete_move(struct irq_cfg *cfg) | |
603 | { | |
604 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
605 | } | |
606 | ||
90a2282e | 607 | /* |
551adc60 | 608 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
609 | */ |
610 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 611 | { |
86ba6551 | 612 | struct apic_chip_data *apicd; |
dccfe314 TG |
613 | struct irq_data *irqd; |
614 | unsigned int vector; | |
56d7d2f4 | 615 | |
db91aa79 MW |
616 | /* |
617 | * The function is called for all descriptors regardless of which | |
618 | * irqdomain they belong to. For example if an IRQ is provided by | |
619 | * an irq_chip as part of a GPIO driver, the chip data for that | |
620 | * descriptor is specific to the irq_chip in question. | |
621 | * | |
622 | * Check first that the chip_data is what we expect | |
623 | * (apic_chip_data) before touching it any further. | |
624 | */ | |
86ba6551 | 625 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 626 | irq_desc_get_irq(desc)); |
86ba6551 | 627 | if (!irqd) |
db91aa79 MW |
628 | return; |
629 | ||
dccfe314 | 630 | raw_spin_lock(&vector_lock); |
86ba6551 | 631 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
632 | if (!apicd) |
633 | goto unlock; | |
db91aa79 | 634 | |
dccfe314 TG |
635 | /* |
636 | * If old_vector is empty, no action required. | |
637 | */ | |
638 | vector = apicd->cfg.old_vector; | |
639 | if (!vector) | |
640 | goto unlock; | |
74afab7a | 641 | |
56d7d2f4 | 642 | /* |
dccfe314 | 643 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
644 | * done yet, then the following setaffinity call will fail with |
645 | * -EBUSY. This can leave the interrupt in a stale state. | |
646 | * | |
551adc60 TG |
647 | * All CPUs are stuck in stop machine with interrupts disabled so |
648 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 649 | * |
551adc60 TG |
650 | * 1) The interrupt is in move_in_progress state. That means that we |
651 | * have not seen an interrupt since the io_apic was reprogrammed to | |
652 | * the new vector. | |
653 | * | |
654 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
655 | * have not been processed yet. | |
656 | */ | |
86ba6551 | 657 | if (apicd->move_in_progress) { |
98229aa3 | 658 | /* |
551adc60 TG |
659 | * In theory there is a race: |
660 | * | |
661 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
662 | * is effective, i.e. it's raised on | |
663 | * the old vector. | |
664 | * | |
665 | * So if the target cpu cannot handle that interrupt before | |
666 | * the old vector is cleaned up, we get a spurious interrupt | |
667 | * and in the worst case the ioapic irq line becomes stale. | |
668 | * | |
669 | * But in case of cpu hotplug this should be a non issue | |
670 | * because if the affinity update happens right before all | |
671 | * cpus rendevouz in stop machine, there is no way that the | |
672 | * interrupt can be blocked on the target cpu because all cpus | |
673 | * loops first with interrupts enabled in stop machine, so the | |
674 | * old vector is not yet cleaned up when the interrupt fires. | |
675 | * | |
676 | * So the only way to run into this issue is if the delivery | |
677 | * of the interrupt on the apic/system bus would be delayed | |
678 | * beyond the point where the target cpu disables interrupts | |
679 | * in stop machine. I doubt that it can happen, but at least | |
680 | * there is a theroretical chance. Virtualization might be | |
681 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
682 | * as stupid as the real hardware. | |
683 | * | |
684 | * Anyway, there is nothing we can do about that at this point | |
685 | * w/o refactoring the whole fixup_irq() business completely. | |
686 | * We print at least the irq number and the old vector number, | |
687 | * so we have the necessary information when a problem in that | |
688 | * area arises. | |
98229aa3 | 689 | */ |
551adc60 | 690 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 691 | irqd->irq, vector); |
98229aa3 | 692 | } |
dccfe314 | 693 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
551adc60 | 694 | /* Cleanup the left overs of the (half finished) move */ |
86ba6551 | 695 | cpumask_clear(apicd->old_domain); |
dccfe314 | 696 | apicd->cfg.old_vector = 0; |
86ba6551 | 697 | apicd->move_in_progress = 0; |
dccfe314 TG |
698 | hlist_del_init(&apicd->clist); |
699 | unlock: | |
56d7d2f4 | 700 | raw_spin_unlock(&vector_lock); |
74afab7a | 701 | } |
74afab7a JL |
702 | #endif |
703 | ||
74afab7a JL |
704 | static void __init print_APIC_field(int base) |
705 | { | |
706 | int i; | |
707 | ||
708 | printk(KERN_DEBUG); | |
709 | ||
710 | for (i = 0; i < 8; i++) | |
711 | pr_cont("%08x", apic_read(base + i*0x10)); | |
712 | ||
713 | pr_cont("\n"); | |
714 | } | |
715 | ||
716 | static void __init print_local_APIC(void *dummy) | |
717 | { | |
718 | unsigned int i, v, ver, maxlvt; | |
719 | u64 icr; | |
720 | ||
849d3569 JL |
721 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
722 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 723 | v = apic_read(APIC_ID); |
849d3569 | 724 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 725 | v = apic_read(APIC_LVR); |
849d3569 | 726 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
727 | ver = GET_APIC_VERSION(v); |
728 | maxlvt = lapic_get_maxlvt(); | |
729 | ||
730 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 731 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
732 | |
733 | /* !82489DX */ | |
734 | if (APIC_INTEGRATED(ver)) { | |
735 | if (!APIC_XAPIC(ver)) { | |
736 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
737 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
738 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
739 | } |
740 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 741 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
742 | } |
743 | ||
744 | /* | |
745 | * Remote read supported only in the 82489DX and local APIC for | |
746 | * Pentium processors. | |
747 | */ | |
748 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
749 | v = apic_read(APIC_RRR); | |
849d3569 | 750 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
751 | } |
752 | ||
753 | v = apic_read(APIC_LDR); | |
849d3569 | 754 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
755 | if (!x2apic_enabled()) { |
756 | v = apic_read(APIC_DFR); | |
849d3569 | 757 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
758 | } |
759 | v = apic_read(APIC_SPIV); | |
849d3569 | 760 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 761 | |
849d3569 | 762 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 763 | print_APIC_field(APIC_ISR); |
849d3569 | 764 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 765 | print_APIC_field(APIC_TMR); |
849d3569 | 766 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
767 | print_APIC_field(APIC_IRR); |
768 | ||
769 | /* !82489DX */ | |
770 | if (APIC_INTEGRATED(ver)) { | |
771 | /* Due to the Pentium erratum 3AP. */ | |
772 | if (maxlvt > 3) | |
773 | apic_write(APIC_ESR, 0); | |
774 | ||
775 | v = apic_read(APIC_ESR); | |
849d3569 | 776 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
777 | } |
778 | ||
779 | icr = apic_icr_read(); | |
849d3569 JL |
780 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
781 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
782 | |
783 | v = apic_read(APIC_LVTT); | |
849d3569 | 784 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
785 | |
786 | if (maxlvt > 3) { | |
787 | /* PC is LVT#4. */ | |
788 | v = apic_read(APIC_LVTPC); | |
849d3569 | 789 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
790 | } |
791 | v = apic_read(APIC_LVT0); | |
849d3569 | 792 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 793 | v = apic_read(APIC_LVT1); |
849d3569 | 794 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
795 | |
796 | if (maxlvt > 2) { | |
797 | /* ERR is LVT#3. */ | |
798 | v = apic_read(APIC_LVTERR); | |
849d3569 | 799 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
800 | } |
801 | ||
802 | v = apic_read(APIC_TMICT); | |
849d3569 | 803 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 804 | v = apic_read(APIC_TMCCT); |
849d3569 | 805 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 806 | v = apic_read(APIC_TDCR); |
849d3569 | 807 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
808 | |
809 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
810 | v = apic_read(APIC_EFEAT); | |
811 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 812 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 813 | v = apic_read(APIC_ECTRL); |
849d3569 | 814 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
815 | for (i = 0; i < maxlvt; i++) { |
816 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 817 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
818 | } |
819 | } | |
820 | pr_cont("\n"); | |
821 | } | |
822 | ||
823 | static void __init print_local_APICs(int maxcpu) | |
824 | { | |
825 | int cpu; | |
826 | ||
827 | if (!maxcpu) | |
828 | return; | |
829 | ||
830 | preempt_disable(); | |
831 | for_each_online_cpu(cpu) { | |
832 | if (cpu >= maxcpu) | |
833 | break; | |
834 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
835 | } | |
836 | preempt_enable(); | |
837 | } | |
838 | ||
839 | static void __init print_PIC(void) | |
840 | { | |
841 | unsigned int v; | |
842 | unsigned long flags; | |
843 | ||
844 | if (!nr_legacy_irqs()) | |
845 | return; | |
846 | ||
849d3569 | 847 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
848 | |
849 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
850 | ||
851 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 852 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
853 | |
854 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 855 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
856 | |
857 | outb(0x0b, 0xa0); | |
858 | outb(0x0b, 0x20); | |
859 | v = inb(0xa0) << 8 | inb(0x20); | |
860 | outb(0x0a, 0xa0); | |
861 | outb(0x0a, 0x20); | |
862 | ||
863 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
864 | ||
849d3569 | 865 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
866 | |
867 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 868 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
869 | } |
870 | ||
871 | static int show_lapic __initdata = 1; | |
872 | static __init int setup_show_lapic(char *arg) | |
873 | { | |
874 | int num = -1; | |
875 | ||
876 | if (strcmp(arg, "all") == 0) { | |
877 | show_lapic = CONFIG_NR_CPUS; | |
878 | } else { | |
879 | get_option(&arg, &num); | |
880 | if (num >= 0) | |
881 | show_lapic = num; | |
882 | } | |
883 | ||
884 | return 1; | |
885 | } | |
886 | __setup("show_lapic=", setup_show_lapic); | |
887 | ||
888 | static int __init print_ICs(void) | |
889 | { | |
890 | if (apic_verbosity == APIC_QUIET) | |
891 | return 0; | |
892 | ||
893 | print_PIC(); | |
894 | ||
895 | /* don't print out if apic is not there */ | |
93984fbd | 896 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
897 | return 0; |
898 | ||
899 | print_local_APICs(show_lapic); | |
900 | print_IO_APICs(); | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | late_initcall(print_ICs); |