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Commit | Line | Data |
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74afab7a | 1 | /* |
fd2fa6c1 | 2 | * Local APIC related interfaces to support IOAPIC, MSI, etc. |
74afab7a JL |
3 | * |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
65d7ed57 | 14 | #include <linux/seq_file.h> |
74afab7a JL |
15 | #include <linux/init.h> |
16 | #include <linux/compiler.h> | |
74afab7a | 17 | #include <linux/slab.h> |
d746d1eb | 18 | #include <asm/irqdomain.h> |
74afab7a JL |
19 | #include <asm/hw_irq.h> |
20 | #include <asm/apic.h> | |
21 | #include <asm/i8259.h> | |
22 | #include <asm/desc.h> | |
23 | #include <asm/irq_remapping.h> | |
24 | ||
8d1e3dca TG |
25 | #include <asm/trace/irq_vectors.h> |
26 | ||
7f3262ed | 27 | struct apic_chip_data { |
ba224fea TG |
28 | struct irq_cfg hw_irq_cfg; |
29 | unsigned int vector; | |
30 | unsigned int prev_vector; | |
029c6e1c TG |
31 | unsigned int cpu; |
32 | unsigned int prev_cpu; | |
69cde000 | 33 | unsigned int irq; |
dccfe314 | 34 | struct hlist_node clist; |
2db1f959 | 35 | unsigned int move_in_progress : 1, |
4900be83 TG |
36 | is_managed : 1, |
37 | can_reserve : 1, | |
38 | has_reserved : 1; | |
7f3262ed JL |
39 | }; |
40 | ||
b5dc8e6c | 41 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 42 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 43 | static DEFINE_RAW_SPINLOCK(vector_lock); |
69cde000 | 44 | static cpumask_var_t vector_searchmask; |
b5dc8e6c | 45 | static struct irq_chip lapic_controller; |
0fa115da | 46 | static struct irq_matrix *vector_matrix; |
dccfe314 TG |
47 | #ifdef CONFIG_SMP |
48 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
49 | #endif | |
74afab7a JL |
50 | |
51 | void lock_vector_lock(void) | |
52 | { | |
53 | /* Used to the online set of cpus does not change | |
54 | * during assign_irq_vector. | |
55 | */ | |
56 | raw_spin_lock(&vector_lock); | |
57 | } | |
58 | ||
59 | void unlock_vector_lock(void) | |
60 | { | |
61 | raw_spin_unlock(&vector_lock); | |
62 | } | |
63 | ||
99a1482d TG |
64 | void init_irq_alloc_info(struct irq_alloc_info *info, |
65 | const struct cpumask *mask) | |
66 | { | |
67 | memset(info, 0, sizeof(*info)); | |
68 | info->mask = mask; | |
69 | } | |
70 | ||
71 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
72 | { | |
73 | if (src) | |
74 | *dst = *src; | |
75 | else | |
76 | memset(dst, 0, sizeof(*dst)); | |
77 | } | |
78 | ||
86ba6551 | 79 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 80 | { |
86ba6551 | 81 | if (!irqd) |
b5dc8e6c JL |
82 | return NULL; |
83 | ||
86ba6551 TG |
84 | while (irqd->parent_data) |
85 | irqd = irqd->parent_data; | |
b5dc8e6c | 86 | |
86ba6551 | 87 | return irqd->chip_data; |
74afab7a JL |
88 | } |
89 | ||
86ba6551 | 90 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 91 | { |
86ba6551 | 92 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 93 | |
ba224fea | 94 | return apicd ? &apicd->hw_irq_cfg : NULL; |
7f3262ed | 95 | } |
c8f3e518 | 96 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
97 | |
98 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 99 | { |
7f3262ed JL |
100 | return irqd_cfg(irq_get_irq_data(irq)); |
101 | } | |
74afab7a | 102 | |
7f3262ed JL |
103 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
104 | { | |
86ba6551 | 105 | struct apic_chip_data *apicd; |
7f3262ed | 106 | |
86ba6551 | 107 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
69cde000 TG |
108 | if (apicd) |
109 | INIT_HLIST_NODE(&apicd->clist); | |
86ba6551 | 110 | return apicd; |
74afab7a JL |
111 | } |
112 | ||
86ba6551 | 113 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 114 | { |
69cde000 | 115 | kfree(apicd); |
74afab7a JL |
116 | } |
117 | ||
ba224fea TG |
118 | static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector, |
119 | unsigned int cpu) | |
74afab7a | 120 | { |
69cde000 | 121 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 122 | |
69cde000 | 123 | lockdep_assert_held(&vector_lock); |
74afab7a | 124 | |
ba224fea TG |
125 | apicd->hw_irq_cfg.vector = vector; |
126 | apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); | |
127 | irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); | |
128 | trace_vector_config(irqd->irq, vector, cpu, | |
129 | apicd->hw_irq_cfg.dest_apicid); | |
69cde000 | 130 | } |
74afab7a | 131 | |
69cde000 TG |
132 | static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, |
133 | unsigned int newcpu) | |
134 | { | |
135 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
136 | struct irq_desc *desc = irq_data_to_desc(irqd); | |
74afab7a | 137 | |
69cde000 | 138 | lockdep_assert_held(&vector_lock); |
74afab7a | 139 | |
ba224fea | 140 | trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector, |
69cde000 | 141 | apicd->cpu); |
74afab7a | 142 | |
69cde000 | 143 | /* Setup the vector move, if required */ |
ba224fea | 144 | if (apicd->vector && cpu_online(apicd->cpu)) { |
69cde000 | 145 | apicd->move_in_progress = true; |
ba224fea | 146 | apicd->prev_vector = apicd->vector; |
69cde000 TG |
147 | apicd->prev_cpu = apicd->cpu; |
148 | } else { | |
ba224fea | 149 | apicd->prev_vector = 0; |
69cde000 | 150 | } |
74afab7a | 151 | |
ba224fea | 152 | apicd->vector = newvec; |
69cde000 TG |
153 | apicd->cpu = newcpu; |
154 | BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec])); | |
155 | per_cpu(vector_irq, newcpu)[newvec] = desc; | |
156 | } | |
74afab7a | 157 | |
2db1f959 TG |
158 | static void vector_assign_managed_shutdown(struct irq_data *irqd) |
159 | { | |
160 | unsigned int cpu = cpumask_first(cpu_online_mask); | |
161 | ||
162 | apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu); | |
163 | } | |
164 | ||
165 | static int reserve_managed_vector(struct irq_data *irqd) | |
166 | { | |
167 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
168 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
169 | unsigned long flags; | |
170 | int ret; | |
171 | ||
172 | raw_spin_lock_irqsave(&vector_lock, flags); | |
173 | apicd->is_managed = true; | |
174 | ret = irq_matrix_reserve_managed(vector_matrix, affmsk); | |
175 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
176 | trace_vector_reserve_managed(irqd->irq, ret); | |
177 | return ret; | |
178 | } | |
179 | ||
4900be83 TG |
180 | static void reserve_irq_vector_locked(struct irq_data *irqd) |
181 | { | |
182 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
183 | ||
184 | irq_matrix_reserve(vector_matrix); | |
185 | apicd->can_reserve = true; | |
186 | apicd->has_reserved = true; | |
187 | trace_vector_reserve(irqd->irq, 0); | |
188 | vector_assign_managed_shutdown(irqd); | |
189 | } | |
190 | ||
191 | static int reserve_irq_vector(struct irq_data *irqd) | |
192 | { | |
193 | unsigned long flags; | |
194 | ||
195 | raw_spin_lock_irqsave(&vector_lock, flags); | |
196 | reserve_irq_vector_locked(irqd); | |
197 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
198 | return 0; | |
199 | } | |
200 | ||
69cde000 TG |
201 | static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest) |
202 | { | |
203 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
4900be83 | 204 | bool resvd = apicd->has_reserved; |
69cde000 | 205 | unsigned int cpu = apicd->cpu; |
ba224fea TG |
206 | int vector = apicd->vector; |
207 | ||
208 | lockdep_assert_held(&vector_lock); | |
74afab7a | 209 | |
3716fd27 | 210 | /* |
69cde000 TG |
211 | * If the current target CPU is online and in the new requested |
212 | * affinity mask, there is no point in moving the interrupt from | |
213 | * one CPU to another. | |
3716fd27 | 214 | */ |
69cde000 TG |
215 | if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest)) |
216 | return 0; | |
217 | ||
4900be83 | 218 | vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu); |
69cde000 TG |
219 | if (vector > 0) |
220 | apic_update_vector(irqd, vector, cpu); | |
4900be83 | 221 | trace_vector_alloc(irqd->irq, vector, resvd, vector); |
69cde000 TG |
222 | return vector; |
223 | } | |
224 | ||
225 | static int assign_vector_locked(struct irq_data *irqd, | |
226 | const struct cpumask *dest) | |
227 | { | |
ba224fea | 228 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
69cde000 TG |
229 | int vector = allocate_vector(irqd, dest); |
230 | ||
231 | if (vector < 0) | |
232 | return vector; | |
233 | ||
ba224fea | 234 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); |
3716fd27 | 235 | return 0; |
74afab7a JL |
236 | } |
237 | ||
69cde000 | 238 | static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest) |
74afab7a | 239 | { |
74afab7a | 240 | unsigned long flags; |
69cde000 | 241 | int ret; |
74afab7a JL |
242 | |
243 | raw_spin_lock_irqsave(&vector_lock, flags); | |
69cde000 TG |
244 | cpumask_and(vector_searchmask, dest, cpu_online_mask); |
245 | ret = assign_vector_locked(irqd, vector_searchmask); | |
74afab7a | 246 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
69cde000 | 247 | return ret; |
74afab7a JL |
248 | } |
249 | ||
2db1f959 TG |
250 | static int assign_irq_vector_any_locked(struct irq_data *irqd) |
251 | { | |
d6ffc6ac TG |
252 | /* Get the affinity mask - either irq_default_affinity or (user) set */ |
253 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
2db1f959 TG |
254 | int node = irq_data_get_node(irqd); |
255 | ||
d6ffc6ac TG |
256 | if (node == NUMA_NO_NODE) |
257 | goto all; | |
258 | /* Try the intersection of @affmsk and node mask */ | |
259 | cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk); | |
260 | if (!assign_vector_locked(irqd, vector_searchmask)) | |
261 | return 0; | |
262 | /* Try the node mask */ | |
263 | if (!assign_vector_locked(irqd, cpumask_of_node(node))) | |
264 | return 0; | |
265 | all: | |
266 | /* Try the full affinity mask */ | |
267 | cpumask_and(vector_searchmask, affmsk, cpu_online_mask); | |
268 | if (!assign_vector_locked(irqd, vector_searchmask)) | |
269 | return 0; | |
270 | /* Try the full online mask */ | |
2db1f959 TG |
271 | return assign_vector_locked(irqd, cpu_online_mask); |
272 | } | |
273 | ||
2db1f959 TG |
274 | static int |
275 | assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info) | |
486ca539 | 276 | { |
2db1f959 TG |
277 | if (irqd_affinity_is_managed(irqd)) |
278 | return reserve_managed_vector(irqd); | |
258d86ee | 279 | if (info->mask) |
69cde000 | 280 | return assign_irq_vector(irqd, info->mask); |
464d1230 TG |
281 | /* |
282 | * Make only a global reservation with no guarantee. A real vector | |
283 | * is associated at activation time. | |
284 | */ | |
4900be83 | 285 | return reserve_irq_vector(irqd); |
2db1f959 TG |
286 | } |
287 | ||
288 | static int | |
289 | assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest) | |
290 | { | |
291 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
292 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
293 | int vector, cpu; | |
294 | ||
295 | cpumask_and(vector_searchmask, vector_searchmask, affmsk); | |
296 | cpu = cpumask_first(vector_searchmask); | |
297 | if (cpu >= nr_cpu_ids) | |
298 | return -EINVAL; | |
299 | /* set_affinity might call here for nothing */ | |
300 | if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask)) | |
486ca539 | 301 | return 0; |
2db1f959 TG |
302 | vector = irq_matrix_alloc_managed(vector_matrix, cpu); |
303 | trace_vector_alloc_managed(irqd->irq, vector, vector); | |
304 | if (vector < 0) | |
305 | return vector; | |
306 | apic_update_vector(irqd, vector, cpu); | |
307 | apic_update_irq_cfg(irqd, vector, cpu); | |
308 | return 0; | |
486ca539 JL |
309 | } |
310 | ||
69cde000 | 311 | static void clear_irq_vector(struct irq_data *irqd) |
74afab7a | 312 | { |
69cde000 | 313 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
2db1f959 | 314 | bool managed = irqd_affinity_is_managed(irqd); |
ba224fea | 315 | unsigned int vector = apicd->vector; |
74afab7a | 316 | |
69cde000 | 317 | lockdep_assert_held(&vector_lock); |
ba224fea | 318 | |
dccfe314 | 319 | if (!vector) |
1bdb8970 | 320 | return; |
74afab7a | 321 | |
ba224fea | 322 | trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector, |
69cde000 TG |
323 | apicd->prev_cpu); |
324 | ||
dccfe314 | 325 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED; |
2db1f959 | 326 | irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); |
ba224fea | 327 | apicd->vector = 0; |
74afab7a | 328 | |
dccfe314 | 329 | /* Clean up move in progress */ |
ba224fea | 330 | vector = apicd->prev_vector; |
dccfe314 | 331 | if (!vector) |
74afab7a | 332 | return; |
74afab7a | 333 | |
dccfe314 | 334 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED; |
2db1f959 | 335 | irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); |
ba224fea | 336 | apicd->prev_vector = 0; |
86ba6551 | 337 | apicd->move_in_progress = 0; |
dccfe314 | 338 | hlist_del_init(&apicd->clist); |
74afab7a JL |
339 | } |
340 | ||
2db1f959 TG |
341 | static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd) |
342 | { | |
343 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
344 | unsigned long flags; | |
345 | ||
346 | trace_vector_deactivate(irqd->irq, apicd->is_managed, | |
4900be83 | 347 | apicd->can_reserve, false); |
2db1f959 | 348 | |
4900be83 TG |
349 | /* Regular fixed assigned interrupt */ |
350 | if (!apicd->is_managed && !apicd->can_reserve) | |
351 | return; | |
352 | /* If the interrupt has a global reservation, nothing to do */ | |
353 | if (apicd->has_reserved) | |
2db1f959 TG |
354 | return; |
355 | ||
356 | raw_spin_lock_irqsave(&vector_lock, flags); | |
357 | clear_irq_vector(irqd); | |
4900be83 TG |
358 | if (apicd->can_reserve) |
359 | reserve_irq_vector_locked(irqd); | |
360 | else | |
361 | vector_assign_managed_shutdown(irqd); | |
2db1f959 TG |
362 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
363 | } | |
364 | ||
4900be83 TG |
365 | static int activate_reserved(struct irq_data *irqd) |
366 | { | |
367 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
368 | int ret; | |
369 | ||
370 | ret = assign_irq_vector_any_locked(irqd); | |
371 | if (!ret) | |
372 | apicd->has_reserved = false; | |
373 | return ret; | |
374 | } | |
375 | ||
2db1f959 TG |
376 | static int activate_managed(struct irq_data *irqd) |
377 | { | |
378 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
379 | int ret; | |
380 | ||
381 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
382 | if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) { | |
383 | /* Something in the core code broke! Survive gracefully */ | |
384 | pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq); | |
385 | return EINVAL; | |
386 | } | |
387 | ||
388 | ret = assign_managed_vector(irqd, vector_searchmask); | |
389 | /* | |
390 | * This should not happen. The vector reservation got buggered. Handle | |
391 | * it gracefully. | |
392 | */ | |
393 | if (WARN_ON_ONCE(ret < 0)) { | |
394 | pr_err("Managed startup irq %u, no vector available\n", | |
395 | irqd->irq); | |
396 | } | |
397 | return ret; | |
398 | } | |
399 | ||
400 | static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, | |
401 | bool early) | |
402 | { | |
403 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
404 | unsigned long flags; | |
405 | int ret = 0; | |
406 | ||
407 | trace_vector_activate(irqd->irq, apicd->is_managed, | |
4900be83 | 408 | apicd->can_reserve, early); |
2db1f959 | 409 | |
4900be83 TG |
410 | /* Nothing to do for fixed assigned vectors */ |
411 | if (!apicd->can_reserve && !apicd->is_managed) | |
2db1f959 TG |
412 | return 0; |
413 | ||
414 | raw_spin_lock_irqsave(&vector_lock, flags); | |
415 | if (early || irqd_is_managed_and_shutdown(irqd)) | |
416 | vector_assign_managed_shutdown(irqd); | |
4900be83 | 417 | else if (apicd->is_managed) |
2db1f959 | 418 | ret = activate_managed(irqd); |
4900be83 TG |
419 | else if (apicd->has_reserved) |
420 | ret = activate_reserved(irqd); | |
2db1f959 TG |
421 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
422 | return ret; | |
423 | } | |
424 | ||
425 | static void vector_free_reserved_and_managed(struct irq_data *irqd) | |
426 | { | |
427 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
428 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
429 | ||
4900be83 TG |
430 | trace_vector_teardown(irqd->irq, apicd->is_managed, |
431 | apicd->has_reserved); | |
2db1f959 | 432 | |
4900be83 TG |
433 | if (apicd->has_reserved) |
434 | irq_matrix_remove_reserved(vector_matrix); | |
2db1f959 TG |
435 | if (apicd->is_managed) |
436 | irq_matrix_remove_managed(vector_matrix, dest); | |
437 | } | |
438 | ||
b5dc8e6c JL |
439 | static void x86_vector_free_irqs(struct irq_domain *domain, |
440 | unsigned int virq, unsigned int nr_irqs) | |
441 | { | |
86ba6551 TG |
442 | struct apic_chip_data *apicd; |
443 | struct irq_data *irqd; | |
111abeba | 444 | unsigned long flags; |
b5dc8e6c JL |
445 | int i; |
446 | ||
447 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
448 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
449 | if (irqd && irqd->chip_data) { | |
111abeba | 450 | raw_spin_lock_irqsave(&vector_lock, flags); |
69cde000 | 451 | clear_irq_vector(irqd); |
2db1f959 | 452 | vector_free_reserved_and_managed(irqd); |
86ba6551 TG |
453 | apicd = irqd->chip_data; |
454 | irq_domain_reset_irq_data(irqd); | |
111abeba | 455 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 456 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
457 | } |
458 | } | |
459 | } | |
460 | ||
464d1230 TG |
461 | static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd, |
462 | struct apic_chip_data *apicd) | |
463 | { | |
464 | unsigned long flags; | |
465 | bool realloc = false; | |
466 | ||
467 | apicd->vector = ISA_IRQ_VECTOR(virq); | |
468 | apicd->cpu = 0; | |
469 | ||
470 | raw_spin_lock_irqsave(&vector_lock, flags); | |
471 | /* | |
472 | * If the interrupt is activated, then it must stay at this vector | |
473 | * position. That's usually the timer interrupt (0). | |
474 | */ | |
475 | if (irqd_is_activated(irqd)) { | |
476 | trace_vector_setup(virq, true, 0); | |
477 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); | |
478 | } else { | |
479 | /* Release the vector */ | |
480 | apicd->can_reserve = true; | |
481 | clear_irq_vector(irqd); | |
482 | realloc = true; | |
483 | } | |
484 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
485 | return realloc; | |
486 | } | |
487 | ||
b5dc8e6c JL |
488 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, |
489 | unsigned int nr_irqs, void *arg) | |
490 | { | |
491 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
492 | struct apic_chip_data *apicd; |
493 | struct irq_data *irqd; | |
5f2dbbc5 | 494 | int i, err, node; |
b5dc8e6c JL |
495 | |
496 | if (disable_apic) | |
497 | return -ENXIO; | |
498 | ||
499 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
500 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
501 | return -ENOSYS; | |
502 | ||
b5dc8e6c | 503 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
504 | irqd = irq_domain_get_irq_data(domain, virq + i); |
505 | BUG_ON(!irqd); | |
506 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
507 | WARN_ON_ONCE(irqd->chip_data); |
508 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 509 | if (!apicd) { |
b5dc8e6c JL |
510 | err = -ENOMEM; |
511 | goto error; | |
512 | } | |
513 | ||
69cde000 | 514 | apicd->irq = virq + i; |
86ba6551 TG |
515 | irqd->chip = &lapic_controller; |
516 | irqd->chip_data = apicd; | |
517 | irqd->hwirq = virq + i; | |
518 | irqd_set_single_target(irqd); | |
4ef76eb6 | 519 | /* |
69cde000 TG |
520 | * Legacy vectors are already assigned when the IOAPIC |
521 | * takes them over. They stay on the same vector. This is | |
522 | * required for check_timer() to work correctly as it might | |
523 | * switch back to legacy mode. Only update the hardware | |
524 | * config. | |
4ef76eb6 TG |
525 | */ |
526 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
464d1230 TG |
527 | if (!vector_configure_legacy(virq + i, irqd, apicd)) |
528 | continue; | |
4ef76eb6 TG |
529 | } |
530 | ||
2db1f959 | 531 | err = assign_irq_vector_policy(irqd, info); |
69cde000 | 532 | trace_vector_setup(virq + i, false, err); |
b5dc8e6c JL |
533 | if (err) |
534 | goto error; | |
535 | } | |
536 | ||
537 | return 0; | |
538 | ||
539 | error: | |
540 | x86_vector_free_irqs(domain, virq, i + 1); | |
541 | return err; | |
542 | } | |
543 | ||
65d7ed57 | 544 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
d553d03f CIK |
545 | static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, |
546 | struct irq_data *irqd, int ind) | |
65d7ed57 | 547 | { |
ba224fea | 548 | unsigned int cpu, vector, prev_cpu, prev_vector; |
65d7ed57 TG |
549 | struct apic_chip_data *apicd; |
550 | unsigned long flags; | |
551 | int irq; | |
552 | ||
553 | if (!irqd) { | |
554 | irq_matrix_debug_show(m, vector_matrix, ind); | |
555 | return; | |
556 | } | |
557 | ||
558 | irq = irqd->irq; | |
559 | if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { | |
560 | seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); | |
561 | seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); | |
562 | return; | |
563 | } | |
564 | ||
565 | apicd = irqd->chip_data; | |
566 | if (!apicd) { | |
567 | seq_printf(m, "%*sVector: Not assigned\n", ind, ""); | |
568 | return; | |
569 | } | |
570 | ||
571 | raw_spin_lock_irqsave(&vector_lock, flags); | |
572 | cpu = apicd->cpu; | |
ba224fea | 573 | vector = apicd->vector; |
65d7ed57 | 574 | prev_cpu = apicd->prev_cpu; |
ba224fea | 575 | prev_vector = apicd->prev_vector; |
65d7ed57 | 576 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
ba224fea | 577 | seq_printf(m, "%*sVector: %5u\n", ind, "", vector); |
65d7ed57 | 578 | seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu); |
ba224fea TG |
579 | if (prev_vector) { |
580 | seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vector); | |
65d7ed57 TG |
581 | seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu); |
582 | } | |
583 | } | |
584 | #endif | |
585 | ||
eb18cf55 | 586 | static const struct irq_domain_ops x86_vector_domain_ops = { |
65d7ed57 TG |
587 | .alloc = x86_vector_alloc_irqs, |
588 | .free = x86_vector_free_irqs, | |
2db1f959 TG |
589 | .activate = x86_vector_activate, |
590 | .deactivate = x86_vector_deactivate, | |
65d7ed57 TG |
591 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
592 | .debug_show = x86_vector_debug_show, | |
593 | #endif | |
b5dc8e6c JL |
594 | }; |
595 | ||
11d686e9 JL |
596 | int __init arch_probe_nr_irqs(void) |
597 | { | |
598 | int nr; | |
599 | ||
600 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
601 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
602 | ||
603 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
fd2fa6c1 | 604 | #if defined(CONFIG_PCI_MSI) |
11d686e9 JL |
605 | /* |
606 | * for MSI and HT dyn irq | |
607 | */ | |
608 | if (gsi_top <= NR_IRQS_LEGACY) | |
609 | nr += 8 * nr_cpu_ids; | |
610 | else | |
611 | nr += gsi_top * 16; | |
612 | #endif | |
613 | if (nr < nr_irqs) | |
614 | nr_irqs = nr; | |
615 | ||
8c058b0b VK |
616 | /* |
617 | * We don't know if PIC is present at this point so we need to do | |
618 | * probe() to get the right number of legacy IRQs. | |
619 | */ | |
620 | return legacy_pic->probe(); | |
11d686e9 JL |
621 | } |
622 | ||
0fa115da TG |
623 | void lapic_assign_legacy_vector(unsigned int irq, bool replace) |
624 | { | |
625 | /* | |
626 | * Use assign system here so it wont get accounted as allocated | |
627 | * and moveable in the cpu hotplug check and it prevents managed | |
628 | * irq reservation from touching it. | |
629 | */ | |
630 | irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); | |
631 | } | |
632 | ||
633 | void __init lapic_assign_system_vectors(void) | |
634 | { | |
635 | unsigned int i, vector = 0; | |
636 | ||
637 | for_each_set_bit_from(vector, system_vectors, NR_VECTORS) | |
638 | irq_matrix_assign_system(vector_matrix, vector, false); | |
639 | ||
640 | if (nr_legacy_irqs() > 1) | |
641 | lapic_assign_legacy_vector(PIC_CASCADE_IR, false); | |
642 | ||
643 | /* System vectors are reserved, online it */ | |
644 | irq_matrix_online(vector_matrix); | |
645 | ||
646 | /* Mark the preallocated legacy interrupts */ | |
647 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
648 | if (i != PIC_CASCADE_IR) | |
649 | irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); | |
650 | } | |
651 | } | |
652 | ||
11d686e9 JL |
653 | int __init arch_early_irq_init(void) |
654 | { | |
9d35f859 TG |
655 | struct fwnode_handle *fn; |
656 | ||
9d35f859 TG |
657 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
658 | BUG_ON(!fn); | |
659 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
660 | NULL); | |
b5dc8e6c | 661 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 662 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
663 | irq_set_default_host(x86_vector_domain); |
664 | ||
52f518a3 JL |
665 | arch_init_msi_domain(x86_vector_domain); |
666 | ||
3716fd27 | 667 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
f7fa7aee | 668 | |
0fa115da TG |
669 | /* |
670 | * Allocate the vector matrix allocator data structure and limit the | |
671 | * search area. | |
672 | */ | |
673 | vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, | |
674 | FIRST_SYSTEM_VECTOR); | |
675 | BUG_ON(!vector_matrix); | |
676 | ||
11d686e9 JL |
677 | return arch_early_ioapic_init(); |
678 | } | |
679 | ||
ba801640 | 680 | #ifdef CONFIG_SMP |
74afab7a | 681 | |
f0cc6cca TG |
682 | static struct irq_desc *__setup_vector_irq(int vector) |
683 | { | |
684 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
685 | ||
686 | /* Check whether the irq is in the legacy space */ | |
687 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
688 | return VECTOR_UNUSED; | |
689 | /* Check whether the irq is handled by the IOAPIC */ | |
690 | if (test_bit(isairq, &io_apic_irqs)) | |
691 | return VECTOR_UNUSED; | |
692 | return irq_to_desc(isairq); | |
693 | } | |
694 | ||
0fa115da TG |
695 | /* Online the local APIC infrastructure and initialize the vectors */ |
696 | void lapic_online(void) | |
74afab7a | 697 | { |
f0cc6cca | 698 | unsigned int vector; |
74afab7a | 699 | |
5a3f75e3 | 700 | lockdep_assert_held(&vector_lock); |
0fa115da TG |
701 | |
702 | /* Online the vector matrix array for this CPU */ | |
703 | irq_matrix_online(vector_matrix); | |
704 | ||
74afab7a | 705 | /* |
f0cc6cca TG |
706 | * The interrupt affinity logic never targets interrupts to offline |
707 | * CPUs. The exception are the legacy PIC interrupts. In general | |
708 | * they are only targeted to CPU0, but depending on the platform | |
709 | * they can be distributed to any online CPU in hardware. The | |
710 | * kernel has no influence on that. So all active legacy vectors | |
711 | * must be installed on all CPUs. All non legacy interrupts can be | |
712 | * cleared. | |
74afab7a | 713 | */ |
f0cc6cca TG |
714 | for (vector = 0; vector < NR_VECTORS; vector++) |
715 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a JL |
716 | } |
717 | ||
0fa115da TG |
718 | void lapic_offline(void) |
719 | { | |
720 | lock_vector_lock(); | |
721 | irq_matrix_offline(vector_matrix); | |
722 | unlock_vector_lock(); | |
723 | } | |
724 | ||
ba801640 TG |
725 | static int apic_set_affinity(struct irq_data *irqd, |
726 | const struct cpumask *dest, bool force) | |
727 | { | |
02edee15 | 728 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
ba801640 TG |
729 | int err; |
730 | ||
02edee15 TG |
731 | /* |
732 | * Core code can call here for inactive interrupts. For inactive | |
733 | * interrupts which use managed or reservation mode there is no | |
734 | * point in going through the vector assignment right now as the | |
735 | * activation will assign a vector which fits the destination | |
736 | * cpumask. Let the core code store the destination mask and be | |
737 | * done with it. | |
738 | */ | |
739 | if (!irqd_is_activated(irqd) && | |
740 | (apicd->is_managed || apicd->can_reserve)) | |
741 | return IRQ_SET_MASK_OK; | |
742 | ||
2db1f959 TG |
743 | raw_spin_lock(&vector_lock); |
744 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
745 | if (irqd_affinity_is_managed(irqd)) | |
746 | err = assign_managed_vector(irqd, vector_searchmask); | |
747 | else | |
748 | err = assign_vector_locked(irqd, vector_searchmask); | |
749 | raw_spin_unlock(&vector_lock); | |
ba801640 TG |
750 | return err ? err : IRQ_SET_MASK_OK; |
751 | } | |
752 | ||
753 | #else | |
754 | # define apic_set_affinity NULL | |
755 | #endif | |
756 | ||
86ba6551 | 757 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 758 | { |
86ba6551 | 759 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 760 | unsigned long flags; |
74afab7a JL |
761 | |
762 | raw_spin_lock_irqsave(&vector_lock, flags); | |
ba224fea | 763 | apic->send_IPI(apicd->cpu, apicd->vector); |
74afab7a JL |
764 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
765 | ||
766 | return 1; | |
767 | } | |
768 | ||
86ba6551 | 769 | void apic_ack_edge(struct irq_data *irqd) |
74afab7a | 770 | { |
86ba6551 TG |
771 | irq_complete_move(irqd_cfg(irqd)); |
772 | irq_move_irq(irqd); | |
74afab7a JL |
773 | ack_APIC_irq(); |
774 | } | |
775 | ||
b5dc8e6c | 776 | static struct irq_chip lapic_controller = { |
8947dfb2 | 777 | .name = "APIC", |
b5dc8e6c | 778 | .irq_ack = apic_ack_edge, |
68f9f440 | 779 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
780 | .irq_retrigger = apic_retrigger_irq, |
781 | }; | |
782 | ||
74afab7a | 783 | #ifdef CONFIG_SMP |
c6c2002b | 784 | |
69cde000 TG |
785 | static void free_moved_vector(struct apic_chip_data *apicd) |
786 | { | |
ba224fea | 787 | unsigned int vector = apicd->prev_vector; |
69cde000 | 788 | unsigned int cpu = apicd->prev_cpu; |
2db1f959 TG |
789 | bool managed = apicd->is_managed; |
790 | ||
791 | /* | |
792 | * This should never happen. Managed interrupts are not | |
793 | * migrated except on CPU down, which does not involve the | |
794 | * cleanup vector. But try to keep the accounting correct | |
795 | * nevertheless. | |
796 | */ | |
797 | WARN_ON_ONCE(managed); | |
69cde000 | 798 | |
0696d059 | 799 | trace_vector_free_moved(apicd->irq, cpu, vector, managed); |
2db1f959 | 800 | irq_matrix_free(vector_matrix, cpu, vector, managed); |
0696d059 | 801 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
69cde000 | 802 | hlist_del_init(&apicd->clist); |
ba224fea | 803 | apicd->prev_vector = 0; |
69cde000 TG |
804 | apicd->move_in_progress = 0; |
805 | } | |
806 | ||
c4158ff5 | 807 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 808 | { |
dccfe314 TG |
809 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
810 | struct apic_chip_data *apicd; | |
811 | struct hlist_node *tmp; | |
74afab7a | 812 | |
6af7faf6 | 813 | entering_ack_irq(); |
df54c493 TG |
814 | /* Prevent vectors vanishing under us */ |
815 | raw_spin_lock(&vector_lock); | |
816 | ||
dccfe314 | 817 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
ba224fea | 818 | unsigned int irr, vector = apicd->prev_vector; |
74afab7a | 819 | |
74afab7a | 820 | /* |
dccfe314 TG |
821 | * Paranoia: Check if the vector that needs to be cleaned |
822 | * up is registered at the APICs IRR. If so, then this is | |
823 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 824 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
825 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
826 | * priority external vector, so on return from this | |
827 | * interrupt the device interrupt will happen first. | |
74afab7a | 828 | */ |
dccfe314 TG |
829 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
830 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 831 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 832 | continue; |
74afab7a | 833 | } |
69cde000 | 834 | free_moved_vector(apicd); |
74afab7a JL |
835 | } |
836 | ||
df54c493 | 837 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 838 | exiting_irq(); |
74afab7a JL |
839 | } |
840 | ||
dccfe314 TG |
841 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
842 | { | |
843 | unsigned int cpu; | |
844 | ||
845 | raw_spin_lock(&vector_lock); | |
846 | apicd->move_in_progress = 0; | |
847 | cpu = apicd->prev_cpu; | |
848 | if (cpu_online(cpu)) { | |
849 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
850 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
851 | } else { | |
ba224fea | 852 | apicd->prev_vector = 0; |
dccfe314 TG |
853 | } |
854 | raw_spin_unlock(&vector_lock); | |
855 | } | |
856 | ||
857 | void send_cleanup_vector(struct irq_cfg *cfg) | |
858 | { | |
859 | struct apic_chip_data *apicd; | |
860 | ||
ba224fea | 861 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
dccfe314 TG |
862 | if (apicd->move_in_progress) |
863 | __send_cleanup_vector(apicd); | |
864 | } | |
865 | ||
74afab7a JL |
866 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
867 | { | |
86ba6551 | 868 | struct apic_chip_data *apicd; |
74afab7a | 869 | |
ba224fea | 870 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
86ba6551 | 871 | if (likely(!apicd->move_in_progress)) |
74afab7a JL |
872 | return; |
873 | ||
ba224fea | 874 | if (vector == apicd->vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 875 | __send_cleanup_vector(apicd); |
74afab7a JL |
876 | } |
877 | ||
878 | void irq_complete_move(struct irq_cfg *cfg) | |
879 | { | |
880 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
881 | } | |
882 | ||
90a2282e | 883 | /* |
551adc60 | 884 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
885 | */ |
886 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 887 | { |
86ba6551 | 888 | struct apic_chip_data *apicd; |
dccfe314 TG |
889 | struct irq_data *irqd; |
890 | unsigned int vector; | |
56d7d2f4 | 891 | |
db91aa79 MW |
892 | /* |
893 | * The function is called for all descriptors regardless of which | |
894 | * irqdomain they belong to. For example if an IRQ is provided by | |
895 | * an irq_chip as part of a GPIO driver, the chip data for that | |
896 | * descriptor is specific to the irq_chip in question. | |
897 | * | |
898 | * Check first that the chip_data is what we expect | |
899 | * (apic_chip_data) before touching it any further. | |
900 | */ | |
86ba6551 | 901 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 902 | irq_desc_get_irq(desc)); |
86ba6551 | 903 | if (!irqd) |
db91aa79 MW |
904 | return; |
905 | ||
dccfe314 | 906 | raw_spin_lock(&vector_lock); |
86ba6551 | 907 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
908 | if (!apicd) |
909 | goto unlock; | |
db91aa79 | 910 | |
dccfe314 | 911 | /* |
ba224fea | 912 | * If prev_vector is empty, no action required. |
dccfe314 | 913 | */ |
ba224fea | 914 | vector = apicd->prev_vector; |
dccfe314 TG |
915 | if (!vector) |
916 | goto unlock; | |
74afab7a | 917 | |
56d7d2f4 | 918 | /* |
dccfe314 | 919 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
920 | * done yet, then the following setaffinity call will fail with |
921 | * -EBUSY. This can leave the interrupt in a stale state. | |
922 | * | |
551adc60 TG |
923 | * All CPUs are stuck in stop machine with interrupts disabled so |
924 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 925 | * |
551adc60 TG |
926 | * 1) The interrupt is in move_in_progress state. That means that we |
927 | * have not seen an interrupt since the io_apic was reprogrammed to | |
928 | * the new vector. | |
929 | * | |
930 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
931 | * have not been processed yet. | |
932 | */ | |
86ba6551 | 933 | if (apicd->move_in_progress) { |
98229aa3 | 934 | /* |
551adc60 TG |
935 | * In theory there is a race: |
936 | * | |
937 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
938 | * is effective, i.e. it's raised on | |
939 | * the old vector. | |
940 | * | |
941 | * So if the target cpu cannot handle that interrupt before | |
942 | * the old vector is cleaned up, we get a spurious interrupt | |
943 | * and in the worst case the ioapic irq line becomes stale. | |
944 | * | |
945 | * But in case of cpu hotplug this should be a non issue | |
946 | * because if the affinity update happens right before all | |
947 | * cpus rendevouz in stop machine, there is no way that the | |
948 | * interrupt can be blocked on the target cpu because all cpus | |
949 | * loops first with interrupts enabled in stop machine, so the | |
950 | * old vector is not yet cleaned up when the interrupt fires. | |
951 | * | |
952 | * So the only way to run into this issue is if the delivery | |
953 | * of the interrupt on the apic/system bus would be delayed | |
954 | * beyond the point where the target cpu disables interrupts | |
955 | * in stop machine. I doubt that it can happen, but at least | |
956 | * there is a theroretical chance. Virtualization might be | |
957 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
958 | * as stupid as the real hardware. | |
959 | * | |
960 | * Anyway, there is nothing we can do about that at this point | |
961 | * w/o refactoring the whole fixup_irq() business completely. | |
962 | * We print at least the irq number and the old vector number, | |
963 | * so we have the necessary information when a problem in that | |
964 | * area arises. | |
98229aa3 | 965 | */ |
551adc60 | 966 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 967 | irqd->irq, vector); |
98229aa3 | 968 | } |
69cde000 | 969 | free_moved_vector(apicd); |
dccfe314 | 970 | unlock: |
56d7d2f4 | 971 | raw_spin_unlock(&vector_lock); |
74afab7a | 972 | } |
2cffad7b TG |
973 | |
974 | #ifdef CONFIG_HOTPLUG_CPU | |
975 | /* | |
976 | * Note, this is not accurate accounting, but at least good enough to | |
977 | * prevent that the actual interrupt move will run out of vectors. | |
978 | */ | |
979 | int lapic_can_unplug_cpu(void) | |
980 | { | |
981 | unsigned int rsvd, avl, tomove, cpu = smp_processor_id(); | |
982 | int ret = 0; | |
983 | ||
984 | raw_spin_lock(&vector_lock); | |
985 | tomove = irq_matrix_allocated(vector_matrix); | |
986 | avl = irq_matrix_available(vector_matrix, true); | |
987 | if (avl < tomove) { | |
988 | pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n", | |
989 | cpu, tomove, avl); | |
990 | ret = -ENOSPC; | |
991 | goto out; | |
992 | } | |
993 | rsvd = irq_matrix_reserved(vector_matrix); | |
994 | if (avl < rsvd) { | |
995 | pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n", | |
996 | rsvd, avl); | |
997 | } | |
998 | out: | |
999 | raw_spin_unlock(&vector_lock); | |
1000 | return ret; | |
1001 | } | |
1002 | #endif /* HOTPLUG_CPU */ | |
1003 | #endif /* SMP */ | |
74afab7a | 1004 | |
74afab7a JL |
1005 | static void __init print_APIC_field(int base) |
1006 | { | |
1007 | int i; | |
1008 | ||
1009 | printk(KERN_DEBUG); | |
1010 | ||
1011 | for (i = 0; i < 8; i++) | |
1012 | pr_cont("%08x", apic_read(base + i*0x10)); | |
1013 | ||
1014 | pr_cont("\n"); | |
1015 | } | |
1016 | ||
1017 | static void __init print_local_APIC(void *dummy) | |
1018 | { | |
1019 | unsigned int i, v, ver, maxlvt; | |
1020 | u64 icr; | |
1021 | ||
849d3569 JL |
1022 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
1023 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 1024 | v = apic_read(APIC_ID); |
849d3569 | 1025 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 1026 | v = apic_read(APIC_LVR); |
849d3569 | 1027 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
1028 | ver = GET_APIC_VERSION(v); |
1029 | maxlvt = lapic_get_maxlvt(); | |
1030 | ||
1031 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 1032 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
1033 | |
1034 | /* !82489DX */ | |
1035 | if (APIC_INTEGRATED(ver)) { | |
1036 | if (!APIC_XAPIC(ver)) { | |
1037 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
1038 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
1039 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
1040 | } |
1041 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 1042 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
1043 | } |
1044 | ||
1045 | /* | |
1046 | * Remote read supported only in the 82489DX and local APIC for | |
1047 | * Pentium processors. | |
1048 | */ | |
1049 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1050 | v = apic_read(APIC_RRR); | |
849d3569 | 1051 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
1052 | } |
1053 | ||
1054 | v = apic_read(APIC_LDR); | |
849d3569 | 1055 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
1056 | if (!x2apic_enabled()) { |
1057 | v = apic_read(APIC_DFR); | |
849d3569 | 1058 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
1059 | } |
1060 | v = apic_read(APIC_SPIV); | |
849d3569 | 1061 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 1062 | |
849d3569 | 1063 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 1064 | print_APIC_field(APIC_ISR); |
849d3569 | 1065 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 1066 | print_APIC_field(APIC_TMR); |
849d3569 | 1067 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
1068 | print_APIC_field(APIC_IRR); |
1069 | ||
1070 | /* !82489DX */ | |
1071 | if (APIC_INTEGRATED(ver)) { | |
1072 | /* Due to the Pentium erratum 3AP. */ | |
1073 | if (maxlvt > 3) | |
1074 | apic_write(APIC_ESR, 0); | |
1075 | ||
1076 | v = apic_read(APIC_ESR); | |
849d3569 | 1077 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
1078 | } |
1079 | ||
1080 | icr = apic_icr_read(); | |
849d3569 JL |
1081 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
1082 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
1083 | |
1084 | v = apic_read(APIC_LVTT); | |
849d3569 | 1085 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
1086 | |
1087 | if (maxlvt > 3) { | |
1088 | /* PC is LVT#4. */ | |
1089 | v = apic_read(APIC_LVTPC); | |
849d3569 | 1090 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
1091 | } |
1092 | v = apic_read(APIC_LVT0); | |
849d3569 | 1093 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 1094 | v = apic_read(APIC_LVT1); |
849d3569 | 1095 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
1096 | |
1097 | if (maxlvt > 2) { | |
1098 | /* ERR is LVT#3. */ | |
1099 | v = apic_read(APIC_LVTERR); | |
849d3569 | 1100 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
1101 | } |
1102 | ||
1103 | v = apic_read(APIC_TMICT); | |
849d3569 | 1104 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 1105 | v = apic_read(APIC_TMCCT); |
849d3569 | 1106 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 1107 | v = apic_read(APIC_TDCR); |
849d3569 | 1108 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
1109 | |
1110 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1111 | v = apic_read(APIC_EFEAT); | |
1112 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 1113 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 1114 | v = apic_read(APIC_ECTRL); |
849d3569 | 1115 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
1116 | for (i = 0; i < maxlvt; i++) { |
1117 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 1118 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
1119 | } |
1120 | } | |
1121 | pr_cont("\n"); | |
1122 | } | |
1123 | ||
1124 | static void __init print_local_APICs(int maxcpu) | |
1125 | { | |
1126 | int cpu; | |
1127 | ||
1128 | if (!maxcpu) | |
1129 | return; | |
1130 | ||
1131 | preempt_disable(); | |
1132 | for_each_online_cpu(cpu) { | |
1133 | if (cpu >= maxcpu) | |
1134 | break; | |
1135 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1136 | } | |
1137 | preempt_enable(); | |
1138 | } | |
1139 | ||
1140 | static void __init print_PIC(void) | |
1141 | { | |
1142 | unsigned int v; | |
1143 | unsigned long flags; | |
1144 | ||
1145 | if (!nr_legacy_irqs()) | |
1146 | return; | |
1147 | ||
849d3569 | 1148 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
1149 | |
1150 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
1151 | ||
1152 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 1153 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
1154 | |
1155 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 1156 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
1157 | |
1158 | outb(0x0b, 0xa0); | |
1159 | outb(0x0b, 0x20); | |
1160 | v = inb(0xa0) << 8 | inb(0x20); | |
1161 | outb(0x0a, 0xa0); | |
1162 | outb(0x0a, 0x20); | |
1163 | ||
1164 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
1165 | ||
849d3569 | 1166 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
1167 | |
1168 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 1169 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
1170 | } |
1171 | ||
1172 | static int show_lapic __initdata = 1; | |
1173 | static __init int setup_show_lapic(char *arg) | |
1174 | { | |
1175 | int num = -1; | |
1176 | ||
1177 | if (strcmp(arg, "all") == 0) { | |
1178 | show_lapic = CONFIG_NR_CPUS; | |
1179 | } else { | |
1180 | get_option(&arg, &num); | |
1181 | if (num >= 0) | |
1182 | show_lapic = num; | |
1183 | } | |
1184 | ||
1185 | return 1; | |
1186 | } | |
1187 | __setup("show_lapic=", setup_show_lapic); | |
1188 | ||
1189 | static int __init print_ICs(void) | |
1190 | { | |
1191 | if (apic_verbosity == APIC_QUIET) | |
1192 | return 0; | |
1193 | ||
1194 | print_PIC(); | |
1195 | ||
1196 | /* don't print out if apic is not there */ | |
93984fbd | 1197 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
1198 | return 0; |
1199 | ||
1200 | print_local_APICs(show_lapic); | |
1201 | print_IO_APICs(); | |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | late_initcall(print_ICs); |