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Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 32 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 33 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 34 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 35 | static struct irq_chip lapic_controller; |
13315320 | 36 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 37 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 38 | #endif |
74afab7a JL |
39 | |
40 | void lock_vector_lock(void) | |
41 | { | |
42 | /* Used to the online set of cpus does not change | |
43 | * during assign_irq_vector. | |
44 | */ | |
45 | raw_spin_lock(&vector_lock); | |
46 | } | |
47 | ||
48 | void unlock_vector_lock(void) | |
49 | { | |
50 | raw_spin_unlock(&vector_lock); | |
51 | } | |
52 | ||
7f3262ed | 53 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 54 | { |
b5dc8e6c JL |
55 | if (!irq_data) |
56 | return NULL; | |
57 | ||
58 | while (irq_data->parent_data) | |
59 | irq_data = irq_data->parent_data; | |
60 | ||
74afab7a JL |
61 | return irq_data->chip_data; |
62 | } | |
63 | ||
7f3262ed JL |
64 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
65 | { | |
66 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
67 | ||
68 | return data ? &data->cfg : NULL; | |
69 | } | |
c8f3e518 | 70 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
71 | |
72 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 73 | { |
7f3262ed JL |
74 | return irqd_cfg(irq_get_irq_data(irq)); |
75 | } | |
74afab7a | 76 | |
7f3262ed JL |
77 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
78 | { | |
79 | struct apic_chip_data *data; | |
80 | ||
81 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
82 | if (!data) | |
74afab7a | 83 | return NULL; |
7f3262ed JL |
84 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
85 | goto out_data; | |
86 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 87 | goto out_domain; |
7f3262ed | 88 | return data; |
74afab7a | 89 | out_domain: |
7f3262ed JL |
90 | free_cpumask_var(data->domain); |
91 | out_data: | |
92 | kfree(data); | |
74afab7a JL |
93 | return NULL; |
94 | } | |
95 | ||
7f3262ed | 96 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 97 | { |
7f3262ed JL |
98 | if (data) { |
99 | free_cpumask_var(data->domain); | |
100 | free_cpumask_var(data->old_domain); | |
101 | kfree(data); | |
b5dc8e6c | 102 | } |
74afab7a JL |
103 | } |
104 | ||
7f3262ed | 105 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
0e24f7c9 TG |
106 | const struct cpumask *mask, |
107 | struct irq_data *irqdata) | |
74afab7a JL |
108 | { |
109 | /* | |
110 | * NOTE! The local APIC isn't very good at handling | |
111 | * multiple interrupts at the same interrupt level. | |
112 | * As the interrupt level is determined by taking the | |
113 | * vector number and shifting that right by 4, we | |
114 | * want to spread these out a bit so that they don't | |
115 | * all fall in the same interrupt level. | |
116 | * | |
117 | * Also, we've got to be careful not to trash gate | |
118 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
119 | */ | |
120 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
121 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 122 | int cpu, vector; |
74afab7a | 123 | |
98229aa3 TG |
124 | /* |
125 | * If there is still a move in progress or the previous move has not | |
126 | * been cleaned up completely, tell the caller to come back later. | |
127 | */ | |
128 | if (d->move_in_progress || | |
129 | cpumask_intersects(d->old_domain, cpu_online_mask)) | |
74afab7a JL |
130 | return -EBUSY; |
131 | ||
74afab7a | 132 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 133 | cpumask_clear(d->old_domain); |
8a580f70 | 134 | cpumask_clear(searched_cpumask); |
74afab7a JL |
135 | cpu = cpumask_first_and(mask, cpu_online_mask); |
136 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 137 | int new_cpu, offset; |
74afab7a | 138 | |
fdba46ff | 139 | cpumask_copy(vector_cpumask, cpumask_of(cpu)); |
74afab7a | 140 | |
3716fd27 TG |
141 | /* |
142 | * Clear the offline cpus from @vector_cpumask for searching | |
143 | * and verify whether the result overlaps with @mask. If true, | |
91cd9cb7 | 144 | * then the call to apic->cpu_mask_to_apicid() will |
3716fd27 TG |
145 | * succeed as well. If not, no point in trying to find a |
146 | * vector in this mask. | |
147 | */ | |
148 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
149 | if (!cpumask_intersects(vector_searchmask, mask)) | |
150 | goto next_cpu; | |
151 | ||
f7fa7aee | 152 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 153 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 154 | goto success; |
74afab7a | 155 | /* |
ab25ac02 TG |
156 | * Mark the cpus which are not longer in the mask for |
157 | * cleanup. | |
74afab7a | 158 | */ |
ab25ac02 TG |
159 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
160 | vector = d->cfg.vector; | |
161 | goto update; | |
74afab7a JL |
162 | } |
163 | ||
164 | vector = current_vector; | |
165 | offset = current_offset; | |
166 | next: | |
167 | vector += 16; | |
05161b9c | 168 | if (vector >= FIRST_SYSTEM_VECTOR) { |
74afab7a JL |
169 | offset = (offset + 1) % 16; |
170 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
171 | } | |
172 | ||
95ffeb4b TG |
173 | /* If the search wrapped around, try the next cpu */ |
174 | if (unlikely(current_vector == vector)) | |
175 | goto next_cpu; | |
74afab7a | 176 | |
7854f822 | 177 | if (test_bit(vector, system_vectors)) |
74afab7a JL |
178 | goto next; |
179 | ||
3716fd27 | 180 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 181 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
182 | goto next; |
183 | } | |
184 | /* Found one! */ | |
185 | current_vector = vector; | |
186 | current_offset = offset; | |
ab25ac02 TG |
187 | /* Schedule the old vector for cleanup on all cpus */ |
188 | if (d->cfg.vector) | |
7f3262ed | 189 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 190 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 191 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 192 | goto update; |
95ffeb4b TG |
193 | |
194 | next_cpu: | |
195 | /* | |
196 | * We exclude the current @vector_cpumask from the requested | |
197 | * @mask and try again with the next online cpu in the | |
198 | * result. We cannot modify @mask, so we use @vector_cpumask | |
199 | * as a temporary buffer here as it will be reassigned when | |
200 | * calling apic->vector_allocation_domain() above. | |
201 | */ | |
202 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
203 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
204 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
205 | continue; | |
74afab7a | 206 | } |
433cbd57 | 207 | return -ENOSPC; |
74afab7a | 208 | |
ab25ac02 | 209 | update: |
847667ef TG |
210 | /* |
211 | * Exclude offline cpus from the cleanup mask and set the | |
212 | * move_in_progress flag when the result is not empty. | |
213 | */ | |
214 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
215 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
551adc60 | 216 | d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; |
ab25ac02 TG |
217 | d->cfg.vector = vector; |
218 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 219 | success: |
3716fd27 TG |
220 | /* |
221 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
222 | * as we already established, that mask & d->domain & cpu_online_mask | |
223 | * is not empty. | |
52b166af TG |
224 | * |
225 | * vector_searchmask is a subset of d->domain and has the offline | |
226 | * cpus masked out. | |
3716fd27 | 227 | */ |
91cd9cb7 | 228 | cpumask_and(vector_searchmask, vector_searchmask, mask); |
0e24f7c9 TG |
229 | BUG_ON(apic->cpu_mask_to_apicid(vector_searchmask, irqdata, |
230 | &d->cfg.dest_apicid)); | |
3716fd27 | 231 | return 0; |
74afab7a JL |
232 | } |
233 | ||
7f3262ed | 234 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
0e24f7c9 TG |
235 | const struct cpumask *mask, |
236 | struct irq_data *irqdata) | |
74afab7a JL |
237 | { |
238 | int err; | |
239 | unsigned long flags; | |
240 | ||
241 | raw_spin_lock_irqsave(&vector_lock, flags); | |
0e24f7c9 | 242 | err = __assign_irq_vector(irq, data, mask, irqdata); |
74afab7a JL |
243 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
244 | return err; | |
245 | } | |
246 | ||
486ca539 JL |
247 | static int assign_irq_vector_policy(int irq, int node, |
248 | struct apic_chip_data *data, | |
0e24f7c9 TG |
249 | struct irq_alloc_info *info, |
250 | struct irq_data *irqdata) | |
486ca539 JL |
251 | { |
252 | if (info && info->mask) | |
0e24f7c9 | 253 | return assign_irq_vector(irq, data, info->mask, irqdata); |
486ca539 | 254 | if (node != NUMA_NO_NODE && |
0e24f7c9 | 255 | assign_irq_vector(irq, data, cpumask_of_node(node), irqdata) == 0) |
486ca539 | 256 | return 0; |
c1d1ee9a | 257 | return assign_irq_vector(irq, data, cpu_online_mask, irqdata); |
486ca539 JL |
258 | } |
259 | ||
7f3262ed | 260 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a | 261 | { |
a782a7e4 | 262 | struct irq_desc *desc; |
a782a7e4 | 263 | int cpu, vector; |
74afab7a | 264 | |
1bdb8970 KB |
265 | if (!data->cfg.vector) |
266 | return; | |
74afab7a | 267 | |
7f3262ed JL |
268 | vector = data->cfg.vector; |
269 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 270 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 271 | |
7f3262ed JL |
272 | data->cfg.vector = 0; |
273 | cpumask_clear(data->domain); | |
74afab7a | 274 | |
98229aa3 TG |
275 | /* |
276 | * If move is in progress or the old_domain mask is not empty, | |
277 | * i.e. the cleanup IPI has not been processed yet, we need to remove | |
278 | * the old references to desc from all cpus vector tables. | |
279 | */ | |
280 | if (!data->move_in_progress && cpumask_empty(data->old_domain)) | |
74afab7a | 281 | return; |
74afab7a | 282 | |
a782a7e4 | 283 | desc = irq_to_desc(irq); |
7f3262ed | 284 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
285 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
286 | vector++) { | |
a782a7e4 | 287 | if (per_cpu(vector_irq, cpu)[vector] != desc) |
74afab7a | 288 | continue; |
7276c6a2 | 289 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
290 | break; |
291 | } | |
292 | } | |
7f3262ed | 293 | data->move_in_progress = 0; |
74afab7a JL |
294 | } |
295 | ||
b5dc8e6c JL |
296 | void init_irq_alloc_info(struct irq_alloc_info *info, |
297 | const struct cpumask *mask) | |
298 | { | |
299 | memset(info, 0, sizeof(*info)); | |
300 | info->mask = mask; | |
301 | } | |
302 | ||
303 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
304 | { | |
305 | if (src) | |
306 | *dst = *src; | |
307 | else | |
308 | memset(dst, 0, sizeof(*dst)); | |
309 | } | |
310 | ||
b5dc8e6c JL |
311 | static void x86_vector_free_irqs(struct irq_domain *domain, |
312 | unsigned int virq, unsigned int nr_irqs) | |
313 | { | |
111abeba | 314 | struct apic_chip_data *apic_data; |
b5dc8e6c | 315 | struct irq_data *irq_data; |
111abeba | 316 | unsigned long flags; |
b5dc8e6c JL |
317 | int i; |
318 | ||
319 | for (i = 0; i < nr_irqs; i++) { | |
320 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
321 | if (irq_data && irq_data->chip_data) { | |
111abeba | 322 | raw_spin_lock_irqsave(&vector_lock, flags); |
b5dc8e6c | 323 | clear_irq_vector(virq + i, irq_data->chip_data); |
111abeba JL |
324 | apic_data = irq_data->chip_data; |
325 | irq_domain_reset_irq_data(irq_data); | |
326 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
327 | free_apic_chip_data(apic_data); | |
13315320 JL |
328 | #ifdef CONFIG_X86_IO_APIC |
329 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 330 | legacy_irq_data[virq + i] = NULL; |
13315320 | 331 | #endif |
b5dc8e6c JL |
332 | } |
333 | } | |
334 | } | |
335 | ||
336 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
337 | unsigned int nr_irqs, void *arg) | |
338 | { | |
339 | struct irq_alloc_info *info = arg; | |
7f3262ed | 340 | struct apic_chip_data *data; |
b5dc8e6c | 341 | struct irq_data *irq_data; |
5f2dbbc5 | 342 | int i, err, node; |
b5dc8e6c JL |
343 | |
344 | if (disable_apic) | |
345 | return -ENXIO; | |
346 | ||
347 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
348 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
349 | return -ENOSYS; | |
350 | ||
b5dc8e6c JL |
351 | for (i = 0; i < nr_irqs; i++) { |
352 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
353 | BUG_ON(!irq_data); | |
5f2dbbc5 | 354 | node = irq_data_get_node(irq_data); |
13315320 | 355 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
356 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
357 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
358 | else |
359 | #endif | |
5f2dbbc5 | 360 | data = alloc_apic_chip_data(node); |
7f3262ed | 361 | if (!data) { |
b5dc8e6c JL |
362 | err = -ENOMEM; |
363 | goto error; | |
364 | } | |
365 | ||
366 | irq_data->chip = &lapic_controller; | |
7f3262ed | 367 | irq_data->chip_data = data; |
b5dc8e6c | 368 | irq_data->hwirq = virq + i; |
fdba46ff | 369 | irqd_set_single_target(irq_data); |
0e24f7c9 TG |
370 | err = assign_irq_vector_policy(virq + i, node, data, info, |
371 | irq_data); | |
b5dc8e6c JL |
372 | if (err) |
373 | goto error; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | ||
378 | error: | |
379 | x86_vector_free_irqs(domain, virq, i + 1); | |
380 | return err; | |
381 | } | |
382 | ||
eb18cf55 TG |
383 | static const struct irq_domain_ops x86_vector_domain_ops = { |
384 | .alloc = x86_vector_alloc_irqs, | |
385 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
386 | }; |
387 | ||
11d686e9 JL |
388 | int __init arch_probe_nr_irqs(void) |
389 | { | |
390 | int nr; | |
391 | ||
392 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
393 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
394 | ||
395 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
396 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
397 | /* | |
398 | * for MSI and HT dyn irq | |
399 | */ | |
400 | if (gsi_top <= NR_IRQS_LEGACY) | |
401 | nr += 8 * nr_cpu_ids; | |
402 | else | |
403 | nr += gsi_top * 16; | |
404 | #endif | |
405 | if (nr < nr_irqs) | |
406 | nr_irqs = nr; | |
407 | ||
8c058b0b VK |
408 | /* |
409 | * We don't know if PIC is present at this point so we need to do | |
410 | * probe() to get the right number of legacy IRQs. | |
411 | */ | |
412 | return legacy_pic->probe(); | |
11d686e9 JL |
413 | } |
414 | ||
13315320 | 415 | #ifdef CONFIG_X86_IO_APIC |
a884d25f | 416 | static void __init init_legacy_irqs(void) |
13315320 JL |
417 | { |
418 | int i, node = cpu_to_node(0); | |
7f3262ed | 419 | struct apic_chip_data *data; |
13315320 JL |
420 | |
421 | /* | |
422 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 423 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
424 | */ |
425 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
426 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
427 | BUG_ON(!data); | |
191a6635 IM |
428 | |
429 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
fdba46ff | 430 | cpumask_copy(data->domain, cpumask_of(0)); |
7f3262ed | 431 | irq_set_chip_data(i, data); |
13315320 JL |
432 | } |
433 | } | |
434 | #else | |
a884d25f | 435 | static inline void init_legacy_irqs(void) { } |
13315320 JL |
436 | #endif |
437 | ||
11d686e9 JL |
438 | int __init arch_early_irq_init(void) |
439 | { | |
9d35f859 TG |
440 | struct fwnode_handle *fn; |
441 | ||
13315320 JL |
442 | init_legacy_irqs(); |
443 | ||
9d35f859 TG |
444 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
445 | BUG_ON(!fn); | |
446 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
447 | NULL); | |
b5dc8e6c | 448 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 449 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
450 | irq_set_default_host(x86_vector_domain); |
451 | ||
52f518a3 | 452 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 453 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 454 | |
f7fa7aee | 455 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 456 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 457 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 458 | |
11d686e9 JL |
459 | return arch_early_ioapic_init(); |
460 | } | |
461 | ||
f0cc6cca TG |
462 | /* Temporary hack to keep things working */ |
463 | static void vector_update_shutdown_irqs(void) | |
74afab7a | 464 | { |
a782a7e4 | 465 | struct irq_desc *desc; |
f0cc6cca | 466 | int irq; |
74afab7a | 467 | |
a782a7e4 | 468 | for_each_irq_desc(irq, desc) { |
f0cc6cca TG |
469 | struct irq_data *irqd = irq_desc_get_irq_data(desc); |
470 | struct apic_chip_data *ad = apic_chip_data(irqd); | |
74afab7a | 471 | |
f0cc6cca TG |
472 | if (ad && cpumask_test_cpu(cpu, ad->domain) && ad->cfg.vector) |
473 | this_cpu_write(vector_irq[ad->cfg.vector], desc); | |
74afab7a | 474 | } |
74afab7a JL |
475 | } |
476 | ||
f0cc6cca TG |
477 | static struct irq_desc *__setup_vector_irq(int vector) |
478 | { | |
479 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
480 | ||
481 | /* Check whether the irq is in the legacy space */ | |
482 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
483 | return VECTOR_UNUSED; | |
484 | /* Check whether the irq is handled by the IOAPIC */ | |
485 | if (test_bit(isairq, &io_apic_irqs)) | |
486 | return VECTOR_UNUSED; | |
487 | return irq_to_desc(isairq); | |
488 | } | |
489 | ||
74afab7a | 490 | /* |
5a3f75e3 | 491 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
492 | */ |
493 | void setup_vector_irq(int cpu) | |
494 | { | |
f0cc6cca | 495 | unsigned int vector; |
74afab7a | 496 | |
5a3f75e3 | 497 | lockdep_assert_held(&vector_lock); |
74afab7a | 498 | /* |
f0cc6cca TG |
499 | * The interrupt affinity logic never targets interrupts to offline |
500 | * CPUs. The exception are the legacy PIC interrupts. In general | |
501 | * they are only targeted to CPU0, but depending on the platform | |
502 | * they can be distributed to any online CPU in hardware. The | |
503 | * kernel has no influence on that. So all active legacy vectors | |
504 | * must be installed on all CPUs. All non legacy interrupts can be | |
505 | * cleared. | |
74afab7a | 506 | */ |
f0cc6cca TG |
507 | for (vector = 0; vector < NR_VECTORS; vector++) |
508 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a | 509 | |
f0cc6cca TG |
510 | /* |
511 | * Until the rewrite of the managed interrupt management is in | |
512 | * place it's necessary to walk the irq descriptors and check for | |
513 | * interrupts which are targeted at this CPU. | |
514 | */ | |
515 | vector_update_shutdown_irqs(); | |
74afab7a JL |
516 | } |
517 | ||
7f3262ed | 518 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 519 | { |
7f3262ed | 520 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
521 | unsigned long flags; |
522 | int cpu; | |
523 | ||
524 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
525 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
526 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
527 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
528 | ||
529 | return 1; | |
530 | } | |
531 | ||
532 | void apic_ack_edge(struct irq_data *data) | |
533 | { | |
a9786091 | 534 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
535 | irq_move_irq(data); |
536 | ack_APIC_irq(); | |
537 | } | |
538 | ||
68f9f440 JL |
539 | static int apic_set_affinity(struct irq_data *irq_data, |
540 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 541 | { |
7f3262ed | 542 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
543 | int err, irq = irq_data->irq; |
544 | ||
97f2645f | 545 | if (!IS_ENABLED(CONFIG_SMP)) |
b5dc8e6c JL |
546 | return -EPERM; |
547 | ||
548 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
549 | return -EINVAL; | |
550 | ||
0e24f7c9 | 551 | err = assign_irq_vector(irq, data, dest, irq_data); |
3716fd27 | 552 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
553 | } |
554 | ||
555 | static struct irq_chip lapic_controller = { | |
8947dfb2 | 556 | .name = "APIC", |
b5dc8e6c | 557 | .irq_ack = apic_ack_edge, |
68f9f440 | 558 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
559 | .irq_retrigger = apic_retrigger_irq, |
560 | }; | |
561 | ||
74afab7a | 562 | #ifdef CONFIG_SMP |
7f3262ed | 563 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a | 564 | { |
c1684f50 | 565 | raw_spin_lock(&vector_lock); |
5da0c121 | 566 | cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); |
c1684f50 | 567 | data->move_in_progress = 0; |
5da0c121 TG |
568 | if (!cpumask_empty(data->old_domain)) |
569 | apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR); | |
c1684f50 | 570 | raw_spin_unlock(&vector_lock); |
74afab7a JL |
571 | } |
572 | ||
c6c2002b JL |
573 | void send_cleanup_vector(struct irq_cfg *cfg) |
574 | { | |
7f3262ed JL |
575 | struct apic_chip_data *data; |
576 | ||
577 | data = container_of(cfg, struct apic_chip_data, cfg); | |
578 | if (data->move_in_progress) | |
579 | __send_cleanup_vector(data); | |
c6c2002b JL |
580 | } |
581 | ||
c4158ff5 | 582 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a JL |
583 | { |
584 | unsigned vector, me; | |
585 | ||
6af7faf6 | 586 | entering_ack_irq(); |
74afab7a | 587 | |
df54c493 TG |
588 | /* Prevent vectors vanishing under us */ |
589 | raw_spin_lock(&vector_lock); | |
590 | ||
74afab7a JL |
591 | me = smp_processor_id(); |
592 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
7f3262ed | 593 | struct apic_chip_data *data; |
a782a7e4 TG |
594 | struct irq_desc *desc; |
595 | unsigned int irr; | |
74afab7a | 596 | |
df54c493 | 597 | retry: |
a782a7e4 TG |
598 | desc = __this_cpu_read(vector_irq[vector]); |
599 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
600 | continue; |
601 | ||
df54c493 TG |
602 | if (!raw_spin_trylock(&desc->lock)) { |
603 | raw_spin_unlock(&vector_lock); | |
604 | cpu_relax(); | |
605 | raw_spin_lock(&vector_lock); | |
606 | goto retry; | |
607 | } | |
74afab7a | 608 | |
a782a7e4 | 609 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 610 | if (!data) |
df54c493 | 611 | goto unlock; |
74afab7a JL |
612 | |
613 | /* | |
98229aa3 TG |
614 | * Nothing to cleanup if irq migration is in progress |
615 | * or this cpu is not set in the cleanup mask. | |
74afab7a | 616 | */ |
98229aa3 TG |
617 | if (data->move_in_progress || |
618 | !cpumask_test_cpu(me, data->old_domain)) | |
74afab7a JL |
619 | goto unlock; |
620 | ||
98229aa3 TG |
621 | /* |
622 | * We have two cases to handle here: | |
623 | * 1) vector is unchanged but the target mask got reduced | |
624 | * 2) vector and the target mask has changed | |
625 | * | |
626 | * #1 is obvious, but in #2 we have two vectors with the same | |
627 | * irq descriptor: the old and the new vector. So we need to | |
628 | * make sure that we only cleanup the old vector. The new | |
629 | * vector has the current @vector number in the config and | |
630 | * this cpu is part of the target mask. We better leave that | |
631 | * one alone. | |
632 | */ | |
7f3262ed JL |
633 | if (vector == data->cfg.vector && |
634 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
635 | goto unlock; |
636 | ||
637 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
638 | /* | |
639 | * Check if the vector that needs to be cleanedup is | |
640 | * registered at the cpu's IRR. If so, then this is not | |
641 | * the best time to clean it up. Lets clean it up in the | |
642 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
643 | * to myself. | |
644 | */ | |
645 | if (irr & (1 << (vector % 32))) { | |
646 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
647 | goto unlock; | |
648 | } | |
7276c6a2 | 649 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
98229aa3 | 650 | cpumask_clear_cpu(me, data->old_domain); |
74afab7a JL |
651 | unlock: |
652 | raw_spin_unlock(&desc->lock); | |
653 | } | |
654 | ||
df54c493 TG |
655 | raw_spin_unlock(&vector_lock); |
656 | ||
6af7faf6 | 657 | exiting_irq(); |
74afab7a JL |
658 | } |
659 | ||
660 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
661 | { | |
662 | unsigned me; | |
7f3262ed | 663 | struct apic_chip_data *data; |
74afab7a | 664 | |
7f3262ed JL |
665 | data = container_of(cfg, struct apic_chip_data, cfg); |
666 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
667 | return; |
668 | ||
669 | me = smp_processor_id(); | |
7f3262ed JL |
670 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
671 | __send_cleanup_vector(data); | |
74afab7a JL |
672 | } |
673 | ||
674 | void irq_complete_move(struct irq_cfg *cfg) | |
675 | { | |
676 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
677 | } | |
678 | ||
90a2282e | 679 | /* |
551adc60 | 680 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
681 | */ |
682 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 683 | { |
db91aa79 MW |
684 | struct irq_data *irqdata; |
685 | struct apic_chip_data *data; | |
686 | struct irq_cfg *cfg; | |
551adc60 | 687 | unsigned int cpu; |
56d7d2f4 | 688 | |
db91aa79 MW |
689 | /* |
690 | * The function is called for all descriptors regardless of which | |
691 | * irqdomain they belong to. For example if an IRQ is provided by | |
692 | * an irq_chip as part of a GPIO driver, the chip data for that | |
693 | * descriptor is specific to the irq_chip in question. | |
694 | * | |
695 | * Check first that the chip_data is what we expect | |
696 | * (apic_chip_data) before touching it any further. | |
697 | */ | |
698 | irqdata = irq_domain_get_irq_data(x86_vector_domain, | |
699 | irq_desc_get_irq(desc)); | |
700 | if (!irqdata) | |
701 | return; | |
702 | ||
703 | data = apic_chip_data(irqdata); | |
704 | cfg = data ? &data->cfg : NULL; | |
705 | ||
56d7d2f4 TG |
706 | if (!cfg) |
707 | return; | |
74afab7a | 708 | |
56d7d2f4 | 709 | /* |
98229aa3 TG |
710 | * This is tricky. If the cleanup of @data->old_domain has not been |
711 | * done yet, then the following setaffinity call will fail with | |
712 | * -EBUSY. This can leave the interrupt in a stale state. | |
713 | * | |
551adc60 TG |
714 | * All CPUs are stuck in stop machine with interrupts disabled so |
715 | * calling __irq_complete_move() would be completely pointless. | |
56d7d2f4 TG |
716 | */ |
717 | raw_spin_lock(&vector_lock); | |
551adc60 TG |
718 | /* |
719 | * Clean out all offline cpus (including the outgoing one) from the | |
720 | * old_domain mask. | |
721 | */ | |
98229aa3 | 722 | cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); |
551adc60 TG |
723 | |
724 | /* | |
725 | * If move_in_progress is cleared and the old_domain mask is empty, | |
726 | * then there is nothing to cleanup. fixup_irqs() will take care of | |
727 | * the stale vectors on the outgoing cpu. | |
728 | */ | |
729 | if (!data->move_in_progress && cpumask_empty(data->old_domain)) { | |
98229aa3 | 730 | raw_spin_unlock(&vector_lock); |
551adc60 TG |
731 | return; |
732 | } | |
733 | ||
734 | /* | |
735 | * 1) The interrupt is in move_in_progress state. That means that we | |
736 | * have not seen an interrupt since the io_apic was reprogrammed to | |
737 | * the new vector. | |
738 | * | |
739 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
740 | * have not been processed yet. | |
741 | */ | |
742 | if (data->move_in_progress) { | |
98229aa3 | 743 | /* |
551adc60 TG |
744 | * In theory there is a race: |
745 | * | |
746 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
747 | * is effective, i.e. it's raised on | |
748 | * the old vector. | |
749 | * | |
750 | * So if the target cpu cannot handle that interrupt before | |
751 | * the old vector is cleaned up, we get a spurious interrupt | |
752 | * and in the worst case the ioapic irq line becomes stale. | |
753 | * | |
754 | * But in case of cpu hotplug this should be a non issue | |
755 | * because if the affinity update happens right before all | |
756 | * cpus rendevouz in stop machine, there is no way that the | |
757 | * interrupt can be blocked on the target cpu because all cpus | |
758 | * loops first with interrupts enabled in stop machine, so the | |
759 | * old vector is not yet cleaned up when the interrupt fires. | |
760 | * | |
761 | * So the only way to run into this issue is if the delivery | |
762 | * of the interrupt on the apic/system bus would be delayed | |
763 | * beyond the point where the target cpu disables interrupts | |
764 | * in stop machine. I doubt that it can happen, but at least | |
765 | * there is a theroretical chance. Virtualization might be | |
766 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
767 | * as stupid as the real hardware. | |
768 | * | |
769 | * Anyway, there is nothing we can do about that at this point | |
770 | * w/o refactoring the whole fixup_irq() business completely. | |
771 | * We print at least the irq number and the old vector number, | |
772 | * so we have the necessary information when a problem in that | |
773 | * area arises. | |
98229aa3 | 774 | */ |
551adc60 TG |
775 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
776 | irqdata->irq, cfg->old_vector); | |
98229aa3 | 777 | } |
551adc60 TG |
778 | /* |
779 | * If old_domain is not empty, then other cpus still have the irq | |
780 | * descriptor set in their vector array. Clean it up. | |
781 | */ | |
782 | for_each_cpu(cpu, data->old_domain) | |
783 | per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED; | |
784 | ||
785 | /* Cleanup the left overs of the (half finished) move */ | |
786 | cpumask_clear(data->old_domain); | |
787 | data->move_in_progress = 0; | |
56d7d2f4 | 788 | raw_spin_unlock(&vector_lock); |
74afab7a | 789 | } |
74afab7a JL |
790 | #endif |
791 | ||
74afab7a JL |
792 | static void __init print_APIC_field(int base) |
793 | { | |
794 | int i; | |
795 | ||
796 | printk(KERN_DEBUG); | |
797 | ||
798 | for (i = 0; i < 8; i++) | |
799 | pr_cont("%08x", apic_read(base + i*0x10)); | |
800 | ||
801 | pr_cont("\n"); | |
802 | } | |
803 | ||
804 | static void __init print_local_APIC(void *dummy) | |
805 | { | |
806 | unsigned int i, v, ver, maxlvt; | |
807 | u64 icr; | |
808 | ||
849d3569 JL |
809 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
810 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 811 | v = apic_read(APIC_ID); |
849d3569 | 812 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 813 | v = apic_read(APIC_LVR); |
849d3569 | 814 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
815 | ver = GET_APIC_VERSION(v); |
816 | maxlvt = lapic_get_maxlvt(); | |
817 | ||
818 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 819 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
820 | |
821 | /* !82489DX */ | |
822 | if (APIC_INTEGRATED(ver)) { | |
823 | if (!APIC_XAPIC(ver)) { | |
824 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
825 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
826 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
827 | } |
828 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 829 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
830 | } |
831 | ||
832 | /* | |
833 | * Remote read supported only in the 82489DX and local APIC for | |
834 | * Pentium processors. | |
835 | */ | |
836 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
837 | v = apic_read(APIC_RRR); | |
849d3569 | 838 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
839 | } |
840 | ||
841 | v = apic_read(APIC_LDR); | |
849d3569 | 842 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
843 | if (!x2apic_enabled()) { |
844 | v = apic_read(APIC_DFR); | |
849d3569 | 845 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
846 | } |
847 | v = apic_read(APIC_SPIV); | |
849d3569 | 848 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 849 | |
849d3569 | 850 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 851 | print_APIC_field(APIC_ISR); |
849d3569 | 852 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 853 | print_APIC_field(APIC_TMR); |
849d3569 | 854 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
855 | print_APIC_field(APIC_IRR); |
856 | ||
857 | /* !82489DX */ | |
858 | if (APIC_INTEGRATED(ver)) { | |
859 | /* Due to the Pentium erratum 3AP. */ | |
860 | if (maxlvt > 3) | |
861 | apic_write(APIC_ESR, 0); | |
862 | ||
863 | v = apic_read(APIC_ESR); | |
849d3569 | 864 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
865 | } |
866 | ||
867 | icr = apic_icr_read(); | |
849d3569 JL |
868 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
869 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
870 | |
871 | v = apic_read(APIC_LVTT); | |
849d3569 | 872 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
873 | |
874 | if (maxlvt > 3) { | |
875 | /* PC is LVT#4. */ | |
876 | v = apic_read(APIC_LVTPC); | |
849d3569 | 877 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
878 | } |
879 | v = apic_read(APIC_LVT0); | |
849d3569 | 880 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 881 | v = apic_read(APIC_LVT1); |
849d3569 | 882 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
883 | |
884 | if (maxlvt > 2) { | |
885 | /* ERR is LVT#3. */ | |
886 | v = apic_read(APIC_LVTERR); | |
849d3569 | 887 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
888 | } |
889 | ||
890 | v = apic_read(APIC_TMICT); | |
849d3569 | 891 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 892 | v = apic_read(APIC_TMCCT); |
849d3569 | 893 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 894 | v = apic_read(APIC_TDCR); |
849d3569 | 895 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
896 | |
897 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
898 | v = apic_read(APIC_EFEAT); | |
899 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 900 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 901 | v = apic_read(APIC_ECTRL); |
849d3569 | 902 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
903 | for (i = 0; i < maxlvt; i++) { |
904 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 905 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
906 | } |
907 | } | |
908 | pr_cont("\n"); | |
909 | } | |
910 | ||
911 | static void __init print_local_APICs(int maxcpu) | |
912 | { | |
913 | int cpu; | |
914 | ||
915 | if (!maxcpu) | |
916 | return; | |
917 | ||
918 | preempt_disable(); | |
919 | for_each_online_cpu(cpu) { | |
920 | if (cpu >= maxcpu) | |
921 | break; | |
922 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
923 | } | |
924 | preempt_enable(); | |
925 | } | |
926 | ||
927 | static void __init print_PIC(void) | |
928 | { | |
929 | unsigned int v; | |
930 | unsigned long flags; | |
931 | ||
932 | if (!nr_legacy_irqs()) | |
933 | return; | |
934 | ||
849d3569 | 935 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
936 | |
937 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
938 | ||
939 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 940 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
941 | |
942 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 943 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
944 | |
945 | outb(0x0b, 0xa0); | |
946 | outb(0x0b, 0x20); | |
947 | v = inb(0xa0) << 8 | inb(0x20); | |
948 | outb(0x0a, 0xa0); | |
949 | outb(0x0a, 0x20); | |
950 | ||
951 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
952 | ||
849d3569 | 953 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
954 | |
955 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 956 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
957 | } |
958 | ||
959 | static int show_lapic __initdata = 1; | |
960 | static __init int setup_show_lapic(char *arg) | |
961 | { | |
962 | int num = -1; | |
963 | ||
964 | if (strcmp(arg, "all") == 0) { | |
965 | show_lapic = CONFIG_NR_CPUS; | |
966 | } else { | |
967 | get_option(&arg, &num); | |
968 | if (num >= 0) | |
969 | show_lapic = num; | |
970 | } | |
971 | ||
972 | return 1; | |
973 | } | |
974 | __setup("show_lapic=", setup_show_lapic); | |
975 | ||
976 | static int __init print_ICs(void) | |
977 | { | |
978 | if (apic_verbosity == APIC_QUIET) | |
979 | return 0; | |
980 | ||
981 | print_PIC(); | |
982 | ||
983 | /* don't print out if apic is not there */ | |
93984fbd | 984 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
985 | return 0; |
986 | ||
987 | print_local_APICs(show_lapic); | |
988 | print_IO_APICs(); | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
993 | late_initcall(print_ICs); |