]>
Commit | Line | Data |
---|---|---|
74afab7a | 1 | /* |
fd2fa6c1 | 2 | * Local APIC related interfaces to support IOAPIC, MSI, etc. |
74afab7a JL |
3 | * |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
f901f138 | 14 | #include <linux/irq.h> |
65d7ed57 | 15 | #include <linux/seq_file.h> |
74afab7a JL |
16 | #include <linux/init.h> |
17 | #include <linux/compiler.h> | |
74afab7a | 18 | #include <linux/slab.h> |
d746d1eb | 19 | #include <asm/irqdomain.h> |
74afab7a JL |
20 | #include <asm/hw_irq.h> |
21 | #include <asm/apic.h> | |
22 | #include <asm/i8259.h> | |
23 | #include <asm/desc.h> | |
24 | #include <asm/irq_remapping.h> | |
25 | ||
8d1e3dca TG |
26 | #include <asm/trace/irq_vectors.h> |
27 | ||
7f3262ed | 28 | struct apic_chip_data { |
ba224fea TG |
29 | struct irq_cfg hw_irq_cfg; |
30 | unsigned int vector; | |
31 | unsigned int prev_vector; | |
029c6e1c TG |
32 | unsigned int cpu; |
33 | unsigned int prev_cpu; | |
69cde000 | 34 | unsigned int irq; |
dccfe314 | 35 | struct hlist_node clist; |
2db1f959 | 36 | unsigned int move_in_progress : 1, |
4900be83 TG |
37 | is_managed : 1, |
38 | can_reserve : 1, | |
39 | has_reserved : 1; | |
7f3262ed JL |
40 | }; |
41 | ||
b5dc8e6c | 42 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 43 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 44 | static DEFINE_RAW_SPINLOCK(vector_lock); |
69cde000 | 45 | static cpumask_var_t vector_searchmask; |
b5dc8e6c | 46 | static struct irq_chip lapic_controller; |
0fa115da | 47 | static struct irq_matrix *vector_matrix; |
dccfe314 TG |
48 | #ifdef CONFIG_SMP |
49 | static DEFINE_PER_CPU(struct hlist_head, cleanup_list); | |
50 | #endif | |
74afab7a JL |
51 | |
52 | void lock_vector_lock(void) | |
53 | { | |
54 | /* Used to the online set of cpus does not change | |
55 | * during assign_irq_vector. | |
56 | */ | |
57 | raw_spin_lock(&vector_lock); | |
58 | } | |
59 | ||
60 | void unlock_vector_lock(void) | |
61 | { | |
62 | raw_spin_unlock(&vector_lock); | |
63 | } | |
64 | ||
99a1482d TG |
65 | void init_irq_alloc_info(struct irq_alloc_info *info, |
66 | const struct cpumask *mask) | |
67 | { | |
68 | memset(info, 0, sizeof(*info)); | |
69 | info->mask = mask; | |
70 | } | |
71 | ||
72 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
73 | { | |
74 | if (src) | |
75 | *dst = *src; | |
76 | else | |
77 | memset(dst, 0, sizeof(*dst)); | |
78 | } | |
79 | ||
86ba6551 | 80 | static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) |
74afab7a | 81 | { |
86ba6551 | 82 | if (!irqd) |
b5dc8e6c JL |
83 | return NULL; |
84 | ||
86ba6551 TG |
85 | while (irqd->parent_data) |
86 | irqd = irqd->parent_data; | |
b5dc8e6c | 87 | |
86ba6551 | 88 | return irqd->chip_data; |
74afab7a JL |
89 | } |
90 | ||
86ba6551 | 91 | struct irq_cfg *irqd_cfg(struct irq_data *irqd) |
7f3262ed | 92 | { |
86ba6551 | 93 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
7f3262ed | 94 | |
ba224fea | 95 | return apicd ? &apicd->hw_irq_cfg : NULL; |
7f3262ed | 96 | } |
c8f3e518 | 97 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
98 | |
99 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 100 | { |
7f3262ed JL |
101 | return irqd_cfg(irq_get_irq_data(irq)); |
102 | } | |
74afab7a | 103 | |
7f3262ed JL |
104 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
105 | { | |
86ba6551 | 106 | struct apic_chip_data *apicd; |
7f3262ed | 107 | |
86ba6551 | 108 | apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); |
69cde000 TG |
109 | if (apicd) |
110 | INIT_HLIST_NODE(&apicd->clist); | |
86ba6551 | 111 | return apicd; |
74afab7a JL |
112 | } |
113 | ||
86ba6551 | 114 | static void free_apic_chip_data(struct apic_chip_data *apicd) |
74afab7a | 115 | { |
69cde000 | 116 | kfree(apicd); |
74afab7a JL |
117 | } |
118 | ||
ba224fea TG |
119 | static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector, |
120 | unsigned int cpu) | |
74afab7a | 121 | { |
69cde000 | 122 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 123 | |
69cde000 | 124 | lockdep_assert_held(&vector_lock); |
74afab7a | 125 | |
ba224fea TG |
126 | apicd->hw_irq_cfg.vector = vector; |
127 | apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); | |
128 | irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); | |
129 | trace_vector_config(irqd->irq, vector, cpu, | |
130 | apicd->hw_irq_cfg.dest_apicid); | |
69cde000 | 131 | } |
74afab7a | 132 | |
69cde000 TG |
133 | static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, |
134 | unsigned int newcpu) | |
135 | { | |
136 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
137 | struct irq_desc *desc = irq_data_to_desc(irqd); | |
4e9bf0e4 | 138 | bool managed = irqd_affinity_is_managed(irqd); |
74afab7a | 139 | |
69cde000 | 140 | lockdep_assert_held(&vector_lock); |
74afab7a | 141 | |
ba224fea | 142 | trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector, |
69cde000 | 143 | apicd->cpu); |
74afab7a | 144 | |
4e9bf0e4 TG |
145 | /* |
146 | * If there is no vector associated or if the associated vector is | |
147 | * the shutdown vector, which is associated to make PCI/MSI | |
148 | * shutdown mode work, then there is nothing to release. Clear out | |
149 | * prev_vector for this and the offlined target case. | |
150 | */ | |
151 | apicd->prev_vector = 0; | |
152 | if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR) | |
153 | goto setnew; | |
154 | /* | |
155 | * If the target CPU of the previous vector is online, then mark | |
156 | * the vector as move in progress and store it for cleanup when the | |
157 | * first interrupt on the new vector arrives. If the target CPU is | |
158 | * offline then the regular release mechanism via the cleanup | |
159 | * vector is not possible and the vector can be immediately freed | |
160 | * in the underlying matrix allocator. | |
161 | */ | |
162 | if (cpu_online(apicd->cpu)) { | |
69cde000 | 163 | apicd->move_in_progress = true; |
ba224fea | 164 | apicd->prev_vector = apicd->vector; |
69cde000 TG |
165 | apicd->prev_cpu = apicd->cpu; |
166 | } else { | |
4e9bf0e4 TG |
167 | irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector, |
168 | managed); | |
69cde000 | 169 | } |
74afab7a | 170 | |
4e9bf0e4 | 171 | setnew: |
ba224fea | 172 | apicd->vector = newvec; |
69cde000 TG |
173 | apicd->cpu = newcpu; |
174 | BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec])); | |
175 | per_cpu(vector_irq, newcpu)[newvec] = desc; | |
176 | } | |
74afab7a | 177 | |
2db1f959 TG |
178 | static void vector_assign_managed_shutdown(struct irq_data *irqd) |
179 | { | |
180 | unsigned int cpu = cpumask_first(cpu_online_mask); | |
181 | ||
182 | apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu); | |
183 | } | |
184 | ||
185 | static int reserve_managed_vector(struct irq_data *irqd) | |
186 | { | |
187 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
188 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
189 | unsigned long flags; | |
190 | int ret; | |
191 | ||
192 | raw_spin_lock_irqsave(&vector_lock, flags); | |
193 | apicd->is_managed = true; | |
194 | ret = irq_matrix_reserve_managed(vector_matrix, affmsk); | |
195 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
196 | trace_vector_reserve_managed(irqd->irq, ret); | |
197 | return ret; | |
198 | } | |
199 | ||
4900be83 TG |
200 | static void reserve_irq_vector_locked(struct irq_data *irqd) |
201 | { | |
202 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
203 | ||
204 | irq_matrix_reserve(vector_matrix); | |
205 | apicd->can_reserve = true; | |
206 | apicd->has_reserved = true; | |
945f50a5 | 207 | irqd_set_can_reserve(irqd); |
4900be83 TG |
208 | trace_vector_reserve(irqd->irq, 0); |
209 | vector_assign_managed_shutdown(irqd); | |
210 | } | |
211 | ||
212 | static int reserve_irq_vector(struct irq_data *irqd) | |
213 | { | |
214 | unsigned long flags; | |
215 | ||
216 | raw_spin_lock_irqsave(&vector_lock, flags); | |
217 | reserve_irq_vector_locked(irqd); | |
218 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
219 | return 0; | |
220 | } | |
221 | ||
69cde000 TG |
222 | static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest) |
223 | { | |
224 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
4900be83 | 225 | bool resvd = apicd->has_reserved; |
69cde000 | 226 | unsigned int cpu = apicd->cpu; |
ba224fea TG |
227 | int vector = apicd->vector; |
228 | ||
229 | lockdep_assert_held(&vector_lock); | |
74afab7a | 230 | |
3716fd27 | 231 | /* |
69cde000 TG |
232 | * If the current target CPU is online and in the new requested |
233 | * affinity mask, there is no point in moving the interrupt from | |
234 | * one CPU to another. | |
3716fd27 | 235 | */ |
69cde000 TG |
236 | if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest)) |
237 | return 0; | |
238 | ||
7e47579d TG |
239 | /* |
240 | * Careful here. @apicd might either have move_in_progress set or | |
241 | * be enqueued for cleanup. Assigning a new vector would either | |
242 | * leave a stale vector on some CPU around or in case of a pending | |
243 | * cleanup corrupt the hlist. | |
244 | */ | |
245 | if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist)) | |
246 | return -EBUSY; | |
247 | ||
4900be83 | 248 | vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu); |
69cde000 TG |
249 | if (vector > 0) |
250 | apic_update_vector(irqd, vector, cpu); | |
4900be83 | 251 | trace_vector_alloc(irqd->irq, vector, resvd, vector); |
69cde000 TG |
252 | return vector; |
253 | } | |
254 | ||
255 | static int assign_vector_locked(struct irq_data *irqd, | |
256 | const struct cpumask *dest) | |
257 | { | |
ba224fea | 258 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
69cde000 TG |
259 | int vector = allocate_vector(irqd, dest); |
260 | ||
261 | if (vector < 0) | |
262 | return vector; | |
263 | ||
ba224fea | 264 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); |
3716fd27 | 265 | return 0; |
74afab7a JL |
266 | } |
267 | ||
69cde000 | 268 | static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest) |
74afab7a | 269 | { |
74afab7a | 270 | unsigned long flags; |
69cde000 | 271 | int ret; |
74afab7a JL |
272 | |
273 | raw_spin_lock_irqsave(&vector_lock, flags); | |
69cde000 TG |
274 | cpumask_and(vector_searchmask, dest, cpu_online_mask); |
275 | ret = assign_vector_locked(irqd, vector_searchmask); | |
74afab7a | 276 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
69cde000 | 277 | return ret; |
74afab7a JL |
278 | } |
279 | ||
2db1f959 TG |
280 | static int assign_irq_vector_any_locked(struct irq_data *irqd) |
281 | { | |
d6ffc6ac TG |
282 | /* Get the affinity mask - either irq_default_affinity or (user) set */ |
283 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
2db1f959 TG |
284 | int node = irq_data_get_node(irqd); |
285 | ||
d6ffc6ac TG |
286 | if (node == NUMA_NO_NODE) |
287 | goto all; | |
288 | /* Try the intersection of @affmsk and node mask */ | |
289 | cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk); | |
290 | if (!assign_vector_locked(irqd, vector_searchmask)) | |
291 | return 0; | |
292 | /* Try the node mask */ | |
293 | if (!assign_vector_locked(irqd, cpumask_of_node(node))) | |
294 | return 0; | |
295 | all: | |
296 | /* Try the full affinity mask */ | |
297 | cpumask_and(vector_searchmask, affmsk, cpu_online_mask); | |
298 | if (!assign_vector_locked(irqd, vector_searchmask)) | |
299 | return 0; | |
300 | /* Try the full online mask */ | |
2db1f959 TG |
301 | return assign_vector_locked(irqd, cpu_online_mask); |
302 | } | |
303 | ||
2db1f959 TG |
304 | static int |
305 | assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info) | |
486ca539 | 306 | { |
2db1f959 TG |
307 | if (irqd_affinity_is_managed(irqd)) |
308 | return reserve_managed_vector(irqd); | |
258d86ee | 309 | if (info->mask) |
69cde000 | 310 | return assign_irq_vector(irqd, info->mask); |
464d1230 TG |
311 | /* |
312 | * Make only a global reservation with no guarantee. A real vector | |
313 | * is associated at activation time. | |
314 | */ | |
4900be83 | 315 | return reserve_irq_vector(irqd); |
2db1f959 TG |
316 | } |
317 | ||
318 | static int | |
319 | assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest) | |
320 | { | |
321 | const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); | |
322 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
323 | int vector, cpu; | |
324 | ||
344541e8 DL |
325 | cpumask_and(vector_searchmask, dest, affmsk); |
326 | ||
2db1f959 TG |
327 | /* set_affinity might call here for nothing */ |
328 | if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask)) | |
486ca539 | 329 | return 0; |
344541e8 DL |
330 | vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask, |
331 | &cpu); | |
2db1f959 TG |
332 | trace_vector_alloc_managed(irqd->irq, vector, vector); |
333 | if (vector < 0) | |
334 | return vector; | |
335 | apic_update_vector(irqd, vector, cpu); | |
336 | apic_update_irq_cfg(irqd, vector, cpu); | |
337 | return 0; | |
486ca539 JL |
338 | } |
339 | ||
69cde000 | 340 | static void clear_irq_vector(struct irq_data *irqd) |
74afab7a | 341 | { |
69cde000 | 342 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
2db1f959 | 343 | bool managed = irqd_affinity_is_managed(irqd); |
ba224fea | 344 | unsigned int vector = apicd->vector; |
74afab7a | 345 | |
69cde000 | 346 | lockdep_assert_held(&vector_lock); |
ba224fea | 347 | |
dccfe314 | 348 | if (!vector) |
1bdb8970 | 349 | return; |
74afab7a | 350 | |
ba224fea | 351 | trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector, |
69cde000 TG |
352 | apicd->prev_cpu); |
353 | ||
3c8b2e14 | 354 | per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_SHUTDOWN; |
2db1f959 | 355 | irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); |
ba224fea | 356 | apicd->vector = 0; |
74afab7a | 357 | |
dccfe314 | 358 | /* Clean up move in progress */ |
ba224fea | 359 | vector = apicd->prev_vector; |
dccfe314 | 360 | if (!vector) |
74afab7a | 361 | return; |
74afab7a | 362 | |
3c8b2e14 | 363 | per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_SHUTDOWN; |
2db1f959 | 364 | irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); |
ba224fea | 365 | apicd->prev_vector = 0; |
86ba6551 | 366 | apicd->move_in_progress = 0; |
dccfe314 | 367 | hlist_del_init(&apicd->clist); |
74afab7a JL |
368 | } |
369 | ||
2db1f959 TG |
370 | static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd) |
371 | { | |
372 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
373 | unsigned long flags; | |
374 | ||
375 | trace_vector_deactivate(irqd->irq, apicd->is_managed, | |
4900be83 | 376 | apicd->can_reserve, false); |
2db1f959 | 377 | |
4900be83 TG |
378 | /* Regular fixed assigned interrupt */ |
379 | if (!apicd->is_managed && !apicd->can_reserve) | |
380 | return; | |
381 | /* If the interrupt has a global reservation, nothing to do */ | |
382 | if (apicd->has_reserved) | |
2db1f959 TG |
383 | return; |
384 | ||
385 | raw_spin_lock_irqsave(&vector_lock, flags); | |
386 | clear_irq_vector(irqd); | |
4900be83 TG |
387 | if (apicd->can_reserve) |
388 | reserve_irq_vector_locked(irqd); | |
389 | else | |
390 | vector_assign_managed_shutdown(irqd); | |
2db1f959 TG |
391 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
392 | } | |
393 | ||
4900be83 TG |
394 | static int activate_reserved(struct irq_data *irqd) |
395 | { | |
396 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
397 | int ret; | |
398 | ||
399 | ret = assign_irq_vector_any_locked(irqd); | |
bc976233 | 400 | if (!ret) { |
4900be83 | 401 | apicd->has_reserved = false; |
bc976233 TG |
402 | /* |
403 | * Core might have disabled reservation mode after | |
404 | * allocating the irq descriptor. Ideally this should | |
405 | * happen before allocation time, but that would require | |
406 | * completely convoluted ways of transporting that | |
407 | * information. | |
408 | */ | |
409 | if (!irqd_can_reserve(irqd)) | |
410 | apicd->can_reserve = false; | |
411 | } | |
0e020bb1 NH |
412 | |
413 | /* | |
414 | * Check to ensure that the effective affinity mask is a subset | |
415 | * the user supplied affinity mask, and warn the user if it is not | |
416 | */ | |
417 | if (!cpumask_subset(irq_data_get_effective_affinity_mask(irqd), | |
418 | irq_data_get_affinity_mask(irqd))) { | |
419 | pr_warn("irq %u: Affinity broken due to vector space exhaustion.\n", | |
420 | irqd->irq); | |
421 | } | |
422 | ||
4900be83 TG |
423 | return ret; |
424 | } | |
425 | ||
2db1f959 TG |
426 | static int activate_managed(struct irq_data *irqd) |
427 | { | |
428 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
429 | int ret; | |
430 | ||
431 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
432 | if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) { | |
433 | /* Something in the core code broke! Survive gracefully */ | |
434 | pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq); | |
2b15a02e | 435 | return -EINVAL; |
2db1f959 TG |
436 | } |
437 | ||
438 | ret = assign_managed_vector(irqd, vector_searchmask); | |
439 | /* | |
440 | * This should not happen. The vector reservation got buggered. Handle | |
441 | * it gracefully. | |
442 | */ | |
443 | if (WARN_ON_ONCE(ret < 0)) { | |
444 | pr_err("Managed startup irq %u, no vector available\n", | |
445 | irqd->irq); | |
446 | } | |
447 | return ret; | |
448 | } | |
449 | ||
450 | static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, | |
702cb0a0 | 451 | bool reserve) |
2db1f959 TG |
452 | { |
453 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
454 | unsigned long flags; | |
455 | int ret = 0; | |
456 | ||
457 | trace_vector_activate(irqd->irq, apicd->is_managed, | |
702cb0a0 | 458 | apicd->can_reserve, reserve); |
2db1f959 | 459 | |
4900be83 TG |
460 | /* Nothing to do for fixed assigned vectors */ |
461 | if (!apicd->can_reserve && !apicd->is_managed) | |
2db1f959 TG |
462 | return 0; |
463 | ||
464 | raw_spin_lock_irqsave(&vector_lock, flags); | |
702cb0a0 | 465 | if (reserve || irqd_is_managed_and_shutdown(irqd)) |
2db1f959 | 466 | vector_assign_managed_shutdown(irqd); |
4900be83 | 467 | else if (apicd->is_managed) |
2db1f959 | 468 | ret = activate_managed(irqd); |
4900be83 TG |
469 | else if (apicd->has_reserved) |
470 | ret = activate_reserved(irqd); | |
2db1f959 TG |
471 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
472 | return ret; | |
473 | } | |
474 | ||
475 | static void vector_free_reserved_and_managed(struct irq_data *irqd) | |
476 | { | |
477 | const struct cpumask *dest = irq_data_get_affinity_mask(irqd); | |
478 | struct apic_chip_data *apicd = apic_chip_data(irqd); | |
479 | ||
4900be83 TG |
480 | trace_vector_teardown(irqd->irq, apicd->is_managed, |
481 | apicd->has_reserved); | |
2db1f959 | 482 | |
4900be83 TG |
483 | if (apicd->has_reserved) |
484 | irq_matrix_remove_reserved(vector_matrix); | |
2db1f959 TG |
485 | if (apicd->is_managed) |
486 | irq_matrix_remove_managed(vector_matrix, dest); | |
487 | } | |
488 | ||
b5dc8e6c JL |
489 | static void x86_vector_free_irqs(struct irq_domain *domain, |
490 | unsigned int virq, unsigned int nr_irqs) | |
491 | { | |
86ba6551 TG |
492 | struct apic_chip_data *apicd; |
493 | struct irq_data *irqd; | |
111abeba | 494 | unsigned long flags; |
b5dc8e6c JL |
495 | int i; |
496 | ||
497 | for (i = 0; i < nr_irqs; i++) { | |
86ba6551 TG |
498 | irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); |
499 | if (irqd && irqd->chip_data) { | |
111abeba | 500 | raw_spin_lock_irqsave(&vector_lock, flags); |
69cde000 | 501 | clear_irq_vector(irqd); |
2db1f959 | 502 | vector_free_reserved_and_managed(irqd); |
86ba6551 TG |
503 | apicd = irqd->chip_data; |
504 | irq_domain_reset_irq_data(irqd); | |
111abeba | 505 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
86ba6551 | 506 | free_apic_chip_data(apicd); |
b5dc8e6c JL |
507 | } |
508 | } | |
509 | } | |
510 | ||
464d1230 TG |
511 | static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd, |
512 | struct apic_chip_data *apicd) | |
513 | { | |
514 | unsigned long flags; | |
515 | bool realloc = false; | |
516 | ||
517 | apicd->vector = ISA_IRQ_VECTOR(virq); | |
518 | apicd->cpu = 0; | |
519 | ||
520 | raw_spin_lock_irqsave(&vector_lock, flags); | |
521 | /* | |
522 | * If the interrupt is activated, then it must stay at this vector | |
523 | * position. That's usually the timer interrupt (0). | |
524 | */ | |
525 | if (irqd_is_activated(irqd)) { | |
526 | trace_vector_setup(virq, true, 0); | |
527 | apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); | |
528 | } else { | |
529 | /* Release the vector */ | |
530 | apicd->can_reserve = true; | |
945f50a5 | 531 | irqd_set_can_reserve(irqd); |
464d1230 TG |
532 | clear_irq_vector(irqd); |
533 | realloc = true; | |
534 | } | |
535 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
536 | return realloc; | |
537 | } | |
538 | ||
b5dc8e6c JL |
539 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, |
540 | unsigned int nr_irqs, void *arg) | |
541 | { | |
542 | struct irq_alloc_info *info = arg; | |
86ba6551 TG |
543 | struct apic_chip_data *apicd; |
544 | struct irq_data *irqd; | |
5f2dbbc5 | 545 | int i, err, node; |
b5dc8e6c JL |
546 | |
547 | if (disable_apic) | |
548 | return -ENXIO; | |
549 | ||
550 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
551 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
552 | return -ENOSYS; | |
553 | ||
b5dc8e6c | 554 | for (i = 0; i < nr_irqs; i++) { |
86ba6551 TG |
555 | irqd = irq_domain_get_irq_data(domain, virq + i); |
556 | BUG_ON(!irqd); | |
557 | node = irq_data_get_node(irqd); | |
4ef76eb6 TG |
558 | WARN_ON_ONCE(irqd->chip_data); |
559 | apicd = alloc_apic_chip_data(node); | |
86ba6551 | 560 | if (!apicd) { |
b5dc8e6c JL |
561 | err = -ENOMEM; |
562 | goto error; | |
563 | } | |
564 | ||
69cde000 | 565 | apicd->irq = virq + i; |
86ba6551 TG |
566 | irqd->chip = &lapic_controller; |
567 | irqd->chip_data = apicd; | |
568 | irqd->hwirq = virq + i; | |
569 | irqd_set_single_target(irqd); | |
4ef76eb6 | 570 | /* |
69cde000 TG |
571 | * Legacy vectors are already assigned when the IOAPIC |
572 | * takes them over. They stay on the same vector. This is | |
573 | * required for check_timer() to work correctly as it might | |
574 | * switch back to legacy mode. Only update the hardware | |
575 | * config. | |
4ef76eb6 TG |
576 | */ |
577 | if (info->flags & X86_IRQ_ALLOC_LEGACY) { | |
464d1230 TG |
578 | if (!vector_configure_legacy(virq + i, irqd, apicd)) |
579 | continue; | |
4ef76eb6 TG |
580 | } |
581 | ||
2db1f959 | 582 | err = assign_irq_vector_policy(irqd, info); |
69cde000 | 583 | trace_vector_setup(virq + i, false, err); |
45d55e7b TG |
584 | if (err) { |
585 | irqd->chip_data = NULL; | |
586 | free_apic_chip_data(apicd); | |
b5dc8e6c | 587 | goto error; |
45d55e7b | 588 | } |
b5dc8e6c JL |
589 | } |
590 | ||
591 | return 0; | |
592 | ||
593 | error: | |
45d55e7b | 594 | x86_vector_free_irqs(domain, virq, i); |
b5dc8e6c JL |
595 | return err; |
596 | } | |
597 | ||
65d7ed57 | 598 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
d553d03f CIK |
599 | static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, |
600 | struct irq_data *irqd, int ind) | |
65d7ed57 | 601 | { |
ba224fea | 602 | unsigned int cpu, vector, prev_cpu, prev_vector; |
65d7ed57 TG |
603 | struct apic_chip_data *apicd; |
604 | unsigned long flags; | |
605 | int irq; | |
606 | ||
607 | if (!irqd) { | |
608 | irq_matrix_debug_show(m, vector_matrix, ind); | |
609 | return; | |
610 | } | |
611 | ||
612 | irq = irqd->irq; | |
613 | if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { | |
614 | seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); | |
615 | seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); | |
616 | return; | |
617 | } | |
618 | ||
619 | apicd = irqd->chip_data; | |
620 | if (!apicd) { | |
621 | seq_printf(m, "%*sVector: Not assigned\n", ind, ""); | |
622 | return; | |
623 | } | |
624 | ||
625 | raw_spin_lock_irqsave(&vector_lock, flags); | |
626 | cpu = apicd->cpu; | |
ba224fea | 627 | vector = apicd->vector; |
65d7ed57 | 628 | prev_cpu = apicd->prev_cpu; |
ba224fea | 629 | prev_vector = apicd->prev_vector; |
65d7ed57 | 630 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
ba224fea | 631 | seq_printf(m, "%*sVector: %5u\n", ind, "", vector); |
65d7ed57 | 632 | seq_printf(m, "%*sTarget: %5u\n", ind, "", cpu); |
ba224fea TG |
633 | if (prev_vector) { |
634 | seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", prev_vector); | |
65d7ed57 TG |
635 | seq_printf(m, "%*sPrevious target: %5u\n", ind, "", prev_cpu); |
636 | } | |
637 | } | |
638 | #endif | |
639 | ||
eb18cf55 | 640 | static const struct irq_domain_ops x86_vector_domain_ops = { |
65d7ed57 TG |
641 | .alloc = x86_vector_alloc_irqs, |
642 | .free = x86_vector_free_irqs, | |
2db1f959 TG |
643 | .activate = x86_vector_activate, |
644 | .deactivate = x86_vector_deactivate, | |
65d7ed57 TG |
645 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
646 | .debug_show = x86_vector_debug_show, | |
647 | #endif | |
b5dc8e6c JL |
648 | }; |
649 | ||
11d686e9 JL |
650 | int __init arch_probe_nr_irqs(void) |
651 | { | |
652 | int nr; | |
653 | ||
654 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
655 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
656 | ||
657 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
fd2fa6c1 | 658 | #if defined(CONFIG_PCI_MSI) |
11d686e9 JL |
659 | /* |
660 | * for MSI and HT dyn irq | |
661 | */ | |
662 | if (gsi_top <= NR_IRQS_LEGACY) | |
663 | nr += 8 * nr_cpu_ids; | |
664 | else | |
665 | nr += gsi_top * 16; | |
666 | #endif | |
667 | if (nr < nr_irqs) | |
668 | nr_irqs = nr; | |
669 | ||
8c058b0b VK |
670 | /* |
671 | * We don't know if PIC is present at this point so we need to do | |
672 | * probe() to get the right number of legacy IRQs. | |
673 | */ | |
674 | return legacy_pic->probe(); | |
11d686e9 JL |
675 | } |
676 | ||
0fa115da TG |
677 | void lapic_assign_legacy_vector(unsigned int irq, bool replace) |
678 | { | |
679 | /* | |
680 | * Use assign system here so it wont get accounted as allocated | |
681 | * and moveable in the cpu hotplug check and it prevents managed | |
682 | * irq reservation from touching it. | |
683 | */ | |
684 | irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); | |
685 | } | |
686 | ||
687 | void __init lapic_assign_system_vectors(void) | |
688 | { | |
689 | unsigned int i, vector = 0; | |
690 | ||
691 | for_each_set_bit_from(vector, system_vectors, NR_VECTORS) | |
692 | irq_matrix_assign_system(vector_matrix, vector, false); | |
693 | ||
694 | if (nr_legacy_irqs() > 1) | |
695 | lapic_assign_legacy_vector(PIC_CASCADE_IR, false); | |
696 | ||
697 | /* System vectors are reserved, online it */ | |
698 | irq_matrix_online(vector_matrix); | |
699 | ||
700 | /* Mark the preallocated legacy interrupts */ | |
701 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
702 | if (i != PIC_CASCADE_IR) | |
703 | irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); | |
704 | } | |
705 | } | |
706 | ||
11d686e9 JL |
707 | int __init arch_early_irq_init(void) |
708 | { | |
9d35f859 TG |
709 | struct fwnode_handle *fn; |
710 | ||
9d35f859 TG |
711 | fn = irq_domain_alloc_named_fwnode("VECTOR"); |
712 | BUG_ON(!fn); | |
713 | x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, | |
714 | NULL); | |
b5dc8e6c | 715 | BUG_ON(x86_vector_domain == NULL); |
9d35f859 | 716 | irq_domain_free_fwnode(fn); |
b5dc8e6c JL |
717 | irq_set_default_host(x86_vector_domain); |
718 | ||
52f518a3 JL |
719 | arch_init_msi_domain(x86_vector_domain); |
720 | ||
3716fd27 | 721 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
f7fa7aee | 722 | |
0fa115da TG |
723 | /* |
724 | * Allocate the vector matrix allocator data structure and limit the | |
725 | * search area. | |
726 | */ | |
727 | vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, | |
728 | FIRST_SYSTEM_VECTOR); | |
729 | BUG_ON(!vector_matrix); | |
730 | ||
11d686e9 JL |
731 | return arch_early_ioapic_init(); |
732 | } | |
733 | ||
ba801640 | 734 | #ifdef CONFIG_SMP |
74afab7a | 735 | |
f0cc6cca TG |
736 | static struct irq_desc *__setup_vector_irq(int vector) |
737 | { | |
738 | int isairq = vector - ISA_IRQ_VECTOR(0); | |
739 | ||
740 | /* Check whether the irq is in the legacy space */ | |
741 | if (isairq < 0 || isairq >= nr_legacy_irqs()) | |
742 | return VECTOR_UNUSED; | |
743 | /* Check whether the irq is handled by the IOAPIC */ | |
744 | if (test_bit(isairq, &io_apic_irqs)) | |
745 | return VECTOR_UNUSED; | |
746 | return irq_to_desc(isairq); | |
747 | } | |
748 | ||
0fa115da TG |
749 | /* Online the local APIC infrastructure and initialize the vectors */ |
750 | void lapic_online(void) | |
74afab7a | 751 | { |
f0cc6cca | 752 | unsigned int vector; |
74afab7a | 753 | |
5a3f75e3 | 754 | lockdep_assert_held(&vector_lock); |
0fa115da TG |
755 | |
756 | /* Online the vector matrix array for this CPU */ | |
757 | irq_matrix_online(vector_matrix); | |
758 | ||
74afab7a | 759 | /* |
f0cc6cca TG |
760 | * The interrupt affinity logic never targets interrupts to offline |
761 | * CPUs. The exception are the legacy PIC interrupts. In general | |
762 | * they are only targeted to CPU0, but depending on the platform | |
763 | * they can be distributed to any online CPU in hardware. The | |
764 | * kernel has no influence on that. So all active legacy vectors | |
765 | * must be installed on all CPUs. All non legacy interrupts can be | |
766 | * cleared. | |
74afab7a | 767 | */ |
f0cc6cca TG |
768 | for (vector = 0; vector < NR_VECTORS; vector++) |
769 | this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); | |
74afab7a JL |
770 | } |
771 | ||
0fa115da TG |
772 | void lapic_offline(void) |
773 | { | |
774 | lock_vector_lock(); | |
775 | irq_matrix_offline(vector_matrix); | |
776 | unlock_vector_lock(); | |
777 | } | |
778 | ||
ba801640 TG |
779 | static int apic_set_affinity(struct irq_data *irqd, |
780 | const struct cpumask *dest, bool force) | |
781 | { | |
02edee15 | 782 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
ba801640 TG |
783 | int err; |
784 | ||
02edee15 TG |
785 | /* |
786 | * Core code can call here for inactive interrupts. For inactive | |
787 | * interrupts which use managed or reservation mode there is no | |
788 | * point in going through the vector assignment right now as the | |
789 | * activation will assign a vector which fits the destination | |
790 | * cpumask. Let the core code store the destination mask and be | |
791 | * done with it. | |
792 | */ | |
793 | if (!irqd_is_activated(irqd) && | |
794 | (apicd->is_managed || apicd->can_reserve)) | |
795 | return IRQ_SET_MASK_OK; | |
796 | ||
2db1f959 TG |
797 | raw_spin_lock(&vector_lock); |
798 | cpumask_and(vector_searchmask, dest, cpu_online_mask); | |
799 | if (irqd_affinity_is_managed(irqd)) | |
800 | err = assign_managed_vector(irqd, vector_searchmask); | |
801 | else | |
802 | err = assign_vector_locked(irqd, vector_searchmask); | |
803 | raw_spin_unlock(&vector_lock); | |
ba801640 TG |
804 | return err ? err : IRQ_SET_MASK_OK; |
805 | } | |
806 | ||
807 | #else | |
808 | # define apic_set_affinity NULL | |
809 | #endif | |
810 | ||
86ba6551 | 811 | static int apic_retrigger_irq(struct irq_data *irqd) |
74afab7a | 812 | { |
86ba6551 | 813 | struct apic_chip_data *apicd = apic_chip_data(irqd); |
74afab7a | 814 | unsigned long flags; |
74afab7a JL |
815 | |
816 | raw_spin_lock_irqsave(&vector_lock, flags); | |
ba224fea | 817 | apic->send_IPI(apicd->cpu, apicd->vector); |
74afab7a JL |
818 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
819 | ||
820 | return 1; | |
821 | } | |
822 | ||
99014a2c | 823 | void apic_ack_irq(struct irq_data *irqd) |
74afab7a | 824 | { |
86ba6551 | 825 | irq_move_irq(irqd); |
74afab7a | 826 | ack_APIC_irq(); |
99014a2c TG |
827 | } |
828 | ||
829 | void apic_ack_edge(struct irq_data *irqd) | |
830 | { | |
831 | irq_complete_move(irqd_cfg(irqd)); | |
832 | apic_ack_irq(irqd); | |
74afab7a JL |
833 | } |
834 | ||
b5dc8e6c | 835 | static struct irq_chip lapic_controller = { |
8947dfb2 | 836 | .name = "APIC", |
b5dc8e6c | 837 | .irq_ack = apic_ack_edge, |
68f9f440 | 838 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
839 | .irq_retrigger = apic_retrigger_irq, |
840 | }; | |
841 | ||
74afab7a | 842 | #ifdef CONFIG_SMP |
c6c2002b | 843 | |
69cde000 TG |
844 | static void free_moved_vector(struct apic_chip_data *apicd) |
845 | { | |
ba224fea | 846 | unsigned int vector = apicd->prev_vector; |
69cde000 | 847 | unsigned int cpu = apicd->prev_cpu; |
2db1f959 TG |
848 | bool managed = apicd->is_managed; |
849 | ||
850 | /* | |
851 | * This should never happen. Managed interrupts are not | |
852 | * migrated except on CPU down, which does not involve the | |
853 | * cleanup vector. But try to keep the accounting correct | |
854 | * nevertheless. | |
855 | */ | |
856 | WARN_ON_ONCE(managed); | |
69cde000 | 857 | |
0696d059 | 858 | trace_vector_free_moved(apicd->irq, cpu, vector, managed); |
2db1f959 | 859 | irq_matrix_free(vector_matrix, cpu, vector, managed); |
0696d059 | 860 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
69cde000 | 861 | hlist_del_init(&apicd->clist); |
ba224fea | 862 | apicd->prev_vector = 0; |
69cde000 TG |
863 | apicd->move_in_progress = 0; |
864 | } | |
865 | ||
c4158ff5 | 866 | asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void) |
74afab7a | 867 | { |
dccfe314 TG |
868 | struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); |
869 | struct apic_chip_data *apicd; | |
870 | struct hlist_node *tmp; | |
74afab7a | 871 | |
6af7faf6 | 872 | entering_ack_irq(); |
df54c493 TG |
873 | /* Prevent vectors vanishing under us */ |
874 | raw_spin_lock(&vector_lock); | |
875 | ||
dccfe314 | 876 | hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { |
ba224fea | 877 | unsigned int irr, vector = apicd->prev_vector; |
74afab7a | 878 | |
74afab7a | 879 | /* |
dccfe314 TG |
880 | * Paranoia: Check if the vector that needs to be cleaned |
881 | * up is registered at the APICs IRR. If so, then this is | |
882 | * not the best time to clean it up. Clean it up in the | |
74afab7a | 883 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
dccfe314 TG |
884 | * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest |
885 | * priority external vector, so on return from this | |
886 | * interrupt the device interrupt will happen first. | |
74afab7a | 887 | */ |
dccfe314 TG |
888 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
889 | if (irr & (1U << (vector % 32))) { | |
74afab7a | 890 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
dccfe314 | 891 | continue; |
74afab7a | 892 | } |
69cde000 | 893 | free_moved_vector(apicd); |
74afab7a JL |
894 | } |
895 | ||
df54c493 | 896 | raw_spin_unlock(&vector_lock); |
6af7faf6 | 897 | exiting_irq(); |
74afab7a JL |
898 | } |
899 | ||
dccfe314 TG |
900 | static void __send_cleanup_vector(struct apic_chip_data *apicd) |
901 | { | |
902 | unsigned int cpu; | |
903 | ||
904 | raw_spin_lock(&vector_lock); | |
905 | apicd->move_in_progress = 0; | |
906 | cpu = apicd->prev_cpu; | |
907 | if (cpu_online(cpu)) { | |
908 | hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); | |
909 | apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); | |
910 | } else { | |
ba224fea | 911 | apicd->prev_vector = 0; |
dccfe314 TG |
912 | } |
913 | raw_spin_unlock(&vector_lock); | |
914 | } | |
915 | ||
916 | void send_cleanup_vector(struct irq_cfg *cfg) | |
917 | { | |
918 | struct apic_chip_data *apicd; | |
919 | ||
ba224fea | 920 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
dccfe314 TG |
921 | if (apicd->move_in_progress) |
922 | __send_cleanup_vector(apicd); | |
923 | } | |
924 | ||
74afab7a JL |
925 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
926 | { | |
86ba6551 | 927 | struct apic_chip_data *apicd; |
74afab7a | 928 | |
ba224fea | 929 | apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); |
86ba6551 | 930 | if (likely(!apicd->move_in_progress)) |
74afab7a JL |
931 | return; |
932 | ||
ba224fea | 933 | if (vector == apicd->vector && apicd->cpu == smp_processor_id()) |
86ba6551 | 934 | __send_cleanup_vector(apicd); |
74afab7a JL |
935 | } |
936 | ||
937 | void irq_complete_move(struct irq_cfg *cfg) | |
938 | { | |
939 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
940 | } | |
941 | ||
90a2282e | 942 | /* |
551adc60 | 943 | * Called from fixup_irqs() with @desc->lock held and interrupts disabled. |
90a2282e TG |
944 | */ |
945 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 946 | { |
86ba6551 | 947 | struct apic_chip_data *apicd; |
dccfe314 TG |
948 | struct irq_data *irqd; |
949 | unsigned int vector; | |
56d7d2f4 | 950 | |
db91aa79 MW |
951 | /* |
952 | * The function is called for all descriptors regardless of which | |
953 | * irqdomain they belong to. For example if an IRQ is provided by | |
954 | * an irq_chip as part of a GPIO driver, the chip data for that | |
955 | * descriptor is specific to the irq_chip in question. | |
956 | * | |
957 | * Check first that the chip_data is what we expect | |
958 | * (apic_chip_data) before touching it any further. | |
959 | */ | |
86ba6551 | 960 | irqd = irq_domain_get_irq_data(x86_vector_domain, |
dccfe314 | 961 | irq_desc_get_irq(desc)); |
86ba6551 | 962 | if (!irqd) |
db91aa79 MW |
963 | return; |
964 | ||
dccfe314 | 965 | raw_spin_lock(&vector_lock); |
86ba6551 | 966 | apicd = apic_chip_data(irqd); |
dccfe314 TG |
967 | if (!apicd) |
968 | goto unlock; | |
db91aa79 | 969 | |
dccfe314 | 970 | /* |
ba224fea | 971 | * If prev_vector is empty, no action required. |
dccfe314 | 972 | */ |
ba224fea | 973 | vector = apicd->prev_vector; |
dccfe314 TG |
974 | if (!vector) |
975 | goto unlock; | |
74afab7a | 976 | |
56d7d2f4 | 977 | /* |
dccfe314 | 978 | * This is tricky. If the cleanup of the old vector has not been |
98229aa3 TG |
979 | * done yet, then the following setaffinity call will fail with |
980 | * -EBUSY. This can leave the interrupt in a stale state. | |
981 | * | |
551adc60 TG |
982 | * All CPUs are stuck in stop machine with interrupts disabled so |
983 | * calling __irq_complete_move() would be completely pointless. | |
dccfe314 | 984 | * |
551adc60 TG |
985 | * 1) The interrupt is in move_in_progress state. That means that we |
986 | * have not seen an interrupt since the io_apic was reprogrammed to | |
987 | * the new vector. | |
988 | * | |
989 | * 2) The interrupt has fired on the new vector, but the cleanup IPIs | |
990 | * have not been processed yet. | |
991 | */ | |
86ba6551 | 992 | if (apicd->move_in_progress) { |
98229aa3 | 993 | /* |
551adc60 TG |
994 | * In theory there is a race: |
995 | * | |
996 | * set_ioapic(new_vector) <-- Interrupt is raised before update | |
997 | * is effective, i.e. it's raised on | |
998 | * the old vector. | |
999 | * | |
1000 | * So if the target cpu cannot handle that interrupt before | |
1001 | * the old vector is cleaned up, we get a spurious interrupt | |
1002 | * and in the worst case the ioapic irq line becomes stale. | |
1003 | * | |
1004 | * But in case of cpu hotplug this should be a non issue | |
1005 | * because if the affinity update happens right before all | |
1006 | * cpus rendevouz in stop machine, there is no way that the | |
1007 | * interrupt can be blocked on the target cpu because all cpus | |
1008 | * loops first with interrupts enabled in stop machine, so the | |
1009 | * old vector is not yet cleaned up when the interrupt fires. | |
1010 | * | |
1011 | * So the only way to run into this issue is if the delivery | |
1012 | * of the interrupt on the apic/system bus would be delayed | |
1013 | * beyond the point where the target cpu disables interrupts | |
1014 | * in stop machine. I doubt that it can happen, but at least | |
1015 | * there is a theroretical chance. Virtualization might be | |
1016 | * able to expose this, but AFAICT the IOAPIC emulation is not | |
1017 | * as stupid as the real hardware. | |
1018 | * | |
1019 | * Anyway, there is nothing we can do about that at this point | |
1020 | * w/o refactoring the whole fixup_irq() business completely. | |
1021 | * We print at least the irq number and the old vector number, | |
1022 | * so we have the necessary information when a problem in that | |
1023 | * area arises. | |
98229aa3 | 1024 | */ |
551adc60 | 1025 | pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", |
dccfe314 | 1026 | irqd->irq, vector); |
98229aa3 | 1027 | } |
69cde000 | 1028 | free_moved_vector(apicd); |
dccfe314 | 1029 | unlock: |
56d7d2f4 | 1030 | raw_spin_unlock(&vector_lock); |
74afab7a | 1031 | } |
2cffad7b TG |
1032 | |
1033 | #ifdef CONFIG_HOTPLUG_CPU | |
1034 | /* | |
1035 | * Note, this is not accurate accounting, but at least good enough to | |
1036 | * prevent that the actual interrupt move will run out of vectors. | |
1037 | */ | |
1038 | int lapic_can_unplug_cpu(void) | |
1039 | { | |
1040 | unsigned int rsvd, avl, tomove, cpu = smp_processor_id(); | |
1041 | int ret = 0; | |
1042 | ||
1043 | raw_spin_lock(&vector_lock); | |
1044 | tomove = irq_matrix_allocated(vector_matrix); | |
1045 | avl = irq_matrix_available(vector_matrix, true); | |
1046 | if (avl < tomove) { | |
1047 | pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n", | |
1048 | cpu, tomove, avl); | |
1049 | ret = -ENOSPC; | |
1050 | goto out; | |
1051 | } | |
1052 | rsvd = irq_matrix_reserved(vector_matrix); | |
1053 | if (avl < rsvd) { | |
1054 | pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n", | |
1055 | rsvd, avl); | |
1056 | } | |
1057 | out: | |
1058 | raw_spin_unlock(&vector_lock); | |
1059 | return ret; | |
1060 | } | |
1061 | #endif /* HOTPLUG_CPU */ | |
1062 | #endif /* SMP */ | |
74afab7a | 1063 | |
74afab7a JL |
1064 | static void __init print_APIC_field(int base) |
1065 | { | |
1066 | int i; | |
1067 | ||
1068 | printk(KERN_DEBUG); | |
1069 | ||
1070 | for (i = 0; i < 8; i++) | |
1071 | pr_cont("%08x", apic_read(base + i*0x10)); | |
1072 | ||
1073 | pr_cont("\n"); | |
1074 | } | |
1075 | ||
1076 | static void __init print_local_APIC(void *dummy) | |
1077 | { | |
1078 | unsigned int i, v, ver, maxlvt; | |
1079 | u64 icr; | |
1080 | ||
849d3569 JL |
1081 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
1082 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 1083 | v = apic_read(APIC_ID); |
849d3569 | 1084 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 1085 | v = apic_read(APIC_LVR); |
849d3569 | 1086 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
1087 | ver = GET_APIC_VERSION(v); |
1088 | maxlvt = lapic_get_maxlvt(); | |
1089 | ||
1090 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 1091 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
1092 | |
1093 | /* !82489DX */ | |
1094 | if (APIC_INTEGRATED(ver)) { | |
1095 | if (!APIC_XAPIC(ver)) { | |
1096 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
1097 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
1098 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
1099 | } |
1100 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 1101 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
1102 | } |
1103 | ||
1104 | /* | |
1105 | * Remote read supported only in the 82489DX and local APIC for | |
1106 | * Pentium processors. | |
1107 | */ | |
1108 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1109 | v = apic_read(APIC_RRR); | |
849d3569 | 1110 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
1111 | } |
1112 | ||
1113 | v = apic_read(APIC_LDR); | |
849d3569 | 1114 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
1115 | if (!x2apic_enabled()) { |
1116 | v = apic_read(APIC_DFR); | |
849d3569 | 1117 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
1118 | } |
1119 | v = apic_read(APIC_SPIV); | |
849d3569 | 1120 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 1121 | |
849d3569 | 1122 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 1123 | print_APIC_field(APIC_ISR); |
849d3569 | 1124 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 1125 | print_APIC_field(APIC_TMR); |
849d3569 | 1126 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
1127 | print_APIC_field(APIC_IRR); |
1128 | ||
1129 | /* !82489DX */ | |
1130 | if (APIC_INTEGRATED(ver)) { | |
1131 | /* Due to the Pentium erratum 3AP. */ | |
1132 | if (maxlvt > 3) | |
1133 | apic_write(APIC_ESR, 0); | |
1134 | ||
1135 | v = apic_read(APIC_ESR); | |
849d3569 | 1136 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
1137 | } |
1138 | ||
1139 | icr = apic_icr_read(); | |
849d3569 JL |
1140 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
1141 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
1142 | |
1143 | v = apic_read(APIC_LVTT); | |
849d3569 | 1144 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
1145 | |
1146 | if (maxlvt > 3) { | |
1147 | /* PC is LVT#4. */ | |
1148 | v = apic_read(APIC_LVTPC); | |
849d3569 | 1149 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
1150 | } |
1151 | v = apic_read(APIC_LVT0); | |
849d3569 | 1152 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 1153 | v = apic_read(APIC_LVT1); |
849d3569 | 1154 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
1155 | |
1156 | if (maxlvt > 2) { | |
1157 | /* ERR is LVT#3. */ | |
1158 | v = apic_read(APIC_LVTERR); | |
849d3569 | 1159 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
1160 | } |
1161 | ||
1162 | v = apic_read(APIC_TMICT); | |
849d3569 | 1163 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 1164 | v = apic_read(APIC_TMCCT); |
849d3569 | 1165 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 1166 | v = apic_read(APIC_TDCR); |
849d3569 | 1167 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
1168 | |
1169 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1170 | v = apic_read(APIC_EFEAT); | |
1171 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 1172 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 1173 | v = apic_read(APIC_ECTRL); |
849d3569 | 1174 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
1175 | for (i = 0; i < maxlvt; i++) { |
1176 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 1177 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
1178 | } |
1179 | } | |
1180 | pr_cont("\n"); | |
1181 | } | |
1182 | ||
1183 | static void __init print_local_APICs(int maxcpu) | |
1184 | { | |
1185 | int cpu; | |
1186 | ||
1187 | if (!maxcpu) | |
1188 | return; | |
1189 | ||
1190 | preempt_disable(); | |
1191 | for_each_online_cpu(cpu) { | |
1192 | if (cpu >= maxcpu) | |
1193 | break; | |
1194 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1195 | } | |
1196 | preempt_enable(); | |
1197 | } | |
1198 | ||
1199 | static void __init print_PIC(void) | |
1200 | { | |
1201 | unsigned int v; | |
1202 | unsigned long flags; | |
1203 | ||
1204 | if (!nr_legacy_irqs()) | |
1205 | return; | |
1206 | ||
849d3569 | 1207 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
1208 | |
1209 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
1210 | ||
1211 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 1212 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
1213 | |
1214 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 1215 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
1216 | |
1217 | outb(0x0b, 0xa0); | |
1218 | outb(0x0b, 0x20); | |
1219 | v = inb(0xa0) << 8 | inb(0x20); | |
1220 | outb(0x0a, 0xa0); | |
1221 | outb(0x0a, 0x20); | |
1222 | ||
1223 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
1224 | ||
849d3569 | 1225 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
1226 | |
1227 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 1228 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
1229 | } |
1230 | ||
1231 | static int show_lapic __initdata = 1; | |
1232 | static __init int setup_show_lapic(char *arg) | |
1233 | { | |
1234 | int num = -1; | |
1235 | ||
1236 | if (strcmp(arg, "all") == 0) { | |
1237 | show_lapic = CONFIG_NR_CPUS; | |
1238 | } else { | |
1239 | get_option(&arg, &num); | |
1240 | if (num >= 0) | |
1241 | show_lapic = num; | |
1242 | } | |
1243 | ||
1244 | return 1; | |
1245 | } | |
1246 | __setup("show_lapic=", setup_show_lapic); | |
1247 | ||
1248 | static int __init print_ICs(void) | |
1249 | { | |
1250 | if (apic_verbosity == APIC_QUIET) | |
1251 | return 0; | |
1252 | ||
1253 | print_PIC(); | |
1254 | ||
1255 | /* don't print out if apic is not there */ | |
93984fbd | 1256 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
74afab7a JL |
1257 | return 0; |
1258 | ||
1259 | print_local_APICs(show_lapic); | |
1260 | print_IO_APICs(); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | late_initcall(print_ICs); |