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Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
9f5314fb | 8 | * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
0b1da1c8 IM |
20 | #include <linux/cpu.h> |
21 | #include <linux/init.h> | |
27229ca6 | 22 | #include <linux/io.h> |
0b1da1c8 | 23 | |
ac23d4ee JS |
24 | #include <asm/uv/uv_mmrs.h> |
25 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
26 | #include <asm/current.h> |
27 | #include <asm/pgtable.h> | |
7019cc2d | 28 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
29 | #include <asm/uv/uv.h> |
30 | #include <asm/apic.h> | |
31 | #include <asm/ipi.h> | |
32 | #include <asm/smp.h> | |
ac23d4ee | 33 | |
510b3725 YL |
34 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
35 | ||
1b9b89e7 YL |
36 | static enum uv_system_type uv_system_type; |
37 | ||
27229ca6 JS |
38 | static int early_get_nodeid(void) |
39 | { | |
40 | union uvh_node_id_u node_id; | |
41 | unsigned long *mmr; | |
42 | ||
43 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr)); | |
44 | node_id.v = *mmr; | |
45 | early_iounmap(mmr, sizeof(*mmr)); | |
46 | return node_id.s.node_id; | |
47 | } | |
48 | ||
f8827c01 | 49 | static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 YL |
50 | { |
51 | if (!strcmp(oem_id, "SGI")) { | |
52 | if (!strcmp(oem_table_id, "UVL")) | |
53 | uv_system_type = UV_LEGACY_APIC; | |
54 | else if (!strcmp(oem_table_id, "UVX")) | |
55 | uv_system_type = UV_X2APIC; | |
56 | else if (!strcmp(oem_table_id, "UVH")) { | |
27229ca6 JS |
57 | __get_cpu_var(x2apic_extra_bits) = |
58 | early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1); | |
1b9b89e7 YL |
59 | uv_system_type = UV_NON_UNIQUE_APIC; |
60 | return 1; | |
61 | } | |
62 | } | |
63 | return 0; | |
64 | } | |
65 | ||
66 | enum uv_system_type get_uv_system_type(void) | |
67 | { | |
68 | return uv_system_type; | |
69 | } | |
70 | ||
71 | int is_uv_system(void) | |
72 | { | |
73 | return uv_system_type != UV_NONE; | |
74 | } | |
8067794b | 75 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 76 | |
ac23d4ee JS |
77 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
78 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
79 | ||
80 | struct uv_blade_info *uv_blade_info; | |
81 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
82 | ||
83 | short *uv_node_to_blade; | |
84 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
85 | ||
86 | short *uv_cpu_to_blade; | |
87 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
88 | ||
89 | short uv_possible_blades; | |
90 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
91 | ||
7019cc2d RA |
92 | unsigned long sn_rtc_cycles_per_second; |
93 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
94 | ||
ac23d4ee JS |
95 | /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ |
96 | ||
bcda016e | 97 | static const struct cpumask *uv_target_cpus(void) |
ac23d4ee | 98 | { |
bcda016e | 99 | return cpumask_of(0); |
ac23d4ee JS |
100 | } |
101 | ||
bcda016e | 102 | static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) |
ac23d4ee | 103 | { |
bcda016e MT |
104 | cpumask_clear(retmask); |
105 | cpumask_set_cpu(cpu, retmask); | |
ac23d4ee JS |
106 | } |
107 | ||
667c5296 | 108 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee | 109 | { |
0b1da1c8 | 110 | #ifdef CONFIG_SMP |
ac23d4ee | 111 | unsigned long val; |
9f5314fb | 112 | int pnode; |
ac23d4ee | 113 | |
9f5314fb | 114 | pnode = uv_apicid_to_pnode(phys_apicid); |
ac23d4ee JS |
115 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
116 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 117 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 118 | APIC_DM_INIT; |
9f5314fb | 119 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
120 | mdelay(10); |
121 | ||
122 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
123 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 124 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 125 | APIC_DM_STARTUP; |
9f5314fb | 126 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf YL |
127 | |
128 | atomic_set(&init_deasserted, 1); | |
0b1da1c8 | 129 | #endif |
ac23d4ee JS |
130 | return 0; |
131 | } | |
132 | ||
133 | static void uv_send_IPI_one(int cpu, int vector) | |
134 | { | |
66666e50 | 135 | unsigned long apicid; |
9f5314fb | 136 | int pnode; |
ac23d4ee | 137 | |
1e0b5d00 | 138 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 139 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 140 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
141 | } |
142 | ||
bcda016e | 143 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
144 | { |
145 | unsigned int cpu; | |
146 | ||
bcda016e | 147 | for_each_cpu(cpu, mask) |
e7986739 MT |
148 | uv_send_IPI_one(cpu, vector); |
149 | } | |
150 | ||
bcda016e | 151 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 152 | { |
e7986739 | 153 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 154 | unsigned int cpu; |
e7986739 | 155 | |
dac5f412 | 156 | for_each_cpu(cpu, mask) { |
e7986739 | 157 | if (cpu != this_cpu) |
ac23d4ee | 158 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 159 | } |
ac23d4ee JS |
160 | } |
161 | ||
162 | static void uv_send_IPI_allbutself(int vector) | |
163 | { | |
e7986739 | 164 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 165 | unsigned int cpu; |
ac23d4ee | 166 | |
dac5f412 | 167 | for_each_online_cpu(cpu) { |
e7986739 MT |
168 | if (cpu != this_cpu) |
169 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 170 | } |
ac23d4ee JS |
171 | } |
172 | ||
173 | static void uv_send_IPI_all(int vector) | |
174 | { | |
bcda016e | 175 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
176 | } |
177 | ||
178 | static int uv_apic_id_registered(void) | |
179 | { | |
180 | return 1; | |
181 | } | |
182 | ||
277d1f58 | 183 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
184 | { |
185 | } | |
186 | ||
bcda016e | 187 | static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) |
ac23d4ee | 188 | { |
ac23d4ee JS |
189 | /* |
190 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
191 | * May as well be the first. | |
192 | */ | |
debccb3e IM |
193 | int cpu = cpumask_first(cpumask); |
194 | ||
247bc6ca | 195 | if ((unsigned)cpu < nr_cpu_ids) |
ac23d4ee JS |
196 | return per_cpu(x86_cpu_to_apicid, cpu); |
197 | else | |
198 | return BAD_APICID; | |
199 | } | |
200 | ||
debccb3e IM |
201 | static unsigned int |
202 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
203 | const struct cpumask *andmask) | |
95d313cf MT |
204 | { |
205 | int cpu; | |
206 | ||
207 | /* | |
208 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
209 | * May as well be the first. | |
210 | */ | |
debccb3e | 211 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
212 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
213 | break; | |
debccb3e | 214 | } |
6eeb7c5a MT |
215 | if (cpu < nr_cpu_ids) |
216 | return per_cpu(x86_cpu_to_apicid, cpu); | |
debccb3e | 217 | |
95d313cf MT |
218 | return BAD_APICID; |
219 | } | |
220 | ||
ca6c8ed4 | 221 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
222 | { |
223 | unsigned int id; | |
224 | ||
225 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
f910a9dc | 226 | id = x | __get_cpu_var(x2apic_extra_bits); |
0c81c746 SS |
227 | |
228 | return id; | |
229 | } | |
230 | ||
1b9b89e7 | 231 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
232 | { |
233 | unsigned long x; | |
234 | ||
235 | /* maskout x2apic_extra_bits ? */ | |
236 | x = id; | |
237 | return x; | |
238 | } | |
239 | ||
240 | static unsigned int uv_read_apic_id(void) | |
241 | { | |
242 | ||
ca6c8ed4 | 243 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
244 | } |
245 | ||
d4c9a9f3 | 246 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 247 | { |
0c81c746 | 248 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
249 | } |
250 | ||
ac23d4ee JS |
251 | static void uv_send_IPI_self(int vector) |
252 | { | |
253 | apic_write(APIC_SELF_IPI, vector); | |
254 | } | |
ac23d4ee | 255 | |
be163a15 | 256 | struct apic apic_x2apic_uv_x = { |
c7967329 IM |
257 | |
258 | .name = "UV large system", | |
259 | .probe = NULL, | |
260 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, | |
261 | .apic_id_registered = uv_apic_id_registered, | |
262 | ||
f8987a10 | 263 | .irq_delivery_mode = dest_Fixed, |
0b06e734 | 264 | .irq_dest_mode = 1, /* logical */ |
c7967329 IM |
265 | |
266 | .target_cpus = uv_target_cpus, | |
08125d3e | 267 | .disable_esr = 0, |
bdb1a9b6 | 268 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
269 | .check_apicid_used = NULL, |
270 | .check_apicid_present = NULL, | |
271 | ||
c7967329 IM |
272 | .vector_allocation_domain = uv_vector_allocation_domain, |
273 | .init_apic_ldr = uv_init_apic_ldr, | |
274 | ||
275 | .ioapic_phys_id_map = NULL, | |
276 | .setup_apic_routing = NULL, | |
277 | .multi_timer_check = NULL, | |
278 | .apicid_to_node = NULL, | |
279 | .cpu_to_logical_apicid = NULL, | |
a21769a4 | 280 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
281 | .apicid_to_cpu_present = NULL, |
282 | .setup_portio_remap = NULL, | |
a27a6210 | 283 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 284 | .enable_apic_mode = NULL, |
d4c9a9f3 | 285 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
286 | .mps_oem_check = NULL, |
287 | ||
ca6c8ed4 | 288 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
289 | .set_apic_id = set_apic_id, |
290 | .apic_id_mask = 0xFFFFFFFFu, | |
291 | ||
292 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | |
293 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, | |
294 | ||
295 | .send_IPI_mask = uv_send_IPI_mask, | |
296 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
297 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
298 | .send_IPI_all = uv_send_IPI_all, | |
299 | .send_IPI_self = uv_send_IPI_self, | |
300 | ||
1f5bcabf | 301 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
abfa584c IM |
302 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
303 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
c7967329 IM |
304 | .wait_for_init_deassert = NULL, |
305 | .smp_callin_clear_local_apic = NULL, | |
c7967329 | 306 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
307 | |
308 | .read = native_apic_msr_read, | |
309 | .write = native_apic_msr_write, | |
310 | .icr_read = native_x2apic_icr_read, | |
311 | .icr_write = native_x2apic_icr_write, | |
312 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
313 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
314 | }; |
315 | ||
9f5314fb | 316 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 317 | { |
9f5314fb | 318 | __get_cpu_var(x2apic_extra_bits) = (pnode << 6); |
ac23d4ee JS |
319 | } |
320 | ||
321 | /* | |
322 | * Called on boot cpu. | |
323 | */ | |
9f5314fb JS |
324 | static __init int boot_pnode_to_blade(int pnode) |
325 | { | |
326 | int blade; | |
327 | ||
328 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
329 | if (pnode == uv_blade_info[blade].pnode) | |
330 | return blade; | |
331 | BUG(); | |
332 | } | |
333 | ||
334 | struct redir_addr { | |
335 | unsigned long redirect; | |
336 | unsigned long alias; | |
337 | }; | |
338 | ||
339 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
340 | ||
341 | static __initdata struct redir_addr redir_addrs[] = { | |
342 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG}, | |
343 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG}, | |
344 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG}, | |
345 | }; | |
346 | ||
347 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
348 | { | |
349 | union uvh_si_alias0_overlay_config_u alias; | |
350 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; | |
351 | int i; | |
352 | ||
353 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
354 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
355 | if (alias.s.base == 0) { | |
356 | *size = (1UL << alias.s.m_alias); | |
357 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
358 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
359 | return; | |
360 | } | |
361 | } | |
362 | BUG(); | |
363 | } | |
364 | ||
83f5d894 JS |
365 | static __init void map_low_mmrs(void) |
366 | { | |
367 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
368 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
369 | } | |
370 | ||
371 | enum map_type {map_wb, map_uc}; | |
372 | ||
d2f904bb JS |
373 | static __init void map_high(char *id, unsigned long base, int shift, |
374 | int max_pnode, enum map_type map_type) | |
83f5d894 JS |
375 | { |
376 | unsigned long bytes, paddr; | |
377 | ||
378 | paddr = base << shift; | |
d2f904bb | 379 | bytes = (1UL << shift) * (max_pnode + 1); |
83f5d894 | 380 | printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, |
0b1da1c8 | 381 | paddr + bytes); |
83f5d894 JS |
382 | if (map_type == map_uc) |
383 | init_extra_mapping_uc(paddr, bytes); | |
384 | else | |
385 | init_extra_mapping_wb(paddr, bytes); | |
386 | ||
387 | } | |
388 | static __init void map_gru_high(int max_pnode) | |
389 | { | |
390 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
391 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
392 | ||
393 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
394 | if (gru.s.enable) | |
d2f904bb | 395 | map_high("GRU", gru.s.base, shift, max_pnode, map_wb); |
83f5d894 JS |
396 | } |
397 | ||
398 | static __init void map_config_high(int max_pnode) | |
399 | { | |
400 | union uvh_rh_gam_cfg_overlay_config_mmr_u cfg; | |
401 | int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
402 | ||
403 | cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR); | |
404 | if (cfg.s.enable) | |
d2f904bb | 405 | map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc); |
83f5d894 JS |
406 | } |
407 | ||
408 | static __init void map_mmr_high(int max_pnode) | |
409 | { | |
410 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
411 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
412 | ||
413 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
414 | if (mmr.s.enable) | |
d2f904bb | 415 | map_high("MMR", mmr.s.base, shift, max_pnode, map_uc); |
83f5d894 JS |
416 | } |
417 | ||
418 | static __init void map_mmioh_high(int max_pnode) | |
419 | { | |
420 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
421 | int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
422 | ||
423 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); | |
424 | if (mmioh.s.enable) | |
d2f904bb | 425 | map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc); |
83f5d894 JS |
426 | } |
427 | ||
7019cc2d RA |
428 | static __init void uv_rtc_init(void) |
429 | { | |
922402f1 RA |
430 | long status; |
431 | u64 ticks_per_sec; | |
7019cc2d | 432 | |
922402f1 RA |
433 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
434 | &ticks_per_sec); | |
435 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
436 | printk(KERN_WARNING |
437 | "unable to determine platform RTC clock frequency, " | |
438 | "guessing.\n"); | |
439 | /* BIOS gives wrong value for clock freq. so guess */ | |
440 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
441 | } else | |
442 | sn_rtc_cycles_per_second = ticks_per_sec; | |
443 | } | |
444 | ||
7f1baa06 MT |
445 | /* |
446 | * percpu heartbeat timer | |
447 | */ | |
448 | static void uv_heartbeat(unsigned long ignored) | |
449 | { | |
450 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
451 | unsigned char bits = uv_hub_info->scir.state; | |
452 | ||
453 | /* flip heartbeat bit */ | |
454 | bits ^= SCIR_CPU_HEARTBEAT; | |
455 | ||
69a72a0e MT |
456 | /* is this cpu idle? */ |
457 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
458 | bits &= ~SCIR_CPU_ACTIVITY; |
459 | else | |
460 | bits |= SCIR_CPU_ACTIVITY; | |
461 | ||
462 | /* update system controller interface reg */ | |
463 | uv_set_scir_bits(bits); | |
464 | ||
465 | /* enable next timer period */ | |
5c333864 | 466 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
467 | } |
468 | ||
469 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
470 | { | |
471 | if (!uv_cpu_hub_info(cpu)->scir.enabled) { | |
472 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; | |
473 | ||
474 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
475 | setup_timer(timer, uv_heartbeat, cpu); | |
476 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
477 | add_timer_on(timer, cpu); | |
478 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
479 | } | |
480 | ||
481 | /* check boot cpu */ | |
482 | if (!uv_cpu_hub_info(0)->scir.enabled) | |
483 | uv_heartbeat_enable(0); | |
484 | } | |
485 | ||
77be80e4 | 486 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
487 | static void __cpuinit uv_heartbeat_disable(int cpu) |
488 | { | |
489 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
490 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
491 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
492 | } | |
493 | uv_set_cpu_scir_bits(cpu, 0xff); | |
494 | } | |
495 | ||
7f1baa06 MT |
496 | /* |
497 | * cpu hotplug notifier | |
498 | */ | |
499 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
500 | unsigned long action, void *hcpu) | |
501 | { | |
502 | long cpu = (long)hcpu; | |
503 | ||
504 | switch (action) { | |
505 | case CPU_ONLINE: | |
506 | uv_heartbeat_enable(cpu); | |
507 | break; | |
508 | case CPU_DOWN_PREPARE: | |
509 | uv_heartbeat_disable(cpu); | |
510 | break; | |
511 | default: | |
512 | break; | |
513 | } | |
514 | return NOTIFY_OK; | |
515 | } | |
516 | ||
517 | static __init void uv_scir_register_cpu_notifier(void) | |
518 | { | |
519 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
520 | } | |
521 | ||
522 | #else /* !CONFIG_HOTPLUG_CPU */ | |
523 | ||
524 | static __init void uv_scir_register_cpu_notifier(void) | |
525 | { | |
526 | } | |
527 | ||
528 | static __init int uv_init_heartbeat(void) | |
529 | { | |
530 | int cpu; | |
531 | ||
532 | if (is_uv_system()) | |
533 | for_each_online_cpu(cpu) | |
534 | uv_heartbeat_enable(cpu); | |
535 | return 0; | |
536 | } | |
537 | ||
538 | late_initcall(uv_init_heartbeat); | |
539 | ||
540 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
541 | ||
8da077d6 JS |
542 | /* |
543 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 544 | * FIXME: hotplug not supported yet |
8da077d6 JS |
545 | */ |
546 | void __cpuinit uv_cpu_init(void) | |
547 | { | |
548 | /* CPU 0 initilization will be done via uv_system_init. */ | |
549 | if (!uv_blade_info) | |
550 | return; | |
551 | ||
552 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
553 | ||
554 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
555 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
556 | } | |
557 | ||
c4bd1fda MS |
558 | |
559 | void __init uv_system_init(void) | |
ac23d4ee JS |
560 | { |
561 | union uvh_si_addr_map_config_u m_n_config; | |
9f5314fb JS |
562 | union uvh_node_id_u node_id; |
563 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
564 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; | |
c4ed3f04 | 565 | int gnode_extra, max_pnode = 0; |
6a891a24 JS |
566 | unsigned long mmr_base, present, paddr; |
567 | unsigned short pnode_mask; | |
ac23d4ee | 568 | |
83f5d894 JS |
569 | map_low_mmrs(); |
570 | ||
ac23d4ee | 571 | m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG); |
9f5314fb JS |
572 | m_val = m_n_config.s.m_skt; |
573 | n_val = m_n_config.s.n_skt; | |
ac23d4ee JS |
574 | mmr_base = |
575 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
576 | ~UV_MMR_ENABLE; | |
c4ed3f04 JS |
577 | pnode_mask = (1 << n_val) - 1; |
578 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); | |
579 | gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; | |
580 | gnode_upper = ((unsigned long)gnode_extra << m_val); | |
581 | printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n", | |
582 | n_val, m_val, gnode_upper, gnode_extra); | |
583 | ||
ac23d4ee JS |
584 | printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); |
585 | ||
9f5314fb JS |
586 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
587 | uv_possible_blades += | |
588 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
ac23d4ee JS |
589 | printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); |
590 | ||
591 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
ef020ab0 | 592 | uv_blade_info = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 593 | BUG_ON(!uv_blade_info); |
6c7184b7 JS |
594 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
595 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 596 | |
9f5314fb JS |
597 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
598 | ||
ac23d4ee | 599 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 600 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 601 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
602 | memset(uv_node_to_blade, 255, bytes); |
603 | ||
604 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 605 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 606 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
607 | memset(uv_cpu_to_blade, 255, bytes); |
608 | ||
9f5314fb JS |
609 | blade = 0; |
610 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
611 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
612 | for (j = 0; j < 64; j++) { | |
613 | if (!test_bit(j, &present)) | |
614 | continue; | |
615 | uv_blade_info[blade].pnode = (i * 64 + j); | |
616 | uv_blade_info[blade].nr_possible_cpus = 0; | |
ac23d4ee | 617 | uv_blade_info[blade].nr_online_cpus = 0; |
9f5314fb | 618 | blade++; |
ac23d4ee | 619 | } |
9f5314fb | 620 | } |
ac23d4ee | 621 | |
7f594232 | 622 | uv_bios_init(); |
922402f1 | 623 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, |
b0f20989 | 624 | &sn_coherency_id, &sn_region_size); |
7019cc2d RA |
625 | uv_rtc_init(); |
626 | ||
9f5314fb JS |
627 | for_each_present_cpu(cpu) { |
628 | nid = cpu_to_node(cpu); | |
629 | pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu)); | |
630 | blade = boot_pnode_to_blade(pnode); | |
631 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
632 | uv_blade_info[blade].nr_possible_cpus++; | |
633 | ||
6c7184b7 JS |
634 | /* Any node on the blade, else will contain -1. */ |
635 | uv_blade_info[blade].memory_nid = nid; | |
636 | ||
9f5314fb | 637 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; |
189f67c4 | 638 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb JS |
639 | uv_cpu_hub_info(cpu)->m_val = m_val; |
640 | uv_cpu_hub_info(cpu)->n_val = m_val; | |
ac23d4ee JS |
641 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
642 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb | 643 | uv_cpu_hub_info(cpu)->pnode = pnode; |
6a891a24 | 644 | uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; |
9f5314fb JS |
645 | uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1; |
646 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; | |
c4ed3f04 | 647 | uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; |
ac23d4ee | 648 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 649 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
7f1baa06 | 650 | uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu; |
ac23d4ee JS |
651 | uv_node_to_blade[nid] = blade; |
652 | uv_cpu_to_blade[cpu] = blade; | |
83f5d894 | 653 | max_pnode = max(pnode, max_pnode); |
ac23d4ee | 654 | |
83f5d894 | 655 | printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, " |
9f5314fb JS |
656 | "lcpu %d, blade %d\n", |
657 | cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid, | |
658 | lcpu, blade); | |
ac23d4ee | 659 | } |
83f5d894 | 660 | |
6a891a24 JS |
661 | /* Add blade/pnode info for nodes without cpus */ |
662 | for_each_online_node(nid) { | |
663 | if (uv_node_to_blade[nid] >= 0) | |
664 | continue; | |
665 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
fc61e663 | 666 | paddr = uv_soc_phys_ram_to_gpa(paddr); |
6a891a24 JS |
667 | pnode = (paddr >> m_val) & pnode_mask; |
668 | blade = boot_pnode_to_blade(pnode); | |
669 | uv_node_to_blade[nid] = blade; | |
670 | } | |
671 | ||
83f5d894 JS |
672 | map_gru_high(max_pnode); |
673 | map_mmr_high(max_pnode); | |
674 | map_config_high(max_pnode); | |
675 | map_mmioh_high(max_pnode); | |
ac23d4ee | 676 | |
8da077d6 | 677 | uv_cpu_init(); |
7f1baa06 | 678 | uv_scir_register_cpu_notifier(); |
a3d732f9 | 679 | proc_mkdir("sgi_uv", NULL); |
ac23d4ee | 680 | } |