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Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
5f40f7d9 | 8 | * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
186f4360 | 15 | #include <linux/export.h> |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
1b3a5d02 | 28 | #include <linux/reboot.h> |
0b1da1c8 | 29 | |
ac23d4ee JS |
30 | #include <asm/uv/uv_mmrs.h> |
31 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
32 | #include <asm/current.h> |
33 | #include <asm/pgtable.h> | |
7019cc2d | 34 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
35 | #include <asm/uv/uv.h> |
36 | #include <asm/apic.h> | |
5520b7e7 | 37 | #include <asm/e820/api.h> |
0b1da1c8 IM |
38 | #include <asm/ipi.h> |
39 | #include <asm/smp.h> | |
fd12a0d6 | 40 | #include <asm/x86_init.h> |
1d44e828 JS |
41 | #include <asm/nmi.h> |
42 | ||
510b3725 YL |
43 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
44 | ||
7243e106 | 45 | static enum uv_system_type uv_system_type; |
74862b03 | 46 | static bool uv_hubless_system; |
7243e106 IM |
47 | static u64 gru_start_paddr, gru_end_paddr; |
48 | static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; | |
49 | static u64 gru_dist_lmask, gru_dist_umask; | |
50 | static union uvh_apicid uvh_apicid; | |
841582ea | 51 | |
7243e106 | 52 | /* Information derived from CPUID: */ |
405422d8 MT |
53 | static struct { |
54 | unsigned int apicid_shift; | |
55 | unsigned int apicid_mask; | |
56 | unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */ | |
57 | unsigned int pnode_mask; | |
58 | unsigned int gpa_shift; | |
81a71176 | 59 | unsigned int gnode_shift; |
405422d8 MT |
60 | } uv_cpuid; |
61 | ||
7a1110e8 JS |
62 | int uv_min_hub_revision_id; |
63 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
7243e106 | 64 | |
8191c9f6 DS |
65 | unsigned int uv_apicid_hibits; |
66 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
fd12a0d6 | 67 | |
1a8880a1 | 68 | static struct apic apic_x2apic_uv_x; |
3edcf2ff | 69 | static struct uv_hub_info_s uv_hub_info_node0; |
1a8880a1 | 70 | |
7243e106 | 71 | /* Set this to use hardware error handler instead of kernel panic: */ |
7563421b | 72 | static int disable_uv_undefined_panic = 1; |
7243e106 | 73 | |
7563421b MT |
74 | unsigned long uv_undefined(char *str) |
75 | { | |
76 | if (likely(!disable_uv_undefined_panic)) | |
77 | panic("UV: error: undefined MMR: %s\n", str); | |
78 | else | |
79 | pr_crit("UV: error: undefined MMR: %s\n", str); | |
7243e106 IM |
80 | |
81 | /* Cause a machine fault: */ | |
82 | return ~0ul; | |
7563421b MT |
83 | } |
84 | EXPORT_SYMBOL(uv_undefined); | |
85 | ||
e6810413 JS |
86 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
87 | { | |
88 | unsigned long val, *mmr; | |
89 | ||
90 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
91 | val = *mmr; | |
92 | early_iounmap(mmr, sizeof(*mmr)); | |
7243e106 | 93 | |
e6810413 JS |
94 | return val; |
95 | } | |
96 | ||
eb41c8be | 97 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 98 | { |
879d5ad0 | 99 | if (gru_dist_base) { |
7243e106 IM |
100 | u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */ |
101 | u64 sl = start & gru_dist_lmask; /* Base offset bits */ | |
879d5ad0 DS |
102 | u64 eu = end & gru_dist_umask; |
103 | u64 el = end & gru_dist_lmask; | |
104 | ||
7243e106 | 105 | /* Must reside completely within a single GRU range: */ |
879d5ad0 DS |
106 | return (sl == gru_dist_base && el == gru_dist_base && |
107 | su >= gru_first_node_paddr && | |
108 | su <= gru_last_node_paddr && | |
109 | eu == su); | |
110 | } else { | |
111 | return start >= gru_start_paddr && end <= gru_end_paddr; | |
112 | } | |
fd12a0d6 JS |
113 | } |
114 | ||
eb41c8be | 115 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
116 | { |
117 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
118 | } | |
1b9b89e7 | 119 | |
d8850ba4 | 120 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
121 | { |
122 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
123 | union uvh_rh_gam_config_mmr_u m_n_config; |
124 | int pnode; | |
7a1110e8 JS |
125 | |
126 | /* Currently, all blades have same revision number */ | |
e6810413 | 127 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 128 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
129 | uv_min_hub_revision_id = node_id.s.revision; |
130 | ||
b15cc4a1 MT |
131 | switch (node_id.s.part_number) { |
132 | case UV2_HUB_PART_NUMBER: | |
133 | case UV2_HUB_PART_NUMBER_X: | |
b495e039 | 134 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; |
b15cc4a1 MT |
135 | break; |
136 | case UV3_HUB_PART_NUMBER: | |
137 | case UV3_HUB_PART_NUMBER_X: | |
dd3c9c4b | 138 | uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; |
b15cc4a1 | 139 | break; |
a0ec83f3 MT |
140 | case UV4_HUB_PART_NUMBER: |
141 | uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; | |
81a71176 | 142 | uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ |
a0ec83f3 | 143 | break; |
b15cc4a1 | 144 | } |
2a919596 JS |
145 | |
146 | uv_hub_info->hub_revision = uv_min_hub_revision_id; | |
405422d8 MT |
147 | uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1; |
148 | pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask; | |
7243e106 | 149 | uv_cpuid.gpa_shift = 46; /* Default unless changed */ |
405422d8 MT |
150 | |
151 | pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n", | |
152 | node_id.s.revision, node_id.s.part_number, node_id.s.node_id, | |
153 | m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode); | |
d8850ba4 | 154 | return pnode; |
27229ca6 JS |
155 | } |
156 | ||
7243e106 IM |
157 | /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ |
158 | ||
159 | #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ | |
160 | #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ | |
161 | #define SMT_TYPE 1 | |
162 | #define CORE_TYPE 2 | |
405422d8 MT |
163 | #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) |
164 | #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) | |
165 | ||
166 | static void set_x2apic_bits(void) | |
167 | { | |
168 | unsigned int eax, ebx, ecx, edx, sub_index; | |
169 | unsigned int sid_shift; | |
170 | ||
171 | cpuid(0, &eax, &ebx, &ecx, &edx); | |
172 | if (eax < 0xb) { | |
173 | pr_info("UV: CPU does not have CPUID.11\n"); | |
174 | return; | |
175 | } | |
7243e106 | 176 | |
405422d8 MT |
177 | cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); |
178 | if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { | |
179 | pr_info("UV: CPUID.11 not implemented\n"); | |
180 | return; | |
181 | } | |
7243e106 | 182 | |
405422d8 MT |
183 | sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); |
184 | sub_index = 1; | |
185 | do { | |
186 | cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); | |
187 | if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { | |
188 | sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); | |
189 | break; | |
190 | } | |
191 | sub_index++; | |
192 | } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); | |
7243e106 IM |
193 | |
194 | uv_cpuid.apicid_shift = 0; | |
195 | uv_cpuid.apicid_mask = (~(-1 << sid_shift)); | |
405422d8 MT |
196 | uv_cpuid.socketid_shift = sid_shift; |
197 | } | |
198 | ||
199 | static void __init early_get_apic_socketid_shift(void) | |
c8f730b1 | 200 | { |
405422d8 MT |
201 | if (is_uv2_hub() || is_uv3_hub()) |
202 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); | |
203 | ||
204 | set_x2apic_bits(); | |
205 | ||
7243e106 IM |
206 | pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); |
207 | pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); | |
c8f730b1 RA |
208 | } |
209 | ||
8191c9f6 DS |
210 | /* |
211 | * Add an extra bit as dictated by bios to the destination apicid of | |
212 | * interrupts potentially passing through the UV HUB. This prevents | |
213 | * a deadlock between interrupts and IO port operations. | |
214 | */ | |
215 | static void __init uv_set_apicid_hibit(void) | |
216 | { | |
2a919596 | 217 | union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; |
8191c9f6 | 218 | |
2a919596 | 219 | if (is_uv1_hub()) { |
7243e106 IM |
220 | apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); |
221 | uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; | |
2a919596 | 222 | } |
8191c9f6 DS |
223 | } |
224 | ||
52459ab9 | 225 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 226 | { |
379b97e2 MT |
227 | int pnodeid; |
228 | int uv_apic; | |
1d2c867c | 229 | |
74862b03 | 230 | if (strncmp(oem_id, "SGI", 3) != 0) { |
231 | if (strncmp(oem_id, "NSGI", 4) == 0) { | |
232 | uv_hubless_system = true; | |
233 | pr_info("UV: OEM IDs %s/%s, HUBLESS\n", | |
234 | oem_id, oem_table_id); | |
235 | } | |
7a4e0170 | 236 | return 0; |
74862b03 | 237 | } |
7a4e0170 | 238 | |
5a52e8f8 MT |
239 | if (numa_off) { |
240 | pr_err("UV: NUMA is off, disabling UV support\n"); | |
241 | return 0; | |
242 | } | |
243 | ||
7243e106 | 244 | /* Set up early hub type field in uv_hub_info for Node 0 */ |
3edcf2ff MT |
245 | uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; |
246 | ||
379b97e2 MT |
247 | /* |
248 | * Determine UV arch type. | |
7243e106 | 249 | * SGI: UV100/1000 |
379b97e2 MT |
250 | * SGI2: UV2000/3000 |
251 | * SGI3: UV300 (truncated to 4 chars because of different varieties) | |
a0ec83f3 | 252 | * SGI4: UV400 (truncated to 4 chars because of different varieties) |
379b97e2 MT |
253 | */ |
254 | uv_hub_info->hub_revision = | |
a0ec83f3 | 255 | !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : |
379b97e2 MT |
256 | !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : |
257 | !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : | |
258 | !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; | |
259 | ||
260 | if (uv_hub_info->hub_revision == 0) | |
261 | goto badbios; | |
262 | ||
263 | pnodeid = early_get_pnodeid(); | |
405422d8 | 264 | early_get_apic_socketid_shift(); |
7243e106 IM |
265 | |
266 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; | |
379b97e2 MT |
267 | x86_platform.nmi_init = uv_nmi_init; |
268 | ||
7243e106 IM |
269 | if (!strcmp(oem_table_id, "UVX")) { |
270 | /* This is the most common hardware variant: */ | |
379b97e2 MT |
271 | uv_system_type = UV_X2APIC; |
272 | uv_apic = 0; | |
273 | ||
7243e106 IM |
274 | } else if (!strcmp(oem_table_id, "UVH")) { |
275 | /* Only UV1 systems: */ | |
379b97e2 | 276 | uv_system_type = UV_NON_UNIQUE_APIC; |
7243e106 | 277 | __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift); |
379b97e2 MT |
278 | uv_set_apicid_hibit(); |
279 | uv_apic = 1; | |
280 | ||
7243e106 IM |
281 | } else if (!strcmp(oem_table_id, "UVL")) { |
282 | /* Only used for very small systems: */ | |
283 | uv_system_type = UV_LEGACY_APIC; | |
379b97e2 MT |
284 | uv_apic = 0; |
285 | ||
286 | } else { | |
287 | goto badbios; | |
1b9b89e7 | 288 | } |
379b97e2 | 289 | |
7243e106 | 290 | pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic); |
379b97e2 MT |
291 | |
292 | return uv_apic; | |
293 | ||
294 | badbios: | |
295 | pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id); | |
296 | pr_err("Current BIOS not supported, update kernel and/or BIOS\n"); | |
297 | BUG(); | |
1b9b89e7 YL |
298 | } |
299 | ||
300 | enum uv_system_type get_uv_system_type(void) | |
301 | { | |
302 | return uv_system_type; | |
303 | } | |
304 | ||
305 | int is_uv_system(void) | |
306 | { | |
307 | return uv_system_type != UV_NONE; | |
308 | } | |
8067794b | 309 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 310 | |
74862b03 | 311 | int is_uv_hubless(void) |
312 | { | |
313 | return uv_hubless_system; | |
314 | } | |
315 | EXPORT_SYMBOL_GPL(is_uv_hubless); | |
316 | ||
3edcf2ff MT |
317 | void **__uv_hub_info_list; |
318 | EXPORT_SYMBOL_GPL(__uv_hub_info_list); | |
ac23d4ee | 319 | |
0045ddd2 MT |
320 | DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); |
321 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); | |
322 | ||
ac23d4ee JS |
323 | short uv_possible_blades; |
324 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
325 | ||
7019cc2d RA |
326 | unsigned long sn_rtc_cycles_per_second; |
327 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
328 | ||
7243e106 IM |
329 | /* The following values are used for the per node hub info struct */ |
330 | static __initdata unsigned short *_node_to_pnode; | |
331 | static __initdata unsigned short _min_socket, _max_socket; | |
332 | static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; | |
333 | static __initdata struct uv_gam_range_entry *uv_gre_table; | |
334 | static __initdata struct uv_gam_parameters *uv_gp_table; | |
335 | static __initdata unsigned short *_socket_to_node; | |
336 | static __initdata unsigned short *_socket_to_pnode; | |
337 | static __initdata unsigned short *_pnode_to_socket; | |
338 | ||
339 | static __initdata struct uv_gam_range_s *_gr_table; | |
340 | ||
1de329c1 | 341 | #define SOCK_EMPTY ((unsigned short)~0) |
906f3b20 | 342 | |
3edcf2ff MT |
343 | extern int uv_hub_info_version(void) |
344 | { | |
345 | return UV_HUB_INFO_VERSION; | |
346 | } | |
347 | EXPORT_SYMBOL(uv_hub_info_version); | |
348 | ||
7243e106 | 349 | /* Build GAM range lookup table: */ |
c85375cd MT |
350 | static __init void build_uv_gr_table(void) |
351 | { | |
352 | struct uv_gam_range_entry *gre = uv_gre_table; | |
353 | struct uv_gam_range_s *grt; | |
354 | unsigned long last_limit = 0, ram_limit = 0; | |
054f621f | 355 | int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; |
c85375cd MT |
356 | |
357 | if (!gre) | |
358 | return; | |
359 | ||
360 | bytes = _gr_table_len * sizeof(struct uv_gam_range_s); | |
361 | grt = kzalloc(bytes, GFP_KERNEL); | |
362 | BUG_ON(!grt); | |
363 | _gr_table = grt; | |
364 | ||
365 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { | |
366 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { | |
7243e106 IM |
367 | if (!ram_limit) { |
368 | /* Mark hole between RAM/non-RAM: */ | |
c85375cd MT |
369 | ram_limit = last_limit; |
370 | last_limit = gre->limit; | |
371 | lsid++; | |
372 | continue; | |
373 | } | |
374 | last_limit = gre->limit; | |
7243e106 | 375 | pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); |
c85375cd MT |
376 | continue; |
377 | } | |
378 | if (_max_socket < gre->sockid) { | |
7243e106 | 379 | pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); |
c85375cd MT |
380 | continue; |
381 | } | |
382 | sid = gre->sockid - _min_socket; | |
7243e106 IM |
383 | if (lsid < sid) { |
384 | /* New range: */ | |
054f621f MT |
385 | grt = &_gr_table[indx]; |
386 | grt->base = lindx; | |
c85375cd MT |
387 | grt->nasid = gre->nasid; |
388 | grt->limit = last_limit = gre->limit; | |
389 | lsid = sid; | |
054f621f | 390 | lindx = indx++; |
c85375cd MT |
391 | continue; |
392 | } | |
7243e106 IM |
393 | /* Update range: */ |
394 | if (lsid == sid && !ram_limit) { | |
395 | /* .. if contiguous: */ | |
396 | if (grt->limit == last_limit) { | |
c85375cd MT |
397 | grt->limit = last_limit = gre->limit; |
398 | continue; | |
399 | } | |
400 | } | |
7243e106 IM |
401 | /* Non-contiguous RAM range: */ |
402 | if (!ram_limit) { | |
c85375cd | 403 | grt++; |
054f621f | 404 | grt->base = lindx; |
c85375cd MT |
405 | grt->nasid = gre->nasid; |
406 | grt->limit = last_limit = gre->limit; | |
407 | continue; | |
408 | } | |
7243e106 IM |
409 | /* Non-contiguous/non-RAM: */ |
410 | grt++; | |
411 | /* base is this entry */ | |
412 | grt->base = grt - _gr_table; | |
c85375cd MT |
413 | grt->nasid = gre->nasid; |
414 | grt->limit = last_limit = gre->limit; | |
415 | lsid++; | |
416 | } | |
417 | ||
7243e106 | 418 | /* Shorten table if possible */ |
c85375cd MT |
419 | grt++; |
420 | i = grt - _gr_table; | |
421 | if (i < _gr_table_len) { | |
422 | void *ret; | |
423 | ||
424 | bytes = i * sizeof(struct uv_gam_range_s); | |
425 | ret = krealloc(_gr_table, bytes, GFP_KERNEL); | |
426 | if (ret) { | |
427 | _gr_table = ret; | |
428 | _gr_table_len = i; | |
429 | } | |
430 | } | |
431 | ||
7243e106 | 432 | /* Display resultant GAM range table: */ |
c85375cd | 433 | for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { |
7243e106 | 434 | unsigned long start, end; |
c85375cd | 435 | int gb = grt->base; |
c85375cd | 436 | |
7243e106 IM |
437 | start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; |
438 | end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; | |
439 | ||
440 | pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); | |
c85375cd MT |
441 | } |
442 | } | |
443 | ||
148f9bb8 | 444 | static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee JS |
445 | { |
446 | unsigned long val; | |
9f5314fb | 447 | int pnode; |
ac23d4ee | 448 | |
9f5314fb | 449 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 450 | phys_apicid |= uv_apicid_hibits; |
7243e106 | 451 | |
ac23d4ee JS |
452 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
453 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 454 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 455 | APIC_DM_INIT; |
7243e106 | 456 | |
9f5314fb | 457 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
458 | |
459 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
460 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 461 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 462 | APIC_DM_STARTUP; |
7243e106 | 463 | |
9f5314fb | 464 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf | 465 | |
ac23d4ee JS |
466 | return 0; |
467 | } | |
468 | ||
469 | static void uv_send_IPI_one(int cpu, int vector) | |
470 | { | |
66666e50 | 471 | unsigned long apicid; |
9f5314fb | 472 | int pnode; |
ac23d4ee | 473 | |
1e0b5d00 | 474 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 475 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 476 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
477 | } |
478 | ||
bcda016e | 479 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
480 | { |
481 | unsigned int cpu; | |
482 | ||
bcda016e | 483 | for_each_cpu(cpu, mask) |
e7986739 MT |
484 | uv_send_IPI_one(cpu, vector); |
485 | } | |
486 | ||
bcda016e | 487 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 488 | { |
e7986739 | 489 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 490 | unsigned int cpu; |
e7986739 | 491 | |
dac5f412 | 492 | for_each_cpu(cpu, mask) { |
e7986739 | 493 | if (cpu != this_cpu) |
ac23d4ee | 494 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 495 | } |
ac23d4ee JS |
496 | } |
497 | ||
498 | static void uv_send_IPI_allbutself(int vector) | |
499 | { | |
e7986739 | 500 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 501 | unsigned int cpu; |
ac23d4ee | 502 | |
dac5f412 | 503 | for_each_online_cpu(cpu) { |
e7986739 MT |
504 | if (cpu != this_cpu) |
505 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 506 | } |
ac23d4ee JS |
507 | } |
508 | ||
509 | static void uv_send_IPI_all(int vector) | |
510 | { | |
bcda016e | 511 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
512 | } |
513 | ||
b7157acf SP |
514 | static int uv_apic_id_valid(int apicid) |
515 | { | |
516 | return 1; | |
517 | } | |
518 | ||
ac23d4ee JS |
519 | static int uv_apic_id_registered(void) |
520 | { | |
521 | return 1; | |
522 | } | |
523 | ||
277d1f58 | 524 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
525 | { |
526 | } | |
527 | ||
ff164324 | 528 | static int |
debccb3e | 529 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
530 | const struct cpumask *andmask, |
531 | unsigned int *apicid) | |
95d313cf | 532 | { |
ea3807ea | 533 | int unsigned cpu; |
95d313cf MT |
534 | |
535 | /* | |
536 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
537 | * May as well be the first. | |
538 | */ | |
debccb3e | 539 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
540 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
541 | break; | |
debccb3e | 542 | } |
ff164324 | 543 | |
ea3807ea | 544 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
545 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
546 | return 0; | |
a5a39156 | 547 | } |
ea3807ea AG |
548 | |
549 | return -EINVAL; | |
95d313cf MT |
550 | } |
551 | ||
ca6c8ed4 | 552 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
553 | { |
554 | unsigned int id; | |
555 | ||
556 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 557 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
558 | |
559 | return id; | |
560 | } | |
561 | ||
1b9b89e7 | 562 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc | 563 | { |
f148b41e MY |
564 | /* CHECKME: Do we need to mask out the xapic extra bits? */ |
565 | return id; | |
f910a9dc YL |
566 | } |
567 | ||
568 | static unsigned int uv_read_apic_id(void) | |
569 | { | |
ca6c8ed4 | 570 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
571 | } |
572 | ||
d4c9a9f3 | 573 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 574 | { |
0c81c746 | 575 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
576 | } |
577 | ||
ac23d4ee JS |
578 | static void uv_send_IPI_self(int vector) |
579 | { | |
580 | apic_write(APIC_SELF_IPI, vector); | |
581 | } | |
ac23d4ee | 582 | |
9ebd680b SS |
583 | static int uv_probe(void) |
584 | { | |
585 | return apic == &apic_x2apic_uv_x; | |
586 | } | |
587 | ||
404f6aac | 588 | static struct apic apic_x2apic_uv_x __ro_after_init = { |
c7967329 IM |
589 | |
590 | .name = "UV large system", | |
9ebd680b | 591 | .probe = uv_probe, |
c7967329 | 592 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
b7157acf | 593 | .apic_id_valid = uv_apic_id_valid, |
c7967329 IM |
594 | .apic_id_registered = uv_apic_id_registered, |
595 | ||
f8987a10 | 596 | .irq_delivery_mode = dest_Fixed, |
7243e106 | 597 | .irq_dest_mode = 0, /* Physical */ |
c7967329 | 598 | |
bf721d3a | 599 | .target_cpus = online_target_cpus, |
08125d3e | 600 | .disable_esr = 0, |
bdb1a9b6 | 601 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 | 602 | .check_apicid_used = NULL, |
c7967329 | 603 | |
9d8e1066 | 604 | .vector_allocation_domain = default_vector_allocation_domain, |
c7967329 IM |
605 | .init_apic_ldr = uv_init_apic_ldr, |
606 | ||
607 | .ioapic_phys_id_map = NULL, | |
608 | .setup_apic_routing = NULL, | |
a21769a4 | 609 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 | 610 | .apicid_to_cpu_present = NULL, |
a27a6210 | 611 | .check_phys_apicid_present = default_check_phys_apicid_present, |
d4c9a9f3 | 612 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 | 613 | |
ca6c8ed4 | 614 | .get_apic_id = x2apic_get_apic_id, |
c7967329 | 615 | .set_apic_id = set_apic_id, |
c7967329 | 616 | |
c7967329 IM |
617 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, |
618 | ||
8642ea95 | 619 | .send_IPI = uv_send_IPI_one, |
c7967329 IM |
620 | .send_IPI_mask = uv_send_IPI_mask, |
621 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
622 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
623 | .send_IPI_all = uv_send_IPI_all, | |
624 | .send_IPI_self = uv_send_IPI_self, | |
625 | ||
1f5bcabf | 626 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
c7967329 | 627 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
628 | |
629 | .read = native_apic_msr_read, | |
630 | .write = native_apic_msr_write, | |
0ab711ae | 631 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
632 | .icr_read = native_x2apic_icr_read, |
633 | .icr_write = native_x2apic_icr_write, | |
634 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
635 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
636 | }; |
637 | ||
148f9bb8 | 638 | static void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 639 | { |
16ee8db6 | 640 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
641 | } |
642 | ||
c443c03d | 643 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 |
9f5314fb JS |
644 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT |
645 | ||
9f5314fb JS |
646 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) |
647 | { | |
62b0cfc2 | 648 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb | 649 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
c443c03d MT |
650 | unsigned long m_redirect; |
651 | unsigned long m_overlay; | |
9f5314fb JS |
652 | int i; |
653 | ||
c443c03d MT |
654 | for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { |
655 | switch (i) { | |
656 | case 0: | |
657 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; | |
7243e106 | 658 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; |
c443c03d MT |
659 | break; |
660 | case 1: | |
661 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; | |
7243e106 | 662 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; |
c443c03d MT |
663 | break; |
664 | case 2: | |
665 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; | |
7243e106 | 666 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; |
c443c03d MT |
667 | break; |
668 | } | |
669 | alias.v = uv_read_local_mmr(m_overlay); | |
036ed8ba | 670 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb | 671 | *size = (1UL << alias.s.m_alias); |
c443c03d | 672 | redirect.v = uv_read_local_mmr(m_redirect); |
7243e106 | 673 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; |
9f5314fb JS |
674 | return; |
675 | } | |
676 | } | |
036ed8ba | 677 | *base = *size = 0; |
9f5314fb JS |
678 | } |
679 | ||
83f5d894 JS |
680 | enum map_type {map_wb, map_uc}; |
681 | ||
7243e106 | 682 | static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) |
83f5d894 JS |
683 | { |
684 | unsigned long bytes, paddr; | |
685 | ||
fcfbb2b5 MT |
686 | paddr = base << pshift; |
687 | bytes = (1UL << bshift) * (max_pnode + 1); | |
b15cc4a1 MT |
688 | if (!paddr) { |
689 | pr_info("UV: Map %s_HI base address NULL\n", id); | |
690 | return; | |
691 | } | |
879d5ad0 | 692 | pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); |
83f5d894 JS |
693 | if (map_type == map_uc) |
694 | init_extra_mapping_uc(paddr, bytes); | |
695 | else | |
696 | init_extra_mapping_wb(paddr, bytes); | |
83f5d894 | 697 | } |
b15cc4a1 | 698 | |
879d5ad0 DS |
699 | static __init void map_gru_distributed(unsigned long c) |
700 | { | |
701 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
702 | u64 paddr; | |
703 | unsigned long bytes; | |
704 | int nid; | |
705 | ||
706 | gru.v = c; | |
7243e106 IM |
707 | |
708 | /* Only base bits 42:28 relevant in dist mode */ | |
879d5ad0 DS |
709 | gru_dist_base = gru.v & 0x000007fff0000000UL; |
710 | if (!gru_dist_base) { | |
711 | pr_info("UV: Map GRU_DIST base address NULL\n"); | |
712 | return; | |
713 | } | |
7243e106 | 714 | |
879d5ad0 DS |
715 | bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; |
716 | gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1); | |
717 | gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1); | |
718 | gru_dist_base &= gru_dist_lmask; /* Clear bits above M */ | |
7243e106 | 719 | |
879d5ad0 DS |
720 | for_each_online_node(nid) { |
721 | paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) | | |
722 | gru_dist_base; | |
723 | init_extra_mapping_wb(paddr, bytes); | |
724 | gru_first_node_paddr = min(paddr, gru_first_node_paddr); | |
725 | gru_last_node_paddr = max(paddr, gru_last_node_paddr); | |
726 | } | |
7243e106 | 727 | |
879d5ad0 DS |
728 | /* Save upper (63:M) bits of address only for is_GRU_range */ |
729 | gru_first_node_paddr &= gru_dist_umask; | |
730 | gru_last_node_paddr &= gru_dist_umask; | |
7243e106 IM |
731 | |
732 | pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr); | |
879d5ad0 DS |
733 | } |
734 | ||
83f5d894 JS |
735 | static __init void map_gru_high(int max_pnode) |
736 | { | |
737 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
738 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
c443c03d MT |
739 | unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; |
740 | unsigned long base; | |
83f5d894 JS |
741 | |
742 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
879d5ad0 | 743 | if (!gru.s.enable) { |
b15cc4a1 | 744 | pr_info("UV: GRU disabled\n"); |
879d5ad0 DS |
745 | return; |
746 | } | |
747 | ||
748 | if (is_uv3_hub() && gru.s3.mode) { | |
749 | map_gru_distributed(gru.v); | |
750 | return; | |
fd12a0d6 | 751 | } |
7243e106 | 752 | |
c443c03d MT |
753 | base = (gru.v & mask) >> shift; |
754 | map_high("GRU", base, shift, shift, max_pnode, map_wb); | |
755 | gru_start_paddr = ((u64)base << shift); | |
879d5ad0 | 756 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); |
83f5d894 JS |
757 | } |
758 | ||
daf7b9c9 JS |
759 | static __init void map_mmr_high(int max_pnode) |
760 | { | |
761 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
762 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
763 | ||
764 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
765 | if (mmr.s.enable) | |
fcfbb2b5 | 766 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
b15cc4a1 MT |
767 | else |
768 | pr_info("UV: MMR disabled\n"); | |
769 | } | |
770 | ||
771 | /* | |
772 | * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY | |
773 | * and REDIRECT MMR regs are exactly the same on UV3. | |
774 | */ | |
775 | struct mmioh_config { | |
776 | unsigned long overlay; | |
777 | unsigned long redirect; | |
778 | char *id; | |
779 | }; | |
780 | ||
781 | static __initdata struct mmioh_config mmiohs[] = { | |
782 | { | |
783 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, | |
784 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, | |
785 | "MMIOH0" | |
786 | }, | |
787 | { | |
788 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, | |
789 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, | |
790 | "MMIOH1" | |
791 | }, | |
792 | }; | |
793 | ||
a2f28e69 | 794 | /* UV3 & UV4 have identical MMIOH overlay configs */ |
b15cc4a1 MT |
795 | static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) |
796 | { | |
797 | union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; | |
798 | unsigned long mmr; | |
799 | unsigned long base; | |
800 | int i, n, shift, m_io, max_io; | |
801 | int nasid, lnasid, fi, li; | |
802 | char *id; | |
803 | ||
804 | id = mmiohs[index].id; | |
805 | overlay.v = uv_read_local_mmr(mmiohs[index].overlay); | |
7243e106 IM |
806 | |
807 | pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", id, overlay.v, overlay.s3.base, overlay.s3.m_io); | |
b15cc4a1 MT |
808 | if (!overlay.s3.enable) { |
809 | pr_info("UV: %s disabled\n", id); | |
810 | return; | |
811 | } | |
812 | ||
813 | shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; | |
814 | base = (unsigned long)overlay.s3.base; | |
815 | m_io = overlay.s3.m_io; | |
816 | mmr = mmiohs[index].redirect; | |
817 | n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; | |
7243e106 IM |
818 | /* Convert to NASID: */ |
819 | min_pnode *= 2; | |
b15cc4a1 MT |
820 | max_pnode *= 2; |
821 | max_io = lnasid = fi = li = -1; | |
822 | ||
823 | for (i = 0; i < n; i++) { | |
824 | union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; | |
825 | ||
826 | redirect.v = uv_read_local_mmr(mmr + i * 8); | |
827 | nasid = redirect.s3.nasid; | |
7243e106 | 828 | /* Invalid NASID: */ |
b15cc4a1 | 829 | if (nasid < min_pnode || max_pnode < nasid) |
7243e106 | 830 | nasid = -1; |
b15cc4a1 MT |
831 | |
832 | if (nasid == lnasid) { | |
833 | li = i; | |
7243e106 IM |
834 | /* Last entry check: */ |
835 | if (i != n-1) | |
b15cc4a1 MT |
836 | continue; |
837 | } | |
838 | ||
7243e106 | 839 | /* Check if we have a cached (or last) redirect to print: */ |
b15cc4a1 MT |
840 | if (lnasid != -1 || (i == n-1 && nasid != -1)) { |
841 | unsigned long addr1, addr2; | |
842 | int f, l; | |
843 | ||
844 | if (lnasid == -1) { | |
845 | f = l = i; | |
846 | lnasid = nasid; | |
847 | } else { | |
848 | f = fi; | |
849 | l = li; | |
850 | } | |
7243e106 IM |
851 | addr1 = (base << shift) + f * (1ULL << m_io); |
852 | addr2 = (base << shift) + (l + 1) * (1ULL << m_io); | |
853 | pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2); | |
b15cc4a1 MT |
854 | if (max_io < l) |
855 | max_io = l; | |
856 | } | |
857 | fi = li = i; | |
858 | lnasid = nasid; | |
859 | } | |
860 | ||
7243e106 | 861 | pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io); |
b15cc4a1 MT |
862 | |
863 | if (max_io >= 0) | |
864 | map_high(id, base, shift, m_io, max_io, map_uc); | |
daf7b9c9 JS |
865 | } |
866 | ||
b15cc4a1 | 867 | static __init void map_mmioh_high(int min_pnode, int max_pnode) |
83f5d894 JS |
868 | { |
869 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
b15cc4a1 MT |
870 | unsigned long mmr, base; |
871 | int shift, enable, m_io, n_io; | |
83f5d894 | 872 | |
a2f28e69 | 873 | if (is_uv3_hub() || is_uv4_hub()) { |
7243e106 | 874 | /* Map both MMIOH regions: */ |
b15cc4a1 MT |
875 | map_mmioh_high_uv3(0, min_pnode, max_pnode); |
876 | map_mmioh_high_uv3(1, min_pnode, max_pnode); | |
877 | return; | |
2a919596 | 878 | } |
b15cc4a1 MT |
879 | |
880 | if (is_uv1_hub()) { | |
7243e106 IM |
881 | mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; |
882 | shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
883 | mmioh.v = uv_read_local_mmr(mmr); | |
884 | enable = !!mmioh.s1.enable; | |
885 | base = mmioh.s1.base; | |
886 | m_io = mmioh.s1.m_io; | |
887 | n_io = mmioh.s1.n_io; | |
b15cc4a1 | 888 | } else if (is_uv2_hub()) { |
7243e106 IM |
889 | mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; |
890 | shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
891 | mmioh.v = uv_read_local_mmr(mmr); | |
892 | enable = !!mmioh.s2.enable; | |
893 | base = mmioh.s2.base; | |
894 | m_io = mmioh.s2.m_io; | |
895 | n_io = mmioh.s2.n_io; | |
896 | } else { | |
b15cc4a1 | 897 | return; |
7243e106 | 898 | } |
b15cc4a1 MT |
899 | |
900 | if (enable) { | |
901 | max_pnode &= (1 << n_io) - 1; | |
7243e106 | 902 | pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode); |
b15cc4a1 MT |
903 | map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); |
904 | } else { | |
905 | pr_info("UV: MMIOH disabled\n"); | |
2a919596 | 906 | } |
83f5d894 JS |
907 | } |
908 | ||
918bc960 JS |
909 | static __init void map_low_mmrs(void) |
910 | { | |
911 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
912 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
913 | } | |
914 | ||
7019cc2d RA |
915 | static __init void uv_rtc_init(void) |
916 | { | |
922402f1 RA |
917 | long status; |
918 | u64 ticks_per_sec; | |
7019cc2d | 919 | |
7243e106 IM |
920 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); |
921 | ||
922402f1 | 922 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { |
7243e106 IM |
923 | pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); |
924 | ||
925 | /* BIOS gives wrong value for clock frequency, so guess: */ | |
7019cc2d | 926 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; |
7243e106 | 927 | } else { |
7019cc2d | 928 | sn_rtc_cycles_per_second = ticks_per_sec; |
7243e106 | 929 | } |
7019cc2d RA |
930 | } |
931 | ||
7f1baa06 MT |
932 | /* |
933 | * percpu heartbeat timer | |
934 | */ | |
935 | static void uv_heartbeat(unsigned long ignored) | |
936 | { | |
d38bb135 MT |
937 | struct timer_list *timer = &uv_scir_info->timer; |
938 | unsigned char bits = uv_scir_info->state; | |
7f1baa06 | 939 | |
7243e106 | 940 | /* Flip heartbeat bit: */ |
7f1baa06 MT |
941 | bits ^= SCIR_CPU_HEARTBEAT; |
942 | ||
7243e106 | 943 | /* Is this CPU idle? */ |
69a72a0e | 944 | if (idle_cpu(raw_smp_processor_id())) |
7f1baa06 MT |
945 | bits &= ~SCIR_CPU_ACTIVITY; |
946 | else | |
947 | bits |= SCIR_CPU_ACTIVITY; | |
948 | ||
7243e106 | 949 | /* Update system controller interface reg: */ |
7f1baa06 MT |
950 | uv_set_scir_bits(bits); |
951 | ||
7243e106 | 952 | /* Enable next timer period: */ |
920a4a70 | 953 | mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
954 | } |
955 | ||
b067a7be | 956 | static int uv_heartbeat_enable(unsigned int cpu) |
7f1baa06 | 957 | { |
d38bb135 MT |
958 | while (!uv_cpu_scir_info(cpu)->enabled) { |
959 | struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer; | |
7f1baa06 MT |
960 | |
961 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
920a4a70 | 962 | setup_pinned_timer(timer, uv_heartbeat, cpu); |
7f1baa06 MT |
963 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; |
964 | add_timer_on(timer, cpu); | |
d38bb135 | 965 | uv_cpu_scir_info(cpu)->enabled = 1; |
7f1baa06 | 966 | |
7243e106 | 967 | /* Also ensure that boot CPU is enabled: */ |
99659a92 RK |
968 | cpu = 0; |
969 | } | |
b067a7be | 970 | return 0; |
7f1baa06 MT |
971 | } |
972 | ||
77be80e4 | 973 | #ifdef CONFIG_HOTPLUG_CPU |
b067a7be | 974 | static int uv_heartbeat_disable(unsigned int cpu) |
7f1baa06 | 975 | { |
d38bb135 MT |
976 | if (uv_cpu_scir_info(cpu)->enabled) { |
977 | uv_cpu_scir_info(cpu)->enabled = 0; | |
978 | del_timer(&uv_cpu_scir_info(cpu)->timer); | |
7f1baa06 MT |
979 | } |
980 | uv_set_cpu_scir_bits(cpu, 0xff); | |
b067a7be | 981 | return 0; |
7f1baa06 MT |
982 | } |
983 | ||
984 | static __init void uv_scir_register_cpu_notifier(void) | |
985 | { | |
b067a7be SAS |
986 | cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online", |
987 | uv_heartbeat_enable, uv_heartbeat_disable); | |
7f1baa06 MT |
988 | } |
989 | ||
990 | #else /* !CONFIG_HOTPLUG_CPU */ | |
991 | ||
992 | static __init void uv_scir_register_cpu_notifier(void) | |
993 | { | |
994 | } | |
995 | ||
996 | static __init int uv_init_heartbeat(void) | |
997 | { | |
998 | int cpu; | |
999 | ||
7243e106 | 1000 | if (is_uv_system()) { |
7f1baa06 MT |
1001 | for_each_online_cpu(cpu) |
1002 | uv_heartbeat_enable(cpu); | |
7243e106 IM |
1003 | } |
1004 | ||
7f1baa06 MT |
1005 | return 0; |
1006 | } | |
1007 | ||
1008 | late_initcall(uv_init_heartbeat); | |
1009 | ||
1010 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
1011 | ||
841582ea | 1012 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
7243e106 | 1013 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) |
841582ea MT |
1014 | { |
1015 | int domain, bus, rc; | |
1016 | ||
7ad35cf2 | 1017 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
841582ea MT |
1018 | return 0; |
1019 | ||
1020 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
1021 | return 0; | |
1022 | ||
1023 | domain = pci_domain_nr(pdev->bus); | |
1024 | bus = pdev->bus->number; | |
1025 | ||
1026 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
841582ea MT |
1027 | |
1028 | return rc; | |
1029 | } | |
1030 | ||
8da077d6 | 1031 | /* |
7243e106 | 1032 | * Called on each CPU to initialize the per_cpu UV data area. |
0b1da1c8 | 1033 | * FIXME: hotplug not supported yet |
8da077d6 | 1034 | */ |
148f9bb8 | 1035 | void uv_cpu_init(void) |
8da077d6 | 1036 | { |
6a6256f9 | 1037 | /* CPU 0 initialization will be done via uv_system_init. */ |
906f3b20 | 1038 | if (smp_processor_id() == 0) |
8da077d6 JS |
1039 | return; |
1040 | ||
906f3b20 | 1041 | uv_hub_info->nr_online_cpus++; |
8da077d6 JS |
1042 | |
1043 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
1044 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
1045 | } | |
1046 | ||
c443c03d MT |
1047 | struct mn { |
1048 | unsigned char m_val; | |
1049 | unsigned char n_val; | |
1050 | unsigned char m_shift; | |
1051 | unsigned char n_lshift; | |
1052 | }; | |
1053 | ||
1054 | static void get_mn(struct mn *mnp) | |
ac23d4ee | 1055 | { |
c443c03d MT |
1056 | union uvh_rh_gam_config_mmr_u m_n_config; |
1057 | union uv3h_gr0_gam_gr_config_u m_gr_config; | |
1058 | ||
7243e106 IM |
1059 | /* Make sure the whole structure is well initialized: */ |
1060 | memset(mnp, 0, sizeof(*mnp)); | |
1061 | ||
1062 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); | |
1063 | mnp->n_val = m_n_config.s.n_skt; | |
1064 | ||
c443c03d | 1065 | if (is_uv4_hub()) { |
7243e106 IM |
1066 | mnp->m_val = 0; |
1067 | mnp->n_lshift = 0; | |
c443c03d | 1068 | } else if (is_uv3_hub()) { |
7243e106 IM |
1069 | mnp->m_val = m_n_config.s3.m_skt; |
1070 | m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); | |
1071 | mnp->n_lshift = m_gr_config.s3.m_skt; | |
c443c03d | 1072 | } else if (is_uv2_hub()) { |
7243e106 IM |
1073 | mnp->m_val = m_n_config.s2.m_skt; |
1074 | mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; | |
c443c03d | 1075 | } else if (is_uv1_hub()) { |
7243e106 IM |
1076 | mnp->m_val = m_n_config.s1.m_skt; |
1077 | mnp->n_lshift = mnp->m_val; | |
c443c03d MT |
1078 | } |
1079 | mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; | |
1080 | } | |
1081 | ||
7243e106 | 1082 | void __init uv_init_hub_info(struct uv_hub_info_s *hi) |
c443c03d | 1083 | { |
9f5314fb | 1084 | union uvh_node_id_u node_id; |
7243e106 | 1085 | struct mn mn; |
c443c03d MT |
1086 | |
1087 | get_mn(&mn); | |
7243e106 | 1088 | hi->gpa_mask = mn.m_val ? |
405422d8 MT |
1089 | (1UL << (mn.m_val + mn.n_val)) - 1 : |
1090 | (1UL << uv_cpuid.gpa_shift) - 1; | |
c443c03d | 1091 | |
7243e106 IM |
1092 | hi->m_val = mn.m_val; |
1093 | hi->n_val = mn.n_val; | |
1094 | hi->m_shift = mn.m_shift; | |
1095 | hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; | |
1096 | hi->hub_revision = uv_hub_info->hub_revision; | |
1097 | hi->pnode_mask = uv_cpuid.pnode_mask; | |
1098 | hi->min_pnode = _min_pnode; | |
1099 | hi->min_socket = _min_socket; | |
1100 | hi->pnode_to_socket = _pnode_to_socket; | |
1101 | hi->socket_to_node = _socket_to_node; | |
1102 | hi->socket_to_pnode = _socket_to_pnode; | |
1103 | hi->gr_table_len = _gr_table_len; | |
1104 | hi->gr_table = _gr_table; | |
1105 | ||
1106 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); | |
1107 | uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); | |
1108 | hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; | |
ad483005 MT |
1109 | if (mn.m_val) |
1110 | hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; | |
c443c03d | 1111 | |
1de329c1 | 1112 | if (uv_gp_table) { |
7243e106 IM |
1113 | hi->global_mmr_base = uv_gp_table->mmr_base; |
1114 | hi->global_mmr_shift = uv_gp_table->mmr_shift; | |
1115 | hi->global_gru_base = uv_gp_table->gru_base; | |
1116 | hi->global_gru_shift = uv_gp_table->gru_shift; | |
1117 | hi->gpa_shift = uv_gp_table->gpa_shift; | |
1118 | hi->gpa_mask = (1UL << hi->gpa_shift) - 1; | |
1de329c1 | 1119 | } else { |
7243e106 IM |
1120 | hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE; |
1121 | hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; | |
1de329c1 | 1122 | } |
c443c03d | 1123 | |
7243e106 | 1124 | get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); |
c443c03d | 1125 | |
7243e106 | 1126 | hi->apic_pnode_shift = uv_cpuid.socketid_shift; |
c443c03d | 1127 | |
7243e106 IM |
1128 | /* Show system specific info: */ |
1129 | pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); | |
1130 | pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); | |
1131 | pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift); | |
1132 | pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); | |
1de329c1 MT |
1133 | } |
1134 | ||
1135 | static void __init decode_gam_params(unsigned long ptr) | |
1136 | { | |
1137 | uv_gp_table = (struct uv_gam_parameters *)ptr; | |
1138 | ||
1139 | pr_info("UV: GAM Params...\n"); | |
1140 | pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", | |
1141 | uv_gp_table->mmr_base, uv_gp_table->mmr_shift, | |
1142 | uv_gp_table->gru_base, uv_gp_table->gru_shift, | |
1143 | uv_gp_table->gpa_shift); | |
1144 | } | |
1145 | ||
1146 | static void __init decode_gam_rng_tbl(unsigned long ptr) | |
1147 | { | |
1148 | struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; | |
1149 | unsigned long lgre = 0; | |
1150 | int index = 0; | |
1151 | int sock_min = 999999, pnode_min = 99999; | |
1152 | int sock_max = -1, pnode_max = -1; | |
1153 | ||
1154 | uv_gre_table = gre; | |
1155 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { | |
1156 | if (!index) { | |
1157 | pr_info("UV: GAM Range Table...\n"); | |
7243e106 | 1158 | pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); |
1de329c1 | 1159 | } |
7243e106 | 1160 | pr_info("UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n", |
1de329c1 MT |
1161 | index++, |
1162 | (unsigned long)lgre << UV_GAM_RANGE_SHFT, | |
1163 | (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, | |
1164 | ((unsigned long)(gre->limit - lgre)) >> | |
1165 | (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */ | |
22ac2bca | 1166 | gre->type, gre->nasid, gre->sockid, gre->pnode); |
1de329c1 MT |
1167 | |
1168 | lgre = gre->limit; | |
1169 | if (sock_min > gre->sockid) | |
1170 | sock_min = gre->sockid; | |
1171 | if (sock_max < gre->sockid) | |
1172 | sock_max = gre->sockid; | |
1173 | if (pnode_min > gre->pnode) | |
1174 | pnode_min = gre->pnode; | |
1175 | if (pnode_max < gre->pnode) | |
1176 | pnode_max = gre->pnode; | |
1177 | } | |
7243e106 IM |
1178 | _min_socket = sock_min; |
1179 | _max_socket = sock_max; | |
1180 | _min_pnode = pnode_min; | |
1181 | _max_pnode = pnode_max; | |
1182 | _gr_table_len = index; | |
1183 | ||
1184 | pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode); | |
1de329c1 MT |
1185 | } |
1186 | ||
eee5715e | 1187 | static int __init decode_uv_systab(void) |
1de329c1 MT |
1188 | { |
1189 | struct uv_systab *st; | |
1190 | int i; | |
1191 | ||
eee5715e MT |
1192 | if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE) |
1193 | return 0; /* No extended UVsystab required */ | |
1194 | ||
1de329c1 | 1195 | st = uv_systab; |
eee5715e MT |
1196 | if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { |
1197 | int rev = st ? st->revision : 0; | |
1198 | ||
7243e106 IM |
1199 | pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST); |
1200 | pr_err("UV: Cannot support UV operations, switching to generic PC\n"); | |
eee5715e | 1201 | uv_system_type = UV_NONE; |
7243e106 | 1202 | |
eee5715e | 1203 | return -EINVAL; |
1de329c1 | 1204 | } |
c443c03d | 1205 | |
1de329c1 MT |
1206 | for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { |
1207 | unsigned long ptr = st->entry[i].offset; | |
c443c03d | 1208 | |
1de329c1 MT |
1209 | if (!ptr) |
1210 | continue; | |
1211 | ||
1212 | ptr = ptr + (unsigned long)st; | |
1213 | ||
1214 | switch (st->entry[i].type) { | |
1215 | case UV_SYSTAB_TYPE_GAM_PARAMS: | |
1216 | decode_gam_params(ptr); | |
1217 | break; | |
1218 | ||
1219 | case UV_SYSTAB_TYPE_GAM_RNG_TBL: | |
1220 | decode_gam_rng_tbl(ptr); | |
1221 | break; | |
1222 | } | |
1223 | } | |
eee5715e | 1224 | return 0; |
c443c03d MT |
1225 | } |
1226 | ||
906f3b20 | 1227 | /* |
7243e106 | 1228 | * Set up physical blade translations from UVH_NODE_PRESENT_TABLE |
906f3b20 MT |
1229 | * .. NB: UVH_NODE_PRESENT_TABLE is going away, |
1230 | * .. being replaced by GAM Range Table | |
1231 | */ | |
1232 | static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) | |
1233 | { | |
f68376fc | 1234 | int i, uv_pb = 0; |
906f3b20 MT |
1235 | |
1236 | pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH); | |
1237 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
1238 | unsigned long np; | |
1239 | ||
1240 | np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
1241 | if (np) | |
1242 | pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); | |
1243 | ||
1244 | uv_pb += hweight64(np); | |
1245 | } | |
1246 | if (uv_possible_blades != uv_pb) | |
1247 | uv_possible_blades = uv_pb; | |
906f3b20 MT |
1248 | } |
1249 | ||
6e27b91c MT |
1250 | static void __init build_socket_tables(void) |
1251 | { | |
1252 | struct uv_gam_range_entry *gre = uv_gre_table; | |
1253 | int num, nump; | |
1254 | int cpu, i, lnid; | |
1255 | int minsock = _min_socket; | |
1256 | int maxsock = _max_socket; | |
1257 | int minpnode = _min_pnode; | |
1258 | int maxpnode = _max_pnode; | |
1259 | size_t bytes; | |
1260 | ||
1261 | if (!gre) { | |
1262 | if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) { | |
1263 | pr_info("UV: No UVsystab socket table, ignoring\n"); | |
7243e106 | 1264 | return; |
6e27b91c | 1265 | } |
7243e106 | 1266 | pr_crit("UV: Error: UVsystab address translations not available!\n"); |
6e27b91c MT |
1267 | BUG(); |
1268 | } | |
1269 | ||
7243e106 | 1270 | /* Build socket id -> node id, pnode */ |
6e27b91c MT |
1271 | num = maxsock - minsock + 1; |
1272 | bytes = num * sizeof(_socket_to_node[0]); | |
1273 | _socket_to_node = kmalloc(bytes, GFP_KERNEL); | |
1274 | _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); | |
1275 | ||
1276 | nump = maxpnode - minpnode + 1; | |
1277 | bytes = nump * sizeof(_pnode_to_socket[0]); | |
1278 | _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); | |
1279 | BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); | |
1280 | ||
1281 | for (i = 0; i < num; i++) | |
1282 | _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; | |
1283 | ||
1284 | for (i = 0; i < nump; i++) | |
1285 | _pnode_to_socket[i] = SOCK_EMPTY; | |
1286 | ||
7243e106 | 1287 | /* Fill in pnode/node/addr conversion list values: */ |
22ac2bca | 1288 | pr_info("UV: GAM Building socket/pnode conversion tables\n"); |
6e27b91c MT |
1289 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { |
1290 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) | |
1291 | continue; | |
1292 | i = gre->sockid - minsock; | |
7243e106 | 1293 | /* Duplicate: */ |
6e27b91c | 1294 | if (_socket_to_pnode[i] != SOCK_EMPTY) |
7243e106 | 1295 | continue; |
6e27b91c | 1296 | _socket_to_pnode[i] = gre->pnode; |
6e27b91c MT |
1297 | |
1298 | i = gre->pnode - minpnode; | |
1299 | _pnode_to_socket[i] = gre->sockid; | |
1300 | ||
7243e106 | 1301 | pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", |
6e27b91c MT |
1302 | gre->sockid, gre->type, gre->nasid, |
1303 | _socket_to_pnode[gre->sockid - minsock], | |
6e27b91c MT |
1304 | _pnode_to_socket[gre->pnode - minpnode]); |
1305 | } | |
1306 | ||
7243e106 | 1307 | /* Set socket -> node values: */ |
6e27b91c MT |
1308 | lnid = -1; |
1309 | for_each_present_cpu(cpu) { | |
1310 | int nid = cpu_to_node(cpu); | |
1311 | int apicid, sockid; | |
1312 | ||
1313 | if (lnid == nid) | |
1314 | continue; | |
1315 | lnid = nid; | |
1316 | apicid = per_cpu(x86_cpu_to_apicid, cpu); | |
1317 | sockid = apicid >> uv_cpuid.socketid_shift; | |
22ac2bca MT |
1318 | _socket_to_node[sockid - minsock] = nid; |
1319 | pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", | |
1320 | sockid, apicid, nid); | |
6e27b91c MT |
1321 | } |
1322 | ||
7243e106 | 1323 | /* Set up physical blade to pnode translation from GAM Range Table: */ |
6e27b91c MT |
1324 | bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); |
1325 | _node_to_pnode = kmalloc(bytes, GFP_KERNEL); | |
1326 | BUG_ON(!_node_to_pnode); | |
1327 | ||
1328 | for (lnid = 0; lnid < num_possible_nodes(); lnid++) { | |
1329 | unsigned short sockid; | |
1330 | ||
1331 | for (sockid = minsock; sockid <= maxsock; sockid++) { | |
1332 | if (lnid == _socket_to_node[sockid - minsock]) { | |
7243e106 | 1333 | _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock]; |
6e27b91c MT |
1334 | break; |
1335 | } | |
1336 | } | |
1337 | if (sockid > maxsock) { | |
1338 | pr_err("UV: socket for node %d not found!\n", lnid); | |
1339 | BUG(); | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | /* | |
1344 | * If socket id == pnode or socket id == node for all nodes, | |
1345 | * system runs faster by removing corresponding conversion table. | |
1346 | */ | |
1347 | pr_info("UV: Checking socket->node/pnode for identity maps\n"); | |
1348 | if (minsock == 0) { | |
1349 | for (i = 0; i < num; i++) | |
7243e106 | 1350 | if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i]) |
6e27b91c MT |
1351 | break; |
1352 | if (i >= num) { | |
1353 | kfree(_socket_to_node); | |
1354 | _socket_to_node = NULL; | |
1355 | pr_info("UV: 1:1 socket_to_node table removed\n"); | |
1356 | } | |
1357 | } | |
1358 | if (minsock == minpnode) { | |
1359 | for (i = 0; i < num; i++) | |
1360 | if (_socket_to_pnode[i] != SOCK_EMPTY && | |
1361 | _socket_to_pnode[i] != i + minpnode) | |
1362 | break; | |
1363 | if (i >= num) { | |
1364 | kfree(_socket_to_pnode); | |
1365 | _socket_to_pnode = NULL; | |
1366 | pr_info("UV: 1:1 socket_to_pnode table removed\n"); | |
1367 | } | |
1368 | } | |
1369 | } | |
1370 | ||
74862b03 | 1371 | static void __init uv_system_init_hub(void) |
c443c03d MT |
1372 | { |
1373 | struct uv_hub_info_s hub_info = {0}; | |
906f3b20 MT |
1374 | int bytes, cpu, nodeid; |
1375 | unsigned short min_pnode = 9999, max_pnode = 0; | |
a0ec83f3 MT |
1376 | char *hub = is_uv4_hub() ? "UV400" : |
1377 | is_uv3_hub() ? "UV300" : | |
1378 | is_uv2_hub() ? "UV2000/3000" : | |
1379 | is_uv1_hub() ? "UV100/1000" : NULL; | |
ac23d4ee | 1380 | |
1912c7af MT |
1381 | if (!hub) { |
1382 | pr_err("UV: Unknown/unsupported UV hub\n"); | |
1383 | return; | |
1384 | } | |
b15cc4a1 | 1385 | pr_info("UV: Found %s hub\n", hub); |
d394f2d9 | 1386 | |
3cd0b535 | 1387 | map_low_mmrs(); |
918bc960 | 1388 | |
7243e106 IM |
1389 | /* Get uv_systab for decoding: */ |
1390 | uv_bios_init(); | |
1391 | ||
1392 | /* If there's an UVsystab problem then abort UV init: */ | |
eee5715e | 1393 | if (decode_uv_systab() < 0) |
7243e106 IM |
1394 | return; |
1395 | ||
6e27b91c | 1396 | build_socket_tables(); |
c85375cd | 1397 | build_uv_gr_table(); |
c443c03d | 1398 | uv_init_hub_info(&hub_info); |
906f3b20 MT |
1399 | uv_possible_blades = num_possible_nodes(); |
1400 | if (!_node_to_pnode) | |
1401 | boot_init_possible_blades(&hub_info); | |
da517a08 | 1402 | |
7243e106 IM |
1403 | /* uv_num_possible_blades() is really the hub count: */ |
1404 | pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); | |
ac23d4ee | 1405 | |
7243e106 | 1406 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); |
c443c03d | 1407 | hub_info.coherency_domain_number = sn_coherency_id; |
7019cc2d RA |
1408 | uv_rtc_init(); |
1409 | ||
906f3b20 MT |
1410 | bytes = sizeof(void *) * uv_num_possible_blades(); |
1411 | __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); | |
1412 | BUG_ON(!__uv_hub_info_list); | |
39d30770 | 1413 | |
906f3b20 MT |
1414 | bytes = sizeof(struct uv_hub_info_s); |
1415 | for_each_node(nodeid) { | |
1416 | struct uv_hub_info_s *new_hub; | |
906f3b20 MT |
1417 | |
1418 | if (__uv_hub_info_list[nodeid]) { | |
7243e106 | 1419 | pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid); |
906f3b20 | 1420 | BUG(); |
3edcf2ff | 1421 | } |
9f5314fb | 1422 | |
906f3b20 | 1423 | /* Allocate new per hub info list */ |
7243e106 | 1424 | new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid); |
906f3b20 MT |
1425 | BUG_ON(!new_hub); |
1426 | __uv_hub_info_list[nodeid] = new_hub; | |
1427 | new_hub = uv_hub_info_list(nodeid); | |
1428 | BUG_ON(!new_hub); | |
1429 | *new_hub = hub_info; | |
1430 | ||
7243e106 | 1431 | /* Use information from GAM table if available: */ |
f68376fc DS |
1432 | if (_node_to_pnode) |
1433 | new_hub->pnode = _node_to_pnode[nodeid]; | |
7243e106 | 1434 | else /* Or fill in during CPU loop: */ |
f68376fc | 1435 | new_hub->pnode = 0xffff; |
7243e106 | 1436 | |
906f3b20 MT |
1437 | new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); |
1438 | new_hub->memory_nid = -1; | |
1439 | new_hub->nr_possible_cpus = 0; | |
1440 | new_hub->nr_online_cpus = 0; | |
1441 | } | |
6c7184b7 | 1442 | |
7243e106 | 1443 | /* Initialize per CPU info: */ |
906f3b20 MT |
1444 | for_each_possible_cpu(cpu) { |
1445 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); | |
f68376fc DS |
1446 | int numa_node_id; |
1447 | unsigned short pnode; | |
0045ddd2 | 1448 | |
906f3b20 | 1449 | nodeid = cpu_to_node(cpu); |
f68376fc DS |
1450 | numa_node_id = numa_cpu_node(cpu); |
1451 | pnode = uv_apicid_to_pnode(apicid); | |
1452 | ||
3edcf2ff | 1453 | uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); |
7243e106 | 1454 | uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; |
906f3b20 MT |
1455 | if (uv_cpu_hub_info(cpu)->memory_nid == -1) |
1456 | uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); | |
7243e106 IM |
1457 | |
1458 | /* Init memoryless node: */ | |
1459 | if (nodeid != numa_node_id && | |
f68376fc DS |
1460 | uv_hub_info_list(numa_node_id)->pnode == 0xffff) |
1461 | uv_hub_info_list(numa_node_id)->pnode = pnode; | |
1462 | else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) | |
1463 | uv_cpu_hub_info(cpu)->pnode = pnode; | |
7243e106 | 1464 | |
906f3b20 | 1465 | uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid); |
ac23d4ee | 1466 | } |
83f5d894 | 1467 | |
906f3b20 | 1468 | for_each_node(nodeid) { |
f68376fc DS |
1469 | unsigned short pnode = uv_hub_info_list(nodeid)->pnode; |
1470 | ||
7243e106 | 1471 | /* Add pnode info for pre-GAM list nodes without CPUs: */ |
f68376fc DS |
1472 | if (pnode == 0xffff) { |
1473 | unsigned long paddr; | |
1474 | ||
1475 | paddr = node_start_pfn(nodeid) << PAGE_SHIFT; | |
1476 | pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); | |
1477 | uv_hub_info_list(nodeid)->pnode = pnode; | |
1478 | } | |
1479 | min_pnode = min(pnode, min_pnode); | |
1480 | max_pnode = max(pnode, max_pnode); | |
906f3b20 MT |
1481 | pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", |
1482 | nodeid, | |
1483 | uv_hub_info_list(nodeid)->pnode, | |
1484 | uv_hub_info_list(nodeid)->nr_possible_cpus); | |
6a891a24 JS |
1485 | } |
1486 | ||
906f3b20 | 1487 | pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); |
83f5d894 | 1488 | map_gru_high(max_pnode); |
daf7b9c9 | 1489 | map_mmr_high(max_pnode); |
b15cc4a1 | 1490 | map_mmioh_high(min_pnode, max_pnode); |
ac23d4ee | 1491 | |
0d12ef0c | 1492 | uv_nmi_setup(); |
8da077d6 | 1493 | uv_cpu_init(); |
7f1baa06 | 1494 | uv_scir_register_cpu_notifier(); |
a3d732f9 | 1495 | proc_mkdir("sgi_uv", NULL); |
841582ea | 1496 | |
7243e106 | 1497 | /* Register Legacy VGA I/O redirection handler: */ |
841582ea | 1498 | pci_register_set_vga_state(uv_set_vga_state); |
818987e9 CW |
1499 | |
1500 | /* | |
1501 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
7243e106 | 1502 | * EFI is not enabled in the kdump kernel: |
818987e9 CW |
1503 | */ |
1504 | if (is_kdump_kernel()) | |
1505 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 1506 | } |
107e0e0c | 1507 | |
74862b03 | 1508 | /* |
1509 | * There is a small amount of UV specific code needed to initialize a | |
1510 | * UV system that does not have a "UV HUB" (referred to as "hubless"). | |
1511 | */ | |
1512 | void __init uv_system_init(void) | |
1513 | { | |
1514 | if (likely(!is_uv_system() && !is_uv_hubless())) | |
1515 | return; | |
1516 | ||
1517 | if (is_uv_system()) | |
1518 | uv_system_init_hub(); | |
abdf1df6 | 1519 | else |
1520 | uv_nmi_setup_hubless(); | |
74862b03 | 1521 | } |
1522 | ||
107e0e0c | 1523 | apic_driver(apic_x2apic_uv_x); |