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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
1da177e4 LT |
33 | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/mtrr.h> | |
37 | #include <asm/mpspec.h> | |
efa2559f | 38 | #include <asm/desc.h> |
773763df | 39 | #include <asm/arch_hooks.h> |
e83a5fdc | 40 | #include <asm/hpet.h> |
1da177e4 | 41 | #include <asm/pgalloc.h> |
773763df | 42 | #include <asm/i8253.h> |
75152114 | 43 | #include <asm/nmi.h> |
95833c83 | 44 | #include <asm/idle.h> |
73dea47f AK |
45 | #include <asm/proto.h> |
46 | #include <asm/timex.h> | |
2c8c0e6b | 47 | #include <asm/apic.h> |
6e1cb38a | 48 | #include <asm/i8259.h> |
1da177e4 | 49 | |
dd46e3ca | 50 | #include <mach_apic.h> |
773763df YL |
51 | #include <mach_apicdef.h> |
52 | #include <mach_ipi.h> | |
5af5573e | 53 | |
80e5609c CG |
54 | /* |
55 | * Sanity check | |
56 | */ | |
57 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
58 | # error SPURIOUS_APIC_VECTOR definition error | |
59 | #endif | |
60 | ||
b3c51170 YL |
61 | #ifdef CONFIG_X86_32 |
62 | /* | |
63 | * Knob to control our willingness to enable the local APIC. | |
64 | * | |
65 | * +1=force-enable | |
66 | */ | |
67 | static int force_enable_local_apic; | |
68 | /* | |
69 | * APIC command line parameters | |
70 | */ | |
71 | static int __init parse_lapic(char *arg) | |
72 | { | |
73 | force_enable_local_apic = 1; | |
74 | return 0; | |
75 | } | |
76 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
77 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
78 | static int enabled_via_apicbase; | |
79 | ||
b3c51170 YL |
80 | #endif |
81 | ||
82 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 83 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
84 | static __init int setup_apicpmtimer(char *s) |
85 | { | |
86 | apic_calibrate_pmtmr = 1; | |
87 | notsc_setup(NULL); | |
88 | return 0; | |
89 | } | |
90 | __setup("apicpmtimer", setup_apicpmtimer); | |
91 | #endif | |
92 | ||
49899eac YL |
93 | #ifdef CONFIG_X86_64 |
94 | #define HAVE_X2APIC | |
95 | #endif | |
96 | ||
97 | #ifdef HAVE_X2APIC | |
89027d35 | 98 | int x2apic; |
6e1cb38a SS |
99 | /* x2apic enabled before OS handover */ |
100 | int x2apic_preenabled; | |
49899eac YL |
101 | int disable_x2apic; |
102 | static __init int setup_nox2apic(char *str) | |
103 | { | |
104 | disable_x2apic = 1; | |
105 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
106 | return 0; | |
107 | } | |
108 | early_param("nox2apic", setup_nox2apic); | |
109 | #endif | |
1da177e4 | 110 | |
b3c51170 YL |
111 | unsigned long mp_lapic_addr; |
112 | int disable_apic; | |
113 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
114 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 115 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
116 | int local_apic_timer_c2_ok; |
117 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
118 | ||
efa2559f YL |
119 | int first_system_vector = 0xfe; |
120 | ||
121 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
122 | ||
e83a5fdc HS |
123 | /* |
124 | * Debug level, exported for io_apic.c | |
125 | */ | |
baa13188 | 126 | unsigned int apic_verbosity; |
e83a5fdc | 127 | |
89c38c28 CG |
128 | int pic_mode; |
129 | ||
bab4b27c AS |
130 | /* Have we found an MP table */ |
131 | int smp_found_config; | |
132 | ||
39928722 AD |
133 | static struct resource lapic_resource = { |
134 | .name = "Local APIC", | |
135 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
136 | }; | |
137 | ||
d03030e9 TG |
138 | static unsigned int calibration_result; |
139 | ||
ba7eda4c TG |
140 | static int lapic_next_event(unsigned long delta, |
141 | struct clock_event_device *evt); | |
142 | static void lapic_timer_setup(enum clock_event_mode mode, | |
143 | struct clock_event_device *evt); | |
e7986739 | 144 | static void lapic_timer_broadcast(const cpumask_t *mask); |
0e078e2f | 145 | static void apic_pm_activate(void); |
ba7eda4c | 146 | |
274cfe59 CG |
147 | /* |
148 | * The local apic timer can be used for any function which is CPU local. | |
149 | */ | |
ba7eda4c TG |
150 | static struct clock_event_device lapic_clockevent = { |
151 | .name = "lapic", | |
152 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
153 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
154 | .shift = 32, | |
155 | .set_mode = lapic_timer_setup, | |
156 | .set_next_event = lapic_next_event, | |
157 | .broadcast = lapic_timer_broadcast, | |
158 | .rating = 100, | |
159 | .irq = -1, | |
160 | }; | |
161 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
162 | ||
d3432896 AK |
163 | static unsigned long apic_phys; |
164 | ||
0e078e2f TG |
165 | /* |
166 | * Get the LAPIC version | |
167 | */ | |
168 | static inline int lapic_get_version(void) | |
ba7eda4c | 169 | { |
0e078e2f | 170 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
171 | } |
172 | ||
0e078e2f | 173 | /* |
9c803869 | 174 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
175 | */ |
176 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 177 | { |
9c803869 | 178 | #ifdef CONFIG_X86_64 |
0e078e2f | 179 | return 1; |
9c803869 CG |
180 | #else |
181 | return APIC_INTEGRATED(lapic_get_version()); | |
182 | #endif | |
ba7eda4c TG |
183 | } |
184 | ||
185 | /* | |
0e078e2f | 186 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 187 | */ |
0e078e2f | 188 | static int modern_apic(void) |
ba7eda4c | 189 | { |
0e078e2f TG |
190 | /* AMD systems use old APIC versions, so check the CPU */ |
191 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
192 | boot_cpu_data.x86 >= 0xf) | |
193 | return 1; | |
194 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
195 | } |
196 | ||
274cfe59 CG |
197 | /* |
198 | * Paravirt kernels also might be using these below ops. So we still | |
199 | * use generic apic_read()/apic_write(), which might be pointing to different | |
200 | * ops in PARAVIRT case. | |
201 | */ | |
1b374e4d | 202 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
203 | { |
204 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
205 | cpu_relax(); | |
206 | } | |
207 | ||
1b374e4d | 208 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 209 | { |
3c6bb07a | 210 | u32 send_status; |
8339e9fb FLV |
211 | int timeout; |
212 | ||
213 | timeout = 0; | |
214 | do { | |
215 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
216 | if (!send_status) | |
217 | break; | |
218 | udelay(100); | |
219 | } while (timeout++ < 1000); | |
220 | ||
221 | return send_status; | |
222 | } | |
223 | ||
1b374e4d SS |
224 | void xapic_icr_write(u32 low, u32 id) |
225 | { | |
ed4e5ec1 | 226 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
227 | apic_write(APIC_ICR, low); |
228 | } | |
229 | ||
230 | u64 xapic_icr_read(void) | |
231 | { | |
232 | u32 icr1, icr2; | |
233 | ||
234 | icr2 = apic_read(APIC_ICR2); | |
235 | icr1 = apic_read(APIC_ICR); | |
236 | ||
cf9768d7 | 237 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
238 | } |
239 | ||
240 | static struct apic_ops xapic_ops = { | |
241 | .read = native_apic_mem_read, | |
242 | .write = native_apic_mem_write, | |
1b374e4d SS |
243 | .icr_read = xapic_icr_read, |
244 | .icr_write = xapic_icr_write, | |
245 | .wait_icr_idle = xapic_wait_icr_idle, | |
246 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
247 | }; | |
248 | ||
249 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
250 | EXPORT_SYMBOL_GPL(apic_ops); |
251 | ||
49899eac | 252 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
253 | static void x2apic_wait_icr_idle(void) |
254 | { | |
255 | /* no need to wait for icr idle in x2apic */ | |
256 | return; | |
257 | } | |
258 | ||
259 | static u32 safe_x2apic_wait_icr_idle(void) | |
260 | { | |
261 | /* no need to wait for icr idle in x2apic */ | |
262 | return 0; | |
263 | } | |
264 | ||
265 | void x2apic_icr_write(u32 low, u32 id) | |
266 | { | |
267 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
268 | } | |
269 | ||
270 | u64 x2apic_icr_read(void) | |
271 | { | |
272 | unsigned long val; | |
273 | ||
274 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
275 | return val; | |
276 | } | |
277 | ||
278 | static struct apic_ops x2apic_ops = { | |
279 | .read = native_apic_msr_read, | |
280 | .write = native_apic_msr_write, | |
13c88fb5 SS |
281 | .icr_read = x2apic_icr_read, |
282 | .icr_write = x2apic_icr_write, | |
283 | .wait_icr_idle = x2apic_wait_icr_idle, | |
284 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
285 | }; | |
49899eac | 286 | #endif |
13c88fb5 | 287 | |
0e078e2f TG |
288 | /** |
289 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
290 | */ | |
e9427101 | 291 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 292 | { |
11a8e778 | 293 | unsigned int v; |
6935d1f9 TG |
294 | |
295 | /* unmask and set to NMI */ | |
296 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
297 | |
298 | /* Level triggered for 82489DX (32bit mode) */ | |
299 | if (!lapic_is_integrated()) | |
300 | v |= APIC_LVT_LEVEL_TRIGGER; | |
301 | ||
11a8e778 | 302 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
303 | } |
304 | ||
7c37e48b CG |
305 | #ifdef CONFIG_X86_32 |
306 | /** | |
307 | * get_physical_broadcast - Get number of physical broadcast IDs | |
308 | */ | |
309 | int get_physical_broadcast(void) | |
310 | { | |
311 | return modern_apic() ? 0xff : 0xf; | |
312 | } | |
313 | #endif | |
314 | ||
0e078e2f TG |
315 | /** |
316 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
317 | */ | |
37e650c7 | 318 | int lapic_get_maxlvt(void) |
1da177e4 | 319 | { |
36a028de | 320 | unsigned int v; |
1da177e4 LT |
321 | |
322 | v = apic_read(APIC_LVR); | |
36a028de CG |
323 | /* |
324 | * - we always have APIC integrated on 64bit mode | |
325 | * - 82489DXs do not report # of LVT entries | |
326 | */ | |
327 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
328 | } |
329 | ||
274cfe59 CG |
330 | /* |
331 | * Local APIC timer | |
332 | */ | |
333 | ||
c40aaec6 | 334 | /* Clock divisor */ |
c40aaec6 | 335 | #define APIC_DIVISOR 16 |
f07f4f90 | 336 | |
0e078e2f TG |
337 | /* |
338 | * This function sets up the local APIC timer, with a timeout of | |
339 | * 'clocks' APIC bus clock. During calibration we actually call | |
340 | * this function twice on the boot CPU, once with a bogus timeout | |
341 | * value, second time for real. The other (noncalibrating) CPUs | |
342 | * call this function only once, with the real, calibrated value. | |
343 | * | |
344 | * We do reads before writes even if unnecessary, to get around the | |
345 | * P5 APIC double write bug. | |
346 | */ | |
0e078e2f | 347 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 348 | { |
0e078e2f | 349 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 350 | |
0e078e2f TG |
351 | lvtt_value = LOCAL_TIMER_VECTOR; |
352 | if (!oneshot) | |
353 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
354 | if (!lapic_is_integrated()) |
355 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
356 | ||
0e078e2f TG |
357 | if (!irqen) |
358 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 359 | |
0e078e2f | 360 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
361 | |
362 | /* | |
0e078e2f | 363 | * Divide PICLK by 16 |
1da177e4 | 364 | */ |
0e078e2f | 365 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
366 | apic_write(APIC_TDCR, |
367 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
368 | APIC_TDR_DIV_16); | |
0e078e2f TG |
369 | |
370 | if (!oneshot) | |
f07f4f90 | 371 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
372 | } |
373 | ||
0e078e2f | 374 | /* |
7b83dae7 RR |
375 | * Setup extended LVT, AMD specific (K8, family 10h) |
376 | * | |
377 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
378 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
379 | * |
380 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
381 | * enables the vector. See also the BKDGs. | |
0e078e2f | 382 | */ |
7b83dae7 RR |
383 | |
384 | #define APIC_EILVT_LVTOFF_MCE 0 | |
385 | #define APIC_EILVT_LVTOFF_IBS 1 | |
386 | ||
387 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 388 | { |
7b83dae7 | 389 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 390 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 391 | |
0e078e2f | 392 | apic_write(reg, v); |
1da177e4 LT |
393 | } |
394 | ||
7b83dae7 RR |
395 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
396 | { | |
397 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
398 | return APIC_EILVT_LVTOFF_MCE; | |
399 | } | |
400 | ||
401 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
402 | { | |
403 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
404 | return APIC_EILVT_LVTOFF_IBS; | |
405 | } | |
6aa360e6 | 406 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 407 | |
0e078e2f TG |
408 | /* |
409 | * Program the next event, relative to now | |
410 | */ | |
411 | static int lapic_next_event(unsigned long delta, | |
412 | struct clock_event_device *evt) | |
1da177e4 | 413 | { |
0e078e2f TG |
414 | apic_write(APIC_TMICT, delta); |
415 | return 0; | |
1da177e4 LT |
416 | } |
417 | ||
0e078e2f TG |
418 | /* |
419 | * Setup the lapic timer in periodic or oneshot mode | |
420 | */ | |
421 | static void lapic_timer_setup(enum clock_event_mode mode, | |
422 | struct clock_event_device *evt) | |
9b7711f0 HS |
423 | { |
424 | unsigned long flags; | |
0e078e2f | 425 | unsigned int v; |
9b7711f0 | 426 | |
0e078e2f TG |
427 | /* Lapic used as dummy for broadcast ? */ |
428 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
429 | return; |
430 | ||
431 | local_irq_save(flags); | |
432 | ||
0e078e2f TG |
433 | switch (mode) { |
434 | case CLOCK_EVT_MODE_PERIODIC: | |
435 | case CLOCK_EVT_MODE_ONESHOT: | |
436 | __setup_APIC_LVTT(calibration_result, | |
437 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
438 | break; | |
439 | case CLOCK_EVT_MODE_UNUSED: | |
440 | case CLOCK_EVT_MODE_SHUTDOWN: | |
441 | v = apic_read(APIC_LVTT); | |
442 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
443 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 444 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
445 | break; |
446 | case CLOCK_EVT_MODE_RESUME: | |
447 | /* Nothing to do here */ | |
448 | break; | |
449 | } | |
9b7711f0 HS |
450 | |
451 | local_irq_restore(flags); | |
452 | } | |
453 | ||
1da177e4 | 454 | /* |
0e078e2f | 455 | * Local APIC timer broadcast function |
1da177e4 | 456 | */ |
e7986739 | 457 | static void lapic_timer_broadcast(const cpumask_t *mask) |
1da177e4 | 458 | { |
0e078e2f | 459 | #ifdef CONFIG_SMP |
e7986739 | 460 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
461 | #endif |
462 | } | |
1da177e4 | 463 | |
0e078e2f TG |
464 | /* |
465 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
466 | * of the boot CPU and register the clock event in the framework. | |
467 | */ | |
db4b5525 | 468 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
469 | { |
470 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 471 | |
0e078e2f | 472 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 473 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 474 | |
0e078e2f TG |
475 | clockevents_register_device(levt); |
476 | } | |
1da177e4 | 477 | |
2f04fa88 YL |
478 | /* |
479 | * In this functions we calibrate APIC bus clocks to the external timer. | |
480 | * | |
481 | * We want to do the calibration only once since we want to have local timer | |
482 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
483 | * frequency. | |
484 | * | |
485 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
486 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
487 | * readout is broken, so it never gets out of the wait loop again. This was | |
488 | * also reported by others. | |
489 | * | |
490 | * Monitoring the jiffies value is inaccurate and the clockevents | |
491 | * infrastructure allows us to do a simple substitution of the interrupt | |
492 | * handler. | |
493 | * | |
494 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
495 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
496 | * back to normal later in the boot process). | |
497 | */ | |
498 | ||
499 | #define LAPIC_CAL_LOOPS (HZ/10) | |
500 | ||
501 | static __initdata int lapic_cal_loops = -1; | |
502 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
503 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
504 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
505 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
506 | ||
507 | /* | |
508 | * Temporary interrupt handler. | |
509 | */ | |
510 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
511 | { | |
512 | unsigned long long tsc = 0; | |
513 | long tapic = apic_read(APIC_TMCCT); | |
514 | unsigned long pm = acpi_pm_read_early(); | |
515 | ||
516 | if (cpu_has_tsc) | |
517 | rdtscll(tsc); | |
518 | ||
519 | switch (lapic_cal_loops++) { | |
520 | case 0: | |
521 | lapic_cal_t1 = tapic; | |
522 | lapic_cal_tsc1 = tsc; | |
523 | lapic_cal_pm1 = pm; | |
524 | lapic_cal_j1 = jiffies; | |
525 | break; | |
526 | ||
527 | case LAPIC_CAL_LOOPS: | |
528 | lapic_cal_t2 = tapic; | |
529 | lapic_cal_tsc2 = tsc; | |
530 | if (pm < lapic_cal_pm1) | |
531 | pm += ACPI_PM_OVRRUN; | |
532 | lapic_cal_pm2 = pm; | |
533 | lapic_cal_j2 = jiffies; | |
534 | break; | |
535 | } | |
536 | } | |
537 | ||
b189892d CG |
538 | static int __init calibrate_by_pmtimer(long deltapm, long *delta) |
539 | { | |
540 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
541 | const long pm_thresh = pm_100ms / 100; | |
542 | unsigned long mult; | |
543 | u64 res; | |
544 | ||
545 | #ifndef CONFIG_X86_PM_TIMER | |
546 | return -1; | |
547 | #endif | |
548 | ||
549 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
550 | ||
551 | /* Check, if the PM timer is available */ | |
552 | if (!deltapm) | |
553 | return -1; | |
554 | ||
555 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
556 | ||
557 | if (deltapm > (pm_100ms - pm_thresh) && | |
558 | deltapm < (pm_100ms + pm_thresh)) { | |
559 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
560 | } else { | |
561 | res = (((u64)deltapm) * mult) >> 22; | |
562 | do_div(res, 1000000); | |
ba21ebb6 | 563 | pr_warning("APIC calibration not consistent " |
b189892d CG |
564 | "with PM Timer: %ldms instead of 100ms\n", |
565 | (long)res); | |
566 | /* Correct the lapic counter value */ | |
567 | res = (((u64)(*delta)) * pm_100ms); | |
568 | do_div(res, deltapm); | |
ba21ebb6 | 569 | pr_info("APIC delta adjusted to PM-Timer: " |
b189892d CG |
570 | "%lu (%ld)\n", (unsigned long)res, *delta); |
571 | *delta = (long)res; | |
572 | } | |
573 | ||
574 | return 0; | |
575 | } | |
576 | ||
2f04fa88 YL |
577 | static int __init calibrate_APIC_clock(void) |
578 | { | |
579 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
580 | void (*real_handler)(struct clock_event_device *dev); |
581 | unsigned long deltaj; | |
b189892d | 582 | long delta; |
2f04fa88 YL |
583 | int pm_referenced = 0; |
584 | ||
585 | local_irq_disable(); | |
586 | ||
587 | /* Replace the global interrupt handler */ | |
588 | real_handler = global_clock_event->event_handler; | |
589 | global_clock_event->event_handler = lapic_cal_handler; | |
590 | ||
591 | /* | |
81608f3c | 592 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
593 | * can underflow in the 100ms detection time frame |
594 | */ | |
81608f3c | 595 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
596 | |
597 | /* Let the interrupts run */ | |
598 | local_irq_enable(); | |
599 | ||
600 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
601 | cpu_relax(); | |
602 | ||
603 | local_irq_disable(); | |
604 | ||
605 | /* Restore the real event handler */ | |
606 | global_clock_event->event_handler = real_handler; | |
607 | ||
608 | /* Build delta t1-t2 as apic timer counts down */ | |
609 | delta = lapic_cal_t1 - lapic_cal_t2; | |
610 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
611 | ||
b189892d CG |
612 | /* we trust the PM based calibration if possible */ |
613 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
614 | &delta); | |
2f04fa88 YL |
615 | |
616 | /* Calculate the scaled math multiplication factor */ | |
617 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
618 | lapic_clockevent.shift); | |
619 | lapic_clockevent.max_delta_ns = | |
620 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
621 | lapic_clockevent.min_delta_ns = | |
622 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
623 | ||
624 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
625 | ||
626 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
627 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
628 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
629 | calibration_result); | |
630 | ||
631 | if (cpu_has_tsc) { | |
632 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
633 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
634 | "%ld.%04ld MHz.\n", | |
635 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
636 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
637 | } | |
638 | ||
639 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
640 | "%u.%04u MHz.\n", | |
641 | calibration_result / (1000000 / HZ), | |
642 | calibration_result % (1000000 / HZ)); | |
643 | ||
644 | /* | |
645 | * Do a sanity check on the APIC calibration result | |
646 | */ | |
647 | if (calibration_result < (1000000 / HZ)) { | |
648 | local_irq_enable(); | |
ba21ebb6 | 649 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
650 | return -1; |
651 | } | |
652 | ||
653 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
654 | ||
b189892d CG |
655 | /* |
656 | * PM timer calibration failed or not turned on | |
657 | * so lets try APIC timer based calibration | |
658 | */ | |
2f04fa88 YL |
659 | if (!pm_referenced) { |
660 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
661 | ||
662 | /* | |
663 | * Setup the apic timer manually | |
664 | */ | |
665 | levt->event_handler = lapic_cal_handler; | |
666 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
667 | lapic_cal_loops = -1; | |
668 | ||
669 | /* Let the interrupts run */ | |
670 | local_irq_enable(); | |
671 | ||
672 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
673 | cpu_relax(); | |
674 | ||
2f04fa88 YL |
675 | /* Stop the lapic timer */ |
676 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
677 | ||
2f04fa88 YL |
678 | /* Jiffies delta */ |
679 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
680 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
681 | ||
682 | /* Check, if the jiffies result is consistent */ | |
683 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
684 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
685 | else | |
686 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
687 | } else | |
688 | local_irq_enable(); | |
689 | ||
690 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
ba21ebb6 | 691 | pr_warning("APIC timer disabled due to verification failure.\n"); |
2f04fa88 YL |
692 | return -1; |
693 | } | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
e83a5fdc HS |
698 | /* |
699 | * Setup the boot APIC | |
700 | * | |
701 | * Calibrate and verify the result. | |
702 | */ | |
0e078e2f TG |
703 | void __init setup_boot_APIC_clock(void) |
704 | { | |
705 | /* | |
274cfe59 CG |
706 | * The local apic timer can be disabled via the kernel |
707 | * commandline or from the CPU detection code. Register the lapic | |
708 | * timer as a dummy clock event source on SMP systems, so the | |
709 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
710 | */ |
711 | if (disable_apic_timer) { | |
ba21ebb6 | 712 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 713 | /* No broadcast on UP ! */ |
9d09951d TG |
714 | if (num_possible_cpus() > 1) { |
715 | lapic_clockevent.mult = 1; | |
0e078e2f | 716 | setup_APIC_timer(); |
9d09951d | 717 | } |
0e078e2f TG |
718 | return; |
719 | } | |
720 | ||
274cfe59 CG |
721 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
722 | "calibrating APIC timer ...\n"); | |
723 | ||
89b3b1f4 | 724 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
725 | /* No broadcast on UP ! */ |
726 | if (num_possible_cpus() > 1) | |
727 | setup_APIC_timer(); | |
728 | return; | |
729 | } | |
730 | ||
0e078e2f TG |
731 | /* |
732 | * If nmi_watchdog is set to IO_APIC, we need the | |
733 | * PIT/HPET going. Otherwise register lapic as a dummy | |
734 | * device. | |
735 | */ | |
736 | if (nmi_watchdog != NMI_IO_APIC) | |
737 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
738 | else | |
ba21ebb6 | 739 | pr_warning("APIC timer registered as dummy," |
116f570e | 740 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 741 | |
274cfe59 | 742 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
743 | setup_APIC_timer(); |
744 | } | |
745 | ||
0e078e2f TG |
746 | void __cpuinit setup_secondary_APIC_clock(void) |
747 | { | |
0e078e2f TG |
748 | setup_APIC_timer(); |
749 | } | |
750 | ||
751 | /* | |
752 | * The guts of the apic timer interrupt | |
753 | */ | |
754 | static void local_apic_timer_interrupt(void) | |
755 | { | |
756 | int cpu = smp_processor_id(); | |
757 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
758 | ||
759 | /* | |
760 | * Normally we should not be here till LAPIC has been initialized but | |
761 | * in some cases like kdump, its possible that there is a pending LAPIC | |
762 | * timer interrupt from previous kernel's context and is delivered in | |
763 | * new kernel the moment interrupts are enabled. | |
764 | * | |
765 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
766 | * its possible that when we get here evt->event_handler is NULL. | |
767 | * Check for event_handler being NULL and discard the interrupt as | |
768 | * spurious. | |
769 | */ | |
770 | if (!evt->event_handler) { | |
ba21ebb6 | 771 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
772 | /* Switch it off */ |
773 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
774 | return; | |
775 | } | |
776 | ||
777 | /* | |
778 | * the NMI deadlock-detector uses this. | |
779 | */ | |
0b23e8cf | 780 | #ifdef CONFIG_X86_64 |
0e078e2f | 781 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
782 | #else |
783 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
784 | #endif | |
0e078e2f TG |
785 | |
786 | evt->event_handler(evt); | |
787 | } | |
788 | ||
789 | /* | |
790 | * Local APIC timer interrupt. This is the most natural way for doing | |
791 | * local interrupts, but local timer interrupts can be emulated by | |
792 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
793 | * | |
794 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
795 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
796 | */ | |
797 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
798 | { | |
799 | struct pt_regs *old_regs = set_irq_regs(regs); | |
800 | ||
801 | /* | |
802 | * NOTE! We'd better ACK the irq immediately, | |
803 | * because timer handling can be slow. | |
804 | */ | |
805 | ack_APIC_irq(); | |
806 | /* | |
807 | * update_process_times() expects us to have done irq_enter(). | |
808 | * Besides, if we don't timer interrupts ignore the global | |
809 | * interrupt lock, which is the WrongThing (tm) to do. | |
810 | */ | |
6460bc73 | 811 | #ifdef CONFIG_X86_64 |
0e078e2f | 812 | exit_idle(); |
6460bc73 | 813 | #endif |
0e078e2f TG |
814 | irq_enter(); |
815 | local_apic_timer_interrupt(); | |
816 | irq_exit(); | |
274cfe59 | 817 | |
0e078e2f TG |
818 | set_irq_regs(old_regs); |
819 | } | |
820 | ||
821 | int setup_profiling_timer(unsigned int multiplier) | |
822 | { | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
0e078e2f TG |
826 | /* |
827 | * Local APIC start and shutdown | |
828 | */ | |
829 | ||
830 | /** | |
831 | * clear_local_APIC - shutdown the local APIC | |
832 | * | |
833 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
834 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
835 | * leftovers during boot. | |
836 | */ | |
837 | void clear_local_APIC(void) | |
838 | { | |
2584a82d | 839 | int maxlvt; |
0e078e2f TG |
840 | u32 v; |
841 | ||
d3432896 AK |
842 | /* APIC hasn't been mapped yet */ |
843 | if (!apic_phys) | |
844 | return; | |
845 | ||
846 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
847 | /* |
848 | * Masking an LVT entry can trigger a local APIC error | |
849 | * if the vector is zero. Mask LVTERR first to prevent this. | |
850 | */ | |
851 | if (maxlvt >= 3) { | |
852 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
853 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
854 | } | |
855 | /* | |
856 | * Careful: we have to set masks only first to deassert | |
857 | * any level-triggered sources. | |
858 | */ | |
859 | v = apic_read(APIC_LVTT); | |
860 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
861 | v = apic_read(APIC_LVT0); | |
862 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
863 | v = apic_read(APIC_LVT1); | |
864 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
865 | if (maxlvt >= 4) { | |
866 | v = apic_read(APIC_LVTPC); | |
867 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
868 | } | |
869 | ||
6764014b CG |
870 | /* lets not touch this if we didn't frob it */ |
871 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
872 | if (maxlvt >= 5) { | |
873 | v = apic_read(APIC_LVTTHMR); | |
874 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
875 | } | |
876 | #endif | |
0e078e2f TG |
877 | /* |
878 | * Clean APIC state for other OSs: | |
879 | */ | |
880 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
881 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
882 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
883 | if (maxlvt >= 3) | |
884 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
885 | if (maxlvt >= 4) | |
886 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
887 | |
888 | /* Integrated APIC (!82489DX) ? */ | |
889 | if (lapic_is_integrated()) { | |
890 | if (maxlvt > 3) | |
891 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
892 | apic_write(APIC_ESR, 0); | |
893 | apic_read(APIC_ESR); | |
894 | } | |
0e078e2f TG |
895 | } |
896 | ||
897 | /** | |
898 | * disable_local_APIC - clear and disable the local APIC | |
899 | */ | |
900 | void disable_local_APIC(void) | |
901 | { | |
902 | unsigned int value; | |
903 | ||
904 | clear_local_APIC(); | |
905 | ||
906 | /* | |
907 | * Disable APIC (implies clearing of registers | |
908 | * for 82489DX!). | |
909 | */ | |
910 | value = apic_read(APIC_SPIV); | |
911 | value &= ~APIC_SPIV_APIC_ENABLED; | |
912 | apic_write(APIC_SPIV, value); | |
990b183e CG |
913 | |
914 | #ifdef CONFIG_X86_32 | |
915 | /* | |
916 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
917 | * restore the disabled state. | |
918 | */ | |
919 | if (enabled_via_apicbase) { | |
920 | unsigned int l, h; | |
921 | ||
922 | rdmsr(MSR_IA32_APICBASE, l, h); | |
923 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
924 | wrmsr(MSR_IA32_APICBASE, l, h); | |
925 | } | |
926 | #endif | |
0e078e2f TG |
927 | } |
928 | ||
fe4024dc CG |
929 | /* |
930 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
931 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
932 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
933 | * for the case where Linux didn't enable the LAPIC. | |
934 | */ | |
0e078e2f TG |
935 | void lapic_shutdown(void) |
936 | { | |
937 | unsigned long flags; | |
938 | ||
939 | if (!cpu_has_apic) | |
940 | return; | |
941 | ||
942 | local_irq_save(flags); | |
943 | ||
fe4024dc CG |
944 | #ifdef CONFIG_X86_32 |
945 | if (!enabled_via_apicbase) | |
946 | clear_local_APIC(); | |
947 | else | |
948 | #endif | |
949 | disable_local_APIC(); | |
950 | ||
0e078e2f TG |
951 | |
952 | local_irq_restore(flags); | |
953 | } | |
954 | ||
955 | /* | |
956 | * This is to verify that we're looking at a real local APIC. | |
957 | * Check these against your board if the CPUs aren't getting | |
958 | * started for no apparent reason. | |
959 | */ | |
960 | int __init verify_local_APIC(void) | |
961 | { | |
962 | unsigned int reg0, reg1; | |
963 | ||
964 | /* | |
965 | * The version register is read-only in a real APIC. | |
966 | */ | |
967 | reg0 = apic_read(APIC_LVR); | |
968 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
969 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
970 | reg1 = apic_read(APIC_LVR); | |
971 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
972 | ||
973 | /* | |
974 | * The two version reads above should print the same | |
975 | * numbers. If the second one is different, then we | |
976 | * poke at a non-APIC. | |
977 | */ | |
978 | if (reg1 != reg0) | |
979 | return 0; | |
980 | ||
981 | /* | |
982 | * Check if the version looks reasonably. | |
983 | */ | |
984 | reg1 = GET_APIC_VERSION(reg0); | |
985 | if (reg1 == 0x00 || reg1 == 0xff) | |
986 | return 0; | |
987 | reg1 = lapic_get_maxlvt(); | |
988 | if (reg1 < 0x02 || reg1 == 0xff) | |
989 | return 0; | |
990 | ||
991 | /* | |
992 | * The ID register is read/write in a real APIC. | |
993 | */ | |
2d7a66d0 | 994 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
995 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
996 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 997 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
998 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
999 | apic_write(APIC_ID, reg0); | |
1000 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
1001 | return 0; | |
1002 | ||
1003 | /* | |
1da177e4 LT |
1004 | * The next two are just to see if we have sane values. |
1005 | * They're only really relevant if we're in Virtual Wire | |
1006 | * compatibility mode, but most boxes are anymore. | |
1007 | */ | |
1008 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1009 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1010 | reg1 = apic_read(APIC_LVT1); |
1011 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1012 | ||
1013 | return 1; | |
1014 | } | |
1015 | ||
0e078e2f TG |
1016 | /** |
1017 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1018 | */ | |
1da177e4 LT |
1019 | void __init sync_Arb_IDs(void) |
1020 | { | |
296cb951 CG |
1021 | /* |
1022 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1023 | * needed on AMD. | |
1024 | */ | |
1025 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1026 | return; |
1027 | ||
1028 | /* | |
1029 | * Wait for idle. | |
1030 | */ | |
1031 | apic_wait_icr_idle(); | |
1032 | ||
1033 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1034 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1035 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1036 | } |
1037 | ||
1da177e4 LT |
1038 | /* |
1039 | * An initial setup of the virtual wire mode. | |
1040 | */ | |
1041 | void __init init_bsp_APIC(void) | |
1042 | { | |
11a8e778 | 1043 | unsigned int value; |
1da177e4 LT |
1044 | |
1045 | /* | |
1046 | * Don't do the setup now if we have a SMP BIOS as the | |
1047 | * through-I/O-APIC virtual wire mode might be active. | |
1048 | */ | |
1049 | if (smp_found_config || !cpu_has_apic) | |
1050 | return; | |
1051 | ||
1da177e4 LT |
1052 | /* |
1053 | * Do not trust the local APIC being empty at bootup. | |
1054 | */ | |
1055 | clear_local_APIC(); | |
1056 | ||
1057 | /* | |
1058 | * Enable APIC. | |
1059 | */ | |
1060 | value = apic_read(APIC_SPIV); | |
1061 | value &= ~APIC_VECTOR_MASK; | |
1062 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1063 | |
1064 | #ifdef CONFIG_X86_32 | |
1065 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1066 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1067 | (boot_cpu_data.x86 == 15)) | |
1068 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1069 | else | |
1070 | #endif | |
1071 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1072 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1073 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1074 | |
1075 | /* | |
1076 | * Set up the virtual wire mode. | |
1077 | */ | |
11a8e778 | 1078 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1079 | value = APIC_DM_NMI; |
638c0411 CG |
1080 | if (!lapic_is_integrated()) /* 82489DX */ |
1081 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1082 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1083 | } |
1084 | ||
c43da2f5 CG |
1085 | static void __cpuinit lapic_setup_esr(void) |
1086 | { | |
9df08f10 CG |
1087 | unsigned int oldvalue, value, maxlvt; |
1088 | ||
1089 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1090 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1091 | return; |
1092 | } | |
c43da2f5 | 1093 | |
9df08f10 | 1094 | if (esr_disable) { |
c43da2f5 | 1095 | /* |
9df08f10 CG |
1096 | * Something untraceable is creating bad interrupts on |
1097 | * secondary quads ... for the moment, just leave the | |
1098 | * ESR disabled - we can't do anything useful with the | |
1099 | * errors anyway - mbligh | |
c43da2f5 | 1100 | */ |
ba21ebb6 | 1101 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1102 | return; |
c43da2f5 | 1103 | } |
9df08f10 CG |
1104 | |
1105 | maxlvt = lapic_get_maxlvt(); | |
1106 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1107 | apic_write(APIC_ESR, 0); | |
1108 | oldvalue = apic_read(APIC_ESR); | |
1109 | ||
1110 | /* enables sending errors */ | |
1111 | value = ERROR_APIC_VECTOR; | |
1112 | apic_write(APIC_LVTERR, value); | |
1113 | ||
1114 | /* | |
1115 | * spec says clear errors after enabling vector. | |
1116 | */ | |
1117 | if (maxlvt > 3) | |
1118 | apic_write(APIC_ESR, 0); | |
1119 | value = apic_read(APIC_ESR); | |
1120 | if (value != oldvalue) | |
1121 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1122 | "vector: 0x%08x after: 0x%08x\n", | |
1123 | oldvalue, value); | |
c43da2f5 CG |
1124 | } |
1125 | ||
1126 | ||
0e078e2f TG |
1127 | /** |
1128 | * setup_local_APIC - setup the local APIC | |
1129 | */ | |
1130 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1131 | { |
739f33b3 | 1132 | unsigned int value; |
da7ed9f9 | 1133 | int i, j; |
1da177e4 | 1134 | |
89c38c28 CG |
1135 | #ifdef CONFIG_X86_32 |
1136 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08ad776e | 1137 | if (lapic_is_integrated() && esr_disable) { |
89c38c28 CG |
1138 | apic_write(APIC_ESR, 0); |
1139 | apic_write(APIC_ESR, 0); | |
1140 | apic_write(APIC_ESR, 0); | |
1141 | apic_write(APIC_ESR, 0); | |
1142 | } | |
1143 | #endif | |
1144 | ||
ac23d4ee | 1145 | preempt_disable(); |
1da177e4 | 1146 | |
1da177e4 LT |
1147 | /* |
1148 | * Double-check whether this APIC is really registered. | |
1149 | * This is meaningless in clustered apic mode, so we skip it. | |
1150 | */ | |
1151 | if (!apic_id_registered()) | |
1152 | BUG(); | |
1153 | ||
1154 | /* | |
1155 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1156 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1157 | * document number 292116). So here it goes... | |
1158 | */ | |
1159 | init_apic_ldr(); | |
1160 | ||
1161 | /* | |
1162 | * Set Task Priority to 'accept all'. We never change this | |
1163 | * later on. | |
1164 | */ | |
1165 | value = apic_read(APIC_TASKPRI); | |
1166 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1167 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1168 | |
da7ed9f9 VG |
1169 | /* |
1170 | * After a crash, we no longer service the interrupts and a pending | |
1171 | * interrupt from previous kernel might still have ISR bit set. | |
1172 | * | |
1173 | * Most probably by now CPU has serviced that pending interrupt and | |
1174 | * it might not have done the ack_APIC_irq() because it thought, | |
1175 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1176 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1177 | * the interrupt. Hence a vector might get locked. It was noticed | |
1178 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1179 | */ | |
1180 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1181 | value = apic_read(APIC_ISR + i*0x10); | |
1182 | for (j = 31; j >= 0; j--) { | |
1183 | if (value & (1<<j)) | |
1184 | ack_APIC_irq(); | |
1185 | } | |
1186 | } | |
1187 | ||
1da177e4 LT |
1188 | /* |
1189 | * Now that we are all set up, enable the APIC | |
1190 | */ | |
1191 | value = apic_read(APIC_SPIV); | |
1192 | value &= ~APIC_VECTOR_MASK; | |
1193 | /* | |
1194 | * Enable APIC | |
1195 | */ | |
1196 | value |= APIC_SPIV_APIC_ENABLED; | |
1197 | ||
89c38c28 CG |
1198 | #ifdef CONFIG_X86_32 |
1199 | /* | |
1200 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1201 | * certain networking cards. If high frequency interrupts are | |
1202 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1203 | * entry is masked/unmasked at a high rate as well then sooner or | |
1204 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1205 | * from the device. If focus CPU is disabled then the hang goes | |
1206 | * away, oh well :-( | |
1207 | * | |
1208 | * [ This bug can be reproduced easily with a level-triggered | |
1209 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1210 | * BX chipset. ] | |
1211 | */ | |
1212 | /* | |
1213 | * Actually disabling the focus CPU check just makes the hang less | |
1214 | * frequent as it makes the interrupt distributon model be more | |
1215 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1216 | * See also the comment in end_level_ioapic_irq(). --macro | |
1217 | */ | |
1218 | ||
1219 | /* | |
1220 | * - enable focus processor (bit==0) | |
1221 | * - 64bit mode always use processor focus | |
1222 | * so no need to set it | |
1223 | */ | |
1224 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1225 | #endif | |
3f14c746 | 1226 | |
1da177e4 LT |
1227 | /* |
1228 | * Set spurious IRQ vector | |
1229 | */ | |
1230 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1231 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1232 | |
1233 | /* | |
1234 | * Set up LVT0, LVT1: | |
1235 | * | |
1236 | * set up through-local-APIC on the BP's LINT0. This is not | |
1237 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1238 | * we delegate interrupts to the 8259A. | |
1239 | */ | |
1240 | /* | |
1241 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1242 | */ | |
1243 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1244 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1245 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1246 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1247 | smp_processor_id()); |
1da177e4 LT |
1248 | } else { |
1249 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1250 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1251 | smp_processor_id()); |
1da177e4 | 1252 | } |
11a8e778 | 1253 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1254 | |
1255 | /* | |
1256 | * only the BP should see the LINT1 NMI signal, obviously. | |
1257 | */ | |
1258 | if (!smp_processor_id()) | |
1259 | value = APIC_DM_NMI; | |
1260 | else | |
1261 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1262 | if (!lapic_is_integrated()) /* 82489DX */ |
1263 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1264 | apic_write(APIC_LVT1, value); |
89c38c28 | 1265 | |
ac23d4ee | 1266 | preempt_enable(); |
739f33b3 | 1267 | } |
1da177e4 | 1268 | |
739f33b3 AK |
1269 | void __cpuinit end_local_APIC_setup(void) |
1270 | { | |
1271 | lapic_setup_esr(); | |
fa6b95fc CG |
1272 | |
1273 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1274 | { |
1275 | unsigned int value; | |
1276 | /* Disable the local apic timer */ | |
1277 | value = apic_read(APIC_LVTT); | |
1278 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1279 | apic_write(APIC_LVTT, value); | |
1280 | } | |
fa6b95fc CG |
1281 | #endif |
1282 | ||
f2802e7f | 1283 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1284 | apic_pm_activate(); |
1da177e4 | 1285 | } |
1da177e4 | 1286 | |
49899eac | 1287 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1288 | void check_x2apic(void) |
1289 | { | |
1290 | int msr, msr2; | |
1291 | ||
1292 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1293 | ||
1294 | if (msr & X2APIC_ENABLE) { | |
ba21ebb6 | 1295 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a SS |
1296 | x2apic_preenabled = x2apic = 1; |
1297 | apic_ops = &x2apic_ops; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | void enable_x2apic(void) | |
1302 | { | |
1303 | int msr, msr2; | |
1304 | ||
1305 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1306 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1307 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1308 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1309 | } | |
1310 | } | |
1311 | ||
2236d252 | 1312 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1313 | { |
1314 | #ifdef CONFIG_INTR_REMAP | |
1315 | int ret; | |
1316 | unsigned long flags; | |
1317 | ||
1318 | if (!cpu_has_x2apic) | |
1319 | return; | |
1320 | ||
1321 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1322 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1323 | "because of nox2apic\n"); | |
6e1cb38a SS |
1324 | return; |
1325 | } | |
1326 | ||
1327 | if (x2apic_preenabled && disable_x2apic) | |
1328 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1329 | ||
1330 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1331 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1332 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1333 | return; |
1334 | } | |
1335 | ||
1336 | ret = dmar_table_init(); | |
1337 | if (ret) { | |
ba21ebb6 | 1338 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1339 | |
1340 | if (x2apic_preenabled) | |
1341 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1342 | else | |
ba21ebb6 | 1343 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1344 | return; |
1345 | } | |
1346 | ||
1347 | local_irq_save(flags); | |
1348 | mask_8259A(); | |
5ffa4eb2 CG |
1349 | |
1350 | ret = save_mask_IO_APIC_setup(); | |
1351 | if (ret) { | |
ba21ebb6 | 1352 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1353 | goto end; |
1354 | } | |
6e1cb38a SS |
1355 | |
1356 | ret = enable_intr_remapping(1); | |
1357 | ||
1358 | if (ret && x2apic_preenabled) { | |
1359 | local_irq_restore(flags); | |
1360 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1361 | } | |
1362 | ||
1363 | if (ret) | |
5ffa4eb2 | 1364 | goto end_restore; |
6e1cb38a SS |
1365 | |
1366 | if (!x2apic) { | |
1367 | x2apic = 1; | |
1368 | apic_ops = &x2apic_ops; | |
1369 | enable_x2apic(); | |
1370 | } | |
5ffa4eb2 CG |
1371 | |
1372 | end_restore: | |
6e1cb38a SS |
1373 | if (ret) |
1374 | /* | |
1375 | * IR enabling failed | |
1376 | */ | |
1377 | restore_IO_APIC_setup(); | |
1378 | else | |
1379 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1380 | ||
5ffa4eb2 | 1381 | end: |
6e1cb38a SS |
1382 | unmask_8259A(); |
1383 | local_irq_restore(flags); | |
1384 | ||
1385 | if (!ret) { | |
1386 | if (!x2apic_preenabled) | |
ba21ebb6 | 1387 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1388 | else |
ba21ebb6 | 1389 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1390 | } else |
ba21ebb6 | 1391 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
6e1cb38a SS |
1392 | #else |
1393 | if (!cpu_has_x2apic) | |
1394 | return; | |
1395 | ||
1396 | if (x2apic_preenabled) | |
1397 | panic("x2apic enabled prior OS handover," | |
1398 | " enable CONFIG_INTR_REMAP"); | |
1399 | ||
ba21ebb6 CG |
1400 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1401 | " and x2apic\n"); | |
6e1cb38a SS |
1402 | #endif |
1403 | ||
1404 | return; | |
1405 | } | |
49899eac | 1406 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1407 | |
be7a656f | 1408 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1409 | /* |
1410 | * Detect and enable local APICs on non-SMP boards. | |
1411 | * Original code written by Keir Fraser. | |
1412 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1413 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1414 | */ |
0e078e2f | 1415 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1416 | { |
1417 | if (!cpu_has_apic) { | |
ba21ebb6 | 1418 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1419 | return -1; |
1420 | } | |
1421 | ||
1422 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1423 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1424 | return 0; |
1425 | } | |
be7a656f YL |
1426 | #else |
1427 | /* | |
1428 | * Detect and initialize APIC | |
1429 | */ | |
1430 | static int __init detect_init_APIC(void) | |
1431 | { | |
1432 | u32 h, l, features; | |
1433 | ||
1434 | /* Disabled by kernel option? */ | |
1435 | if (disable_apic) | |
1436 | return -1; | |
1437 | ||
1438 | switch (boot_cpu_data.x86_vendor) { | |
1439 | case X86_VENDOR_AMD: | |
1440 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1441 | (boot_cpu_data.x86 == 15)) | |
1442 | break; | |
1443 | goto no_apic; | |
1444 | case X86_VENDOR_INTEL: | |
1445 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1446 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1447 | break; | |
1448 | goto no_apic; | |
1449 | default: | |
1450 | goto no_apic; | |
1451 | } | |
1452 | ||
1453 | if (!cpu_has_apic) { | |
1454 | /* | |
1455 | * Over-ride BIOS and try to enable the local APIC only if | |
1456 | * "lapic" specified. | |
1457 | */ | |
1458 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1459 | pr_info("Local APIC disabled by BIOS -- " |
1460 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1461 | return -1; |
1462 | } | |
1463 | /* | |
1464 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1465 | * MSR. This can only be done in software for Intel P6 or later | |
1466 | * and AMD K7 (Model > 1) or later. | |
1467 | */ | |
1468 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1469 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1470 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1471 | l &= ~MSR_IA32_APICBASE_BASE; |
1472 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1473 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1474 | enabled_via_apicbase = 1; | |
1475 | } | |
1476 | } | |
1477 | /* | |
1478 | * The APIC feature bit should now be enabled | |
1479 | * in `cpuid' | |
1480 | */ | |
1481 | features = cpuid_edx(1); | |
1482 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1483 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1484 | return -1; |
1485 | } | |
1486 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1487 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1488 | ||
1489 | /* The BIOS may have set up the APIC at some other address */ | |
1490 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1491 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1492 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1493 | ||
ba21ebb6 | 1494 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1495 | |
1496 | apic_pm_activate(); | |
1497 | ||
1498 | return 0; | |
1499 | ||
1500 | no_apic: | |
ba21ebb6 | 1501 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1502 | return -1; |
1503 | } | |
1504 | #endif | |
1da177e4 | 1505 | |
f28c0ae2 | 1506 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1507 | void __init early_init_lapic_mapping(void) |
1508 | { | |
431ee79d | 1509 | unsigned long phys_addr; |
8643f9d0 YL |
1510 | |
1511 | /* | |
1512 | * If no local APIC can be found then go out | |
1513 | * : it means there is no mpatable and MADT | |
1514 | */ | |
1515 | if (!smp_found_config) | |
1516 | return; | |
1517 | ||
431ee79d | 1518 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1519 | |
431ee79d | 1520 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1521 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1522 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1523 | |
1524 | /* | |
1525 | * Fetch the APIC ID of the BSP in case we have a | |
1526 | * default configuration (or the MP table is broken). | |
1527 | */ | |
4c9961d5 | 1528 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1529 | } |
f28c0ae2 | 1530 | #endif |
8643f9d0 | 1531 | |
0e078e2f TG |
1532 | /** |
1533 | * init_apic_mappings - initialize APIC mappings | |
1534 | */ | |
1da177e4 LT |
1535 | void __init init_apic_mappings(void) |
1536 | { | |
49899eac | 1537 | #ifdef HAVE_X2APIC |
6e1cb38a | 1538 | if (x2apic) { |
4c9961d5 | 1539 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1540 | return; |
1541 | } | |
49899eac | 1542 | #endif |
6e1cb38a | 1543 | |
1da177e4 LT |
1544 | /* |
1545 | * If no local APIC can be found then set up a fake all | |
1546 | * zeroes page to simulate the local APIC and another | |
1547 | * one for the IO-APIC. | |
1548 | */ | |
1549 | if (!smp_found_config && detect_init_APIC()) { | |
1550 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1551 | apic_phys = __pa(apic_phys); | |
1552 | } else | |
1553 | apic_phys = mp_lapic_addr; | |
1554 | ||
1555 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1556 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1557 | APIC_BASE, apic_phys); |
1da177e4 LT |
1558 | |
1559 | /* | |
1560 | * Fetch the APIC ID of the BSP in case we have a | |
1561 | * default configuration (or the MP table is broken). | |
1562 | */ | |
f28c0ae2 YL |
1563 | if (boot_cpu_physical_apicid == -1U) |
1564 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1565 | } |
1566 | ||
1567 | /* | |
0e078e2f TG |
1568 | * This initializes the IO-APIC and APIC hardware if this is |
1569 | * a UP kernel. | |
1da177e4 | 1570 | */ |
1b313f4a CG |
1571 | int apic_version[MAX_APICS]; |
1572 | ||
0e078e2f | 1573 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1574 | { |
fa2bd35a | 1575 | #ifdef CONFIG_X86_64 |
0e078e2f | 1576 | if (disable_apic) { |
ba21ebb6 | 1577 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1578 | return -1; |
1579 | } | |
1580 | if (!cpu_has_apic) { | |
1581 | disable_apic = 1; | |
ba21ebb6 | 1582 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1583 | return -1; |
1584 | } | |
fa2bd35a YL |
1585 | #else |
1586 | if (!smp_found_config && !cpu_has_apic) | |
1587 | return -1; | |
1588 | ||
1589 | /* | |
1590 | * Complain if the BIOS pretends there is one. | |
1591 | */ | |
1592 | if (!cpu_has_apic && | |
1593 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1594 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1595 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1596 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1597 | return -1; | |
1598 | } | |
1599 | #endif | |
1600 | ||
49899eac | 1601 | #ifdef HAVE_X2APIC |
6e1cb38a | 1602 | enable_IR_x2apic(); |
49899eac | 1603 | #endif |
fa2bd35a | 1604 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1605 | setup_apic_routing(); |
fa2bd35a | 1606 | #endif |
6e1cb38a | 1607 | |
0e078e2f | 1608 | verify_local_APIC(); |
b5841765 GC |
1609 | connect_bsp_APIC(); |
1610 | ||
fa2bd35a | 1611 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1612 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1613 | #else |
1614 | /* | |
1615 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1616 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1617 | * might be zero if read from MP tables. Get it from LAPIC. | |
1618 | */ | |
1619 | # ifdef CONFIG_CRASH_DUMP | |
1620 | boot_cpu_physical_apicid = read_apic_id(); | |
1621 | # endif | |
1622 | #endif | |
1623 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1624 | setup_local_APIC(); |
1da177e4 | 1625 | |
fa2bd35a | 1626 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1627 | /* |
1628 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1629 | * We need clear_IO_APIC before enabling vector on BP | |
1630 | */ | |
1631 | if (!skip_ioapic_setup && nr_ioapics) | |
1632 | enable_IO_APIC(); | |
fa2bd35a | 1633 | #endif |
739f33b3 | 1634 | |
fa2bd35a | 1635 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1636 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1637 | #endif |
acae7d90 | 1638 | localise_nmi_watchdog(); |
739f33b3 AK |
1639 | end_local_APIC_setup(); |
1640 | ||
fa2bd35a | 1641 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1642 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1643 | setup_IO_APIC(); | |
fa2bd35a | 1644 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1645 | else |
1646 | nr_ioapics = 0; | |
fa2bd35a YL |
1647 | # endif |
1648 | #endif | |
1649 | ||
1650 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1651 | setup_boot_APIC_clock(); |
1652 | check_nmi_watchdog(); | |
fa2bd35a YL |
1653 | #else |
1654 | setup_boot_clock(); | |
1655 | #endif | |
1656 | ||
0e078e2f | 1657 | return 0; |
1da177e4 LT |
1658 | } |
1659 | ||
1660 | /* | |
0e078e2f | 1661 | * Local APIC interrupts |
1da177e4 LT |
1662 | */ |
1663 | ||
0e078e2f TG |
1664 | /* |
1665 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1666 | */ | |
dc1528dd | 1667 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1668 | { |
dc1528dd YL |
1669 | u32 v; |
1670 | ||
1671 | #ifdef CONFIG_X86_64 | |
0e078e2f | 1672 | exit_idle(); |
dc1528dd | 1673 | #endif |
0e078e2f | 1674 | irq_enter(); |
1da177e4 | 1675 | /* |
0e078e2f TG |
1676 | * Check if this really is a spurious interrupt and ACK it |
1677 | * if it is a vectored one. Just in case... | |
1678 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1679 | */ |
0e078e2f TG |
1680 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1681 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1682 | ack_APIC_irq(); | |
c4d58cbd | 1683 | |
dc1528dd | 1684 | #ifdef CONFIG_X86_64 |
0e078e2f | 1685 | add_pda(irq_spurious_count, 1); |
dc1528dd YL |
1686 | #else |
1687 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
ba21ebb6 CG |
1688 | pr_info("spurious APIC interrupt on CPU#%d, " |
1689 | "should never happen.\n", smp_processor_id()); | |
dc1528dd YL |
1690 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1691 | #endif | |
0e078e2f TG |
1692 | irq_exit(); |
1693 | } | |
1da177e4 | 1694 | |
0e078e2f TG |
1695 | /* |
1696 | * This interrupt should never happen with our APIC/SMP architecture | |
1697 | */ | |
dc1528dd | 1698 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1699 | { |
dc1528dd | 1700 | u32 v, v1; |
1da177e4 | 1701 | |
dc1528dd | 1702 | #ifdef CONFIG_X86_64 |
0e078e2f | 1703 | exit_idle(); |
dc1528dd | 1704 | #endif |
0e078e2f TG |
1705 | irq_enter(); |
1706 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1707 | v = apic_read(APIC_ESR); | |
1708 | apic_write(APIC_ESR, 0); | |
1709 | v1 = apic_read(APIC_ESR); | |
1710 | ack_APIC_irq(); | |
1711 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1712 | |
ba21ebb6 CG |
1713 | /* |
1714 | * Here is what the APIC error bits mean: | |
1715 | * 0: Send CS error | |
1716 | * 1: Receive CS error | |
1717 | * 2: Send accept error | |
1718 | * 3: Receive accept error | |
1719 | * 4: Reserved | |
1720 | * 5: Send illegal vector | |
1721 | * 6: Received illegal vector | |
1722 | * 7: Illegal register address | |
1723 | */ | |
1724 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1725 | smp_processor_id(), v , v1); |
1726 | irq_exit(); | |
1da177e4 LT |
1727 | } |
1728 | ||
b5841765 | 1729 | /** |
36c9d674 CG |
1730 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1731 | */ | |
b5841765 GC |
1732 | void __init connect_bsp_APIC(void) |
1733 | { | |
36c9d674 CG |
1734 | #ifdef CONFIG_X86_32 |
1735 | if (pic_mode) { | |
1736 | /* | |
1737 | * Do not trust the local APIC being empty at bootup. | |
1738 | */ | |
1739 | clear_local_APIC(); | |
1740 | /* | |
1741 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1742 | * local APIC to INT and NMI lines. | |
1743 | */ | |
1744 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1745 | "enabling APIC mode.\n"); | |
1746 | outb(0x70, 0x22); | |
1747 | outb(0x01, 0x23); | |
1748 | } | |
1749 | #endif | |
b5841765 GC |
1750 | enable_apic_mode(); |
1751 | } | |
1752 | ||
274cfe59 CG |
1753 | /** |
1754 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1755 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1756 | * | |
1757 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1758 | * APIC is disabled. | |
1759 | */ | |
0e078e2f | 1760 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1761 | { |
1b4ee4e4 CG |
1762 | unsigned int value; |
1763 | ||
c177b0bc CG |
1764 | #ifdef CONFIG_X86_32 |
1765 | if (pic_mode) { | |
1766 | /* | |
1767 | * Put the board back into PIC mode (has an effect only on | |
1768 | * certain older boards). Note that APIC interrupts, including | |
1769 | * IPIs, won't work beyond this point! The only exception are | |
1770 | * INIT IPIs. | |
1771 | */ | |
1772 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1773 | "entering PIC mode.\n"); | |
1774 | outb(0x70, 0x22); | |
1775 | outb(0x00, 0x23); | |
1776 | return; | |
1777 | } | |
1778 | #endif | |
1779 | ||
0e078e2f | 1780 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1781 | |
0e078e2f TG |
1782 | /* For the spurious interrupt use vector F, and enable it */ |
1783 | value = apic_read(APIC_SPIV); | |
1784 | value &= ~APIC_VECTOR_MASK; | |
1785 | value |= APIC_SPIV_APIC_ENABLED; | |
1786 | value |= 0xf; | |
1787 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1788 | |
0e078e2f TG |
1789 | if (!virt_wire_setup) { |
1790 | /* | |
1791 | * For LVT0 make it edge triggered, active high, | |
1792 | * external and enabled | |
1793 | */ | |
1794 | value = apic_read(APIC_LVT0); | |
1795 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1796 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1797 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1798 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1799 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1800 | apic_write(APIC_LVT0, value); | |
1801 | } else { | |
1802 | /* Disable LVT0 */ | |
1803 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1804 | } | |
b8ce3359 | 1805 | |
c177b0bc CG |
1806 | /* |
1807 | * For LVT1 make it edge triggered, active high, | |
1808 | * nmi and enabled | |
1809 | */ | |
0e078e2f TG |
1810 | value = apic_read(APIC_LVT1); |
1811 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1812 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1813 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1814 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1815 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1816 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1817 | } |
1818 | ||
be8a5685 AS |
1819 | void __cpuinit generic_processor_info(int apicid, int version) |
1820 | { | |
1821 | int cpu; | |
be8a5685 | 1822 | |
1b313f4a CG |
1823 | /* |
1824 | * Validate version | |
1825 | */ | |
1826 | if (version == 0x0) { | |
ba21ebb6 | 1827 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1828 | "fixing up to 0x10. (tell your hw vendor)\n", |
1829 | version); | |
1b313f4a | 1830 | version = 0x10; |
be8a5685 | 1831 | } |
1b313f4a | 1832 | apic_version[apicid] = version; |
be8a5685 | 1833 | |
3b11ce7f MT |
1834 | if (num_processors >= nr_cpu_ids) { |
1835 | int max = nr_cpu_ids; | |
1836 | int thiscpu = max + disabled_cpus; | |
1837 | ||
1838 | pr_warning( | |
1839 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1840 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1841 | ||
1842 | disabled_cpus++; | |
be8a5685 AS |
1843 | return; |
1844 | } | |
1845 | ||
1846 | num_processors++; | |
3b11ce7f | 1847 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 AS |
1848 | |
1849 | physid_set(apicid, phys_cpu_present_map); | |
1850 | if (apicid == boot_cpu_physical_apicid) { | |
1851 | /* | |
1852 | * x86_bios_cpu_apicid is required to have processors listed | |
1853 | * in same order as logical cpu numbers. Hence the first | |
1854 | * entry is BSP, and so on. | |
1855 | */ | |
1856 | cpu = 0; | |
1857 | } | |
e0da3364 YL |
1858 | if (apicid > max_physical_apicid) |
1859 | max_physical_apicid = apicid; | |
1860 | ||
1b313f4a CG |
1861 | #ifdef CONFIG_X86_32 |
1862 | /* | |
1863 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1864 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1865 | * before this can be done without some confusion. | |
1866 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1867 | * - Ashok Raj <ashok.raj@intel.com> | |
1868 | */ | |
1869 | if (max_physical_apicid >= 8) { | |
1870 | switch (boot_cpu_data.x86_vendor) { | |
1871 | case X86_VENDOR_INTEL: | |
1872 | if (!APIC_XAPIC(version)) { | |
1873 | def_to_bigsmp = 0; | |
1874 | break; | |
1875 | } | |
1876 | /* If P4 and above fall through */ | |
1877 | case X86_VENDOR_AMD: | |
1878 | def_to_bigsmp = 1; | |
1879 | } | |
1880 | } | |
1881 | #endif | |
1882 | ||
1883 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1884 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1885 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1886 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1887 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1888 | |
1889 | cpu_to_apicid[cpu] = apicid; | |
1890 | bios_cpu_apicid[cpu] = apicid; | |
1891 | } else { | |
1892 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1893 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1894 | } | |
1b313f4a | 1895 | #endif |
be8a5685 | 1896 | |
1de88cd4 MT |
1897 | set_cpu_possible(cpu, true); |
1898 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1899 | } |
1900 | ||
3491998d | 1901 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1902 | int hard_smp_processor_id(void) |
1903 | { | |
1904 | return read_apic_id(); | |
1905 | } | |
3491998d | 1906 | #endif |
0c81c746 | 1907 | |
89039b37 | 1908 | /* |
0e078e2f | 1909 | * Power management |
89039b37 | 1910 | */ |
0e078e2f TG |
1911 | #ifdef CONFIG_PM |
1912 | ||
1913 | static struct { | |
274cfe59 CG |
1914 | /* |
1915 | * 'active' is true if the local APIC was enabled by us and | |
1916 | * not the BIOS; this signifies that we are also responsible | |
1917 | * for disabling it before entering apm/acpi suspend | |
1918 | */ | |
0e078e2f TG |
1919 | int active; |
1920 | /* r/w apic fields */ | |
1921 | unsigned int apic_id; | |
1922 | unsigned int apic_taskpri; | |
1923 | unsigned int apic_ldr; | |
1924 | unsigned int apic_dfr; | |
1925 | unsigned int apic_spiv; | |
1926 | unsigned int apic_lvtt; | |
1927 | unsigned int apic_lvtpc; | |
1928 | unsigned int apic_lvt0; | |
1929 | unsigned int apic_lvt1; | |
1930 | unsigned int apic_lvterr; | |
1931 | unsigned int apic_tmict; | |
1932 | unsigned int apic_tdcr; | |
1933 | unsigned int apic_thmr; | |
1934 | } apic_pm_state; | |
1935 | ||
1936 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1937 | { | |
1938 | unsigned long flags; | |
1939 | int maxlvt; | |
89039b37 | 1940 | |
0e078e2f TG |
1941 | if (!apic_pm_state.active) |
1942 | return 0; | |
89039b37 | 1943 | |
0e078e2f | 1944 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1945 | |
2d7a66d0 | 1946 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1947 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1948 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1949 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1950 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1951 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1952 | if (maxlvt >= 4) | |
1953 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1954 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1955 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1956 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1957 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1958 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1959 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1960 | if (maxlvt >= 5) |
1961 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1962 | #endif | |
24968cfd | 1963 | |
0e078e2f TG |
1964 | local_irq_save(flags); |
1965 | disable_local_APIC(); | |
1966 | local_irq_restore(flags); | |
1967 | return 0; | |
1da177e4 LT |
1968 | } |
1969 | ||
0e078e2f | 1970 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1971 | { |
0e078e2f TG |
1972 | unsigned int l, h; |
1973 | unsigned long flags; | |
1974 | int maxlvt; | |
1da177e4 | 1975 | |
0e078e2f TG |
1976 | if (!apic_pm_state.active) |
1977 | return 0; | |
89b831ef | 1978 | |
0e078e2f | 1979 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1980 | |
0e078e2f | 1981 | local_irq_save(flags); |
92206c90 | 1982 | |
49899eac | 1983 | #ifdef HAVE_X2APIC |
92206c90 CG |
1984 | if (x2apic) |
1985 | enable_x2apic(); | |
1986 | else | |
1987 | #endif | |
d5e629a6 | 1988 | { |
92206c90 CG |
1989 | /* |
1990 | * Make sure the APICBASE points to the right address | |
1991 | * | |
1992 | * FIXME! This will be wrong if we ever support suspend on | |
1993 | * SMP! We'll need to do this as part of the CPU restore! | |
1994 | */ | |
6e1cb38a SS |
1995 | rdmsr(MSR_IA32_APICBASE, l, h); |
1996 | l &= ~MSR_IA32_APICBASE_BASE; | |
1997 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1998 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1999 | } |
6e1cb38a | 2000 | |
0e078e2f TG |
2001 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2002 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2003 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2004 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2005 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2006 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2007 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2008 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2009 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2010 | if (maxlvt >= 5) |
2011 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2012 | #endif | |
2013 | if (maxlvt >= 4) | |
2014 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2015 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2016 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2017 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2018 | apic_write(APIC_ESR, 0); | |
2019 | apic_read(APIC_ESR); | |
2020 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2021 | apic_write(APIC_ESR, 0); | |
2022 | apic_read(APIC_ESR); | |
92206c90 | 2023 | |
0e078e2f | 2024 | local_irq_restore(flags); |
92206c90 | 2025 | |
0e078e2f TG |
2026 | return 0; |
2027 | } | |
b8ce3359 | 2028 | |
274cfe59 CG |
2029 | /* |
2030 | * This device has no shutdown method - fully functioning local APICs | |
2031 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2032 | */ | |
2033 | ||
0e078e2f TG |
2034 | static struct sysdev_class lapic_sysclass = { |
2035 | .name = "lapic", | |
2036 | .resume = lapic_resume, | |
2037 | .suspend = lapic_suspend, | |
2038 | }; | |
b8ce3359 | 2039 | |
0e078e2f | 2040 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2041 | .id = 0, |
2042 | .cls = &lapic_sysclass, | |
0e078e2f | 2043 | }; |
b8ce3359 | 2044 | |
0e078e2f TG |
2045 | static void __cpuinit apic_pm_activate(void) |
2046 | { | |
2047 | apic_pm_state.active = 1; | |
1da177e4 LT |
2048 | } |
2049 | ||
0e078e2f | 2050 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2051 | { |
0e078e2f | 2052 | int error; |
e83a5fdc | 2053 | |
0e078e2f TG |
2054 | if (!cpu_has_apic) |
2055 | return 0; | |
2056 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2057 | |
0e078e2f TG |
2058 | error = sysdev_class_register(&lapic_sysclass); |
2059 | if (!error) | |
2060 | error = sysdev_register(&device_lapic); | |
2061 | return error; | |
1da177e4 | 2062 | } |
0e078e2f TG |
2063 | device_initcall(init_lapic_sysfs); |
2064 | ||
2065 | #else /* CONFIG_PM */ | |
2066 | ||
2067 | static void apic_pm_activate(void) { } | |
2068 | ||
2069 | #endif /* CONFIG_PM */ | |
1da177e4 | 2070 | |
f28c0ae2 | 2071 | #ifdef CONFIG_X86_64 |
1da177e4 | 2072 | /* |
f8bf3c65 | 2073 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2074 | * |
2075 | * Thus far, the major user of this is IBM's Summit2 series: | |
2076 | * | |
637029c6 | 2077 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2078 | * multi-chassis. Use available data to take a good guess. |
2079 | * If in doubt, go HPET. | |
2080 | */ | |
f8bf3c65 | 2081 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2082 | { |
2083 | int i, clusters, zeros; | |
2084 | unsigned id; | |
322850af | 2085 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2086 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2087 | ||
322850af YL |
2088 | /* |
2089 | * there is not this kind of box with AMD CPU yet. | |
2090 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2091 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2092 | * vsmp box still need checking... |
322850af | 2093 | */ |
1cb68487 | 2094 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2095 | return 0; |
2096 | ||
23ca4bba | 2097 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2098 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2099 | |
168ef543 | 2100 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2101 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2102 | if (bios_cpu_apicid) { |
2103 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 2104 | } |
2105 | else if (i < nr_cpu_ids) { | |
2106 | if (cpu_present(i)) | |
2107 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2108 | else | |
2109 | continue; | |
2110 | } | |
2111 | else | |
2112 | break; | |
2113 | ||
1da177e4 LT |
2114 | if (id != BAD_APICID) |
2115 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2116 | } | |
2117 | ||
2118 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2119 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2120 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2121 | * Since clusters are allocated sequentially, count zeros only if | |
2122 | * they are bounded by ones. | |
1da177e4 LT |
2123 | */ |
2124 | clusters = 0; | |
2125 | zeros = 0; | |
2126 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2127 | if (test_bit(i, clustermap)) { | |
2128 | clusters += 1 + zeros; | |
2129 | zeros = 0; | |
2130 | } else | |
2131 | ++zeros; | |
2132 | } | |
2133 | ||
1cb68487 RT |
2134 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2135 | * not guaranteed to be synced between boards | |
2136 | */ | |
2137 | if (is_vsmp_box() && clusters > 1) | |
2138 | return 1; | |
2139 | ||
1da177e4 | 2140 | /* |
f8bf3c65 | 2141 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2142 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2143 | * out, but AFAIK this will work even for them. | |
2144 | */ | |
2145 | return (clusters > 2); | |
2146 | } | |
f28c0ae2 | 2147 | #endif |
1da177e4 LT |
2148 | |
2149 | /* | |
0e078e2f | 2150 | * APIC command line parameters |
1da177e4 | 2151 | */ |
789fa735 | 2152 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2153 | { |
1da177e4 | 2154 | disable_apic = 1; |
9175fc06 | 2155 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2156 | return 0; |
2157 | } | |
2158 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2159 | |
2c8c0e6b | 2160 | /* same as disableapic, for compatibility */ |
789fa735 | 2161 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2162 | { |
789fa735 | 2163 | return setup_disableapic(arg); |
6935d1f9 | 2164 | } |
2c8c0e6b | 2165 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2166 | |
2e7c2838 LT |
2167 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2168 | { | |
2169 | local_apic_timer_c2_ok = 1; | |
2170 | return 0; | |
2171 | } | |
2172 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2173 | ||
36fef094 | 2174 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2175 | { |
1da177e4 | 2176 | disable_apic_timer = 1; |
36fef094 | 2177 | return 0; |
6935d1f9 | 2178 | } |
36fef094 CG |
2179 | early_param("noapictimer", parse_disable_apic_timer); |
2180 | ||
2181 | static int __init parse_nolapic_timer(char *arg) | |
2182 | { | |
2183 | disable_apic_timer = 1; | |
2184 | return 0; | |
6935d1f9 | 2185 | } |
36fef094 | 2186 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2187 | |
79af9bec CG |
2188 | static int __init apic_set_verbosity(char *arg) |
2189 | { | |
2190 | if (!arg) { | |
2191 | #ifdef CONFIG_X86_64 | |
2192 | skip_ioapic_setup = 0; | |
79af9bec CG |
2193 | return 0; |
2194 | #endif | |
2195 | return -EINVAL; | |
2196 | } | |
2197 | ||
2198 | if (strcmp("debug", arg) == 0) | |
2199 | apic_verbosity = APIC_DEBUG; | |
2200 | else if (strcmp("verbose", arg) == 0) | |
2201 | apic_verbosity = APIC_VERBOSE; | |
2202 | else { | |
ba21ebb6 | 2203 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2204 | " use apic=verbose or apic=debug\n", arg); |
2205 | return -EINVAL; | |
2206 | } | |
2207 | ||
2208 | return 0; | |
2209 | } | |
2210 | early_param("apic", apic_set_verbosity); | |
2211 | ||
1e934dda YL |
2212 | static int __init lapic_insert_resource(void) |
2213 | { | |
2214 | if (!apic_phys) | |
2215 | return -1; | |
2216 | ||
2217 | /* Put local APIC into the resource map. */ | |
2218 | lapic_resource.start = apic_phys; | |
2219 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2220 | insert_resource(&iomem_resource, &lapic_resource); | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
2225 | /* | |
2226 | * need call insert after e820_reserve_resources() | |
2227 | * that is using request_resource | |
2228 | */ | |
2229 | late_initcall(lapic_insert_resource); |