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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
f3705136 | 26 | #include <linux/cpu.h> |
e9e2cdb4 | 27 | #include <linux/clockchips.h> |
d36b49b9 | 28 | #include <linux/acpi_pmtmr.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
ad62ca2b | 30 | #include <linux/dmi.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
36 | #include <asm/desc.h> | |
37 | #include <asm/arch_hooks.h> | |
38 | #include <asm/hpet.h> | |
306e440d | 39 | #include <asm/i8253.h> |
3e4ff115 | 40 | #include <asm/nmi.h> |
1da177e4 LT |
41 | |
42 | #include <mach_apic.h> | |
382dbd07 | 43 | #include <mach_apicdef.h> |
6eb0a0fd | 44 | #include <mach_ipi.h> |
1da177e4 | 45 | |
e05d723f TG |
46 | /* |
47 | * Sanity check | |
48 | */ | |
ff8a03a6 | 49 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
e05d723f TG |
50 | # error SPURIOUS_APIC_VECTOR definition error |
51 | #endif | |
52 | ||
8f6e2ca9 AS |
53 | unsigned long mp_lapic_addr; |
54 | ||
9635b47d EB |
55 | /* |
56 | * Knob to control our willingness to enable the local APIC. | |
e05d723f | 57 | * |
914bebfa | 58 | * +1=force-enable |
9635b47d | 59 | */ |
914bebfa YL |
60 | static int force_enable_local_apic; |
61 | int disable_apic; | |
9635b47d | 62 | |
d36b49b9 TG |
63 | /* Local APIC timer verification ok */ |
64 | static int local_apic_timer_verify_ok; | |
aa276e1c TG |
65 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
66 | static int local_apic_timer_disabled; | |
e585bef8 TG |
67 | /* Local APIC timer works in C2 */ |
68 | int local_apic_timer_c2_ok; | |
69 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
e9e2cdb4 | 70 | |
ce178331 AM |
71 | int first_system_vector = 0xfe; |
72 | ||
73 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
74 | ||
1da177e4 | 75 | /* |
e05d723f | 76 | * Debug level, exported for io_apic.c |
1da177e4 LT |
77 | */ |
78 | int apic_verbosity; | |
79 | ||
f3918352 AS |
80 | int pic_mode; |
81 | ||
bab4b27c AS |
82 | /* Have we found an MP table */ |
83 | int smp_found_config; | |
84 | ||
746f2eb7 CG |
85 | static struct resource lapic_resource = { |
86 | .name = "Local APIC", | |
87 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
88 | }; | |
89 | ||
e9e2cdb4 | 90 | static unsigned int calibration_result; |
1da177e4 | 91 | |
e9e2cdb4 TG |
92 | static int lapic_next_event(unsigned long delta, |
93 | struct clock_event_device *evt); | |
94 | static void lapic_timer_setup(enum clock_event_mode mode, | |
95 | struct clock_event_device *evt); | |
96 | static void lapic_timer_broadcast(cpumask_t mask); | |
97 | static void apic_pm_activate(void); | |
e05d723f | 98 | |
e9e2cdb4 TG |
99 | /* |
100 | * The local apic timer can be used for any function which is CPU local. | |
101 | */ | |
102 | static struct clock_event_device lapic_clockevent = { | |
103 | .name = "lapic", | |
104 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
d36b49b9 | 105 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
e9e2cdb4 TG |
106 | .shift = 32, |
107 | .set_mode = lapic_timer_setup, | |
108 | .set_next_event = lapic_next_event, | |
109 | .broadcast = lapic_timer_broadcast, | |
110 | .rating = 100, | |
111 | .irq = -1, | |
112 | }; | |
113 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
e05d723f TG |
114 | |
115 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
116 | static int enabled_via_apicbase; | |
117 | ||
d3432896 AK |
118 | static unsigned long apic_phys; |
119 | ||
e05d723f TG |
120 | /* |
121 | * Get the LAPIC version | |
122 | */ | |
123 | static inline int lapic_get_version(void) | |
95d769aa | 124 | { |
e05d723f | 125 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
126 | } |
127 | ||
1da177e4 | 128 | /* |
ab4a574e | 129 | * Check, if the APIC is integrated or a separate chip |
1da177e4 | 130 | */ |
e05d723f | 131 | static inline int lapic_is_integrated(void) |
1da177e4 | 132 | { |
e05d723f | 133 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
134 | } |
135 | ||
e05d723f TG |
136 | /* |
137 | * Check, whether this is a modern or a first generation APIC | |
138 | */ | |
139 | static int modern_apic(void) | |
1da177e4 | 140 | { |
e05d723f TG |
141 | /* AMD systems use old APIC versions, so check the CPU */ |
142 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
143 | boot_cpu_data.x86 >= 0xf) | |
144 | return 1; | |
145 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
146 | } |
147 | ||
f2b218dd FLV |
148 | void apic_wait_icr_idle(void) |
149 | { | |
150 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
151 | cpu_relax(); | |
152 | } | |
153 | ||
42e0a9aa | 154 | u32 safe_apic_wait_icr_idle(void) |
f2b218dd | 155 | { |
42e0a9aa | 156 | u32 send_status; |
f2b218dd FLV |
157 | int timeout; |
158 | ||
159 | timeout = 0; | |
160 | do { | |
161 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
162 | if (!send_status) | |
163 | break; | |
164 | udelay(100); | |
165 | } while (timeout++ < 1000); | |
166 | ||
167 | return send_status; | |
168 | } | |
169 | ||
e05d723f TG |
170 | /** |
171 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
172 | */ | |
e9427101 | 173 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 174 | { |
e05d723f | 175 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 176 | |
e05d723f TG |
177 | /* Level triggered for 82489DX */ |
178 | if (!lapic_is_integrated()) | |
1da177e4 LT |
179 | v |= APIC_LVT_LEVEL_TRIGGER; |
180 | apic_write_around(APIC_LVT0, v); | |
181 | } | |
182 | ||
e05d723f TG |
183 | /** |
184 | * get_physical_broadcast - Get number of physical broadcast IDs | |
185 | */ | |
1da177e4 LT |
186 | int get_physical_broadcast(void) |
187 | { | |
e05d723f | 188 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
189 | } |
190 | ||
e05d723f TG |
191 | /** |
192 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
193 | */ | |
194 | int lapic_get_maxlvt(void) | |
1da177e4 | 195 | { |
e05d723f | 196 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 197 | |
1da177e4 | 198 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 199 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
200 | } |
201 | ||
e05d723f TG |
202 | /* |
203 | * Local APIC timer | |
204 | */ | |
205 | ||
d36b49b9 TG |
206 | /* Clock divisor is set to 16 */ |
207 | #define APIC_DIVISOR 16 | |
e05d723f TG |
208 | |
209 | /* | |
210 | * This function sets up the local APIC timer, with a timeout of | |
211 | * 'clocks' APIC bus clock. During calibration we actually call | |
212 | * this function twice on the boot CPU, once with a bogus timeout | |
213 | * value, second time for real. The other (noncalibrating) CPUs | |
214 | * call this function only once, with the real, calibrated value. | |
215 | * | |
216 | * We do reads before writes even if unnecessary, to get around the | |
217 | * P5 APIC double write bug. | |
218 | */ | |
e9e2cdb4 | 219 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 220 | { |
e05d723f | 221 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 222 | |
e9e2cdb4 TG |
223 | lvtt_value = LOCAL_TIMER_VECTOR; |
224 | if (!oneshot) | |
225 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
e05d723f TG |
226 | if (!lapic_is_integrated()) |
227 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
228 | ||
e9e2cdb4 | 229 | if (!irqen) |
e05d723f TG |
230 | lvtt_value |= APIC_LVT_MASKED; |
231 | ||
232 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
233 | |
234 | /* | |
e05d723f | 235 | * Divide PICLK by 16 |
1da177e4 | 236 | */ |
e05d723f TG |
237 | tmp_value = apic_read(APIC_TDCR); |
238 | apic_write_around(APIC_TDCR, (tmp_value | |
239 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
240 | | APIC_TDR_DIV_16); | |
1da177e4 | 241 | |
e9e2cdb4 TG |
242 | if (!oneshot) |
243 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
244 | } | |
245 | ||
246 | /* | |
247 | * Program the next event, relative to now | |
248 | */ | |
249 | static int lapic_next_event(unsigned long delta, | |
250 | struct clock_event_device *evt) | |
251 | { | |
252 | apic_write_around(APIC_TMICT, delta); | |
253 | return 0; | |
1da177e4 LT |
254 | } |
255 | ||
e9e2cdb4 TG |
256 | /* |
257 | * Setup the lapic timer in periodic or oneshot mode | |
258 | */ | |
259 | static void lapic_timer_setup(enum clock_event_mode mode, | |
260 | struct clock_event_device *evt) | |
1da177e4 | 261 | { |
e05d723f | 262 | unsigned long flags; |
e9e2cdb4 | 263 | unsigned int v; |
e05d723f | 264 | |
d36b49b9 TG |
265 | /* Lapic used for broadcast ? */ |
266 | if (!local_apic_timer_verify_ok) | |
267 | return; | |
268 | ||
e05d723f | 269 | local_irq_save(flags); |
1da177e4 | 270 | |
e9e2cdb4 TG |
271 | switch (mode) { |
272 | case CLOCK_EVT_MODE_PERIODIC: | |
273 | case CLOCK_EVT_MODE_ONESHOT: | |
274 | __setup_APIC_LVTT(calibration_result, | |
275 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
276 | break; | |
277 | case CLOCK_EVT_MODE_UNUSED: | |
278 | case CLOCK_EVT_MODE_SHUTDOWN: | |
279 | v = apic_read(APIC_LVTT); | |
280 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
281 | apic_write_around(APIC_LVTT, v); | |
282 | break; | |
18de5bc4 TG |
283 | case CLOCK_EVT_MODE_RESUME: |
284 | /* Nothing to do here */ | |
285 | break; | |
e9e2cdb4 | 286 | } |
e05d723f TG |
287 | |
288 | local_irq_restore(flags); | |
289 | } | |
290 | ||
e9e2cdb4 TG |
291 | /* |
292 | * Local APIC timer broadcast function | |
293 | */ | |
294 | static void lapic_timer_broadcast(cpumask_t mask) | |
295 | { | |
296 | #ifdef CONFIG_SMP | |
297 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
298 | #endif | |
299 | } | |
300 | ||
301 | /* | |
302 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
303 | * of the boot CPU and register the clock event in the framework. | |
304 | */ | |
305 | static void __devinit setup_APIC_timer(void) | |
306 | { | |
307 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
308 | ||
309 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); | |
310 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
311 | ||
312 | clockevents_register_device(levt); | |
313 | } | |
314 | ||
e05d723f | 315 | /* |
d36b49b9 TG |
316 | * In this functions we calibrate APIC bus clocks to the external timer. |
317 | * | |
318 | * We want to do the calibration only once since we want to have local timer | |
319 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
320 | * frequency. | |
321 | * | |
322 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
323 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
324 | * readout is broken, so it never gets out of the wait loop again. This was | |
325 | * also reported by others. | |
e05d723f | 326 | * |
d36b49b9 TG |
327 | * Monitoring the jiffies value is inaccurate and the clockevents |
328 | * infrastructure allows us to do a simple substitution of the interrupt | |
329 | * handler. | |
e9e2cdb4 | 330 | * |
d36b49b9 TG |
331 | * The calibration routine also uses the pm_timer when possible, as the PIT |
332 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
333 | * back to normal later in the boot process). | |
e05d723f TG |
334 | */ |
335 | ||
d36b49b9 | 336 | #define LAPIC_CAL_LOOPS (HZ/10) |
e05d723f | 337 | |
f5352fd0 | 338 | static __initdata int lapic_cal_loops = -1; |
d36b49b9 TG |
339 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
340 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
341 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
342 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
1da177e4 | 343 | |
d36b49b9 TG |
344 | /* |
345 | * Temporary interrupt handler. | |
346 | */ | |
347 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
348 | { | |
349 | unsigned long long tsc = 0; | |
350 | long tapic = apic_read(APIC_TMCCT); | |
351 | unsigned long pm = acpi_pm_read_early(); | |
1da177e4 | 352 | |
d36b49b9 TG |
353 | if (cpu_has_tsc) |
354 | rdtscll(tsc); | |
355 | ||
356 | switch (lapic_cal_loops++) { | |
357 | case 0: | |
358 | lapic_cal_t1 = tapic; | |
359 | lapic_cal_tsc1 = tsc; | |
360 | lapic_cal_pm1 = pm; | |
361 | lapic_cal_j1 = jiffies; | |
362 | break; | |
e05d723f | 363 | |
d36b49b9 TG |
364 | case LAPIC_CAL_LOOPS: |
365 | lapic_cal_t2 = tapic; | |
366 | lapic_cal_tsc2 = tsc; | |
367 | if (pm < lapic_cal_pm1) | |
368 | pm += ACPI_PM_OVRRUN; | |
369 | lapic_cal_pm2 = pm; | |
370 | lapic_cal_j2 = jiffies; | |
371 | break; | |
372 | } | |
373 | } | |
1da177e4 | 374 | |
d36b49b9 TG |
375 | /* |
376 | * Setup the boot APIC | |
377 | * | |
378 | * Calibrate and verify the result. | |
379 | */ | |
380 | void __init setup_boot_APIC_clock(void) | |
381 | { | |
382 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
383 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | |
384 | const long pm_thresh = pm_100ms/100; | |
385 | void (*real_handler)(struct clock_event_device *dev); | |
386 | unsigned long deltaj; | |
387 | long delta, deltapm; | |
ca1b940c | 388 | int pm_referenced = 0; |
1da177e4 | 389 | |
ad62ca2b TG |
390 | /* |
391 | * The local apic timer can be disabled via the kernel | |
d3f7eae1 | 392 | * commandline or from the CPU detection code. Register the lapic |
ad62ca2b TG |
393 | * timer as a dummy clock event source on SMP systems, so the |
394 | * broadcast mechanism is used. On UP systems simply ignore it. | |
395 | */ | |
396 | if (local_apic_timer_disabled) { | |
397 | /* No broadcast on UP ! */ | |
9d09951d TG |
398 | if (num_possible_cpus() > 1) { |
399 | lapic_clockevent.mult = 1; | |
ad62ca2b | 400 | setup_APIC_timer(); |
9d09951d | 401 | } |
ad62ca2b TG |
402 | return; |
403 | } | |
404 | ||
d36b49b9 TG |
405 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
406 | "calibrating APIC timer ...\n"); | |
1da177e4 | 407 | |
d36b49b9 TG |
408 | local_irq_disable(); |
409 | ||
410 | /* Replace the global interrupt handler */ | |
411 | real_handler = global_clock_event->event_handler; | |
412 | global_clock_event->event_handler = lapic_cal_handler; | |
1da177e4 | 413 | |
1da177e4 | 414 | /* |
d36b49b9 TG |
415 | * Setup the APIC counter to 1e9. There is no way the lapic |
416 | * can underflow in the 100ms detection time frame | |
1da177e4 | 417 | */ |
d36b49b9 | 418 | __setup_APIC_LVTT(1000000000, 0, 0); |
1da177e4 | 419 | |
d36b49b9 TG |
420 | /* Let the interrupts run */ |
421 | local_irq_enable(); | |
422 | ||
ca1b940c TG |
423 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
424 | cpu_relax(); | |
d36b49b9 TG |
425 | |
426 | local_irq_disable(); | |
427 | ||
428 | /* Restore the real event handler */ | |
429 | global_clock_event->event_handler = real_handler; | |
430 | ||
431 | /* Build delta t1-t2 as apic timer counts down */ | |
432 | delta = lapic_cal_t1 - lapic_cal_t2; | |
433 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
434 | ||
435 | /* Check, if the PM timer is available */ | |
436 | deltapm = lapic_cal_pm2 - lapic_cal_pm1; | |
437 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
438 | ||
439 | if (deltapm) { | |
440 | unsigned long mult; | |
441 | u64 res; | |
442 | ||
443 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
444 | ||
445 | if (deltapm > (pm_100ms - pm_thresh) && | |
446 | deltapm < (pm_100ms + pm_thresh)) { | |
447 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
448 | } else { | |
449 | res = (((u64) deltapm) * mult) >> 22; | |
450 | do_div(res, 1000000); | |
451 | printk(KERN_WARNING "APIC calibration not consistent " | |
452 | "with PM Timer: %ldms instead of 100ms\n", | |
453 | (long)res); | |
454 | /* Correct the lapic counter value */ | |
ff8a03a6 | 455 | res = (((u64) delta) * pm_100ms); |
d36b49b9 TG |
456 | do_div(res, deltapm); |
457 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
458 | "%lu (%ld)\n", (unsigned long) res, delta); | |
459 | delta = (long) res; | |
460 | } | |
ca1b940c | 461 | pm_referenced = 1; |
d36b49b9 | 462 | } |
e05d723f | 463 | |
e9e2cdb4 | 464 | /* Calculate the scaled math multiplication factor */ |
877084fb AM |
465 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
466 | lapic_clockevent.shift); | |
e9e2cdb4 TG |
467 | lapic_clockevent.max_delta_ns = |
468 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
469 | lapic_clockevent.min_delta_ns = | |
470 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
471 | ||
d36b49b9 TG |
472 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
473 | ||
474 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
e9e2cdb4 | 475 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
d36b49b9 TG |
476 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
477 | calibration_result); | |
e9e2cdb4 | 478 | |
d36b49b9 TG |
479 | if (cpu_has_tsc) { |
480 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
e05d723f | 481 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
d36b49b9 TG |
482 | "%ld.%04ld MHz.\n", |
483 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
484 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
485 | } | |
e05d723f TG |
486 | |
487 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
d36b49b9 TG |
488 | "%u.%04u MHz.\n", |
489 | calibration_result / (1000000 / HZ), | |
490 | calibration_result % (1000000 / HZ)); | |
e05d723f | 491 | |
d36b49b9 | 492 | local_apic_timer_verify_ok = 1; |
d36b49b9 | 493 | |
c2b84b30 TG |
494 | /* |
495 | * Do a sanity check on the APIC calibration result | |
496 | */ | |
497 | if (calibration_result < (1000000 / HZ)) { | |
498 | local_irq_enable(); | |
499 | printk(KERN_WARNING | |
500 | "APIC frequency too slow, disabling apic timer\n"); | |
501 | /* No broadcast on UP ! */ | |
502 | if (num_possible_cpus() > 1) | |
503 | setup_APIC_timer(); | |
504 | return; | |
505 | } | |
506 | ||
ca1b940c TG |
507 | /* We trust the pm timer based calibration */ |
508 | if (!pm_referenced) { | |
509 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
d36b49b9 | 510 | |
ca1b940c TG |
511 | /* |
512 | * Setup the apic timer manually | |
513 | */ | |
514 | levt->event_handler = lapic_cal_handler; | |
515 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
516 | lapic_cal_loops = -1; | |
d36b49b9 | 517 | |
ca1b940c TG |
518 | /* Let the interrupts run */ |
519 | local_irq_enable(); | |
d36b49b9 | 520 | |
f5352fd0 | 521 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
ca1b940c | 522 | cpu_relax(); |
d36b49b9 | 523 | |
ca1b940c | 524 | local_irq_disable(); |
d36b49b9 | 525 | |
ca1b940c TG |
526 | /* Stop the lapic timer */ |
527 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
d36b49b9 | 528 | |
ca1b940c | 529 | local_irq_enable(); |
d36b49b9 | 530 | |
ca1b940c TG |
531 | /* Jiffies delta */ |
532 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
533 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
d36b49b9 | 534 | |
d36b49b9 | 535 | /* Check, if the jiffies result is consistent */ |
ca1b940c | 536 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
d36b49b9 | 537 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
ca1b940c TG |
538 | else |
539 | local_apic_timer_verify_ok = 0; | |
4edc5db8 IM |
540 | } else |
541 | local_irq_enable(); | |
e05d723f | 542 | |
d36b49b9 TG |
543 | if (!local_apic_timer_verify_ok) { |
544 | printk(KERN_WARNING | |
545 | "APIC timer disabled due to verification failure.\n"); | |
546 | /* No broadcast on UP ! */ | |
547 | if (num_possible_cpus() == 1) | |
548 | return; | |
a5f5e43e TG |
549 | } else { |
550 | /* | |
551 | * If nmi_watchdog is set to IO_APIC, we need the | |
552 | * PIT/HPET going. Otherwise register lapic as a dummy | |
553 | * device. | |
554 | */ | |
555 | if (nmi_watchdog != NMI_IO_APIC) | |
556 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
820de5c3 IM |
557 | else |
558 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 559 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
a5f5e43e | 560 | } |
d36b49b9 TG |
561 | |
562 | /* Setup the lapic or request the broadcast */ | |
563 | setup_APIC_timer(); | |
e05d723f | 564 | } |
1da177e4 | 565 | |
e05d723f TG |
566 | void __devinit setup_secondary_APIC_clock(void) |
567 | { | |
e9e2cdb4 | 568 | setup_APIC_timer(); |
e05d723f | 569 | } |
1da177e4 | 570 | |
e05d723f | 571 | /* |
e9e2cdb4 | 572 | * The guts of the apic timer interrupt |
e05d723f | 573 | */ |
e9e2cdb4 | 574 | static void local_apic_timer_interrupt(void) |
e05d723f | 575 | { |
e9e2cdb4 TG |
576 | int cpu = smp_processor_id(); |
577 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
1da177e4 LT |
578 | |
579 | /* | |
d36b49b9 TG |
580 | * Normally we should not be here till LAPIC has been initialized but |
581 | * in some cases like kdump, its possible that there is a pending LAPIC | |
582 | * timer interrupt from previous kernel's context and is delivered in | |
583 | * new kernel the moment interrupts are enabled. | |
e05d723f | 584 | * |
d36b49b9 TG |
585 | * Interrupts are enabled early and LAPIC is setup much later, hence |
586 | * its possible that when we get here evt->event_handler is NULL. | |
587 | * Check for event_handler being NULL and discard the interrupt as | |
588 | * spurious. | |
1da177e4 | 589 | */ |
e9e2cdb4 TG |
590 | if (!evt->event_handler) { |
591 | printk(KERN_WARNING | |
592 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
593 | /* Switch it off */ | |
594 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
595 | return; | |
596 | } | |
597 | ||
0e078e2f TG |
598 | /* |
599 | * the NMI deadlock-detector uses this. | |
600 | */ | |
e9e2cdb4 TG |
601 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
602 | ||
603 | evt->event_handler(evt); | |
e05d723f TG |
604 | } |
605 | ||
606 | /* | |
607 | * Local APIC timer interrupt. This is the most natural way for doing | |
608 | * local interrupts, but local timer interrupts can be emulated by | |
609 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
610 | * | |
611 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
612 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
613 | */ | |
75604d7f | 614 | void smp_apic_timer_interrupt(struct pt_regs *regs) |
e05d723f TG |
615 | { |
616 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1da177e4 LT |
617 | |
618 | /* | |
e05d723f TG |
619 | * NOTE! We'd better ACK the irq immediately, |
620 | * because timer handling can be slow. | |
1da177e4 | 621 | */ |
e05d723f | 622 | ack_APIC_irq(); |
1a75a3f0 | 623 | /* |
e05d723f TG |
624 | * update_process_times() expects us to have done irq_enter(). |
625 | * Besides, if we don't timer interrupts ignore the global | |
626 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 627 | */ |
e05d723f | 628 | irq_enter(); |
e9e2cdb4 | 629 | local_apic_timer_interrupt(); |
e05d723f | 630 | irq_exit(); |
1a75a3f0 | 631 | |
e9e2cdb4 | 632 | set_irq_regs(old_regs); |
e05d723f TG |
633 | } |
634 | ||
635 | int setup_profiling_timer(unsigned int multiplier) | |
636 | { | |
637 | return -EINVAL; | |
638 | } | |
639 | ||
e319e765 RR |
640 | /* |
641 | * Setup extended LVT, AMD specific (K8, family 10h) | |
642 | * | |
643 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
644 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
645 | */ | |
646 | ||
647 | #define APIC_EILVT_LVTOFF_MCE 0 | |
648 | #define APIC_EILVT_LVTOFF_IBS 1 | |
649 | ||
650 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
651 | { | |
652 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; | |
653 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; | |
654 | apic_write(reg, v); | |
655 | } | |
656 | ||
657 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) | |
658 | { | |
659 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
660 | return APIC_EILVT_LVTOFF_MCE; | |
661 | } | |
662 | ||
663 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
664 | { | |
665 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
666 | return APIC_EILVT_LVTOFF_IBS; | |
667 | } | |
668 | ||
e05d723f TG |
669 | /* |
670 | * Local APIC start and shutdown | |
671 | */ | |
672 | ||
673 | /** | |
674 | * clear_local_APIC - shutdown the local APIC | |
675 | * | |
676 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
677 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
678 | * leftovers during boot. | |
679 | */ | |
680 | void clear_local_APIC(void) | |
681 | { | |
d3432896 | 682 | int maxlvt; |
0e078e2f | 683 | u32 v; |
1da177e4 | 684 | |
d3432896 AK |
685 | /* APIC hasn't been mapped yet */ |
686 | if (!apic_phys) | |
687 | return; | |
688 | ||
689 | maxlvt = lapic_get_maxlvt(); | |
1da177e4 | 690 | /* |
e05d723f TG |
691 | * Masking an LVT entry can trigger a local APIC error |
692 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 693 | */ |
e05d723f TG |
694 | if (maxlvt >= 3) { |
695 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
696 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
697 | } | |
1da177e4 | 698 | /* |
e05d723f TG |
699 | * Careful: we have to set masks only first to deassert |
700 | * any level-triggered sources. | |
1da177e4 | 701 | */ |
e05d723f TG |
702 | v = apic_read(APIC_LVTT); |
703 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
704 | v = apic_read(APIC_LVT0); | |
705 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
706 | v = apic_read(APIC_LVT1); | |
707 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
708 | if (maxlvt >= 4) { | |
709 | v = apic_read(APIC_LVTPC); | |
710 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 711 | } |
1da177e4 | 712 | |
e05d723f TG |
713 | /* lets not touch this if we didn't frob it */ |
714 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
715 | if (maxlvt >= 5) { | |
716 | v = apic_read(APIC_LVTTHMR); | |
717 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
718 | } | |
719 | #endif | |
1da177e4 | 720 | /* |
e05d723f | 721 | * Clean APIC state for other OSs: |
1da177e4 | 722 | */ |
e05d723f TG |
723 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
724 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
725 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
726 | if (maxlvt >= 3) | |
727 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
728 | if (maxlvt >= 4) | |
729 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 730 | |
e05d723f TG |
731 | #ifdef CONFIG_X86_MCE_P4THERMAL |
732 | if (maxlvt >= 5) | |
733 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
734 | #endif | |
735 | /* Integrated APIC (!82489DX) ? */ | |
736 | if (lapic_is_integrated()) { | |
1da177e4 | 737 | if (maxlvt > 3) |
e05d723f | 738 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 739 | apic_write(APIC_ESR, 0); |
e05d723f | 740 | apic_read(APIC_ESR); |
1da177e4 | 741 | } |
e05d723f | 742 | } |
1da177e4 | 743 | |
e05d723f TG |
744 | /** |
745 | * disable_local_APIC - clear and disable the local APIC | |
746 | */ | |
747 | void disable_local_APIC(void) | |
748 | { | |
749 | unsigned long value; | |
750 | ||
751 | clear_local_APIC(); | |
752 | ||
753 | /* | |
754 | * Disable APIC (implies clearing of registers | |
755 | * for 82489DX!). | |
756 | */ | |
757 | value = apic_read(APIC_SPIV); | |
758 | value &= ~APIC_SPIV_APIC_ENABLED; | |
759 | apic_write_around(APIC_SPIV, value); | |
760 | ||
761 | /* | |
762 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
763 | * restore the disabled state. | |
764 | */ | |
765 | if (enabled_via_apicbase) { | |
766 | unsigned int l, h; | |
767 | ||
768 | rdmsr(MSR_IA32_APICBASE, l, h); | |
769 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
770 | wrmsr(MSR_IA32_APICBASE, l, h); | |
771 | } | |
1da177e4 LT |
772 | } |
773 | ||
774 | /* | |
e05d723f TG |
775 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
776 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
777 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 778 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
779 | */ |
780 | void lapic_shutdown(void) | |
781 | { | |
67963132 MS |
782 | unsigned long flags; |
783 | ||
77f72b19 | 784 | if (!cpu_has_apic) |
1da177e4 LT |
785 | return; |
786 | ||
67963132 | 787 | local_irq_save(flags); |
77f72b19 ZM |
788 | clear_local_APIC(); |
789 | ||
790 | if (enabled_via_apicbase) | |
791 | disable_local_APIC(); | |
792 | ||
67963132 | 793 | local_irq_restore(flags); |
1da177e4 LT |
794 | } |
795 | ||
e05d723f TG |
796 | /* |
797 | * This is to verify that we're looking at a real local APIC. | |
798 | * Check these against your board if the CPUs aren't getting | |
799 | * started for no apparent reason. | |
800 | */ | |
801 | int __init verify_local_APIC(void) | |
1da177e4 | 802 | { |
e05d723f | 803 | unsigned int reg0, reg1; |
1da177e4 | 804 | |
e05d723f TG |
805 | /* |
806 | * The version register is read-only in a real APIC. | |
807 | */ | |
808 | reg0 = apic_read(APIC_LVR); | |
809 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
810 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
811 | reg1 = apic_read(APIC_LVR); | |
812 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
813 | ||
814 | /* | |
815 | * The two version reads above should print the same | |
816 | * numbers. If the second one is different, then we | |
817 | * poke at a non-APIC. | |
818 | */ | |
819 | if (reg1 != reg0) | |
1da177e4 LT |
820 | return 0; |
821 | ||
e05d723f TG |
822 | /* |
823 | * Check if the version looks reasonably. | |
824 | */ | |
825 | reg1 = GET_APIC_VERSION(reg0); | |
826 | if (reg1 == 0x00 || reg1 == 0xff) | |
827 | return 0; | |
828 | reg1 = lapic_get_maxlvt(); | |
829 | if (reg1 < 0x02 || reg1 == 0xff) | |
830 | return 0; | |
f990fff4 | 831 | |
e05d723f TG |
832 | /* |
833 | * The ID register is read/write in a real APIC. | |
834 | */ | |
835 | reg0 = apic_read(APIC_ID); | |
836 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
837 | ||
838 | /* | |
839 | * The next two are just to see if we have sane values. | |
840 | * They're only really relevant if we're in Virtual Wire | |
841 | * compatibility mode, but most boxes are anymore. | |
842 | */ | |
843 | reg0 = apic_read(APIC_LVT0); | |
844 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
845 | reg1 = apic_read(APIC_LVT1); | |
846 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
847 | ||
848 | return 1; | |
1da177e4 LT |
849 | } |
850 | ||
e05d723f TG |
851 | /** |
852 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
853 | */ | |
854 | void __init sync_Arb_IDs(void) | |
1da177e4 | 855 | { |
e05d723f TG |
856 | /* |
857 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
858 | * needed on AMD. | |
859 | */ | |
f44d9efd | 860 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
e05d723f TG |
861 | return; |
862 | /* | |
863 | * Wait for idle. | |
864 | */ | |
865 | apic_wait_icr_idle(); | |
1da177e4 | 866 | |
e05d723f TG |
867 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
868 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
869 | | APIC_DM_INIT); | |
870 | } | |
1da177e4 | 871 | |
e05d723f TG |
872 | /* |
873 | * An initial setup of the virtual wire mode. | |
874 | */ | |
875 | void __init init_bsp_APIC(void) | |
876 | { | |
877 | unsigned long value; | |
f990fff4 | 878 | |
e05d723f TG |
879 | /* |
880 | * Don't do the setup now if we have a SMP BIOS as the | |
881 | * through-I/O-APIC virtual wire mode might be active. | |
882 | */ | |
883 | if (smp_found_config || !cpu_has_apic) | |
884 | return; | |
1da177e4 LT |
885 | |
886 | /* | |
e05d723f | 887 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 888 | */ |
e05d723f | 889 | clear_local_APIC(); |
1da177e4 | 890 | |
e05d723f TG |
891 | /* |
892 | * Enable APIC. | |
893 | */ | |
894 | value = apic_read(APIC_SPIV); | |
895 | value &= ~APIC_VECTOR_MASK; | |
896 | value |= APIC_SPIV_APIC_ENABLED; | |
897 | ||
898 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
899 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
900 | (boot_cpu_data.x86 == 15)) | |
901 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
902 | else | |
903 | value |= APIC_SPIV_FOCUS_DISABLED; | |
904 | value |= SPURIOUS_APIC_VECTOR; | |
905 | apic_write_around(APIC_SPIV, value); | |
906 | ||
907 | /* | |
908 | * Set up the virtual wire mode. | |
909 | */ | |
910 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
911 | value = APIC_DM_NMI; | |
912 | if (!lapic_is_integrated()) /* 82489DX */ | |
913 | value |= APIC_LVT_LEVEL_TRIGGER; | |
914 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
915 | } |
916 | ||
a4928cff | 917 | static void __cpuinit lapic_setup_esr(void) |
df7939ae GOC |
918 | { |
919 | unsigned long oldvalue, value, maxlvt; | |
920 | if (lapic_is_integrated() && !esr_disable) { | |
921 | /* !82489DX */ | |
922 | maxlvt = lapic_get_maxlvt(); | |
923 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
924 | apic_write(APIC_ESR, 0); | |
925 | oldvalue = apic_read(APIC_ESR); | |
926 | ||
927 | /* enables sending errors */ | |
928 | value = ERROR_APIC_VECTOR; | |
929 | apic_write_around(APIC_LVTERR, value); | |
930 | /* | |
931 | * spec says clear errors after enabling vector. | |
932 | */ | |
933 | if (maxlvt > 3) | |
934 | apic_write(APIC_ESR, 0); | |
935 | value = apic_read(APIC_ESR); | |
936 | if (value != oldvalue) | |
937 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
938 | "vector: 0x%08lx after: 0x%08lx\n", | |
939 | oldvalue, value); | |
940 | } else { | |
941 | if (esr_disable) | |
942 | /* | |
943 | * Something untraceable is creating bad interrupts on | |
944 | * secondary quads ... for the moment, just leave the | |
945 | * ESR disabled - we can't do anything useful with the | |
946 | * errors anyway - mbligh | |
947 | */ | |
948 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
949 | else | |
950 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
951 | } | |
952 | } | |
953 | ||
954 | ||
e05d723f TG |
955 | /** |
956 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 957 | */ |
d5337983 | 958 | void __cpuinit setup_local_APIC(void) |
e05d723f | 959 | { |
df7939ae | 960 | unsigned long value, integrated; |
e05d723f | 961 | int i, j; |
1da177e4 | 962 | |
e05d723f TG |
963 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
964 | if (esr_disable) { | |
965 | apic_write(APIC_ESR, 0); | |
966 | apic_write(APIC_ESR, 0); | |
967 | apic_write(APIC_ESR, 0); | |
968 | apic_write(APIC_ESR, 0); | |
969 | } | |
1da177e4 | 970 | |
e05d723f | 971 | integrated = lapic_is_integrated(); |
1da177e4 | 972 | |
e05d723f TG |
973 | /* |
974 | * Double-check whether this APIC is really registered. | |
975 | */ | |
976 | if (!apic_id_registered()) | |
22d5c67c | 977 | WARN_ON_ONCE(1); |
1da177e4 | 978 | |
e05d723f TG |
979 | /* |
980 | * Intel recommends to set DFR, LDR and TPR before enabling | |
981 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
982 | * document number 292116). So here it goes... | |
983 | */ | |
984 | init_apic_ldr(); | |
1da177e4 | 985 | |
e05d723f TG |
986 | /* |
987 | * Set Task Priority to 'accept all'. We never change this | |
988 | * later on. | |
989 | */ | |
990 | value = apic_read(APIC_TASKPRI); | |
991 | value &= ~APIC_TPRI_MASK; | |
992 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 993 | |
e05d723f TG |
994 | /* |
995 | * After a crash, we no longer service the interrupts and a pending | |
996 | * interrupt from previous kernel might still have ISR bit set. | |
997 | * | |
998 | * Most probably by now CPU has serviced that pending interrupt and | |
999 | * it might not have done the ack_APIC_irq() because it thought, | |
1000 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1001 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1002 | * the interrupt. Hence a vector might get locked. It was noticed | |
1003 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1004 | */ | |
1005 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1006 | value = apic_read(APIC_ISR + i*0x10); | |
1007 | for (j = 31; j >= 0; j--) { | |
1008 | if (value & (1<<j)) | |
1009 | ack_APIC_irq(); | |
1010 | } | |
1011 | } | |
1da177e4 | 1012 | |
e05d723f TG |
1013 | /* |
1014 | * Now that we are all set up, enable the APIC | |
1015 | */ | |
1016 | value = apic_read(APIC_SPIV); | |
1017 | value &= ~APIC_VECTOR_MASK; | |
1018 | /* | |
1019 | * Enable APIC | |
1020 | */ | |
1021 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 1022 | |
e05d723f TG |
1023 | /* |
1024 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1025 | * certain networking cards. If high frequency interrupts are | |
1026 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1027 | * entry is masked/unmasked at a high rate as well then sooner or | |
1028 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1029 | * from the device. If focus CPU is disabled then the hang goes | |
1030 | * away, oh well :-( | |
1031 | * | |
1032 | * [ This bug can be reproduced easily with a level-triggered | |
1033 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1034 | * BX chipset. ] | |
1035 | */ | |
1036 | /* | |
1037 | * Actually disabling the focus CPU check just makes the hang less | |
1038 | * frequent as it makes the interrupt distributon model be more | |
1039 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1040 | * See also the comment in end_level_ioapic_irq(). --macro | |
1041 | */ | |
1da177e4 | 1042 | |
e05d723f TG |
1043 | /* Enable focus processor (bit==0) */ |
1044 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1045 | |
e05d723f TG |
1046 | /* |
1047 | * Set spurious IRQ vector | |
1048 | */ | |
1049 | value |= SPURIOUS_APIC_VECTOR; | |
1050 | apic_write_around(APIC_SPIV, value); | |
1051 | ||
1052 | /* | |
1053 | * Set up LVT0, LVT1: | |
1054 | * | |
1055 | * set up through-local-APIC on the BP's LINT0. This is not | |
27b46d76 | 1056 | * strictly necessary in pure symmetric-IO mode, but sometimes |
e05d723f TG |
1057 | * we delegate interrupts to the 8259A. |
1058 | */ | |
1059 | /* | |
1060 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1061 | */ | |
1062 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
1063 | if (!smp_processor_id() && (pic_mode || !value)) { | |
1064 | value = APIC_DM_EXTINT; | |
1065 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
1066 | smp_processor_id()); | |
1067 | } else { | |
1068 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
1069 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
1070 | smp_processor_id()); | |
1071 | } | |
1072 | apic_write_around(APIC_LVT0, value); | |
1073 | ||
1074 | /* | |
1075 | * only the BP should see the LINT1 NMI signal, obviously. | |
1076 | */ | |
1077 | if (!smp_processor_id()) | |
1078 | value = APIC_DM_NMI; | |
1079 | else | |
1080 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
1081 | if (!integrated) /* 82489DX */ | |
1082 | value |= APIC_LVT_LEVEL_TRIGGER; | |
1083 | apic_write_around(APIC_LVT1, value); | |
ac60aae5 | 1084 | } |
e05d723f | 1085 | |
ac60aae5 GOC |
1086 | void __cpuinit end_local_APIC_setup(void) |
1087 | { | |
1088 | unsigned long value; | |
1da177e4 | 1089 | |
ac60aae5 | 1090 | lapic_setup_esr(); |
e9e2cdb4 TG |
1091 | /* Disable the local apic timer */ |
1092 | value = apic_read(APIC_LVTT); | |
1093 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1094 | apic_write_around(APIC_LVTT, value); | |
1095 | ||
e05d723f TG |
1096 | setup_apic_nmi_watchdog(NULL); |
1097 | apic_pm_activate(); | |
1da177e4 LT |
1098 | } |
1099 | ||
e05d723f TG |
1100 | /* |
1101 | * Detect and initialize APIC | |
1102 | */ | |
e83a5fdc | 1103 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1104 | { |
1105 | u32 h, l, features; | |
1da177e4 LT |
1106 | |
1107 | /* Disabled by kernel option? */ | |
914bebfa | 1108 | if (disable_apic) |
1da177e4 LT |
1109 | return -1; |
1110 | ||
1da177e4 LT |
1111 | switch (boot_cpu_data.x86_vendor) { |
1112 | case X86_VENDOR_AMD: | |
1113 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 1114 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
1115 | break; |
1116 | goto no_apic; | |
1117 | case X86_VENDOR_INTEL: | |
1118 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1119 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1120 | break; | |
1121 | goto no_apic; | |
1122 | default: | |
1123 | goto no_apic; | |
1124 | } | |
1125 | ||
1126 | if (!cpu_has_apic) { | |
1127 | /* | |
e05d723f TG |
1128 | * Over-ride BIOS and try to enable the local APIC only if |
1129 | * "lapic" specified. | |
1da177e4 | 1130 | */ |
914bebfa | 1131 | if (!force_enable_local_apic) { |
e05d723f | 1132 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
1133 | "you can enable it with \"lapic\"\n"); |
1134 | return -1; | |
1135 | } | |
1136 | /* | |
e05d723f TG |
1137 | * Some BIOSes disable the local APIC in the APIC_BASE |
1138 | * MSR. This can only be done in software for Intel P6 or later | |
1139 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
1140 | */ |
1141 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1142 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
1143 | printk(KERN_INFO |
1144 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
1145 | l &= ~MSR_IA32_APICBASE_BASE; |
1146 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1147 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1148 | enabled_via_apicbase = 1; | |
1149 | } | |
1150 | } | |
1151 | /* | |
1152 | * The APIC feature bit should now be enabled | |
1153 | * in `cpuid' | |
1154 | */ | |
1155 | features = cpuid_edx(1); | |
1156 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 1157 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
1158 | return -1; |
1159 | } | |
53756d37 | 1160 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 LT |
1161 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1162 | ||
1163 | /* The BIOS may have set up the APIC at some other address */ | |
1164 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
1165 | if (l & MSR_IA32_APICBASE_ENABLE) |
1166 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 1167 | |
e05d723f | 1168 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 1169 | |
e05d723f | 1170 | apic_pm_activate(); |
1da177e4 | 1171 | |
e05d723f | 1172 | return 0; |
1da177e4 | 1173 | |
e05d723f TG |
1174 | no_apic: |
1175 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1176 | return -1; | |
1177 | } | |
1da177e4 | 1178 | |
e05d723f TG |
1179 | /** |
1180 | * init_apic_mappings - initialize APIC mappings | |
1181 | */ | |
1182 | void __init init_apic_mappings(void) | |
1da177e4 | 1183 | { |
1da177e4 | 1184 | /* |
e05d723f TG |
1185 | * If no local APIC can be found then set up a fake all |
1186 | * zeroes page to simulate the local APIC and another | |
1187 | * one for the IO-APIC. | |
1da177e4 | 1188 | */ |
e05d723f TG |
1189 | if (!smp_found_config && detect_init_APIC()) { |
1190 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1191 | apic_phys = __pa(apic_phys); | |
1192 | } else | |
1193 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1194 | |
e05d723f TG |
1195 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1196 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1197 | apic_phys); | |
1da177e4 | 1198 | |
e05d723f TG |
1199 | /* |
1200 | * Fetch the APIC ID of the BSP in case we have a | |
1201 | * default configuration (or the MP table is broken). | |
1202 | */ | |
1203 | if (boot_cpu_physical_apicid == -1U) | |
05f2d12c | 1204 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 | 1205 | |
1da177e4 LT |
1206 | } |
1207 | ||
e05d723f TG |
1208 | /* |
1209 | * This initializes the IO-APIC and APIC hardware if this is | |
1210 | * a UP kernel. | |
1211 | */ | |
e81b2c62 AS |
1212 | |
1213 | int apic_version[MAX_APICS]; | |
1214 | ||
e83a5fdc | 1215 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1216 | { |
914bebfa | 1217 | if (disable_apic) |
53756d37 | 1218 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1da177e4 | 1219 | |
e05d723f TG |
1220 | if (!smp_found_config && !cpu_has_apic) |
1221 | return -1; | |
6eb0a0fd | 1222 | |
e05d723f TG |
1223 | /* |
1224 | * Complain if the BIOS pretends there is one. | |
1225 | */ | |
1226 | if (!cpu_has_apic && | |
1227 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1228 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1229 | boot_cpu_physical_apicid); | |
53756d37 | 1230 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
e05d723f | 1231 | return -1; |
6eb0a0fd | 1232 | } |
6eb0a0fd | 1233 | |
e05d723f | 1234 | verify_local_APIC(); |
6eb0a0fd | 1235 | |
e05d723f | 1236 | connect_bsp_APIC(); |
6eb0a0fd | 1237 | |
e05d723f TG |
1238 | /* |
1239 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1240 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1241 | * might be zero if read from MP tables. Get it from LAPIC. | |
1242 | */ | |
1243 | #ifdef CONFIG_CRASH_DUMP | |
05f2d12c | 1244 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
e05d723f | 1245 | #endif |
b6df1b8b | 1246 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
1da177e4 | 1247 | |
e05d723f | 1248 | setup_local_APIC(); |
1da177e4 | 1249 | |
acae7d90 MR |
1250 | #ifdef CONFIG_X86_IO_APIC |
1251 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) | |
1252 | #endif | |
1253 | localise_nmi_watchdog(); | |
ac60aae5 | 1254 | end_local_APIC_setup(); |
e05d723f TG |
1255 | #ifdef CONFIG_X86_IO_APIC |
1256 | if (smp_found_config) | |
1257 | if (!skip_ioapic_setup && nr_ioapics) | |
1258 | setup_IO_APIC(); | |
1da177e4 | 1259 | #endif |
e05d723f | 1260 | setup_boot_clock(); |
1da177e4 | 1261 | |
e05d723f | 1262 | return 0; |
1da177e4 LT |
1263 | } |
1264 | ||
e05d723f TG |
1265 | /* |
1266 | * Local APIC interrupts | |
1267 | */ | |
1268 | ||
1da177e4 LT |
1269 | /* |
1270 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1271 | */ | |
e9e2cdb4 | 1272 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1273 | { |
1274 | unsigned long v; | |
1275 | ||
1276 | irq_enter(); | |
1277 | /* | |
1278 | * Check if this really is a spurious interrupt and ACK it | |
1279 | * if it is a vectored one. Just in case... | |
1280 | * Spurious interrupts should not be ACKed. | |
1281 | */ | |
1282 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1283 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1284 | ack_APIC_irq(); | |
1285 | ||
1286 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1287 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1288 | "should never happen.\n", smp_processor_id()); | |
38e760a1 | 1289 | __get_cpu_var(irq_stat).irq_spurious_count++; |
1da177e4 LT |
1290 | irq_exit(); |
1291 | } | |
1292 | ||
1293 | /* | |
1294 | * This interrupt should never happen with our APIC/SMP architecture | |
1295 | */ | |
e9e2cdb4 | 1296 | void smp_error_interrupt(struct pt_regs *regs) |
1da177e4 LT |
1297 | { |
1298 | unsigned long v, v1; | |
1299 | ||
1300 | irq_enter(); | |
1301 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1302 | v = apic_read(APIC_ESR); | |
1303 | apic_write(APIC_ESR, 0); | |
1304 | v1 = apic_read(APIC_ESR); | |
1305 | ack_APIC_irq(); | |
1306 | atomic_inc(&irq_err_count); | |
1307 | ||
1308 | /* Here is what the APIC error bits mean: | |
1309 | 0: Send CS error | |
1310 | 1: Receive CS error | |
1311 | 2: Send accept error | |
1312 | 3: Receive accept error | |
1313 | 4: Reserved | |
1314 | 5: Send illegal vector | |
1315 | 6: Received illegal vector | |
1316 | 7: Illegal register address | |
1317 | */ | |
ff8a03a6 | 1318 | printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", |
e05d723f | 1319 | smp_processor_id(), v , v1); |
1da177e4 LT |
1320 | irq_exit(); |
1321 | } | |
1322 | ||
17c9ab1e GOC |
1323 | #ifdef CONFIG_SMP |
1324 | void __init smp_intr_init(void) | |
1325 | { | |
1326 | /* | |
1327 | * IRQ0 must be given a fixed assignment and initialized, | |
1328 | * because it's used before the IO-APIC is set up. | |
1329 | */ | |
1330 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1331 | ||
1332 | /* | |
1333 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1334 | * IPI, driven by wakeup. | |
1335 | */ | |
305b92a2 | 1336 | alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); |
17c9ab1e GOC |
1337 | |
1338 | /* IPI for invalidation */ | |
305b92a2 | 1339 | alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); |
17c9ab1e GOC |
1340 | |
1341 | /* IPI for generic function call */ | |
305b92a2 | 1342 | alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); |
17c9ab1e GOC |
1343 | } |
1344 | #endif | |
1345 | ||
1da177e4 | 1346 | /* |
e05d723f | 1347 | * Initialize APIC interrupts |
1da177e4 | 1348 | */ |
e05d723f | 1349 | void __init apic_intr_init(void) |
1da177e4 | 1350 | { |
e05d723f TG |
1351 | #ifdef CONFIG_SMP |
1352 | smp_intr_init(); | |
1353 | #endif | |
1354 | /* self generated IPI for local APIC timer */ | |
305b92a2 | 1355 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
1da177e4 | 1356 | |
e05d723f | 1357 | /* IPI vectors for APIC spurious and error interrupts */ |
305b92a2 AM |
1358 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
1359 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1360 | |
e05d723f TG |
1361 | /* thermal monitor LVT interrupt */ |
1362 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
305b92a2 | 1363 | alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); |
e05d723f TG |
1364 | #endif |
1365 | } | |
1366 | ||
1367 | /** | |
1368 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1369 | */ | |
1370 | void __init connect_bsp_APIC(void) | |
1371 | { | |
1372 | if (pic_mode) { | |
1373 | /* | |
1374 | * Do not trust the local APIC being empty at bootup. | |
1375 | */ | |
1376 | clear_local_APIC(); | |
1377 | /* | |
1378 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1379 | * local APIC to INT and NMI lines. | |
1380 | */ | |
1381 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1382 | "enabling APIC mode.\n"); | |
1383 | outb(0x70, 0x22); | |
1384 | outb(0x01, 0x23); | |
1da177e4 | 1385 | } |
e05d723f TG |
1386 | enable_apic_mode(); |
1387 | } | |
1da177e4 | 1388 | |
e05d723f TG |
1389 | /** |
1390 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1391 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1392 | * | |
1393 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1394 | * APIC is disabled. | |
1395 | */ | |
1396 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1397 | { | |
1398 | if (pic_mode) { | |
1399 | /* | |
1400 | * Put the board back into PIC mode (has an effect only on | |
1401 | * certain older boards). Note that APIC interrupts, including | |
1402 | * IPIs, won't work beyond this point! The only exception are | |
1403 | * INIT IPIs. | |
1404 | */ | |
1405 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1406 | "entering PIC mode.\n"); | |
1407 | outb(0x70, 0x22); | |
1408 | outb(0x00, 0x23); | |
1409 | } else { | |
1410 | /* Go back to Virtual Wire compatibility mode */ | |
1411 | unsigned long value; | |
1da177e4 | 1412 | |
e05d723f TG |
1413 | /* For the spurious interrupt use vector F, and enable it */ |
1414 | value = apic_read(APIC_SPIV); | |
1415 | value &= ~APIC_VECTOR_MASK; | |
1416 | value |= APIC_SPIV_APIC_ENABLED; | |
1417 | value |= 0xf; | |
1418 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1419 | |
e05d723f TG |
1420 | if (!virt_wire_setup) { |
1421 | /* | |
1422 | * For LVT0 make it edge triggered, active high, | |
1423 | * external and enabled | |
1424 | */ | |
1425 | value = apic_read(APIC_LVT0); | |
1426 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1427 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
ff8a03a6 | 1428 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
e05d723f TG |
1429 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1430 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1431 | apic_write_around(APIC_LVT0, value); | |
1432 | } else { | |
1433 | /* Disable LVT0 */ | |
1434 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1435 | } | |
1da177e4 | 1436 | |
e05d723f TG |
1437 | /* |
1438 | * For LVT1 make it edge triggered, active high, nmi and | |
1439 | * enabled | |
1440 | */ | |
1441 | value = apic_read(APIC_LVT1); | |
1442 | value &= ~( | |
1443 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1444 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1445 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1446 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1447 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1448 | apic_write_around(APIC_LVT1, value); | |
1449 | } | |
1450 | } | |
1da177e4 | 1451 | |
903dcb5a AS |
1452 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
1453 | ||
1454 | void __cpuinit generic_processor_info(int apicid, int version) | |
1455 | { | |
1456 | int cpu; | |
1457 | cpumask_t tmp_map; | |
1458 | physid_mask_t phys_cpu; | |
1459 | ||
1460 | /* | |
1461 | * Validate version | |
1462 | */ | |
1463 | if (version == 0x0) { | |
1464 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1465 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1466 | version); | |
1467 | version = 0x10; | |
1468 | } | |
1469 | apic_version[apicid] = version; | |
1470 | ||
1471 | phys_cpu = apicid_to_cpu_present(apicid); | |
1472 | physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu); | |
1473 | ||
1474 | if (num_processors >= NR_CPUS) { | |
1475 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1476 | " Processor ignored.\n", NR_CPUS); | |
1477 | return; | |
1478 | } | |
1479 | ||
1480 | if (num_processors >= maxcpus) { | |
1481 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1482 | " Processor ignored.\n", maxcpus); | |
1483 | return; | |
1484 | } | |
1485 | ||
1486 | num_processors++; | |
1487 | cpus_complement(tmp_map, cpu_present_map); | |
1488 | cpu = first_cpu(tmp_map); | |
1489 | ||
1490 | if (apicid == boot_cpu_physical_apicid) | |
1491 | /* | |
1492 | * x86_bios_cpu_apicid is required to have processors listed | |
1493 | * in same order as logical cpu numbers. Hence the first | |
1494 | * entry is BSP, and so on. | |
1495 | */ | |
1496 | cpu = 0; | |
1497 | ||
e0da3364 YL |
1498 | if (apicid > max_physical_apicid) |
1499 | max_physical_apicid = apicid; | |
1500 | ||
903dcb5a AS |
1501 | /* |
1502 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1503 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1504 | * before this can be done without some confusion. | |
1505 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1506 | * - Ashok Raj <ashok.raj@intel.com> | |
1507 | */ | |
e0da3364 | 1508 | if (max_physical_apicid >= 8) { |
903dcb5a AS |
1509 | switch (boot_cpu_data.x86_vendor) { |
1510 | case X86_VENDOR_INTEL: | |
1511 | if (!APIC_XAPIC(version)) { | |
1512 | def_to_bigsmp = 0; | |
1513 | break; | |
1514 | } | |
1515 | /* If P4 and above fall through */ | |
1516 | case X86_VENDOR_AMD: | |
1517 | def_to_bigsmp = 1; | |
1518 | } | |
1519 | } | |
1520 | #ifdef CONFIG_SMP | |
1521 | /* are we being called early in kernel startup? */ | |
23ca4bba MT |
1522 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1523 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1524 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
903dcb5a AS |
1525 | |
1526 | cpu_to_apicid[cpu] = apicid; | |
1527 | bios_cpu_apicid[cpu] = apicid; | |
1528 | } else { | |
1529 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1530 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1531 | } | |
1532 | #endif | |
1533 | cpu_set(cpu, cpu_possible_map); | |
1534 | cpu_set(cpu, cpu_present_map); | |
1535 | } | |
1536 | ||
e05d723f TG |
1537 | /* |
1538 | * Power management | |
1539 | */ | |
1540 | #ifdef CONFIG_PM | |
1541 | ||
1542 | static struct { | |
1543 | int active; | |
1544 | /* r/w apic fields */ | |
1545 | unsigned int apic_id; | |
1546 | unsigned int apic_taskpri; | |
1547 | unsigned int apic_ldr; | |
1548 | unsigned int apic_dfr; | |
1549 | unsigned int apic_spiv; | |
1550 | unsigned int apic_lvtt; | |
1551 | unsigned int apic_lvtpc; | |
1552 | unsigned int apic_lvt0; | |
1553 | unsigned int apic_lvt1; | |
1554 | unsigned int apic_lvterr; | |
1555 | unsigned int apic_tmict; | |
1556 | unsigned int apic_tdcr; | |
1557 | unsigned int apic_thmr; | |
1558 | } apic_pm_state; | |
1559 | ||
1560 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1561 | { | |
1562 | unsigned long flags; | |
1563 | int maxlvt; | |
1564 | ||
1565 | if (!apic_pm_state.active) | |
1566 | return 0; | |
1567 | ||
1568 | maxlvt = lapic_get_maxlvt(); | |
1569 | ||
1570 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1571 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1572 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1573 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1574 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1575 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1576 | if (maxlvt >= 4) | |
1577 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1578 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1579 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1580 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1581 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1582 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1583 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1584 | if (maxlvt >= 5) | |
1585 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1586 | #endif |
1e4c85f9 | 1587 | |
e05d723f TG |
1588 | local_irq_save(flags); |
1589 | disable_local_APIC(); | |
1590 | local_irq_restore(flags); | |
1e4c85f9 | 1591 | return 0; |
1da177e4 | 1592 | } |
1a3f239d | 1593 | |
e05d723f | 1594 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1595 | { |
e05d723f TG |
1596 | unsigned int l, h; |
1597 | unsigned long flags; | |
1598 | int maxlvt; | |
1599 | ||
1600 | if (!apic_pm_state.active) | |
1601 | return 0; | |
1602 | ||
1603 | maxlvt = lapic_get_maxlvt(); | |
1604 | ||
1605 | local_irq_save(flags); | |
1606 | ||
1607 | /* | |
1608 | * Make sure the APICBASE points to the right address | |
1609 | * | |
1610 | * FIXME! This will be wrong if we ever support suspend on | |
1611 | * SMP! We'll need to do this as part of the CPU restore! | |
1612 | */ | |
1613 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1614 | l &= ~MSR_IA32_APICBASE_BASE; | |
1615 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1616 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1617 | ||
1618 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1619 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1620 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1621 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1622 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1623 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1624 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1625 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1626 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1627 | if (maxlvt >= 5) | |
1628 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1629 | #endif | |
1630 | if (maxlvt >= 4) | |
1631 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1632 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1633 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1634 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1635 | apic_write(APIC_ESR, 0); | |
1636 | apic_read(APIC_ESR); | |
1637 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1638 | apic_write(APIC_ESR, 0); | |
1639 | apic_read(APIC_ESR); | |
1640 | local_irq_restore(flags); | |
1a3f239d RR |
1641 | return 0; |
1642 | } | |
1a3f239d | 1643 | |
e05d723f TG |
1644 | /* |
1645 | * This device has no shutdown method - fully functioning local APICs | |
1646 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1647 | */ | |
1648 | ||
1649 | static struct sysdev_class lapic_sysclass = { | |
af5ca3f4 | 1650 | .name = "lapic", |
e05d723f TG |
1651 | .resume = lapic_resume, |
1652 | .suspend = lapic_suspend, | |
1653 | }; | |
1654 | ||
1655 | static struct sys_device device_lapic = { | |
1656 | .id = 0, | |
1657 | .cls = &lapic_sysclass, | |
1658 | }; | |
1659 | ||
1660 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1661 | { |
e05d723f | 1662 | apic_pm_state.active = 1; |
1a3f239d | 1663 | } |
1a3f239d | 1664 | |
e05d723f TG |
1665 | static int __init init_lapic_sysfs(void) |
1666 | { | |
1667 | int error; | |
1668 | ||
1669 | if (!cpu_has_apic) | |
1670 | return 0; | |
1671 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1672 | ||
1673 | error = sysdev_class_register(&lapic_sysclass); | |
1674 | if (!error) | |
1675 | error = sysdev_register(&device_lapic); | |
1676 | return error; | |
1677 | } | |
1678 | device_initcall(init_lapic_sysfs); | |
1679 | ||
1680 | #else /* CONFIG_PM */ | |
1681 | ||
1682 | static void apic_pm_activate(void) { } | |
1683 | ||
1684 | #endif /* CONFIG_PM */ | |
0e078e2f TG |
1685 | |
1686 | /* | |
1687 | * APIC command line parameters | |
1688 | */ | |
1689 | static int __init parse_lapic(char *arg) | |
1690 | { | |
914bebfa | 1691 | force_enable_local_apic = 1; |
0e078e2f TG |
1692 | return 0; |
1693 | } | |
1694 | early_param("lapic", parse_lapic); | |
1695 | ||
1696 | static int __init parse_nolapic(char *arg) | |
1697 | { | |
914bebfa | 1698 | disable_apic = 1; |
53756d37 | 1699 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
0e078e2f TG |
1700 | return 0; |
1701 | } | |
1702 | early_param("nolapic", parse_nolapic); | |
1703 | ||
1704 | static int __init parse_disable_lapic_timer(char *arg) | |
1705 | { | |
1706 | local_apic_timer_disabled = 1; | |
1707 | return 0; | |
1708 | } | |
1709 | early_param("nolapic_timer", parse_disable_lapic_timer); | |
1710 | ||
1711 | static int __init parse_lapic_timer_c2_ok(char *arg) | |
1712 | { | |
1713 | local_apic_timer_c2_ok = 1; | |
1714 | return 0; | |
1715 | } | |
1716 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1717 | ||
1718 | static int __init apic_set_verbosity(char *str) | |
1719 | { | |
1720 | if (strcmp("debug", str) == 0) | |
1721 | apic_verbosity = APIC_DEBUG; | |
1722 | else if (strcmp("verbose", str) == 0) | |
1723 | apic_verbosity = APIC_VERBOSE; | |
1724 | return 1; | |
1725 | } | |
1726 | __setup("apic=", apic_set_verbosity); | |
1727 | ||
746f2eb7 CG |
1728 | static int __init lapic_insert_resource(void) |
1729 | { | |
1730 | if (!apic_phys) | |
1731 | return -1; | |
1732 | ||
1733 | /* Put local APIC into the resource map. */ | |
1734 | lapic_resource.start = apic_phys; | |
1735 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1736 | insert_resource(&iomem_resource, &lapic_resource); | |
1737 | ||
1738 | return 0; | |
1739 | } | |
1740 | ||
1741 | /* | |
1742 | * need call insert after e820_reserve_resources() | |
1743 | * that is using request_resource | |
1744 | */ | |
1745 | late_initcall(lapic_insert_resource); |